Pileus Git - ~andy/linux/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/firmware.h>
  25 #include <linux/videodev2.h>
  26 #include <media/v4l2-common.h>
  27 #include "pvrusb2.h"
  28 #include "pvrusb2-std.h"
  29 #include "pvrusb2-util.h"
  30 #include "pvrusb2-hdw.h"
  31 #include "pvrusb2-i2c-core.h"
  32 #include "pvrusb2-i2c-track.h"
  33 #include "pvrusb2-tuner.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38 #include "pvrusb2-fx2-cmd.h"
  39 #include "pvrusb2-wm8775.h"
  40 #include "pvrusb2-video-v4l.h"
  41 #include "pvrusb2-cx2584x-v4l.h"
  42 #include "pvrusb2-audio.h"
  43
  44 #define TV_MIN_FREQ     55250000L
  45 #define TV_MAX_FREQ    850000000L
  46
  47 /* This defines a minimum interval that the decoder must remain quiet
  48    before we are allowed to start it running. */
  49 #define TIME_MSEC_DECODER_WAIT 50
  50
  51 /* This defines a minimum interval that the encoder must remain quiet
  52    before we are allowed to configure it.  I had this originally set to
  53    50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
  54    things work better when it's set to 100msec. */
  55 #define TIME_MSEC_ENCODER_WAIT 100
  56
  57 /* This defines the minimum interval that the encoder must successfully run
  58    before we consider that the encoder has run at least once since its
  59    firmware has been loaded.  This measurement is in important for cases
  60    where we can't do something until we know that the encoder has been run
  61    at least once. */
  62 #define TIME_MSEC_ENCODER_OK 250
  63
  64 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  65 static DEFINE_MUTEX(pvr2_unit_mtx);
  66
  67 static int ctlchg;
  68 static int procreload;
  69 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  70 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  71 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  72 static int init_pause_msec;
  73
  74 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  75 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  76 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  77 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  78 module_param(procreload, int, S_IRUGO|S_IWUSR);
  79 MODULE_PARM_DESC(procreload,
  80                  "Attempt init failure recovery with firmware reload");
  81 module_param_array(tuner,    int, NULL, 0444);
  82 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  83 module_param_array(video_std,    int, NULL, 0444);
  84 MODULE_PARM_DESC(video_std,"specify initial video standard");
  85 module_param_array(tolerance,    int, NULL, 0444);
  86 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  87
  88 /* US Broadcast channel 7 (175.25 MHz) */
  89 static int default_tv_freq    = 175250000L;
  90 /* 104.3 MHz, a usable FM station for my area */
  91 static int default_radio_freq = 104300000L;
  92
  93 module_param_named(tv_freq, default_tv_freq, int, 0444);
  94 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  95 module_param_named(radio_freq, default_radio_freq, int, 0444);
  96 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  97
  98 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  99 #define PVR2_CTL_READ_ENDPOINT   0x81
 100
 101 #define PVR2_GPIO_IN 0x9008
 102 #define PVR2_GPIO_OUT 0x900c
 103 #define PVR2_GPIO_DIR 0x9020
 104
 105 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 106
 107 #define PVR2_FIRMWARE_ENDPOINT   0x02
 108
 109 /* size of a firmware chunk */
 110 #define FIRMWARE_CHUNK_SIZE 0x2000
 111
 112 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
 113                                         struct v4l2_subdev *);
 114
 115 static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
 116         [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
 117         [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
 118         [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
 119         [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
 120 };
 121
 122 static const char *module_names[] = {
 123         [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 124         [PVR2_CLIENT_ID_CX25840] = "cx25840",
 125         [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 126         [PVR2_CLIENT_ID_TUNER] = "tuner",
 127         [PVR2_CLIENT_ID_CS53132A] = "cs53132a",
 128         [PVR2_CLIENT_ID_WM8775] = "wm8775",
 129 };
 130
 131
 132 static const unsigned char *module_i2c_addresses[] = {
 133         [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 134         [PVR2_CLIENT_ID_WM8775] = "\x1b",
 135 };
 136
 137
 138 /* Define the list of additional controls we'll dynamically construct based
 139    on query of the cx2341x module. */
 140 struct pvr2_mpeg_ids {
 141         const char *strid;
 142         int id;
 143 };
 144 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 145         {
 146                 .strid = "audio_layer",
 147                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 148         },{
 149                 .strid = "audio_bitrate",
 150                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 151         },{
 152                 /* Already using audio_mode elsewhere :-( */
 153                 .strid = "mpeg_audio_mode",
 154                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 155         },{
 156                 .strid = "mpeg_audio_mode_extension",
 157                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 158         },{
 159                 .strid = "audio_emphasis",
 160                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 161         },{
 162                 .strid = "audio_crc",
 163                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 164         },{
 165                 .strid = "video_aspect",
 166                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 167         },{
 168                 .strid = "video_b_frames",
 169                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 170         },{
 171                 .strid = "video_gop_size",
 172                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 173         },{
 174                 .strid = "video_gop_closure",
 175                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 176         },{
 177                 .strid = "video_bitrate_mode",
 178                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 179         },{
 180                 .strid = "video_bitrate",
 181                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 182         },{
 183                 .strid = "video_bitrate_peak",
 184                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 185         },{
 186                 .strid = "video_temporal_decimation",
 187                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 188         },{
 189                 .strid = "stream_type",
 190                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 191         },{
 192                 .strid = "video_spatial_filter_mode",
 193                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 194         },{
 195                 .strid = "video_spatial_filter",
 196                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 197         },{
 198                 .strid = "video_luma_spatial_filter_type",
 199                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 200         },{
 201                 .strid = "video_chroma_spatial_filter_type",
 202                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 203         },{
 204                 .strid = "video_temporal_filter_mode",
 205                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 206         },{
 207                 .strid = "video_temporal_filter",
 208                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 209         },{
 210                 .strid = "video_median_filter_type",
 211                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 212         },{
 213                 .strid = "video_luma_median_filter_top",
 214                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 215         },{
 216                 .strid = "video_luma_median_filter_bottom",
 217                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 218         },{
 219                 .strid = "video_chroma_median_filter_top",
 220                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 221         },{
 222                 .strid = "video_chroma_median_filter_bottom",
 223                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 224         }
 225 };
 226 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 227
 228
 229 static const char *control_values_srate[] = {
 230         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 231         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 232         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 233 };
 234
 235
 236
 237 static const char *control_values_input[] = {
 238         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 239         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 240         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 241         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 242         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 243 };
 244
 245
 246 static const char *control_values_audiomode[] = {
 247         [V4L2_TUNER_MODE_MONO]   = "Mono",
 248         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 249         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 250         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 251         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 252 };
 253
 254
 255 static const char *control_values_hsm[] = {
 256         [PVR2_CVAL_HSM_FAIL] = "Fail",
 257         [PVR2_CVAL_HSM_HIGH] = "High",
 258         [PVR2_CVAL_HSM_FULL] = "Full",
 259 };
 260
 261
 262 static const char *pvr2_state_names[] = {
 263         [PVR2_STATE_NONE] =    "none",
 264         [PVR2_STATE_DEAD] =    "dead",
 265         [PVR2_STATE_COLD] =    "cold",
 266         [PVR2_STATE_WARM] =    "warm",
 267         [PVR2_STATE_ERROR] =   "error",
 268         [PVR2_STATE_READY] =   "ready",
 269         [PVR2_STATE_RUN] =     "run",
 270 };
 271
 272
 273 struct pvr2_fx2cmd_descdef {
 274         unsigned char id;
 275         unsigned char *desc;
 276 };
 277
 278 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 279         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 280         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 281         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 282         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 283         {FX2CMD_REG_WRITE, "write encoder register"},
 284         {FX2CMD_REG_READ, "read encoder register"},
 285         {FX2CMD_MEMSEL, "encoder memsel"},
 286         {FX2CMD_I2C_WRITE, "i2c write"},
 287         {FX2CMD_I2C_READ, "i2c read"},
 288         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 289         {FX2CMD_STREAMING_ON, "stream on"},
 290         {FX2CMD_STREAMING_OFF, "stream off"},
 291         {FX2CMD_FWPOST1, "fwpost1"},
 292         {FX2CMD_POWER_OFF, "power off"},
 293         {FX2CMD_POWER_ON, "power on"},
 294         {FX2CMD_DEEP_RESET, "deep reset"},
 295         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 296         {FX2CMD_GET_IR_CODE, "get IR code"},
 297         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 298         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 299         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 300         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 301         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 302         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 303         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 304 };
 305
 306
 307 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 308 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 309 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 310 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 311 static void pvr2_hdw_worker_i2c(struct work_struct *work);
 312 static void pvr2_hdw_worker_poll(struct work_struct *work);
 313 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 314 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 315 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 316 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 317 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 318 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 319 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 320 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 321 static void pvr2_hdw_quiescent_timeout(unsigned long);
 322 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 323 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 324 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 325 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 326                                 unsigned int timeout,int probe_fl,
 327                                 void *write_data,unsigned int write_len,
 328                                 void *read_data,unsigned int read_len);
 329 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 330
 331
 332 static void trace_stbit(const char *name,int val)
 333 {
 334         pvr2_trace(PVR2_TRACE_STBITS,
 335                    "State bit %s <-- %s",
 336                    name,(val ? "true" : "false"));
 337 }
 338
 339 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 340 {
 341         struct pvr2_hdw *hdw = cptr->hdw;
 342         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 343                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 344         } else {
 345                 *vp = 0;
 346         }
 347         return 0;
 348 }
 349
 350 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 351 {
 352         struct pvr2_hdw *hdw = cptr->hdw;
 353         unsigned int slotId = hdw->freqProgSlot;
 354         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 355                 hdw->freqTable[slotId-1] = v;
 356                 /* Handle side effects correctly - if we're tuned to this
 357                    slot, then forgot the slot id relation since the stored
 358                    frequency has been changed. */
 359                 if (hdw->freqSelector) {
 360                         if (hdw->freqSlotRadio == slotId) {
 361                                 hdw->freqSlotRadio = 0;
 362                         }
 363                 } else {
 364                         if (hdw->freqSlotTelevision == slotId) {
 365                                 hdw->freqSlotTelevision = 0;
 366                         }
 367                 }
 368         }
 369         return 0;
 370 }
 371
 372 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 373 {
 374         *vp = cptr->hdw->freqProgSlot;
 375         return 0;
 376 }
 377
 378 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 379 {
 380         struct pvr2_hdw *hdw = cptr->hdw;
 381         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 382                 hdw->freqProgSlot = v;
 383         }
 384         return 0;
 385 }
 386
 387 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 388 {
 389         struct pvr2_hdw *hdw = cptr->hdw;
 390         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 391         return 0;
 392 }
 393
 394 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 395 {
 396         unsigned freq = 0;
 397         struct pvr2_hdw *hdw = cptr->hdw;
 398         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 399         if (slotId > 0) {
 400                 freq = hdw->freqTable[slotId-1];
 401                 if (!freq) return 0;
 402                 pvr2_hdw_set_cur_freq(hdw,freq);
 403         }
 404         if (hdw->freqSelector) {
 405                 hdw->freqSlotRadio = slotId;
 406         } else {
 407                 hdw->freqSlotTelevision = slotId;
 408         }
 409         return 0;
 410 }
 411
 412 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 413 {
 414         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 415         return 0;
 416 }
 417
 418 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 419 {
 420         return cptr->hdw->freqDirty != 0;
 421 }
 422
 423 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 424 {
 425         cptr->hdw->freqDirty = 0;
 426 }
 427
 428 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 429 {
 430         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 431         return 0;
 432 }
 433
 434 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 435 {
 436         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 437         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 438         if (stat != 0) {
 439                 return stat;
 440         }
 441         *left = cap->bounds.left;
 442         return 0;
 443 }
 444
 445 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 446 {
 447         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 448         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 449         if (stat != 0) {
 450                 return stat;
 451         }
 452         *left = cap->bounds.left;
 453         if (cap->bounds.width > cptr->hdw->cropw_val) {
 454                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 455         }
 456         return 0;
 457 }
 458
 459 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 460 {
 461         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 462         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 463         if (stat != 0) {
 464                 return stat;
 465         }
 466         *top = cap->bounds.top;
 467         return 0;
 468 }
 469
 470 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 471 {
 472         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 473         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 474         if (stat != 0) {
 475                 return stat;
 476         }
 477         *top = cap->bounds.top;
 478         if (cap->bounds.height > cptr->hdw->croph_val) {
 479                 *top += cap->bounds.height - cptr->hdw->croph_val;
 480         }
 481         return 0;
 482 }
 483
 484 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
 485 {
 486         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 487         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 488         if (stat != 0) {
 489                 return stat;
 490         }
 491         *val = 0;
 492         if (cap->bounds.width > cptr->hdw->cropl_val) {
 493                 *val = cap->bounds.width - cptr->hdw->cropl_val;
 494         }
 495         return 0;
 496 }
 497
 498 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
 499 {
 500         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 501         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 502         if (stat != 0) {
 503                 return stat;
 504         }
 505         *val = 0;
 506         if (cap->bounds.height > cptr->hdw->cropt_val) {
 507                 *val = cap->bounds.height - cptr->hdw->cropt_val;
 508         }
 509         return 0;
 510 }
 511
 512 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 513 {
 514         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 515         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 516         if (stat != 0) {
 517                 return stat;
 518         }
 519         *val = cap->bounds.left;
 520         return 0;
 521 }
 522
 523 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 524 {
 525         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 526         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 527         if (stat != 0) {
 528                 return stat;
 529         }
 530         *val = cap->bounds.top;
 531         return 0;
 532 }
 533
 534 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 535 {
 536         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 537         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 538         if (stat != 0) {
 539                 return stat;
 540         }
 541         *val = cap->bounds.width;
 542         return 0;
 543 }
 544
 545 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 546 {
 547         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 548         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 549         if (stat != 0) {
 550                 return stat;
 551         }
 552         *val = cap->bounds.height;
 553         return 0;
 554 }
 555
 556 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 557 {
 558         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 559         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 560         if (stat != 0) {
 561                 return stat;
 562         }
 563         *val = cap->defrect.left;
 564         return 0;
 565 }
 566
 567 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 568 {
 569         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 570         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 571         if (stat != 0) {
 572                 return stat;
 573         }
 574         *val = cap->defrect.top;
 575         return 0;
 576 }
 577
 578 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 579 {
 580         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 581         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 582         if (stat != 0) {
 583                 return stat;
 584         }
 585         *val = cap->defrect.width;
 586         return 0;
 587 }
 588
 589 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 590 {
 591         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 592         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 593         if (stat != 0) {
 594                 return stat;
 595         }
 596         *val = cap->defrect.height;
 597         return 0;
 598 }
 599
 600 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 601 {
 602         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 603         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 604         if (stat != 0) {
 605                 return stat;
 606         }
 607         *val = cap->pixelaspect.numerator;
 608         return 0;
 609 }
 610
 611 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 612 {
 613         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 614         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 615         if (stat != 0) {
 616                 return stat;
 617         }
 618         *val = cap->pixelaspect.denominator;
 619         return 0;
 620 }
 621
 622 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 623 {
 624         /* Actual maximum depends on the video standard in effect. */
 625         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 626                 *vp = 480;
 627         } else {
 628                 *vp = 576;
 629         }
 630         return 0;
 631 }
 632
 633 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 634 {
 635         /* Actual minimum depends on device digitizer type. */
 636         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 637                 *vp = 75;
 638         } else {
 639                 *vp = 17;
 640         }
 641         return 0;
 642 }
 643
 644 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 645 {
 646         *vp = cptr->hdw->input_val;
 647         return 0;
 648 }
 649
 650 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 651 {
 652         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 653 }
 654
 655 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 656 {
 657         return pvr2_hdw_set_input(cptr->hdw,v);
 658 }
 659
 660 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 661 {
 662         return cptr->hdw->input_dirty != 0;
 663 }
 664
 665 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 666 {
 667         cptr->hdw->input_dirty = 0;
 668 }
 669
 670
 671 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 672 {
 673         unsigned long fv;
 674         struct pvr2_hdw *hdw = cptr->hdw;
 675         if (hdw->tuner_signal_stale) {
 676                 pvr2_hdw_status_poll(hdw);
 677         }
 678         fv = hdw->tuner_signal_info.rangehigh;
 679         if (!fv) {
 680                 /* Safety fallback */
 681                 *vp = TV_MAX_FREQ;
 682                 return 0;
 683         }
 684         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 685                 fv = (fv * 125) / 2;
 686         } else {
 687                 fv = fv * 62500;
 688         }
 689         *vp = fv;
 690         return 0;
 691 }
 692
 693 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 694 {
 695         unsigned long fv;
 696         struct pvr2_hdw *hdw = cptr->hdw;
 697         if (hdw->tuner_signal_stale) {
 698                 pvr2_hdw_status_poll(hdw);
 699         }
 700         fv = hdw->tuner_signal_info.rangelow;
 701         if (!fv) {
 702                 /* Safety fallback */
 703                 *vp = TV_MIN_FREQ;
 704                 return 0;
 705         }
 706         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 707                 fv = (fv * 125) / 2;
 708         } else {
 709                 fv = fv * 62500;
 710         }
 711         *vp = fv;
 712         return 0;
 713 }
 714
 715 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 716 {
 717         return cptr->hdw->enc_stale != 0;
 718 }
 719
 720 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 721 {
 722         cptr->hdw->enc_stale = 0;
 723         cptr->hdw->enc_unsafe_stale = 0;
 724 }
 725
 726 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 727 {
 728         int ret;
 729         struct v4l2_ext_controls cs;
 730         struct v4l2_ext_control c1;
 731         memset(&cs,0,sizeof(cs));
 732         memset(&c1,0,sizeof(c1));
 733         cs.controls = &c1;
 734         cs.count = 1;
 735         c1.id = cptr->info->v4l_id;
 736         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 737                                 VIDIOC_G_EXT_CTRLS);
 738         if (ret) return ret;
 739         *vp = c1.value;
 740         return 0;
 741 }
 742
 743 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 744 {
 745         int ret;
 746         struct pvr2_hdw *hdw = cptr->hdw;
 747         struct v4l2_ext_controls cs;
 748         struct v4l2_ext_control c1;
 749         memset(&cs,0,sizeof(cs));
 750         memset(&c1,0,sizeof(c1));
 751         cs.controls = &c1;
 752         cs.count = 1;
 753         c1.id = cptr->info->v4l_id;
 754         c1.value = v;
 755         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 756                                 hdw->state_encoder_run, &cs,
 757                                 VIDIOC_S_EXT_CTRLS);
 758         if (ret == -EBUSY) {
 759                 /* Oops.  cx2341x is telling us it's not safe to change
 760                    this control while we're capturing.  Make a note of this
 761                    fact so that the pipeline will be stopped the next time
 762                    controls are committed.  Then go on ahead and store this
 763                    change anyway. */
 764                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 765                                         0, &cs,
 766                                         VIDIOC_S_EXT_CTRLS);
 767                 if (!ret) hdw->enc_unsafe_stale = !0;
 768         }
 769         if (ret) return ret;
 770         hdw->enc_stale = !0;
 771         return 0;
 772 }
 773
 774 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 775 {
 776         struct v4l2_queryctrl qctrl;
 777         struct pvr2_ctl_info *info;
 778         qctrl.id = cptr->info->v4l_id;
 779         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 780         /* Strip out the const so we can adjust a function pointer.  It's
 781            OK to do this here because we know this is a dynamically created
 782            control, so the underlying storage for the info pointer is (a)
 783            private to us, and (b) not in read-only storage.  Either we do
 784            this or we significantly complicate the underlying control
 785            implementation. */
 786         info = (struct pvr2_ctl_info *)(cptr->info);
 787         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 788                 if (info->set_value) {
 789                         info->set_value = NULL;
 790                 }
 791         } else {
 792                 if (!(info->set_value)) {
 793                         info->set_value = ctrl_cx2341x_set;
 794                 }
 795         }
 796         return qctrl.flags;
 797 }
 798
 799 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 800 {
 801         *vp = cptr->hdw->state_pipeline_req;
 802         return 0;
 803 }
 804
 805 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 806 {
 807         *vp = cptr->hdw->master_state;
 808         return 0;
 809 }
 810
 811 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 812 {
 813         int result = pvr2_hdw_is_hsm(cptr->hdw);
 814         *vp = PVR2_CVAL_HSM_FULL;
 815         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 816         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 817         return 0;
 818 }
 819
 820 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 821 {
 822         *vp = cptr->hdw->std_mask_avail;
 823         return 0;
 824 }
 825
 826 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 827 {
 828         struct pvr2_hdw *hdw = cptr->hdw;
 829         v4l2_std_id ns;
 830         ns = hdw->std_mask_avail;
 831         ns = (ns & ~m) | (v & m);
 832         if (ns == hdw->std_mask_avail) return 0;
 833         hdw->std_mask_avail = ns;
 834         pvr2_hdw_internal_set_std_avail(hdw);
 835         pvr2_hdw_internal_find_stdenum(hdw);
 836         return 0;
 837 }
 838
 839 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 840                                char *bufPtr,unsigned int bufSize,
 841                                unsigned int *len)
 842 {
 843         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 844         return 0;
 845 }
 846
 847 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 848                                const char *bufPtr,unsigned int bufSize,
 849                                int *mskp,int *valp)
 850 {
 851         int ret;
 852         v4l2_std_id id;
 853         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 854         if (ret < 0) return ret;
 855         if (mskp) *mskp = id;
 856         if (valp) *valp = id;
 857         return 0;
 858 }
 859
 860 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 861 {
 862         *vp = cptr->hdw->std_mask_cur;
 863         return 0;
 864 }
 865
 866 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 867 {
 868         struct pvr2_hdw *hdw = cptr->hdw;
 869         v4l2_std_id ns;
 870         ns = hdw->std_mask_cur;
 871         ns = (ns & ~m) | (v & m);
 872         if (ns == hdw->std_mask_cur) return 0;
 873         hdw->std_mask_cur = ns;
 874         hdw->std_dirty = !0;
 875         pvr2_hdw_internal_find_stdenum(hdw);
 876         return 0;
 877 }
 878
 879 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 880 {
 881         return cptr->hdw->std_dirty != 0;
 882 }
 883
 884 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 885 {
 886         cptr->hdw->std_dirty = 0;
 887 }
 888
 889 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 890 {
 891         struct pvr2_hdw *hdw = cptr->hdw;
 892         pvr2_hdw_status_poll(hdw);
 893         *vp = hdw->tuner_signal_info.signal;
 894         return 0;
 895 }
 896
 897 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 898 {
 899         int val = 0;
 900         unsigned int subchan;
 901         struct pvr2_hdw *hdw = cptr->hdw;
 902         pvr2_hdw_status_poll(hdw);
 903         subchan = hdw->tuner_signal_info.rxsubchans;
 904         if (subchan & V4L2_TUNER_SUB_MONO) {
 905                 val |= (1 << V4L2_TUNER_MODE_MONO);
 906         }
 907         if (subchan & V4L2_TUNER_SUB_STEREO) {
 908                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 909         }
 910         if (subchan & V4L2_TUNER_SUB_LANG1) {
 911                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 912         }
 913         if (subchan & V4L2_TUNER_SUB_LANG2) {
 914                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 915         }
 916         *vp = val;
 917         return 0;
 918 }
 919
 920
 921 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 922 {
 923         struct pvr2_hdw *hdw = cptr->hdw;
 924         if (v < 0) return -EINVAL;
 925         if (v > hdw->std_enum_cnt) return -EINVAL;
 926         hdw->std_enum_cur = v;
 927         if (!v) return 0;
 928         v--;
 929         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 930         hdw->std_mask_cur = hdw->std_defs[v].id;
 931         hdw->std_dirty = !0;
 932         return 0;
 933 }
 934
 935
 936 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 937 {
 938         *vp = cptr->hdw->std_enum_cur;
 939         return 0;
 940 }
 941
 942
 943 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 944 {
 945         return cptr->hdw->std_dirty != 0;
 946 }
 947
 948
 949 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 950 {
 951         cptr->hdw->std_dirty = 0;
 952 }
 953
 954
 955 #define DEFINT(vmin,vmax) \
 956         .type = pvr2_ctl_int, \
 957         .def.type_int.min_value = vmin, \
 958         .def.type_int.max_value = vmax
 959
 960 #define DEFENUM(tab) \
 961         .type = pvr2_ctl_enum, \
 962         .def.type_enum.count = ARRAY_SIZE(tab), \
 963         .def.type_enum.value_names = tab
 964
 965 #define DEFBOOL \
 966         .type = pvr2_ctl_bool
 967
 968 #define DEFMASK(msk,tab) \
 969         .type = pvr2_ctl_bitmask, \
 970         .def.type_bitmask.valid_bits = msk, \
 971         .def.type_bitmask.bit_names = tab
 972
 973 #define DEFREF(vname) \
 974         .set_value = ctrl_set_##vname, \
 975         .get_value = ctrl_get_##vname, \
 976         .is_dirty = ctrl_isdirty_##vname, \
 977         .clear_dirty = ctrl_cleardirty_##vname
 978
 979
 980 #define VCREATE_FUNCS(vname) \
 981 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 982 {*vp = cptr->hdw->vname##_val; return 0;} \
 983 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 984 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 985 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 986 {return cptr->hdw->vname##_dirty != 0;} \
 987 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 988 {cptr->hdw->vname##_dirty = 0;}
 989
 990 VCREATE_FUNCS(brightness)
 991 VCREATE_FUNCS(contrast)
 992 VCREATE_FUNCS(saturation)
 993 VCREATE_FUNCS(hue)
 994 VCREATE_FUNCS(volume)
 995 VCREATE_FUNCS(balance)
 996 VCREATE_FUNCS(bass)
 997 VCREATE_FUNCS(treble)
 998 VCREATE_FUNCS(mute)
 999 VCREATE_FUNCS(cropl)
1000 VCREATE_FUNCS(cropt)
1001 VCREATE_FUNCS(cropw)
1002 VCREATE_FUNCS(croph)
1003 VCREATE_FUNCS(audiomode)
1004 VCREATE_FUNCS(res_hor)
1005 VCREATE_FUNCS(res_ver)
1006 VCREATE_FUNCS(srate)
1007
1008 /* Table definition of all controls which can be manipulated */
1009 static const struct pvr2_ctl_info control_defs[] = {
1010         {
1011                 .v4l_id = V4L2_CID_BRIGHTNESS,
1012                 .desc = "Brightness",
1013                 .name = "brightness",
1014                 .default_value = 128,
1015                 DEFREF(brightness),
1016                 DEFINT(0,255),
1017         },{
1018                 .v4l_id = V4L2_CID_CONTRAST,
1019                 .desc = "Contrast",
1020                 .name = "contrast",
1021                 .default_value = 68,
1022                 DEFREF(contrast),
1023                 DEFINT(0,127),
1024         },{
1025                 .v4l_id = V4L2_CID_SATURATION,
1026                 .desc = "Saturation",
1027                 .name = "saturation",
1028                 .default_value = 64,
1029                 DEFREF(saturation),
1030                 DEFINT(0,127),
1031         },{
1032                 .v4l_id = V4L2_CID_HUE,
1033                 .desc = "Hue",
1034                 .name = "hue",
1035                 .default_value = 0,
1036                 DEFREF(hue),
1037                 DEFINT(-128,127),
1038         },{
1039                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1040                 .desc = "Volume",
1041                 .name = "volume",
1042                 .default_value = 62000,
1043                 DEFREF(volume),
1044                 DEFINT(0,65535),
1045         },{
1046                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1047                 .desc = "Balance",
1048                 .name = "balance",
1049                 .default_value = 0,
1050                 DEFREF(balance),
1051                 DEFINT(-32768,32767),
1052         },{
1053                 .v4l_id = V4L2_CID_AUDIO_BASS,
1054                 .desc = "Bass",
1055                 .name = "bass",
1056                 .default_value = 0,
1057                 DEFREF(bass),
1058                 DEFINT(-32768,32767),
1059         },{
1060                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1061                 .desc = "Treble",
1062                 .name = "treble",
1063                 .default_value = 0,
1064                 DEFREF(treble),
1065                 DEFINT(-32768,32767),
1066         },{
1067                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1068                 .desc = "Mute",
1069                 .name = "mute",
1070                 .default_value = 0,
1071                 DEFREF(mute),
1072                 DEFBOOL,
1073         }, {
1074                 .desc = "Capture crop left margin",
1075                 .name = "crop_left",
1076                 .internal_id = PVR2_CID_CROPL,
1077                 .default_value = 0,
1078                 DEFREF(cropl),
1079                 DEFINT(-129, 340),
1080                 .get_min_value = ctrl_cropl_min_get,
1081                 .get_max_value = ctrl_cropl_max_get,
1082                 .get_def_value = ctrl_get_cropcapdl,
1083         }, {
1084                 .desc = "Capture crop top margin",
1085                 .name = "crop_top",
1086                 .internal_id = PVR2_CID_CROPT,
1087                 .default_value = 0,
1088                 DEFREF(cropt),
1089                 DEFINT(-35, 544),
1090                 .get_min_value = ctrl_cropt_min_get,
1091                 .get_max_value = ctrl_cropt_max_get,
1092                 .get_def_value = ctrl_get_cropcapdt,
1093         }, {
1094                 .desc = "Capture crop width",
1095                 .name = "crop_width",
1096                 .internal_id = PVR2_CID_CROPW,
1097                 .default_value = 720,
1098                 DEFREF(cropw),
1099                 .get_max_value = ctrl_cropw_max_get,
1100                 .get_def_value = ctrl_get_cropcapdw,
1101         }, {
1102                 .desc = "Capture crop height",
1103                 .name = "crop_height",
1104                 .internal_id = PVR2_CID_CROPH,
1105                 .default_value = 480,
1106                 DEFREF(croph),
1107                 .get_max_value = ctrl_croph_max_get,
1108                 .get_def_value = ctrl_get_cropcapdh,
1109         }, {
1110                 .desc = "Capture capability pixel aspect numerator",
1111                 .name = "cropcap_pixel_numerator",
1112                 .internal_id = PVR2_CID_CROPCAPPAN,
1113                 .get_value = ctrl_get_cropcappan,
1114         }, {
1115                 .desc = "Capture capability pixel aspect denominator",
1116                 .name = "cropcap_pixel_denominator",
1117                 .internal_id = PVR2_CID_CROPCAPPAD,
1118                 .get_value = ctrl_get_cropcappad,
1119         }, {
1120                 .desc = "Capture capability bounds top",
1121                 .name = "cropcap_bounds_top",
1122                 .internal_id = PVR2_CID_CROPCAPBT,
1123                 .get_value = ctrl_get_cropcapbt,
1124         }, {
1125                 .desc = "Capture capability bounds left",
1126                 .name = "cropcap_bounds_left",
1127                 .internal_id = PVR2_CID_CROPCAPBL,
1128                 .get_value = ctrl_get_cropcapbl,
1129         }, {
1130                 .desc = "Capture capability bounds width",
1131                 .name = "cropcap_bounds_width",
1132                 .internal_id = PVR2_CID_CROPCAPBW,
1133                 .get_value = ctrl_get_cropcapbw,
1134         }, {
1135                 .desc = "Capture capability bounds height",
1136                 .name = "cropcap_bounds_height",
1137                 .internal_id = PVR2_CID_CROPCAPBH,
1138                 .get_value = ctrl_get_cropcapbh,
1139         },{
1140                 .desc = "Video Source",
1141                 .name = "input",
1142                 .internal_id = PVR2_CID_INPUT,
1143                 .default_value = PVR2_CVAL_INPUT_TV,
1144                 .check_value = ctrl_check_input,
1145                 DEFREF(input),
1146                 DEFENUM(control_values_input),
1147         },{
1148                 .desc = "Audio Mode",
1149                 .name = "audio_mode",
1150                 .internal_id = PVR2_CID_AUDIOMODE,
1151                 .default_value = V4L2_TUNER_MODE_STEREO,
1152                 DEFREF(audiomode),
1153                 DEFENUM(control_values_audiomode),
1154         },{
1155                 .desc = "Horizontal capture resolution",
1156                 .name = "resolution_hor",
1157                 .internal_id = PVR2_CID_HRES,
1158                 .default_value = 720,
1159                 DEFREF(res_hor),
1160                 DEFINT(19,720),
1161         },{
1162                 .desc = "Vertical capture resolution",
1163                 .name = "resolution_ver",
1164                 .internal_id = PVR2_CID_VRES,
1165                 .default_value = 480,
1166                 DEFREF(res_ver),
1167                 DEFINT(17,576),
1168                 /* Hook in check for video standard and adjust maximum
1169                    depending on the standard. */
1170                 .get_max_value = ctrl_vres_max_get,
1171                 .get_min_value = ctrl_vres_min_get,
1172         },{
1173                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1174                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1175                 .desc = "Audio Sampling Frequency",
1176                 .name = "srate",
1177                 DEFREF(srate),
1178                 DEFENUM(control_values_srate),
1179         },{
1180                 .desc = "Tuner Frequency (Hz)",
1181                 .name = "frequency",
1182                 .internal_id = PVR2_CID_FREQUENCY,
1183                 .default_value = 0,
1184                 .set_value = ctrl_freq_set,
1185                 .get_value = ctrl_freq_get,
1186                 .is_dirty = ctrl_freq_is_dirty,
1187                 .clear_dirty = ctrl_freq_clear_dirty,
1188                 DEFINT(0,0),
1189                 /* Hook in check for input value (tv/radio) and adjust
1190                    max/min values accordingly */
1191                 .get_max_value = ctrl_freq_max_get,
1192                 .get_min_value = ctrl_freq_min_get,
1193         },{
1194                 .desc = "Channel",
1195                 .name = "channel",
1196                 .set_value = ctrl_channel_set,
1197                 .get_value = ctrl_channel_get,
1198                 DEFINT(0,FREQTABLE_SIZE),
1199         },{
1200                 .desc = "Channel Program Frequency",
1201                 .name = "freq_table_value",
1202                 .set_value = ctrl_channelfreq_set,
1203                 .get_value = ctrl_channelfreq_get,
1204                 DEFINT(0,0),
1205                 /* Hook in check for input value (tv/radio) and adjust
1206                    max/min values accordingly */
1207                 .get_max_value = ctrl_freq_max_get,
1208                 .get_min_value = ctrl_freq_min_get,
1209         },{
1210                 .desc = "Channel Program ID",
1211                 .name = "freq_table_channel",
1212                 .set_value = ctrl_channelprog_set,
1213                 .get_value = ctrl_channelprog_get,
1214                 DEFINT(0,FREQTABLE_SIZE),
1215         },{
1216                 .desc = "Streaming Enabled",
1217                 .name = "streaming_enabled",
1218                 .get_value = ctrl_streamingenabled_get,
1219                 DEFBOOL,
1220         },{
1221                 .desc = "USB Speed",
1222                 .name = "usb_speed",
1223                 .get_value = ctrl_hsm_get,
1224                 DEFENUM(control_values_hsm),
1225         },{
1226                 .desc = "Master State",
1227                 .name = "master_state",
1228                 .get_value = ctrl_masterstate_get,
1229                 DEFENUM(pvr2_state_names),
1230         },{
1231                 .desc = "Signal Present",
1232                 .name = "signal_present",
1233                 .get_value = ctrl_signal_get,
1234                 DEFINT(0,65535),
1235         },{
1236                 .desc = "Audio Modes Present",
1237                 .name = "audio_modes_present",
1238                 .get_value = ctrl_audio_modes_present_get,
1239                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1240                    v4l.  Nothing outside of this module cares about this,
1241                    but I reuse it in order to also reuse the
1242                    control_values_audiomode string table. */
1243                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1244                          (1 << V4L2_TUNER_MODE_STEREO)|
1245                          (1 << V4L2_TUNER_MODE_LANG1)|
1246                          (1 << V4L2_TUNER_MODE_LANG2)),
1247                         control_values_audiomode),
1248         },{
1249                 .desc = "Video Standards Available Mask",
1250                 .name = "video_standard_mask_available",
1251                 .internal_id = PVR2_CID_STDAVAIL,
1252                 .skip_init = !0,
1253                 .get_value = ctrl_stdavail_get,
1254                 .set_value = ctrl_stdavail_set,
1255                 .val_to_sym = ctrl_std_val_to_sym,
1256                 .sym_to_val = ctrl_std_sym_to_val,
1257                 .type = pvr2_ctl_bitmask,
1258         },{
1259                 .desc = "Video Standards In Use Mask",
1260                 .name = "video_standard_mask_active",
1261                 .internal_id = PVR2_CID_STDCUR,
1262                 .skip_init = !0,
1263                 .get_value = ctrl_stdcur_get,
1264                 .set_value = ctrl_stdcur_set,
1265                 .is_dirty = ctrl_stdcur_is_dirty,
1266                 .clear_dirty = ctrl_stdcur_clear_dirty,
1267                 .val_to_sym = ctrl_std_val_to_sym,
1268                 .sym_to_val = ctrl_std_sym_to_val,
1269                 .type = pvr2_ctl_bitmask,
1270         },{
1271                 .desc = "Video Standard Name",
1272                 .name = "video_standard",
1273                 .internal_id = PVR2_CID_STDENUM,
1274                 .skip_init = !0,
1275                 .get_value = ctrl_stdenumcur_get,
1276                 .set_value = ctrl_stdenumcur_set,
1277                 .is_dirty = ctrl_stdenumcur_is_dirty,
1278                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1279                 .type = pvr2_ctl_enum,
1280         }
1281 };
1282
1283 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1284
1285
1286 const char *pvr2_config_get_name(enum pvr2_config cfg)
1287 {
1288         switch (cfg) {
1289         case pvr2_config_empty: return "empty";
1290         case pvr2_config_mpeg: return "mpeg";
1291         case pvr2_config_vbi: return "vbi";
1292         case pvr2_config_pcm: return "pcm";
1293         case pvr2_config_rawvideo: return "raw video";
1294         }
1295         return "<unknown>";
1296 }
1297
1298
1299 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1300 {
1301         return hdw->usb_dev;
1302 }
1303
1304
1305 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1306 {
1307         return hdw->serial_number;
1308 }
1309
1310
1311 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1312 {
1313         return hdw->bus_info;
1314 }
1315
1316
1317 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1318 {
1319         return hdw->identifier;
1320 }
1321
1322
1323 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1324 {
1325         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1326 }
1327
1328 /* Set the currently tuned frequency and account for all possible
1329    driver-core side effects of this action. */
1330 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1331 {
1332         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1333                 if (hdw->freqSelector) {
1334                         /* Swing over to radio frequency selection */
1335                         hdw->freqSelector = 0;
1336                         hdw->freqDirty = !0;
1337                 }
1338                 if (hdw->freqValRadio != val) {
1339                         hdw->freqValRadio = val;
1340                         hdw->freqSlotRadio = 0;
1341                         hdw->freqDirty = !0;
1342                 }
1343         } else {
1344                 if (!(hdw->freqSelector)) {
1345                         /* Swing over to television frequency selection */
1346                         hdw->freqSelector = 1;
1347                         hdw->freqDirty = !0;
1348                 }
1349                 if (hdw->freqValTelevision != val) {
1350                         hdw->freqValTelevision = val;
1351                         hdw->freqSlotTelevision = 0;
1352                         hdw->freqDirty = !0;
1353                 }
1354         }
1355 }
1356
1357 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1358 {
1359         return hdw->unit_number;
1360 }
1361
1362
1363 /* Attempt to locate one of the given set of files.  Messages are logged
1364    appropriate to what has been found.  The return value will be 0 or
1365    greater on success (it will be the index of the file name found) and
1366    fw_entry will be filled in.  Otherwise a negative error is returned on
1367    failure.  If the return value is -ENOENT then no viable firmware file
1368    could be located. */
1369 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1370                                 const struct firmware **fw_entry,
1371                                 const char *fwtypename,
1372                                 unsigned int fwcount,
1373                                 const char *fwnames[])
1374 {
1375         unsigned int idx;
1376         int ret = -EINVAL;
1377         for (idx = 0; idx < fwcount; idx++) {
1378                 ret = request_firmware(fw_entry,
1379                                        fwnames[idx],
1380                                        &hdw->usb_dev->dev);
1381                 if (!ret) {
1382                         trace_firmware("Located %s firmware: %s;"
1383                                        " uploading...",
1384                                        fwtypename,
1385                                        fwnames[idx]);
1386                         return idx;
1387                 }
1388                 if (ret == -ENOENT) continue;
1389                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1390                            "request_firmware fatal error with code=%d",ret);
1391                 return ret;
1392         }
1393         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1394                    "***WARNING***"
1395                    " Device %s firmware"
1396                    " seems to be missing.",
1397                    fwtypename);
1398         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1399                    "Did you install the pvrusb2 firmware files"
1400                    " in their proper location?");
1401         if (fwcount == 1) {
1402                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1403                            "request_firmware unable to locate %s file %s",
1404                            fwtypename,fwnames[0]);
1405         } else {
1406                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1407                            "request_firmware unable to locate"
1408                            " one of the following %s files:",
1409                            fwtypename);
1410                 for (idx = 0; idx < fwcount; idx++) {
1411                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1412                                    "request_firmware: Failed to find %s",
1413                                    fwnames[idx]);
1414                 }
1415         }
1416         return ret;
1417 }
1418
1419
1420 /*
1421  * pvr2_upload_firmware1().
1422  *
1423  * Send the 8051 firmware to the device.  After the upload, arrange for
1424  * device to re-enumerate.
1425  *
1426  * NOTE : the pointer to the firmware data given by request_firmware()
1427  * is not suitable for an usb transaction.
1428  *
1429  */
1430 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1431 {
1432         const struct firmware *fw_entry = NULL;
1433         void  *fw_ptr;
1434         unsigned int pipe;
1435         int ret;
1436         u16 address;
1437
1438         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1439                 hdw->fw1_state = FW1_STATE_OK;
1440                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1441                            "Connected device type defines"
1442                            " no firmware to upload; ignoring firmware");
1443                 return -ENOTTY;
1444         }
1445
1446         hdw->fw1_state = FW1_STATE_FAILED; // default result
1447
1448         trace_firmware("pvr2_upload_firmware1");
1449
1450         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1451                                    hdw->hdw_desc->fx2_firmware.cnt,
1452                                    hdw->hdw_desc->fx2_firmware.lst);
1453         if (ret < 0) {
1454                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1455                 return ret;
1456         }
1457
1458         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1459         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1460
1461         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1462
1463         if (fw_entry->size != 0x2000){
1464                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1465                 release_firmware(fw_entry);
1466                 return -ENOMEM;
1467         }
1468
1469         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1470         if (fw_ptr == NULL){
1471                 release_firmware(fw_entry);
1472                 return -ENOMEM;
1473         }
1474
1475         /* We have to hold the CPU during firmware upload. */
1476         pvr2_hdw_cpureset_assert(hdw,1);
1477
1478         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1479            chunk. */
1480
1481         ret = 0;
1482         for(address = 0; address < fw_entry->size; address += 0x800) {
1483                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1484                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1485                                        0, fw_ptr, 0x800, HZ);
1486         }
1487
1488         trace_firmware("Upload done, releasing device's CPU");
1489
1490         /* Now release the CPU.  It will disconnect and reconnect later. */
1491         pvr2_hdw_cpureset_assert(hdw,0);
1492
1493         kfree(fw_ptr);
1494         release_firmware(fw_entry);
1495
1496         trace_firmware("Upload done (%d bytes sent)",ret);
1497
1498         /* We should have written 8192 bytes */
1499         if (ret == 8192) {
1500                 hdw->fw1_state = FW1_STATE_RELOAD;
1501                 return 0;
1502         }
1503
1504         return -EIO;
1505 }
1506
1507
1508 /*
1509  * pvr2_upload_firmware2()
1510  *
1511  * This uploads encoder firmware on endpoint 2.
1512  *
1513  */
1514
1515 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1516 {
1517         const struct firmware *fw_entry = NULL;
1518         void  *fw_ptr;
1519         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1520         int actual_length;
1521         int ret = 0;
1522         int fwidx;
1523         static const char *fw_files[] = {
1524                 CX2341X_FIRM_ENC_FILENAME,
1525         };
1526
1527         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1528                 return 0;
1529         }
1530
1531         trace_firmware("pvr2_upload_firmware2");
1532
1533         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1534                                    ARRAY_SIZE(fw_files), fw_files);
1535         if (ret < 0) return ret;
1536         fwidx = ret;
1537         ret = 0;
1538         /* Since we're about to completely reinitialize the encoder,
1539            invalidate our cached copy of its configuration state.  Next
1540            time we configure the encoder, then we'll fully configure it. */
1541         hdw->enc_cur_valid = 0;
1542
1543         /* Encoder is about to be reset so note that as far as we're
1544            concerned now, the encoder has never been run. */
1545         del_timer_sync(&hdw->encoder_run_timer);
1546         if (hdw->state_encoder_runok) {
1547                 hdw->state_encoder_runok = 0;
1548                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1549         }
1550
1551         /* First prepare firmware loading */
1552         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1553         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1554         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1555         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1556         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1557         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1558         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1559         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1560         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1561         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1562         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1563         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1564         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1565         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1566         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1567         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1568         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1569         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1570
1571         if (ret) {
1572                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1573                            "firmware2 upload prep failed, ret=%d",ret);
1574                 release_firmware(fw_entry);
1575                 goto done;
1576         }
1577
1578         /* Now send firmware */
1579
1580         fw_len = fw_entry->size;
1581
1582         if (fw_len % sizeof(u32)) {
1583                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1584                            "size of %s firmware"
1585                            " must be a multiple of %zu bytes",
1586                            fw_files[fwidx],sizeof(u32));
1587                 release_firmware(fw_entry);
1588                 ret = -EINVAL;
1589                 goto done;
1590         }
1591
1592         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1593         if (fw_ptr == NULL){
1594                 release_firmware(fw_entry);
1595                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1596                            "failed to allocate memory for firmware2 upload");
1597                 ret = -ENOMEM;
1598                 goto done;
1599         }
1600
1601         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1602
1603         fw_done = 0;
1604         for (fw_done = 0; fw_done < fw_len;) {
1605                 bcnt = fw_len - fw_done;
1606                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1607                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1608                 /* Usbsnoop log shows that we must swap bytes... */
1609                 /* Some background info: The data being swapped here is a
1610                    firmware image destined for the mpeg encoder chip that
1611                    lives at the other end of a USB endpoint.  The encoder
1612                    chip always talks in 32 bit chunks and its storage is
1613                    organized into 32 bit words.  However from the file
1614                    system to the encoder chip everything is purely a byte
1615                    stream.  The firmware file's contents are always 32 bit
1616                    swapped from what the encoder expects.  Thus the need
1617                    always exists to swap the bytes regardless of the endian
1618                    type of the host processor and therefore swab32() makes
1619                    the most sense. */
1620                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1621                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1622
1623                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1624                                     &actual_length, HZ);
1625                 ret |= (actual_length != bcnt);
1626                 if (ret) break;
1627                 fw_done += bcnt;
1628         }
1629
1630         trace_firmware("upload of %s : %i / %i ",
1631                        fw_files[fwidx],fw_done,fw_len);
1632
1633         kfree(fw_ptr);
1634         release_firmware(fw_entry);
1635
1636         if (ret) {
1637                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1638                            "firmware2 upload transfer failure");
1639                 goto done;
1640         }
1641
1642         /* Finish upload */
1643
1644         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1645         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1646         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1647
1648         if (ret) {
1649                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1650                            "firmware2 upload post-proc failure");
1651         }
1652
1653  done:
1654         if (hdw->hdw_desc->signal_routing_scheme ==
1655             PVR2_ROUTING_SCHEME_GOTVIEW) {
1656                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1657                    hardware. */
1658                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1659         }
1660         return ret;
1661 }
1662
1663
1664 static const char *pvr2_get_state_name(unsigned int st)
1665 {
1666         if (st < ARRAY_SIZE(pvr2_state_names)) {
1667                 return pvr2_state_names[st];
1668         }
1669         return "???";
1670 }
1671
1672 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1673 {
1674         if (hdw->decoder_ctrl) {
1675                 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt, enablefl);
1676                 return 0;
1677         }
1678         /* Even though we really only care about the video decoder chip at
1679            this point, we'll broadcast stream on/off to all sub-devices
1680            anyway, just in case somebody else wants to hear the
1681            command... */
1682         v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1683         if (hdw->decoder_client_id) {
1684                 /* We get here if the encoder has been noticed.  Otherwise
1685                    we'll issue a warning to the user (which should
1686                    normally never happen). */
1687                 return 0;
1688         }
1689         if (!hdw->flag_decoder_missed) {
1690                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1691                            "WARNING: No decoder present");
1692                 hdw->flag_decoder_missed = !0;
1693                 trace_stbit("flag_decoder_missed",
1694                             hdw->flag_decoder_missed);
1695         }
1696         return -EIO;
1697 }
1698
1699
1700 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1701 {
1702         if (hdw->decoder_ctrl == ptr) return;
1703         hdw->decoder_ctrl = ptr;
1704         if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1705                 hdw->flag_decoder_missed = 0;
1706                 trace_stbit("flag_decoder_missed",
1707                             hdw->flag_decoder_missed);
1708                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1709                            "Decoder has appeared");
1710                 pvr2_hdw_state_sched(hdw);
1711         }
1712 }
1713
1714
1715 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1716 {
1717         return hdw->master_state;
1718 }
1719
1720
1721 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1722 {
1723         if (!hdw->flag_tripped) return 0;
1724         hdw->flag_tripped = 0;
1725         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1726                    "Clearing driver error statuss");
1727         return !0;
1728 }
1729
1730
1731 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1732 {
1733         int fl;
1734         LOCK_TAKE(hdw->big_lock); do {
1735                 fl = pvr2_hdw_untrip_unlocked(hdw);
1736         } while (0); LOCK_GIVE(hdw->big_lock);
1737         if (fl) pvr2_hdw_state_sched(hdw);
1738         return 0;
1739 }
1740
1741
1742
1743
1744 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1745 {
1746         return hdw->state_pipeline_req != 0;
1747 }
1748
1749
1750 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1751 {
1752         int ret,st;
1753         LOCK_TAKE(hdw->big_lock); do {
1754                 pvr2_hdw_untrip_unlocked(hdw);
1755                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1756                         hdw->state_pipeline_req = enable_flag != 0;
1757                         pvr2_trace(PVR2_TRACE_START_STOP,
1758                                    "/*--TRACE_STREAM--*/ %s",
1759                                    enable_flag ? "enable" : "disable");
1760                 }
1761                 pvr2_hdw_state_sched(hdw);
1762         } while (0); LOCK_GIVE(hdw->big_lock);
1763         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1764         if (enable_flag) {
1765                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1766                         if (st != PVR2_STATE_READY) return -EIO;
1767                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1768                 }
1769         }
1770         return 0;
1771 }
1772
1773
1774 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1775 {
1776         int fl;
1777         LOCK_TAKE(hdw->big_lock);
1778         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1779                 hdw->desired_stream_type = config;
1780                 hdw->state_pipeline_config = 0;
1781                 trace_stbit("state_pipeline_config",
1782                             hdw->state_pipeline_config);
1783                 pvr2_hdw_state_sched(hdw);
1784         }
1785         LOCK_GIVE(hdw->big_lock);
1786         if (fl) return 0;
1787         return pvr2_hdw_wait(hdw,0);
1788 }
1789
1790
1791 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1792 {
1793         int unit_number = hdw->unit_number;
1794         int tp = -1;
1795         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1796                 tp = tuner[unit_number];
1797         }
1798         if (tp < 0) return -EINVAL;
1799         hdw->tuner_type = tp;
1800         hdw->tuner_updated = !0;
1801         return 0;
1802 }
1803
1804
1805 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1806 {
1807         int unit_number = hdw->unit_number;
1808         int tp = 0;
1809         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1810                 tp = video_std[unit_number];
1811                 if (tp) return tp;
1812         }
1813         return 0;
1814 }
1815
1816
1817 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1818 {
1819         int unit_number = hdw->unit_number;
1820         int tp = 0;
1821         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1822                 tp = tolerance[unit_number];
1823         }
1824         return tp;
1825 }
1826
1827
1828 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1829 {
1830         /* Try a harmless request to fetch the eeprom's address over
1831            endpoint 1.  See what happens.  Only the full FX2 image can
1832            respond to this.  If this probe fails then likely the FX2
1833            firmware needs be loaded. */
1834         int result;
1835         LOCK_TAKE(hdw->ctl_lock); do {
1836                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1837                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1838                                            hdw->cmd_buffer,1,
1839                                            hdw->cmd_buffer,1);
1840                 if (result < 0) break;
1841         } while(0); LOCK_GIVE(hdw->ctl_lock);
1842         if (result) {
1843                 pvr2_trace(PVR2_TRACE_INIT,
1844                            "Probe of device endpoint 1 result status %d",
1845                            result);
1846         } else {
1847                 pvr2_trace(PVR2_TRACE_INIT,
1848                            "Probe of device endpoint 1 succeeded");
1849         }
1850         return result == 0;
1851 }
1852
1853 struct pvr2_std_hack {
1854         v4l2_std_id pat;  /* Pattern to match */
1855         v4l2_std_id msk;  /* Which bits we care about */
1856         v4l2_std_id std;  /* What additional standards or default to set */
1857 };
1858
1859 /* This data structure labels specific combinations of standards from
1860    tveeprom that we'll try to recognize.  If we recognize one, then assume
1861    a specified default standard to use.  This is here because tveeprom only
1862    tells us about available standards not the intended default standard (if
1863    any) for the device in question.  We guess the default based on what has
1864    been reported as available.  Note that this is only for guessing a
1865    default - which can always be overridden explicitly - and if the user
1866    has otherwise named a default then that default will always be used in
1867    place of this table. */
1868 static const struct pvr2_std_hack std_eeprom_maps[] = {
1869         {       /* PAL(B/G) */
1870                 .pat = V4L2_STD_B|V4L2_STD_GH,
1871                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1872         },
1873         {       /* NTSC(M) */
1874                 .pat = V4L2_STD_MN,
1875                 .std = V4L2_STD_NTSC_M,
1876         },
1877         {       /* PAL(I) */
1878                 .pat = V4L2_STD_PAL_I,
1879                 .std = V4L2_STD_PAL_I,
1880         },
1881         {       /* SECAM(L/L') */
1882                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1883                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1884         },
1885         {       /* PAL(D/D1/K) */
1886                 .pat = V4L2_STD_DK,
1887                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1888         },
1889 };
1890
1891 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1892 {
1893         char buf[40];
1894         unsigned int bcnt;
1895         v4l2_std_id std1,std2,std3;
1896
1897         std1 = get_default_standard(hdw);
1898         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1899
1900         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1901         pvr2_trace(PVR2_TRACE_STD,
1902                    "Supported video standard(s) reported available"
1903                    " in hardware: %.*s",
1904                    bcnt,buf);
1905
1906         hdw->std_mask_avail = hdw->std_mask_eeprom;
1907
1908         std2 = (std1|std3) & ~hdw->std_mask_avail;
1909         if (std2) {
1910                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1911                 pvr2_trace(PVR2_TRACE_STD,
1912                            "Expanding supported video standards"
1913                            " to include: %.*s",
1914                            bcnt,buf);
1915                 hdw->std_mask_avail |= std2;
1916         }
1917
1918         pvr2_hdw_internal_set_std_avail(hdw);
1919
1920         if (std1) {
1921                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1922                 pvr2_trace(PVR2_TRACE_STD,
1923                            "Initial video standard forced to %.*s",
1924                            bcnt,buf);
1925                 hdw->std_mask_cur = std1;
1926                 hdw->std_dirty = !0;
1927                 pvr2_hdw_internal_find_stdenum(hdw);
1928                 return;
1929         }
1930         if (std3) {
1931                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1932                 pvr2_trace(PVR2_TRACE_STD,
1933                            "Initial video standard"
1934                            " (determined by device type): %.*s",bcnt,buf);
1935                 hdw->std_mask_cur = std3;
1936                 hdw->std_dirty = !0;
1937                 pvr2_hdw_internal_find_stdenum(hdw);
1938                 return;
1939         }
1940
1941         {
1942                 unsigned int idx;
1943                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1944                         if (std_eeprom_maps[idx].msk ?
1945                             ((std_eeprom_maps[idx].pat ^
1946                              hdw->std_mask_eeprom) &
1947                              std_eeprom_maps[idx].msk) :
1948                             (std_eeprom_maps[idx].pat !=
1949                              hdw->std_mask_eeprom)) continue;
1950                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1951                                                   std_eeprom_maps[idx].std);
1952                         pvr2_trace(PVR2_TRACE_STD,
1953                                    "Initial video standard guessed as %.*s",
1954                                    bcnt,buf);
1955                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1956                         hdw->std_dirty = !0;
1957                         pvr2_hdw_internal_find_stdenum(hdw);
1958                         return;
1959                 }
1960         }
1961
1962         if (hdw->std_enum_cnt > 1) {
1963                 // Autoselect the first listed standard
1964                 hdw->std_enum_cur = 1;
1965                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1966                 hdw->std_dirty = !0;
1967                 pvr2_trace(PVR2_TRACE_STD,
1968                            "Initial video standard auto-selected to %s",
1969                            hdw->std_defs[hdw->std_enum_cur-1].name);
1970                 return;
1971         }
1972
1973         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1974                    "Unable to select a viable initial video standard");
1975 }
1976
1977
1978 static unsigned int pvr2_copy_i2c_addr_list(
1979         unsigned short *dst, const unsigned char *src,
1980         unsigned int dst_max)
1981 {
1982         unsigned int cnt = 0;
1983         if (!src) return 0;
1984         while (src[cnt] && (cnt + 1) < dst_max) {
1985                 dst[cnt] = src[cnt];
1986                 cnt++;
1987         }
1988         dst[cnt] = I2C_CLIENT_END;
1989         return cnt;
1990 }
1991
1992
1993 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1994                                 const struct pvr2_device_client_desc *cd)
1995 {
1996         const char *fname;
1997         unsigned char mid;
1998         struct v4l2_subdev *sd;
1999         unsigned int i2ccnt;
2000         const unsigned char *p;
2001         /* Arbitrary count - max # i2c addresses we will probe */
2002         unsigned short i2caddr[25];
2003
2004         mid = cd->module_id;
2005         fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2006         if (!fname) {
2007                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2008                            "Module ID %u for device %s has no name",
2009                            mid,
2010                            hdw->hdw_desc->description);
2011                 return -EINVAL;
2012         }
2013         pvr2_trace(PVR2_TRACE_INIT,
2014                    "Module ID %u (%s) for device %s being loaded...",
2015                    mid, fname,
2016                    hdw->hdw_desc->description);
2017
2018         i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2019                                          ARRAY_SIZE(i2caddr));
2020         if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2021                          module_i2c_addresses[mid] : NULL) != NULL)) {
2022                 /* Second chance: Try default i2c address list */
2023                 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2024                                                  ARRAY_SIZE(i2caddr));
2025                 if (i2ccnt) {
2026                         pvr2_trace(PVR2_TRACE_INIT,
2027                                    "Module ID %u:"
2028                                    " Using default i2c address list",
2029                                    mid);
2030                 }
2031         }
2032
2033         if (!i2ccnt) {
2034                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2035                            "Module ID %u (%s) for device %s:"
2036                            " No i2c addresses",
2037                            mid, fname, hdw->hdw_desc->description);
2038                 return -EINVAL;
2039         }
2040
2041         /* Note how the 2nd and 3rd arguments are the same for both
2042          * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev().  Why?
2043          * Well the 2nd argument is the module name to load, while the 3rd
2044          * argument is documented in the framework as being the "chipid" -
2045          * and every other place where I can find examples of this, the
2046          * "chipid" appears to just be the module name again.  So here we
2047          * just do the same thing. */
2048         if (i2ccnt == 1) {
2049                 pvr2_trace(PVR2_TRACE_INIT,
2050                            "Module ID %u:"
2051                            " Setting up with specified i2c address 0x%x",
2052                            mid, i2caddr[0]);
2053                 sd = v4l2_i2c_new_subdev(&hdw->i2c_adap,
2054                                          fname, fname,
2055                                          i2caddr[0]);
2056         } else {
2057                 pvr2_trace(PVR2_TRACE_INIT,
2058                            "Module ID %u:"
2059                            " Setting up with address probe list",
2060                            mid);
2061                 sd = v4l2_i2c_new_probed_subdev(&hdw->i2c_adap,
2062                                                 fname, fname,
2063                                                 i2caddr);
2064         }
2065
2066         if (!sd) {
2067                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2068                            "Module ID %u (%s) for device %s failed to load",
2069                            mid, fname, hdw->hdw_desc->description);
2070                 return -EIO;
2071         }
2072
2073         /* Tag this sub-device instance with the module ID we know about.
2074            In other places we'll use that tag to determine if the instance
2075            requires special handling. */
2076         sd->grp_id = mid;
2077
2078         /* If we have both old and new i2c layers enabled, make sure that
2079            old layer isn't also tracking this module.  This is a debugging
2080            aid, in normal situations there's no reason for both mechanisms
2081            to be enabled. */
2082         pvr2_i2c_untrack_subdev(hdw, sd);
2083         pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2084
2085
2086         /* client-specific setup... */
2087         switch (mid) {
2088         case PVR2_CLIENT_ID_CX25840:
2089                 hdw->decoder_client_id = mid;
2090                 {
2091                         /*
2092                           Mike Isely <isely@pobox.com> 19-Nov-2006 - This
2093                           bit of nuttiness for cx25840 causes that module
2094                           to correctly set up its video scaling.  This is
2095                           really a problem in the cx25840 module itself,
2096                           but we work around it here.  The problem has not
2097                           been seen in ivtv because there VBI is supported
2098                           and set up.  We don't do VBI here (at least not
2099                           yet) and thus we never attempted to even set it
2100                           up.
2101                         */
2102                         struct v4l2_format fmt;
2103                         pvr2_trace(PVR2_TRACE_INIT,
2104                                    "Module ID %u:"
2105                                    " Executing cx25840 VBI hack",
2106                                    mid);
2107                         memset(&fmt, 0, sizeof(fmt));
2108                         fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2109                         v4l2_device_call_all(&hdw->v4l2_dev, mid,
2110                                              video, s_fmt, &fmt);
2111                 }
2112                 break;
2113         case PVR2_CLIENT_ID_SAA7115:
2114                 hdw->decoder_client_id = mid;
2115                 break;
2116         default: break;
2117         }
2118
2119         return 0;
2120 }
2121
2122
2123 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2124 {
2125         unsigned int idx;
2126         const struct pvr2_string_table *cm;
2127         const struct pvr2_device_client_table *ct;
2128         int okFl = !0;
2129
2130         cm = &hdw->hdw_desc->client_modules;
2131         for (idx = 0; idx < cm->cnt; idx++) {
2132                 request_module(cm->lst[idx]);
2133         }
2134
2135         ct = &hdw->hdw_desc->client_table;
2136         for (idx = 0; idx < ct->cnt; idx++) {
2137                 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2138         }
2139         if (!okFl) pvr2_hdw_render_useless(hdw);
2140 }
2141
2142
2143 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2144 {
2145         int ret;
2146         unsigned int idx;
2147         struct pvr2_ctrl *cptr;
2148         int reloadFl = 0;
2149         if (hdw->hdw_desc->fx2_firmware.cnt) {
2150                 if (!reloadFl) {
2151                         reloadFl =
2152                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2153                                  == 0);
2154                         if (reloadFl) {
2155                                 pvr2_trace(PVR2_TRACE_INIT,
2156                                            "USB endpoint config looks strange"
2157                                            "; possibly firmware needs to be"
2158                                            " loaded");
2159                         }
2160                 }
2161                 if (!reloadFl) {
2162                         reloadFl = !pvr2_hdw_check_firmware(hdw);
2163                         if (reloadFl) {
2164                                 pvr2_trace(PVR2_TRACE_INIT,
2165                                            "Check for FX2 firmware failed"
2166                                            "; possibly firmware needs to be"
2167                                            " loaded");
2168                         }
2169                 }
2170                 if (reloadFl) {
2171                         if (pvr2_upload_firmware1(hdw) != 0) {
2172                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2173                                            "Failure uploading firmware1");
2174                         }
2175                         return;
2176                 }
2177         }
2178         hdw->fw1_state = FW1_STATE_OK;
2179
2180         if (!pvr2_hdw_dev_ok(hdw)) return;
2181
2182         if (!hdw->hdw_desc->flag_no_powerup) {
2183                 pvr2_hdw_cmd_powerup(hdw);
2184                 if (!pvr2_hdw_dev_ok(hdw)) return;
2185         }
2186
2187         /* Take the IR chip out of reset, if appropriate */
2188         if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
2189                 pvr2_issue_simple_cmd(hdw,
2190                                       FX2CMD_HCW_ZILOG_RESET |
2191                                       (1 << 8) |
2192                                       ((0) << 16));
2193         }
2194
2195         // This step MUST happen after the earlier powerup step.
2196         pvr2_i2c_track_init(hdw);
2197         pvr2_i2c_core_init(hdw);
2198         if (!pvr2_hdw_dev_ok(hdw)) return;
2199
2200         pvr2_hdw_load_modules(hdw);
2201         if (!pvr2_hdw_dev_ok(hdw)) return;
2202
2203         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2204                 cptr = hdw->controls + idx;
2205                 if (cptr->info->skip_init) continue;
2206                 if (!cptr->info->set_value) continue;
2207                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2208         }
2209
2210         /* Set up special default values for the television and radio
2211            frequencies here.  It's not really important what these defaults
2212            are, but I set them to something usable in the Chicago area just
2213            to make driver testing a little easier. */
2214
2215         hdw->freqValTelevision = default_tv_freq;
2216         hdw->freqValRadio = default_radio_freq;
2217
2218         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2219         // thread-safe against the normal pvr2_send_request() mechanism.
2220         // (We should make it thread safe).
2221
2222         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2223                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2224                 if (!pvr2_hdw_dev_ok(hdw)) return;
2225                 if (ret < 0) {
2226                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2227                                    "Unable to determine location of eeprom,"
2228                                    " skipping");
2229                 } else {
2230                         hdw->eeprom_addr = ret;
2231                         pvr2_eeprom_analyze(hdw);
2232                         if (!pvr2_hdw_dev_ok(hdw)) return;
2233                 }
2234         } else {
2235                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2236                 hdw->tuner_updated = !0;
2237                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2238         }
2239
2240         if (hdw->serial_number) {
2241                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2242                                 "sn-%lu", hdw->serial_number);
2243         } else if (hdw->unit_number >= 0) {
2244                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2245                                 "unit-%c",
2246                                 hdw->unit_number + 'a');
2247         } else {
2248                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2249                                 "unit-??");
2250         }
2251         hdw->identifier[idx] = 0;
2252
2253         pvr2_hdw_setup_std(hdw);
2254
2255         if (!get_default_tuner_type(hdw)) {
2256                 pvr2_trace(PVR2_TRACE_INIT,
2257                            "pvr2_hdw_setup: Tuner type overridden to %d",
2258                            hdw->tuner_type);
2259         }
2260
2261         pvr2_i2c_core_check_stale(hdw);
2262         hdw->tuner_updated = 0;
2263
2264         if (!pvr2_hdw_dev_ok(hdw)) return;
2265
2266         if (hdw->hdw_desc->signal_routing_scheme ==
2267             PVR2_ROUTING_SCHEME_GOTVIEW) {
2268                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2269                    hardware. */
2270                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2271         }
2272
2273         pvr2_hdw_commit_setup(hdw);
2274
2275         hdw->vid_stream = pvr2_stream_create();
2276         if (!pvr2_hdw_dev_ok(hdw)) return;
2277         pvr2_trace(PVR2_TRACE_INIT,
2278                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2279         if (hdw->vid_stream) {
2280                 idx = get_default_error_tolerance(hdw);
2281                 if (idx) {
2282                         pvr2_trace(PVR2_TRACE_INIT,
2283                                    "pvr2_hdw_setup: video stream %p"
2284                                    " setting tolerance %u",
2285                                    hdw->vid_stream,idx);
2286                 }
2287                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2288                                   PVR2_VID_ENDPOINT,idx);
2289         }
2290
2291         if (!pvr2_hdw_dev_ok(hdw)) return;
2292
2293         hdw->flag_init_ok = !0;
2294
2295         pvr2_hdw_state_sched(hdw);
2296 }
2297
2298
2299 /* Set up the structure and attempt to put the device into a usable state.
2300    This can be a time-consuming operation, which is why it is not done
2301    internally as part of the create() step. */
2302 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2303 {
2304         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2305         do {
2306                 pvr2_hdw_setup_low(hdw);
2307                 pvr2_trace(PVR2_TRACE_INIT,
2308                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2309                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2310                 if (pvr2_hdw_dev_ok(hdw)) {
2311                         if (hdw->flag_init_ok) {
2312                                 pvr2_trace(
2313                                         PVR2_TRACE_INFO,
2314                                         "Device initialization"
2315                                         " completed successfully.");
2316                                 break;
2317                         }
2318                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2319                                 pvr2_trace(
2320                                         PVR2_TRACE_INFO,
2321                                         "Device microcontroller firmware"
2322                                         " (re)loaded; it should now reset"
2323                                         " and reconnect.");
2324                                 break;
2325                         }
2326                         pvr2_trace(
2327                                 PVR2_TRACE_ERROR_LEGS,
2328                                 "Device initialization was not successful.");
2329                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2330                                 pvr2_trace(
2331                                         PVR2_TRACE_ERROR_LEGS,
2332                                         "Giving up since device"
2333                                         " microcontroller firmware"
2334                                         " appears to be missing.");
2335                                 break;
2336                         }
2337                 }
2338                 if (procreload) {
2339                         pvr2_trace(
2340                                 PVR2_TRACE_ERROR_LEGS,
2341                                 "Attempting pvrusb2 recovery by reloading"
2342                                 " primary firmware.");
2343                         pvr2_trace(
2344                                 PVR2_TRACE_ERROR_LEGS,
2345                                 "If this works, device should disconnect"
2346                                 " and reconnect in a sane state.");
2347                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2348                         pvr2_upload_firmware1(hdw);
2349                 } else {
2350                         pvr2_trace(
2351                                 PVR2_TRACE_ERROR_LEGS,
2352                                 "***WARNING*** pvrusb2 device hardware"
2353                                 " appears to be jammed"
2354                                 " and I can't clear it.");
2355                         pvr2_trace(
2356                                 PVR2_TRACE_ERROR_LEGS,
2357                                 "You might need to power cycle"
2358                                 " the pvrusb2 device"
2359                                 " in order to recover.");
2360                 }
2361         } while (0);
2362         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2363 }
2364
2365
2366 /* Perform second stage initialization.  Set callback pointer first so that
2367    we can avoid a possible initialization race (if the kernel thread runs
2368    before the callback has been set). */
2369 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2370                         void (*callback_func)(void *),
2371                         void *callback_data)
2372 {
2373         LOCK_TAKE(hdw->big_lock); do {
2374                 if (hdw->flag_disconnected) {
2375                         /* Handle a race here: If we're already
2376                            disconnected by this point, then give up.  If we
2377                            get past this then we'll remain connected for
2378                            the duration of initialization since the entire
2379                            initialization sequence is now protected by the
2380                            big_lock. */
2381                         break;
2382                 }
2383                 hdw->state_data = callback_data;
2384                 hdw->state_func = callback_func;
2385                 pvr2_hdw_setup(hdw);
2386         } while (0); LOCK_GIVE(hdw->big_lock);
2387         return hdw->flag_init_ok;
2388 }
2389
2390
2391 /* Create, set up, and return a structure for interacting with the
2392    underlying hardware.  */
2393 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2394                                  const struct usb_device_id *devid)
2395 {
2396         unsigned int idx,cnt1,cnt2,m;
2397         struct pvr2_hdw *hdw = NULL;
2398         int valid_std_mask;
2399         struct pvr2_ctrl *cptr;
2400         struct usb_device *usb_dev;
2401         const struct pvr2_device_desc *hdw_desc;
2402         __u8 ifnum;
2403         struct v4l2_queryctrl qctrl;
2404         struct pvr2_ctl_info *ciptr;
2405
2406         usb_dev = interface_to_usbdev(intf);
2407
2408         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2409
2410         if (hdw_desc == NULL) {
2411                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2412                            " No device description pointer,"
2413                            " unable to continue.");
2414                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2415                            " please contact Mike Isely <isely@pobox.com>"
2416                            " to get it included in the driver\n");
2417                 goto fail;
2418         }
2419
2420         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2421         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2422                    hdw,hdw_desc->description);
2423         if (!hdw) goto fail;
2424
2425         init_timer(&hdw->quiescent_timer);
2426         hdw->quiescent_timer.data = (unsigned long)hdw;
2427         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2428
2429         init_timer(&hdw->encoder_wait_timer);
2430         hdw->encoder_wait_timer.data = (unsigned long)hdw;
2431         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2432
2433         init_timer(&hdw->encoder_run_timer);
2434         hdw->encoder_run_timer.data = (unsigned long)hdw;
2435         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2436
2437         hdw->master_state = PVR2_STATE_DEAD;
2438
2439         init_waitqueue_head(&hdw->state_wait_data);
2440
2441         hdw->tuner_signal_stale = !0;
2442         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2443
2444         /* Calculate which inputs are OK */
2445         m = 0;
2446         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2447         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2448                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2449         }
2450         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2451         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2452         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2453         hdw->input_avail_mask = m;
2454         hdw->input_allowed_mask = hdw->input_avail_mask;
2455
2456         /* If not a hybrid device, pathway_state never changes.  So
2457            initialize it here to what it should forever be. */
2458         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2459                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2460         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2461                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2462         }
2463
2464         hdw->control_cnt = CTRLDEF_COUNT;
2465         hdw->control_cnt += MPEGDEF_COUNT;
2466         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2467                                 GFP_KERNEL);
2468         if (!hdw->controls) goto fail;
2469         hdw->hdw_desc = hdw_desc;
2470         for (idx = 0; idx < hdw->control_cnt; idx++) {
2471                 cptr = hdw->controls + idx;
2472                 cptr->hdw = hdw;
2473         }
2474         for (idx = 0; idx < 32; idx++) {
2475                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2476         }
2477         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2478                 cptr = hdw->controls + idx;
2479                 cptr->info = control_defs+idx;
2480         }
2481
2482         /* Ensure that default input choice is a valid one. */
2483         m = hdw->input_avail_mask;
2484         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2485                 if (!((1 << idx) & m)) continue;
2486                 hdw->input_val = idx;
2487                 break;
2488         }
2489
2490         /* Define and configure additional controls from cx2341x module. */
2491         hdw->mpeg_ctrl_info = kzalloc(
2492                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2493         if (!hdw->mpeg_ctrl_info) goto fail;
2494         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2495                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2496                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2497                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2498                 ciptr->name = mpeg_ids[idx].strid;
2499                 ciptr->v4l_id = mpeg_ids[idx].id;
2500                 ciptr->skip_init = !0;
2501                 ciptr->get_value = ctrl_cx2341x_get;
2502                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2503                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2504                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2505                 qctrl.id = ciptr->v4l_id;
2506                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2507                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2508                         ciptr->set_value = ctrl_cx2341x_set;
2509                 }
2510                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2511                         PVR2_CTLD_INFO_DESC_SIZE);
2512                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2513                 ciptr->default_value = qctrl.default_value;
2514                 switch (qctrl.type) {
2515                 default:
2516                 case V4L2_CTRL_TYPE_INTEGER:
2517                         ciptr->type = pvr2_ctl_int;
2518                         ciptr->def.type_int.min_value = qctrl.minimum;
2519                         ciptr->def.type_int.max_value = qctrl.maximum;
2520                         break;
2521                 case V4L2_CTRL_TYPE_BOOLEAN:
2522                         ciptr->type = pvr2_ctl_bool;
2523                         break;
2524                 case V4L2_CTRL_TYPE_MENU:
2525                         ciptr->type = pvr2_ctl_enum;
2526                         ciptr->def.type_enum.value_names =
2527                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2528                                                                 ciptr->v4l_id);
2529                         for (cnt1 = 0;
2530                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2531                              cnt1++) { }
2532                         ciptr->def.type_enum.count = cnt1;
2533                         break;
2534                 }
2535                 cptr->info = ciptr;
2536         }
2537
2538         // Initialize video standard enum dynamic control
2539         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2540         if (cptr) {
2541                 memcpy(&hdw->std_info_enum,cptr->info,
2542                        sizeof(hdw->std_info_enum));
2543                 cptr->info = &hdw->std_info_enum;
2544
2545         }
2546         // Initialize control data regarding video standard masks
2547         valid_std_mask = pvr2_std_get_usable();
2548         for (idx = 0; idx < 32; idx++) {
2549                 if (!(valid_std_mask & (1 << idx))) continue;
2550                 cnt1 = pvr2_std_id_to_str(
2551                         hdw->std_mask_names[idx],
2552                         sizeof(hdw->std_mask_names[idx])-1,
2553                         1 << idx);
2554                 hdw->std_mask_names[idx][cnt1] = 0;
2555         }
2556         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2557         if (cptr) {
2558                 memcpy(&hdw->std_info_avail,cptr->info,
2559                        sizeof(hdw->std_info_avail));
2560                 cptr->info = &hdw->std_info_avail;
2561                 hdw->std_info_avail.def.type_bitmask.bit_names =
2562                         hdw->std_mask_ptrs;
2563                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2564                         valid_std_mask;
2565         }
2566         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2567         if (cptr) {
2568                 memcpy(&hdw->std_info_cur,cptr->info,
2569                        sizeof(hdw->std_info_cur));
2570                 cptr->info = &hdw->std_info_cur;
2571                 hdw->std_info_cur.def.type_bitmask.bit_names =
2572                         hdw->std_mask_ptrs;
2573                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2574                         valid_std_mask;
2575         }
2576
2577         hdw->cropcap_stale = !0;
2578         hdw->eeprom_addr = -1;
2579         hdw->unit_number = -1;
2580         hdw->v4l_minor_number_video = -1;
2581         hdw->v4l_minor_number_vbi = -1;
2582         hdw->v4l_minor_number_radio = -1;
2583         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2584         if (!hdw->ctl_write_buffer) goto fail;
2585         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2586         if (!hdw->ctl_read_buffer) goto fail;
2587         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2588         if (!hdw->ctl_write_urb) goto fail;
2589         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2590         if (!hdw->ctl_read_urb) goto fail;
2591
2592         if (v4l2_device_register(&usb_dev->dev, &hdw->v4l2_dev) != 0) {
2593                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2594                            "Error registering with v4l core, giving up");
2595                 goto fail;
2596         }
2597         mutex_lock(&pvr2_unit_mtx); do {
2598                 for (idx = 0; idx < PVR_NUM; idx++) {
2599                         if (unit_pointers[idx]) continue;
2600                         hdw->unit_number = idx;
2601                         unit_pointers[idx] = hdw;
2602                         break;
2603                 }
2604         } while (0); mutex_unlock(&pvr2_unit_mtx);
2605
2606         cnt1 = 0;
2607         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2608         cnt1 += cnt2;
2609         if (hdw->unit_number >= 0) {
2610                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2611                                  ('a' + hdw->unit_number));
2612                 cnt1 += cnt2;
2613         }
2614         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2615         hdw->name[cnt1] = 0;
2616
2617         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2618         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2619         INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2620
2621         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2622                    hdw->unit_number,hdw->name);
2623
2624         hdw->tuner_type = -1;
2625         hdw->flag_ok = !0;
2626
2627         hdw->usb_intf = intf;
2628         hdw->usb_dev = usb_dev;
2629
2630         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2631
2632         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2633         usb_set_interface(hdw->usb_dev,ifnum,0);
2634
2635         mutex_init(&hdw->ctl_lock_mutex);
2636         mutex_init(&hdw->big_lock_mutex);
2637
2638         return hdw;
2639  fail:
2640         if (hdw) {
2641                 del_timer_sync(&hdw->quiescent_timer);
2642                 del_timer_sync(&hdw->encoder_run_timer);
2643                 del_timer_sync(&hdw->encoder_wait_timer);
2644                 if (hdw->workqueue) {
2645                         flush_workqueue(hdw->workqueue);
2646                         destroy_workqueue(hdw->workqueue);
2647                         hdw->workqueue = NULL;
2648                 }
2649                 usb_free_urb(hdw->ctl_read_urb);
2650                 usb_free_urb(hdw->ctl_write_urb);
2651                 kfree(hdw->ctl_read_buffer);
2652                 kfree(hdw->ctl_write_buffer);
2653                 kfree(hdw->controls);
2654                 kfree(hdw->mpeg_ctrl_info);
2655                 kfree(hdw->std_defs);
2656                 kfree(hdw->std_enum_names);
2657                 kfree(hdw);
2658         }
2659         return NULL;
2660 }
2661
2662
2663 /* Remove _all_ associations between this driver and the underlying USB
2664    layer. */
2665 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2666 {
2667         if (hdw->flag_disconnected) return;
2668         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2669         if (hdw->ctl_read_urb) {
2670                 usb_kill_urb(hdw->ctl_read_urb);
2671                 usb_free_urb(hdw->ctl_read_urb);
2672                 hdw->ctl_read_urb = NULL;
2673         }
2674         if (hdw->ctl_write_urb) {
2675                 usb_kill_urb(hdw->ctl_write_urb);
2676                 usb_free_urb(hdw->ctl_write_urb);
2677                 hdw->ctl_write_urb = NULL;
2678         }
2679         if (hdw->ctl_read_buffer) {
2680                 kfree(hdw->ctl_read_buffer);
2681                 hdw->ctl_read_buffer = NULL;
2682         }
2683         if (hdw->ctl_write_buffer) {
2684                 kfree(hdw->ctl_write_buffer);
2685                 hdw->ctl_write_buffer = NULL;
2686         }
2687         hdw->flag_disconnected = !0;
2688         /* If we don't do this, then there will be a dangling struct device
2689            reference to our disappearing device persisting inside the V4L
2690            core... */
2691         if (hdw->v4l2_dev.dev) {
2692                 dev_set_drvdata(hdw->v4l2_dev.dev, NULL);
2693                 hdw->v4l2_dev.dev = NULL;
2694         }
2695         hdw->usb_dev = NULL;
2696         hdw->usb_intf = NULL;
2697         pvr2_hdw_render_useless(hdw);
2698 }
2699
2700
2701 /* Destroy hardware interaction structure */
2702 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2703 {
2704         if (!hdw) return;
2705         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2706         if (hdw->workqueue) {
2707                 flush_workqueue(hdw->workqueue);
2708                 destroy_workqueue(hdw->workqueue);
2709                 hdw->workqueue = NULL;
2710         }
2711         del_timer_sync(&hdw->quiescent_timer);
2712         del_timer_sync(&hdw->encoder_run_timer);
2713         del_timer_sync(&hdw->encoder_wait_timer);
2714         if (hdw->fw_buffer) {
2715                 kfree(hdw->fw_buffer);
2716                 hdw->fw_buffer = NULL;
2717         }
2718         if (hdw->vid_stream) {
2719                 pvr2_stream_destroy(hdw->vid_stream);
2720                 hdw->vid_stream = NULL;
2721         }
2722         if (hdw->decoder_ctrl) {
2723                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2724         }
2725         pvr2_i2c_core_done(hdw);
2726         pvr2_i2c_track_done(hdw);
2727         v4l2_device_unregister(&hdw->v4l2_dev);
2728         pvr2_hdw_remove_usb_stuff(hdw);
2729         mutex_lock(&pvr2_unit_mtx); do {
2730                 if ((hdw->unit_number >= 0) &&
2731                     (hdw->unit_number < PVR_NUM) &&
2732                     (unit_pointers[hdw->unit_number] == hdw)) {
2733                         unit_pointers[hdw->unit_number] = NULL;
2734                 }
2735         } while (0); mutex_unlock(&pvr2_unit_mtx);
2736         kfree(hdw->controls);
2737         kfree(hdw->mpeg_ctrl_info);
2738         kfree(hdw->std_defs);
2739         kfree(hdw->std_enum_names);
2740         kfree(hdw);
2741 }
2742
2743
2744 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2745 {
2746         return (hdw && hdw->flag_ok);
2747 }
2748
2749
2750 /* Called when hardware has been unplugged */
2751 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2752 {
2753         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2754         LOCK_TAKE(hdw->big_lock);
2755         LOCK_TAKE(hdw->ctl_lock);
2756         pvr2_hdw_remove_usb_stuff(hdw);
2757         LOCK_GIVE(hdw->ctl_lock);
2758         LOCK_GIVE(hdw->big_lock);
2759 }
2760
2761
2762 // Attempt to autoselect an appropriate value for std_enum_cur given
2763 // whatever is currently in std_mask_cur
2764 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2765 {
2766         unsigned int idx;
2767         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2768                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2769                         hdw->std_enum_cur = idx;
2770                         return;
2771                 }
2772         }
2773         hdw->std_enum_cur = 0;
2774 }
2775
2776
2777 // Calculate correct set of enumerated standards based on currently known
2778 // set of available standards bits.
2779 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2780 {
2781         struct v4l2_standard *newstd;
2782         unsigned int std_cnt;
2783         unsigned int idx;
2784
2785         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2786
2787         if (hdw->std_defs) {
2788                 kfree(hdw->std_defs);
2789                 hdw->std_defs = NULL;
2790         }
2791         hdw->std_enum_cnt = 0;
2792         if (hdw->std_enum_names) {
2793                 kfree(hdw->std_enum_names);
2794                 hdw->std_enum_names = NULL;
2795         }
2796
2797         if (!std_cnt) {
2798                 pvr2_trace(
2799                         PVR2_TRACE_ERROR_LEGS,
2800                         "WARNING: Failed to identify any viable standards");
2801         }
2802         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2803         hdw->std_enum_names[0] = "none";
2804         for (idx = 0; idx < std_cnt; idx++) {
2805                 hdw->std_enum_names[idx+1] =
2806                         newstd[idx].name;
2807         }
2808         // Set up the dynamic control for this standard
2809         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2810         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2811         hdw->std_defs = newstd;
2812         hdw->std_enum_cnt = std_cnt+1;
2813         hdw->std_enum_cur = 0;
2814         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2815 }
2816
2817
2818 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2819                                struct v4l2_standard *std,
2820                                unsigned int idx)
2821 {
2822         int ret = -EINVAL;
2823         if (!idx) return ret;
2824         LOCK_TAKE(hdw->big_lock); do {
2825                 if (idx >= hdw->std_enum_cnt) break;
2826                 idx--;
2827                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2828                 ret = 0;
2829         } while (0); LOCK_GIVE(hdw->big_lock);
2830         return ret;
2831 }
2832
2833
2834 /* Get the number of defined controls */
2835 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2836 {
2837         return hdw->control_cnt;
2838 }
2839
2840
2841 /* Retrieve a control handle given its index (0..count-1) */
2842 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2843                                              unsigned int idx)
2844 {
2845         if (idx >= hdw->control_cnt) return NULL;
2846         return hdw->controls + idx;
2847 }
2848
2849
2850 /* Retrieve a control handle given its index (0..count-1) */
2851 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2852                                           unsigned int ctl_id)
2853 {
2854         struct pvr2_ctrl *cptr;
2855         unsigned int idx;
2856         int i;
2857
2858         /* This could be made a lot more efficient, but for now... */
2859         for (idx = 0; idx < hdw->control_cnt; idx++) {
2860                 cptr = hdw->controls + idx;
2861                 i = cptr->info->internal_id;
2862                 if (i && (i == ctl_id)) return cptr;
2863         }
2864         return NULL;
2865 }
2866
2867
2868 /* Given a V4L ID, retrieve the control structure associated with it. */
2869 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2870 {
2871         struct pvr2_ctrl *cptr;
2872         unsigned int idx;
2873         int i;
2874
2875         /* This could be made a lot more efficient, but for now... */
2876         for (idx = 0; idx < hdw->control_cnt; idx++) {
2877                 cptr = hdw->controls + idx;
2878                 i = cptr->info->v4l_id;
2879                 if (i && (i == ctl_id)) return cptr;
2880         }
2881         return NULL;
2882 }
2883
2884
2885 /* Given a V4L ID for its immediate predecessor, retrieve the control
2886    structure associated with it. */
2887 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2888                                             unsigned int ctl_id)
2889 {
2890         struct pvr2_ctrl *cptr,*cp2;
2891         unsigned int idx;
2892         int i;
2893
2894         /* This could be made a lot more efficient, but for now... */
2895         cp2 = NULL;
2896         for (idx = 0; idx < hdw->control_cnt; idx++) {
2897                 cptr = hdw->controls + idx;
2898                 i = cptr->info->v4l_id;
2899                 if (!i) continue;
2900                 if (i <= ctl_id) continue;
2901                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2902                 cp2 = cptr;
2903         }
2904         return cp2;
2905         return NULL;
2906 }
2907
2908
2909 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2910 {
2911         switch (tp) {
2912         case pvr2_ctl_int: return "integer";
2913         case pvr2_ctl_enum: return "enum";
2914         case pvr2_ctl_bool: return "boolean";
2915         case pvr2_ctl_bitmask: return "bitmask";
2916         }
2917         return "";
2918 }
2919
2920
2921 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2922                                     const char *name, int val)
2923 {
2924         struct v4l2_control ctrl;
2925         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2926         memset(&ctrl, 0, sizeof(ctrl));
2927         ctrl.id = id;
2928         ctrl.value = val;
2929         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2930 }
2931
2932 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2933         if ((hdw)->lab##_dirty) { \
2934                 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2935         }
2936
2937 /* Execute whatever commands are required to update the state of all the
2938    sub-devices so that they match our current control values. */
2939 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2940 {
2941         struct v4l2_subdev *sd;
2942         unsigned int id;
2943         pvr2_subdev_update_func fp;
2944
2945         if (hdw->input_dirty || hdw->std_dirty) {
2946                 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_standard");
2947                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2948                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2949                                              tuner, s_radio);
2950                 } else {
2951                         v4l2_std_id vs;
2952                         vs = hdw->std_mask_cur;
2953                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2954                                              tuner, s_std, vs);
2955                 }
2956                 hdw->tuner_signal_stale = !0;
2957                 hdw->cropcap_stale = !0;
2958         }
2959
2960         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2961         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2962         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2963         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2964         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2965         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2966         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2967         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2968         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2969
2970         if (hdw->input_dirty || hdw->audiomode_dirty) {
2971                 struct v4l2_tuner vt;
2972                 memset(&vt, 0, sizeof(vt));
2973                 vt.audmode = hdw->audiomode_val;
2974                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2975         }
2976
2977         if (hdw->freqDirty) {
2978                 unsigned long fv;
2979                 struct v4l2_frequency freq;
2980                 fv = pvr2_hdw_get_cur_freq(hdw);
2981                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2982                 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2983                 memset(&freq, 0, sizeof(freq));
2984                 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2985                         /* ((fv * 1000) / 62500) */
2986                         freq.frequency = (fv * 2) / 125;
2987                 } else {
2988                         freq.frequency = fv / 62500;
2989                 }
2990                 /* tuner-core currently doesn't seem to care about this, but
2991                    let's set it anyway for completeness. */
2992                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2993                         freq.type = V4L2_TUNER_RADIO;
2994                 } else {
2995                         freq.type = V4L2_TUNER_ANALOG_TV;
2996                 }
2997                 freq.tuner = 0;
2998                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2999                                      s_frequency, &freq);
3000         }
3001
3002         if (hdw->res_hor_dirty || hdw->res_ver_dirty) {
3003                 struct v4l2_format fmt;
3004                 memset(&fmt, 0, sizeof(fmt));
3005                 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
3006                 fmt.fmt.pix.width = hdw->res_hor_val;
3007                 fmt.fmt.pix.height = hdw->res_ver_val;
3008                 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_size(%dx%d)",
3009                            fmt.fmt.pix.width, fmt.fmt.pix.height);
3010                 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
3011         }
3012
3013         if (hdw->srate_dirty) {
3014                 u32 val;
3015                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3016                            hdw->srate_val);
3017                 switch (hdw->srate_val) {
3018                 default:
3019                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3020                         val = 48000;
3021                         break;
3022                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3023                         val = 44100;
3024                         break;
3025                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3026                         val = 32000;
3027                         break;
3028                 }
3029                 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3030                                      audio, s_clock_freq, val);
3031         }
3032
3033         /* Unable to set crop parameters; there is apparently no equivalent
3034            for VIDIOC_S_CROP */
3035
3036         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3037                 id = sd->grp_id;
3038                 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3039                 fp = pvr2_module_update_functions[id];
3040                 if (!fp) continue;
3041                 (*fp)(hdw, sd);
3042         }
3043
3044         if (hdw->tuner_signal_stale && hdw->cropcap_stale) {
3045                 pvr2_hdw_status_poll(hdw);
3046         }
3047 }
3048
3049
3050 /* Figure out if we need to commit control changes.  If so, mark internal
3051    state flags to indicate this fact and return true.  Otherwise do nothing
3052    else and return false. */
3053 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
3054 {
3055         unsigned int idx;
3056         struct pvr2_ctrl *cptr;
3057         int value;
3058         int commit_flag = 0;
3059         char buf[100];
3060         unsigned int bcnt,ccnt;
3061
3062         for (idx = 0; idx < hdw->control_cnt; idx++) {
3063                 cptr = hdw->controls + idx;
3064                 if (!cptr->info->is_dirty) continue;
3065                 if (!cptr->info->is_dirty(cptr)) continue;
3066                 commit_flag = !0;
3067
3068                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
3069                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3070                                  cptr->info->name);
3071                 value = 0;
3072                 cptr->info->get_value(cptr,&value);
3073                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3074                                                 buf+bcnt,
3075                                                 sizeof(buf)-bcnt,&ccnt);
3076                 bcnt += ccnt;
3077                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3078                                   get_ctrl_typename(cptr->info->type));
3079                 pvr2_trace(PVR2_TRACE_CTL,
3080                            "/*--TRACE_COMMIT--*/ %.*s",
3081                            bcnt,buf);
3082         }
3083
3084         if (!commit_flag) {
3085                 /* Nothing has changed */
3086                 return 0;
3087         }
3088
3089         hdw->state_pipeline_config = 0;
3090         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3091         pvr2_hdw_state_sched(hdw);
3092
3093         return !0;
3094 }
3095
3096
3097 /* Perform all operations needed to commit all control changes.  This must
3098    be performed in synchronization with the pipeline state and is thus
3099    expected to be called as part of the driver's worker thread.  Return
3100    true if commit successful, otherwise return false to indicate that
3101    commit isn't possible at this time. */
3102 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3103 {
3104         unsigned int idx;
3105         struct pvr2_ctrl *cptr;
3106         int disruptive_change;
3107
3108         /* Handle some required side effects when the video standard is
3109            changed.... */
3110         if (hdw->std_dirty) {
3111                 int nvres;
3112                 int gop_size;
3113                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3114                         nvres = 480;
3115                         gop_size = 15;
3116                 } else {
3117                         nvres = 576;
3118                         gop_size = 12;
3119                 }
3120                 /* Rewrite the vertical resolution to be appropriate to the
3121                    video standard that has been selected. */
3122                 if (nvres != hdw->res_ver_val) {
3123                         hdw->res_ver_val = nvres;
3124                         hdw->res_ver_dirty = !0;
3125                 }
3126                 /* Rewrite the GOP size to be appropriate to the video
3127                    standard that has been selected. */
3128                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3129                         struct v4l2_ext_controls cs;
3130                         struct v4l2_ext_control c1;
3131                         memset(&cs, 0, sizeof(cs));
3132                         memset(&c1, 0, sizeof(c1));
3133                         cs.controls = &c1;
3134                         cs.count = 1;
3135                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3136                         c1.value = gop_size;
3137                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3138                                           VIDIOC_S_EXT_CTRLS);
3139                 }
3140         }
3141
3142         if (hdw->input_dirty && hdw->state_pathway_ok &&
3143             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3144               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3145              hdw->pathway_state)) {
3146                 /* Change of mode being asked for... */
3147                 hdw->state_pathway_ok = 0;
3148                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3149         }
3150         if (!hdw->state_pathway_ok) {
3151                 /* Can't commit anything until pathway is ok. */
3152                 return 0;
3153         }
3154         /* The broadcast decoder can only scale down, so if
3155          * res_*_dirty && crop window < output format ==> enlarge crop.
3156          *
3157          * The mpeg encoder receives fields of res_hor_val dots and
3158          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3159          */
3160         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3161                 hdw->cropw_val = hdw->res_hor_val;
3162                 hdw->cropw_dirty = !0;
3163         } else if (hdw->cropw_dirty) {
3164                 hdw->res_hor_dirty = !0;           /* must rescale */
3165                 hdw->res_hor_val = min(720, hdw->cropw_val);
3166         }
3167         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3168                 hdw->croph_val = hdw->res_ver_val;
3169                 hdw->croph_dirty = !0;
3170         } else if (hdw->croph_dirty) {
3171                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3172                 hdw->res_ver_dirty = !0;
3173                 hdw->res_ver_val = min(nvres, hdw->croph_val);
3174         }
3175
3176         /* If any of the below has changed, then we can't do the update
3177            while the pipeline is running.  Pipeline must be paused first
3178            and decoder -> encoder connection be made quiescent before we
3179            can proceed. */
3180         disruptive_change =
3181                 (hdw->std_dirty ||
3182                  hdw->enc_unsafe_stale ||
3183                  hdw->srate_dirty ||
3184                  hdw->res_ver_dirty ||
3185                  hdw->res_hor_dirty ||
3186                  hdw->cropw_dirty ||
3187                  hdw->croph_dirty ||
3188                  hdw->input_dirty ||
3189                  (hdw->active_stream_type != hdw->desired_stream_type));
3190         if (disruptive_change && !hdw->state_pipeline_idle) {
3191                 /* Pipeline is not idle; we can't proceed.  Arrange to
3192                    cause pipeline to stop so that we can try this again
3193                    later.... */
3194                 hdw->state_pipeline_pause = !0;
3195                 return 0;
3196         }
3197
3198         if (hdw->srate_dirty) {
3199                 /* Write new sample rate into control structure since
3200                  * the master copy is stale.  We must track srate
3201                  * separate from the mpeg control structure because
3202                  * other logic also uses this value. */
3203                 struct v4l2_ext_controls cs;
3204                 struct v4l2_ext_control c1;
3205                 memset(&cs,0,sizeof(cs));
3206                 memset(&c1,0,sizeof(c1));
3207                 cs.controls = &c1;
3208                 cs.count = 1;
3209                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3210                 c1.value = hdw->srate_val;
3211                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3212         }
3213
3214         /* Scan i2c core at this point - before we clear all the dirty
3215            bits.  Various parts of the i2c core will notice dirty bits as
3216            appropriate and arrange to broadcast or directly send updates to
3217            the client drivers in order to keep everything in sync */
3218         pvr2_i2c_core_check_stale(hdw);
3219
3220         if (hdw->active_stream_type != hdw->desired_stream_type) {
3221                 /* Handle any side effects of stream config here */
3222                 hdw->active_stream_type = hdw->desired_stream_type;
3223         }
3224
3225         if (hdw->hdw_desc->signal_routing_scheme ==
3226             PVR2_ROUTING_SCHEME_GOTVIEW) {
3227                 u32 b;
3228                 /* Handle GOTVIEW audio switching */
3229                 pvr2_hdw_gpio_get_out(hdw,&b);
3230                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3231                         /* Set GPIO 11 */
3232                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3233                 } else {
3234                         /* Clear GPIO 11 */
3235                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3236                 }
3237         }
3238
3239         for (idx = 0; idx < hdw->control_cnt; idx++) {
3240                 cptr = hdw->controls + idx;
3241                 if (!cptr->info->clear_dirty) continue;
3242                 cptr->info->clear_dirty(cptr);
3243         }
3244
3245         /* Check and update state for all sub-devices. */
3246         pvr2_subdev_update(hdw);
3247
3248         /* Now execute i2c core update */
3249         pvr2_i2c_core_sync(hdw);
3250
3251         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3252             hdw->state_encoder_run) {
3253                 /* If encoder isn't running or it can't be touched, then
3254                    this will get worked out later when we start the
3255                    encoder. */
3256                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3257         }
3258
3259         hdw->state_pipeline_config = !0;
3260         /* Hardware state may have changed in a way to cause the cropping
3261            capabilities to have changed.  So mark it stale, which will
3262            cause a later re-fetch. */
3263         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3264         return !0;
3265 }
3266
3267
3268 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3269 {
3270         int fl;
3271         LOCK_TAKE(hdw->big_lock);
3272         fl = pvr2_hdw_commit_setup(hdw);
3273         LOCK_GIVE(hdw->big_lock);
3274         if (!fl) return 0;
3275         return pvr2_hdw_wait(hdw,0);
3276 }
3277
3278
3279 static void pvr2_hdw_worker_i2c(struct work_struct *work)
3280 {
3281         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
3282         LOCK_TAKE(hdw->big_lock); do {
3283                 pvr2_i2c_core_sync(hdw);
3284         } while (0); LOCK_GIVE(hdw->big_lock);
3285 }
3286
3287
3288 static void pvr2_hdw_worker_poll(struct work_struct *work)
3289 {
3290         int fl = 0;
3291         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3292         LOCK_TAKE(hdw->big_lock); do {
3293                 fl = pvr2_hdw_state_eval(hdw);
3294         } while (0); LOCK_GIVE(hdw->big_lock);
3295         if (fl && hdw->state_func) {
3296                 hdw->state_func(hdw->state_data);
3297         }
3298 }
3299
3300
3301 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3302 {
3303         return wait_event_interruptible(
3304                 hdw->state_wait_data,
3305                 (hdw->state_stale == 0) &&
3306                 (!state || (hdw->master_state != state)));
3307 }
3308
3309
3310 /* Return name for this driver instance */
3311 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3312 {
3313         return hdw->name;
3314 }
3315
3316
3317 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3318 {
3319         return hdw->hdw_desc->description;
3320 }
3321
3322
3323 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3324 {
3325         return hdw->hdw_desc->shortname;
3326 }
3327
3328
3329 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3330 {
3331         int result;
3332         LOCK_TAKE(hdw->ctl_lock); do {
3333                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3334                 result = pvr2_send_request(hdw,
3335                                            hdw->cmd_buffer,1,
3336                                            hdw->cmd_buffer,1);
3337                 if (result < 0) break;
3338                 result = (hdw->cmd_buffer[0] != 0);
3339         } while(0); LOCK_GIVE(hdw->ctl_lock);
3340         return result;
3341 }
3342
3343
3344 /* Execute poll of tuner status */
3345 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3346 {
3347         LOCK_TAKE(hdw->big_lock); do {
3348                 pvr2_hdw_status_poll(hdw);
3349         } while (0); LOCK_GIVE(hdw->big_lock);
3350 }
3351
3352
3353 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3354 {
3355         if (!hdw->cropcap_stale) {
3356                 return 0;
3357         }
3358         pvr2_hdw_status_poll(hdw);
3359         if (hdw->cropcap_stale) {
3360                 return -EIO;
3361         }
3362         return 0;
3363 }
3364
3365
3366 /* Return information about cropping capabilities */
3367 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3368 {
3369         int stat = 0;
3370         LOCK_TAKE(hdw->big_lock);
3371         stat = pvr2_hdw_check_cropcap(hdw);
3372         if (!stat) {
3373                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3374         }
3375         LOCK_GIVE(hdw->big_lock);
3376         return stat;
3377 }
3378
3379
3380 /* Return information about the tuner */
3381 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3382 {
3383         LOCK_TAKE(hdw->big_lock); do {
3384                 if (hdw->tuner_signal_stale) {
3385                         pvr2_hdw_status_poll(hdw);
3386                 }
3387                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3388         } while (0); LOCK_GIVE(hdw->big_lock);
3389         return 0;
3390 }
3391
3392
3393 /* Get handle to video output stream */
3394 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3395 {
3396         return hp->vid_stream;
3397 }
3398
3399
3400 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3401 {
3402         int nr = pvr2_hdw_get_unit_number(hdw);
3403         LOCK_TAKE(hdw->big_lock); do {
3404                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3405                 hdw->log_requested = !0;
3406                 pvr2_i2c_core_check_stale(hdw);
3407                 pvr2_i2c_core_sync(hdw);
3408                 hdw->log_requested = 0;
3409                 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3410                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3411                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3412                 pvr2_hdw_state_log_state(hdw);
3413                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3414         } while (0); LOCK_GIVE(hdw->big_lock);
3415 }
3416
3417
3418 /* Grab EEPROM contents, needed for direct method. */
3419 #define EEPROM_SIZE 8192
3420 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3421 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3422 {
3423         struct i2c_msg msg[2];
3424         u8 *eeprom;
3425         u8 iadd[2];
3426         u8 addr;
3427         u16 eepromSize;
3428         unsigned int offs;
3429         int ret;
3430         int mode16 = 0;
3431         unsigned pcnt,tcnt;
3432         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3433         if (!eeprom) {
3434                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3435                            "Failed to allocate memory"
3436                            " required to read eeprom");
3437                 return NULL;
3438         }
3439
3440         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3441                      hdw->eeprom_addr);
3442         addr = hdw->eeprom_addr;
3443         /* Seems that if the high bit is set, then the *real* eeprom
3444            address is shifted right now bit position (noticed this in
3445            newer PVR USB2 hardware) */
3446         if (addr & 0x80) addr >>= 1;
3447
3448         /* FX2 documentation states that a 16bit-addressed eeprom is
3449            expected if the I2C address is an odd number (yeah, this is
3450            strange but it's what they do) */
3451         mode16 = (addr & 1);
3452         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3453         trace_eeprom("Examining %d byte eeprom at location 0x%x"
3454                      " using %d bit addressing",eepromSize,addr,
3455                      mode16 ? 16 : 8);
3456
3457         msg[0].addr = addr;
3458         msg[0].flags = 0;
3459         msg[0].len = mode16 ? 2 : 1;
3460         msg[0].buf = iadd;
3461         msg[1].addr = addr;
3462         msg[1].flags = I2C_M_RD;
3463
3464         /* We have to do the actual eeprom data fetch ourselves, because
3465            (1) we're only fetching part of the eeprom, and (2) if we were
3466            getting the whole thing our I2C driver can't grab it in one
3467            pass - which is what tveeprom is otherwise going to attempt */
3468         memset(eeprom,0,EEPROM_SIZE);
3469         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3470                 pcnt = 16;
3471                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3472                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3473                 if (mode16) {
3474                         iadd[0] = offs >> 8;
3475                         iadd[1] = offs;
3476                 } else {
3477                         iadd[0] = offs;
3478                 }
3479                 msg[1].len = pcnt;
3480                 msg[1].buf = eeprom+tcnt;
3481                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3482                                         msg,ARRAY_SIZE(msg))) != 2) {
3483                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3484                                    "eeprom fetch set offs err=%d",ret);
3485                         kfree(eeprom);
3486                         return NULL;
3487                 }
3488         }
3489         return eeprom;
3490 }
3491
3492
3493 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3494                                 int prom_flag,
3495                                 int enable_flag)
3496 {
3497         int ret;
3498         u16 address;
3499         unsigned int pipe;
3500         LOCK_TAKE(hdw->big_lock); do {
3501                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3502
3503                 if (!enable_flag) {
3504                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3505                                    "Cleaning up after CPU firmware fetch");
3506                         kfree(hdw->fw_buffer);
3507                         hdw->fw_buffer = NULL;
3508                         hdw->fw_size = 0;
3509                         if (hdw->fw_cpu_flag) {
3510                                 /* Now release the CPU.  It will disconnect
3511                                    and reconnect later. */
3512                                 pvr2_hdw_cpureset_assert(hdw,0);
3513                         }
3514                         break;
3515                 }
3516
3517                 hdw->fw_cpu_flag = (prom_flag == 0);
3518                 if (hdw->fw_cpu_flag) {
3519                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3520                                    "Preparing to suck out CPU firmware");
3521                         hdw->fw_size = 0x2000;
3522                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3523                         if (!hdw->fw_buffer) {
3524                                 hdw->fw_size = 0;
3525                                 break;
3526                         }
3527
3528                         /* We have to hold the CPU during firmware upload. */
3529                         pvr2_hdw_cpureset_assert(hdw,1);
3530
3531                         /* download the firmware from address 0000-1fff in 2048
3532                            (=0x800) bytes chunk. */
3533
3534                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3535                                    "Grabbing CPU firmware");
3536                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3537                         for(address = 0; address < hdw->fw_size;
3538                             address += 0x800) {
3539                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3540                                                       0xa0,0xc0,
3541                                                       address,0,
3542                                                       hdw->fw_buffer+address,
3543                                                       0x800,HZ);
3544                                 if (ret < 0) break;
3545                         }
3546
3547                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3548                                    "Done grabbing CPU firmware");
3549                 } else {
3550                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3551                                    "Sucking down EEPROM contents");
3552                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3553                         if (!hdw->fw_buffer) {
3554                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3555                                            "EEPROM content suck failed.");
3556                                 break;
3557                         }
3558                         hdw->fw_size = EEPROM_SIZE;
3559                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3560                                    "Done sucking down EEPROM contents");
3561                 }
3562
3563         } while (0); LOCK_GIVE(hdw->big_lock);
3564 }
3565
3566
3567 /* Return true if we're in a mode for retrieval CPU firmware */
3568 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3569 {
3570         return hdw->fw_buffer != NULL;
3571 }
3572
3573
3574 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3575                        char *buf,unsigned int cnt)
3576 {
3577         int ret = -EINVAL;
3578         LOCK_TAKE(hdw->big_lock); do {
3579                 if (!buf) break;
3580                 if (!cnt) break;
3581
3582                 if (!hdw->fw_buffer) {
3583                         ret = -EIO;
3584                         break;
3585                 }
3586
3587                 if (offs >= hdw->fw_size) {
3588                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3589                                    "Read firmware data offs=%d EOF",
3590                                    offs);
3591                         ret = 0;
3592                         break;
3593                 }
3594
3595                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3596
3597                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3598
3599                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3600                            "Read firmware data offs=%d cnt=%d",
3601                            offs,cnt);
3602                 ret = cnt;
3603         } while (0); LOCK_GIVE(hdw->big_lock);
3604
3605         return ret;
3606 }
3607
3608
3609 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3610                                   enum pvr2_v4l_type index)
3611 {
3612         switch (index) {
3613         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3614         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3615         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3616         default: return -1;
3617         }
3618 }
3619
3620
3621 /* Store a v4l minor device number */
3622 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3623                                      enum pvr2_v4l_type index,int v)
3624 {
3625         switch (index) {
3626         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3627         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3628         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3629         default: break;
3630         }
3631 }
3632
3633
3634 static void pvr2_ctl_write_complete(struct urb *urb)
3635 {
3636         struct pvr2_hdw *hdw = urb->context;
3637         hdw->ctl_write_pend_flag = 0;
3638         if (hdw->ctl_read_pend_flag) return;
3639         complete(&hdw->ctl_done);
3640 }
3641
3642
3643 static void pvr2_ctl_read_complete(struct urb *urb)
3644 {
3645         struct pvr2_hdw *hdw = urb->context;
3646         hdw->ctl_read_pend_flag = 0;
3647         if (hdw->ctl_write_pend_flag) return;
3648         complete(&hdw->ctl_done);
3649 }
3650
3651
3652 static void pvr2_ctl_timeout(unsigned long data)
3653 {
3654         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3655         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3656                 hdw->ctl_timeout_flag = !0;
3657                 if (hdw->ctl_write_pend_flag)
3658                         usb_unlink_urb(hdw->ctl_write_urb);
3659                 if (hdw->ctl_read_pend_flag)
3660                         usb_unlink_urb(hdw->ctl_read_urb);
3661         }
3662 }
3663
3664
3665 /* Issue a command and get a response from the device.  This extended
3666    version includes a probe flag (which if set means that device errors
3667    should not be logged or treated as fatal) and a timeout in jiffies.
3668    This can be used to non-lethally probe the health of endpoint 1. */
3669 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3670                                 unsigned int timeout,int probe_fl,
3671                                 void *write_data,unsigned int write_len,
3672                                 void *read_data,unsigned int read_len)
3673 {
3674         unsigned int idx;
3675         int status = 0;
3676         struct timer_list timer;
3677         if (!hdw->ctl_lock_held) {
3678                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3679                            "Attempted to execute control transfer"
3680                            " without lock!!");
3681                 return -EDEADLK;
3682         }
3683         if (!hdw->flag_ok && !probe_fl) {
3684                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3685                            "Attempted to execute control transfer"
3686                            " when device not ok");
3687                 return -EIO;
3688         }
3689         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3690                 if (!probe_fl) {
3691                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3692                                    "Attempted to execute control transfer"
3693                                    " when USB is disconnected");
3694                 }
3695                 return -ENOTTY;
3696         }
3697
3698         /* Ensure that we have sane parameters */
3699         if (!write_data) write_len = 0;
3700         if (!read_data) read_len = 0;
3701         if (write_len > PVR2_CTL_BUFFSIZE) {
3702                 pvr2_trace(
3703                         PVR2_TRACE_ERROR_LEGS,
3704                         "Attempted to execute %d byte"
3705                         " control-write transfer (limit=%d)",
3706                         write_len,PVR2_CTL_BUFFSIZE);
3707                 return -EINVAL;
3708         }
3709         if (read_len > PVR2_CTL_BUFFSIZE) {
3710                 pvr2_trace(
3711                         PVR2_TRACE_ERROR_LEGS,
3712                         "Attempted to execute %d byte"
3713                         " control-read transfer (limit=%d)",
3714                         write_len,PVR2_CTL_BUFFSIZE);
3715                 return -EINVAL;
3716         }
3717         if ((!write_len) && (!read_len)) {
3718                 pvr2_trace(
3719                         PVR2_TRACE_ERROR_LEGS,
3720                         "Attempted to execute null control transfer?");
3721                 return -EINVAL;
3722         }
3723
3724
3725         hdw->cmd_debug_state = 1;
3726         if (write_len) {
3727                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3728         } else {
3729                 hdw->cmd_debug_code = 0;
3730         }
3731         hdw->cmd_debug_write_len = write_len;
3732         hdw->cmd_debug_read_len = read_len;
3733
3734         /* Initialize common stuff */
3735         init_completion(&hdw->ctl_done);
3736         hdw->ctl_timeout_flag = 0;
3737         hdw->ctl_write_pend_flag = 0;
3738         hdw->ctl_read_pend_flag = 0;
3739         init_timer(&timer);
3740         timer.expires = jiffies + timeout;
3741         timer.data = (unsigned long)hdw;
3742         timer.function = pvr2_ctl_timeout;
3743
3744         if (write_len) {
3745                 hdw->cmd_debug_state = 2;
3746                 /* Transfer write data to internal buffer */
3747                 for (idx = 0; idx < write_len; idx++) {
3748                         hdw->ctl_write_buffer[idx] =
3749                                 ((unsigned char *)write_data)[idx];
3750                 }
3751                 /* Initiate a write request */
3752                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3753                                   hdw->usb_dev,
3754                                   usb_sndbulkpipe(hdw->usb_dev,
3755                                                   PVR2_CTL_WRITE_ENDPOINT),
3756                                   hdw->ctl_write_buffer,
3757                                   write_len,
3758                                   pvr2_ctl_write_complete,
3759                                   hdw);
3760                 hdw->ctl_write_urb->actual_length = 0;
3761                 hdw->ctl_write_pend_flag = !0;
3762                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3763                 if (status < 0) {
3764                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3765                                    "Failed to submit write-control"
3766                                    " URB status=%d",status);
3767                         hdw->ctl_write_pend_flag = 0;
3768                         goto done;
3769                 }
3770         }
3771
3772         if (read_len) {
3773                 hdw->cmd_debug_state = 3;
3774                 memset(hdw->ctl_read_buffer,0x43,read_len);
3775                 /* Initiate a read request */
3776                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3777                                   hdw->usb_dev,
3778                                   usb_rcvbulkpipe(hdw->usb_dev,
3779                                                   PVR2_CTL_READ_ENDPOINT),
3780                                   hdw->ctl_read_buffer,
3781                                   read_len,
3782                                   pvr2_ctl_read_complete,
3783                                   hdw);
3784                 hdw->ctl_read_urb->actual_length = 0;
3785                 hdw->ctl_read_pend_flag = !0;
3786                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3787                 if (status < 0) {
3788                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3789                                    "Failed to submit read-control"
3790                                    " URB status=%d",status);
3791                         hdw->ctl_read_pend_flag = 0;
3792                         goto done;
3793                 }
3794         }
3795
3796         /* Start timer */
3797         add_timer(&timer);
3798
3799         /* Now wait for all I/O to complete */
3800         hdw->cmd_debug_state = 4;
3801         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3802                 wait_for_completion(&hdw->ctl_done);
3803         }
3804         hdw->cmd_debug_state = 5;
3805
3806         /* Stop timer */
3807         del_timer_sync(&timer);
3808
3809         hdw->cmd_debug_state = 6;
3810         status = 0;
3811
3812         if (hdw->ctl_timeout_flag) {
3813                 status = -ETIMEDOUT;
3814                 if (!probe_fl) {
3815                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3816                                    "Timed out control-write");
3817                 }
3818                 goto done;
3819         }
3820
3821         if (write_len) {
3822                 /* Validate results of write request */
3823                 if ((hdw->ctl_write_urb->status != 0) &&
3824                     (hdw->ctl_write_urb->status != -ENOENT) &&
3825                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3826                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3827                         /* USB subsystem is reporting some kind of failure
3828                            on the write */
3829                         status = hdw->ctl_write_urb->status;
3830                         if (!probe_fl) {
3831                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3832                                            "control-write URB failure,"
3833                                            " status=%d",
3834                                            status);
3835                         }
3836                         goto done;
3837                 }
3838                 if (hdw->ctl_write_urb->actual_length < write_len) {
3839                         /* Failed to write enough data */
3840                         status = -EIO;
3841                         if (!probe_fl) {
3842                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3843                                            "control-write URB short,"
3844                                            " expected=%d got=%d",
3845                                            write_len,
3846                                            hdw->ctl_write_urb->actual_length);
3847                         }
3848                         goto done;
3849                 }
3850         }
3851         if (read_len) {
3852                 /* Validate results of read request */
3853                 if ((hdw->ctl_read_urb->status != 0) &&
3854                     (hdw->ctl_read_urb->status != -ENOENT) &&
3855                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3856                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3857                         /* USB subsystem is reporting some kind of failure
3858                            on the read */
3859                         status = hdw->ctl_read_urb->status;
3860                         if (!probe_fl) {
3861                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3862                                            "control-read URB failure,"
3863                                            " status=%d",
3864                                            status);
3865                         }
3866                         goto done;
3867                 }
3868                 if (hdw->ctl_read_urb->actual_length < read_len) {
3869                         /* Failed to read enough data */
3870                         status = -EIO;
3871                         if (!probe_fl) {
3872                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3873                                            "control-read URB short,"
3874                                            " expected=%d got=%d",
3875                                            read_len,
3876                                            hdw->ctl_read_urb->actual_length);
3877                         }
3878                         goto done;
3879                 }
3880                 /* Transfer retrieved data out from internal buffer */
3881                 for (idx = 0; idx < read_len; idx++) {
3882                         ((unsigned char *)read_data)[idx] =
3883                                 hdw->ctl_read_buffer[idx];
3884                 }
3885         }
3886
3887  done:
3888
3889         hdw->cmd_debug_state = 0;
3890         if ((status < 0) && (!probe_fl)) {
3891                 pvr2_hdw_render_useless(hdw);
3892         }
3893         return status;
3894 }
3895
3896
3897 int pvr2_send_request(struct pvr2_hdw *hdw,
3898                       void *write_data,unsigned int write_len,
3899                       void *read_data,unsigned int read_len)
3900 {
3901         return pvr2_send_request_ex(hdw,HZ*4,0,
3902                                     write_data,write_len,
3903                                     read_data,read_len);
3904 }
3905
3906
3907 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3908 {
3909         int ret;
3910         unsigned int cnt = 1;
3911         unsigned int args = 0;
3912         LOCK_TAKE(hdw->ctl_lock);
3913         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3914         args = (cmdcode >> 8) & 0xffu;
3915         args = (args > 2) ? 2 : args;
3916         if (args) {
3917                 cnt += args;
3918                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3919                 if (args > 1) {
3920                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3921                 }
3922         }
3923         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3924                 unsigned int idx;
3925                 unsigned int ccnt,bcnt;
3926                 char tbuf[50];
3927                 cmdcode &= 0xffu;
3928                 bcnt = 0;
3929                 ccnt = scnprintf(tbuf+bcnt,
3930                                  sizeof(tbuf)-bcnt,
3931                                  "Sending FX2 command 0x%x",cmdcode);
3932                 bcnt += ccnt;
3933                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3934                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3935                                 ccnt = scnprintf(tbuf+bcnt,
3936                                                  sizeof(tbuf)-bcnt,
3937                                                  " \"%s\"",
3938                                                  pvr2_fx2cmd_desc[idx].desc);
3939                                 bcnt += ccnt;
3940                                 break;
3941                         }
3942                 }
3943                 if (args) {
3944                         ccnt = scnprintf(tbuf+bcnt,
3945                                          sizeof(tbuf)-bcnt,
3946                                          " (%u",hdw->cmd_buffer[1]);
3947                         bcnt += ccnt;
3948                         if (args > 1) {
3949                                 ccnt = scnprintf(tbuf+bcnt,
3950                                                  sizeof(tbuf)-bcnt,
3951                                                  ",%u",hdw->cmd_buffer[2]);
3952                                 bcnt += ccnt;
3953                         }
3954                         ccnt = scnprintf(tbuf+bcnt,
3955                                          sizeof(tbuf)-bcnt,
3956                                          ")");
3957                         bcnt += ccnt;
3958                 }
3959                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3960         }
3961         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3962         LOCK_GIVE(hdw->ctl_lock);
3963         return ret;
3964 }
3965
3966
3967 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3968 {
3969         int ret;
3970
3971         LOCK_TAKE(hdw->ctl_lock);
3972
3973         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3974         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3975         hdw->cmd_buffer[5] = 0;
3976         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3977         hdw->cmd_buffer[7] = reg & 0xff;
3978
3979
3980         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3981
3982         LOCK_GIVE(hdw->ctl_lock);
3983
3984         return ret;
3985 }
3986
3987
3988 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3989 {
3990         int ret = 0;
3991
3992         LOCK_TAKE(hdw->ctl_lock);
3993
3994         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3995         hdw->cmd_buffer[1] = 0;
3996         hdw->cmd_buffer[2] = 0;
3997         hdw->cmd_buffer[3] = 0;
3998         hdw->cmd_buffer[4] = 0;
3999         hdw->cmd_buffer[5] = 0;
4000         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4001         hdw->cmd_buffer[7] = reg & 0xff;
4002
4003         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4004         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4005
4006         LOCK_GIVE(hdw->ctl_lock);
4007
4008         return ret;
4009 }
4010
4011
4012 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
4013 {
4014         if (!hdw->flag_ok) return;
4015         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4016                    "Device being rendered inoperable");
4017         if (hdw->vid_stream) {
4018                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
4019         }
4020         hdw->flag_ok = 0;
4021         trace_stbit("flag_ok",hdw->flag_ok);
4022         pvr2_hdw_state_sched(hdw);
4023 }
4024
4025
4026 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4027 {
4028         int ret;
4029         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
4030         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
4031         if (ret == 0) {
4032                 ret = usb_reset_device(hdw->usb_dev);
4033                 usb_unlock_device(hdw->usb_dev);
4034         } else {
4035                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4036                            "Failed to lock USB device ret=%d",ret);
4037         }
4038         if (init_pause_msec) {
4039                 pvr2_trace(PVR2_TRACE_INFO,
4040                            "Waiting %u msec for hardware to settle",
4041                            init_pause_msec);
4042                 msleep(init_pause_msec);
4043         }
4044
4045 }
4046
4047
4048 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4049 {
4050         char da[1];
4051         unsigned int pipe;
4052         int ret;
4053
4054         if (!hdw->usb_dev) return;
4055
4056         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4057
4058         da[0] = val ? 0x01 : 0x00;
4059
4060         /* Write the CPUCS register on the 8051.  The lsb of the register
4061            is the reset bit; a 1 asserts reset while a 0 clears it. */
4062         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4063         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4064         if (ret < 0) {
4065                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4066                            "cpureset_assert(%d) error=%d",val,ret);
4067                 pvr2_hdw_render_useless(hdw);
4068         }
4069 }
4070
4071
4072 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4073 {
4074         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4075 }
4076
4077
4078 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4079 {
4080         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4081 }
4082
4083
4084 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4085 {
4086         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
4087 }
4088
4089
4090 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4091 {
4092         pvr2_trace(PVR2_TRACE_INIT,
4093                    "Requesting decoder reset");
4094         if (hdw->decoder_ctrl) {
4095                 if (!hdw->decoder_ctrl->force_reset) {
4096                         pvr2_trace(PVR2_TRACE_INIT,
4097                                    "Unable to reset decoder: not implemented");
4098                         return -ENOTTY;
4099                 }
4100                 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
4101                 return 0;
4102         } else {
4103         }
4104         if (hdw->decoder_client_id) {
4105                 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4106                                      core, reset, 0);
4107                 return 0;
4108         }
4109         pvr2_trace(PVR2_TRACE_INIT,
4110                    "Unable to reset decoder: nothing attached");
4111         return -ENOTTY;
4112 }
4113
4114
4115 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4116 {
4117         hdw->flag_ok = !0;
4118         return pvr2_issue_simple_cmd(hdw,
4119                                      FX2CMD_HCW_DEMOD_RESETIN |
4120                                      (1 << 8) |
4121                                      ((onoff ? 1 : 0) << 16));
4122 }
4123
4124
4125 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4126 {
4127         hdw->flag_ok = !0;
4128         return pvr2_issue_simple_cmd(hdw,(onoff ?
4129                                           FX2CMD_ONAIR_DTV_POWER_ON :
4130                                           FX2CMD_ONAIR_DTV_POWER_OFF));
4131 }
4132
4133
4134 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4135                                                 int onoff)
4136 {
4137         return pvr2_issue_simple_cmd(hdw,(onoff ?
4138                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
4139                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
4140 }
4141
4142
4143 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4144 {
4145         int cmode;
4146         /* Compare digital/analog desired setting with current setting.  If
4147            they don't match, fix it... */
4148         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4149         if (cmode == hdw->pathway_state) {
4150                 /* They match; nothing to do */
4151                 return;
4152         }
4153
4154         switch (hdw->hdw_desc->digital_control_scheme) {
4155         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4156                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4157                 if (cmode == PVR2_PATHWAY_ANALOG) {
4158                         /* If moving to analog mode, also force the decoder
4159                            to reset.  If no decoder is attached, then it's
4160                            ok to ignore this because if/when the decoder
4161                            attaches, it will reset itself at that time. */
4162                         pvr2_hdw_cmd_decoder_reset(hdw);
4163                 }
4164                 break;
4165         case PVR2_DIGITAL_SCHEME_ONAIR:
4166                 /* Supposedly we should always have the power on whether in
4167                    digital or analog mode.  But for now do what appears to
4168                    work... */
4169                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4170                 break;
4171         default: break;
4172         }
4173
4174         pvr2_hdw_untrip_unlocked(hdw);
4175         hdw->pathway_state = cmode;
4176 }
4177
4178
4179 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4180 {
4181         /* change some GPIO data
4182          *
4183          * note: bit d7 of dir appears to control the LED,
4184          * so we shut it off here.
4185          *
4186          */
4187         if (onoff) {
4188                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4189         } else {
4190                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4191         }
4192         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4193 }
4194
4195
4196 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4197
4198 static led_method_func led_methods[] = {
4199         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4200 };
4201
4202
4203 /* Toggle LED */
4204 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4205 {
4206         unsigned int scheme_id;
4207         led_method_func fp;
4208
4209         if ((!onoff) == (!hdw->led_on)) return;
4210
4211         hdw->led_on = onoff != 0;
4212
4213         scheme_id = hdw->hdw_desc->led_scheme;
4214         if (scheme_id < ARRAY_SIZE(led_methods)) {
4215                 fp = led_methods[scheme_id];
4216         } else {
4217                 fp = NULL;
4218         }
4219
4220         if (fp) (*fp)(hdw,onoff);
4221 }
4222
4223
4224 /* Stop / start video stream transport */
4225 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4226 {
4227         int ret;
4228
4229         /* If we're in analog mode, then just issue the usual analog
4230            command. */
4231         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4232                 return pvr2_issue_simple_cmd(hdw,
4233                                              (runFl ?
4234                                               FX2CMD_STREAMING_ON :
4235                                               FX2CMD_STREAMING_OFF));
4236                 /*Note: Not reached */
4237         }
4238
4239         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4240                 /* Whoops, we don't know what mode we're in... */
4241                 return -EINVAL;
4242         }
4243
4244         /* To get here we have to be in digital mode.  The mechanism here
4245            is unfortunately different for different vendors.  So we switch
4246            on the device's digital scheme attribute in order to figure out
4247            what to do. */
4248         switch (hdw->hdw_desc->digital_control_scheme) {
4249         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4250                 return pvr2_issue_simple_cmd(hdw,
4251                                              (runFl ?
4252                                               FX2CMD_HCW_DTV_STREAMING_ON :
4253                                               FX2CMD_HCW_DTV_STREAMING_OFF));
4254         case PVR2_DIGITAL_SCHEME_ONAIR:
4255                 ret = pvr2_issue_simple_cmd(hdw,
4256                                             (runFl ?
4257                                              FX2CMD_STREAMING_ON :
4258                                              FX2CMD_STREAMING_OFF));
4259                 if (ret) return ret;
4260                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4261         default:
4262                 return -EINVAL;
4263         }
4264 }
4265
4266
4267 /* Evaluate whether or not state_pathway_ok can change */
4268 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4269 {
4270         if (hdw->state_pathway_ok) {
4271                 /* Nothing to do if pathway is already ok */
4272                 return 0;
4273         }
4274         if (!hdw->state_pipeline_idle) {
4275                 /* Not allowed to change anything if pipeline is not idle */
4276                 return 0;
4277         }
4278         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4279         hdw->state_pathway_ok = !0;
4280         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4281         return !0;
4282 }
4283
4284
4285 /* Evaluate whether or not state_encoder_ok can change */
4286 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4287 {
4288         if (hdw->state_encoder_ok) return 0;
4289         if (hdw->flag_tripped) return 0;
4290         if (hdw->state_encoder_run) return 0;
4291         if (hdw->state_encoder_config) return 0;
4292         if (hdw->state_decoder_run) return 0;
4293         if (hdw->state_usbstream_run) return 0;
4294         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4295                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4296         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4297                 return 0;
4298         }
4299
4300         if (pvr2_upload_firmware2(hdw) < 0) {
4301                 hdw->flag_tripped = !0;
4302                 trace_stbit("flag_tripped",hdw->flag_tripped);
4303                 return !0;
4304         }
4305         hdw->state_encoder_ok = !0;
4306         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4307         return !0;
4308 }
4309
4310
4311 /* Evaluate whether or not state_encoder_config can change */
4312 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4313 {
4314         if (hdw->state_encoder_config) {
4315                 if (hdw->state_encoder_ok) {
4316                         if (hdw->state_pipeline_req &&
4317                             !hdw->state_pipeline_pause) return 0;
4318                 }
4319                 hdw->state_encoder_config = 0;
4320                 hdw->state_encoder_waitok = 0;
4321                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4322                 /* paranoia - solve race if timer just completed */
4323                 del_timer_sync(&hdw->encoder_wait_timer);
4324         } else {
4325                 if (!hdw->state_pathway_ok ||
4326                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4327                     !hdw->state_encoder_ok ||
4328                     !hdw->state_pipeline_idle ||
4329                     hdw->state_pipeline_pause ||
4330                     !hdw->state_pipeline_req ||
4331                     !hdw->state_pipeline_config) {
4332                         /* We must reset the enforced wait interval if
4333                            anything has happened that might have disturbed
4334                            the encoder.  This should be a rare case. */
4335                         if (timer_pending(&hdw->encoder_wait_timer)) {
4336                                 del_timer_sync(&hdw->encoder_wait_timer);
4337                         }
4338                         if (hdw->state_encoder_waitok) {
4339                                 /* Must clear the state - therefore we did
4340                                    something to a state bit and must also
4341                                    return true. */
4342                                 hdw->state_encoder_waitok = 0;
4343                                 trace_stbit("state_encoder_waitok",
4344                                             hdw->state_encoder_waitok);
4345                                 return !0;
4346                         }
4347                         return 0;
4348                 }
4349                 if (!hdw->state_encoder_waitok) {
4350                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4351                                 /* waitok flag wasn't set and timer isn't
4352                                    running.  Check flag once more to avoid
4353                                    a race then start the timer.  This is
4354                                    the point when we measure out a minimal
4355                                    quiet interval before doing something to
4356                                    the encoder. */
4357                                 if (!hdw->state_encoder_waitok) {
4358                                         hdw->encoder_wait_timer.expires =
4359                                                 jiffies +
4360                                                 (HZ * TIME_MSEC_ENCODER_WAIT
4361                                                  / 1000);
4362                                         add_timer(&hdw->encoder_wait_timer);
4363                                 }
4364                         }
4365                         /* We can't continue until we know we have been
4366                            quiet for the interval measured by this
4367                            timer. */
4368                         return 0;
4369                 }
4370                 pvr2_encoder_configure(hdw);
4371                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4372         }
4373         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4374         return !0;
4375 }
4376
4377
4378 /* Return true if the encoder should not be running. */
4379 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4380 {
4381         if (!hdw->state_encoder_ok) {
4382                 /* Encoder isn't healthy at the moment, so stop it. */
4383                 return !0;
4384         }
4385         if (!hdw->state_pathway_ok) {
4386                 /* Mode is not understood at the moment (i.e. it wants to
4387                    change), so encoder must be stopped. */
4388                 return !0;
4389         }
4390
4391         switch (hdw->pathway_state) {
4392         case PVR2_PATHWAY_ANALOG:
4393                 if (!hdw->state_decoder_run) {
4394                         /* We're in analog mode and the decoder is not
4395                            running; thus the encoder should be stopped as
4396                            well. */
4397                         return !0;
4398                 }
4399                 break;
4400         case PVR2_PATHWAY_DIGITAL:
4401                 if (hdw->state_encoder_runok) {
4402                         /* This is a funny case.  We're in digital mode so
4403                            really the encoder should be stopped.  However
4404                            if it really is running, only kill it after
4405                            runok has been set.  This gives a chance for the
4406                            onair quirk to function (encoder must run
4407                            briefly first, at least once, before onair
4408                            digital streaming can work). */
4409                         return !0;
4410                 }
4411                 break;
4412         default:
4413                 /* Unknown mode; so encoder should be stopped. */
4414                 return !0;
4415         }
4416
4417         /* If we get here, we haven't found a reason to stop the
4418            encoder. */
4419         return 0;
4420 }
4421
4422
4423 /* Return true if the encoder should be running. */
4424 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4425 {
4426         if (!hdw->state_encoder_ok) {
4427                 /* Don't run the encoder if it isn't healthy... */
4428                 return 0;
4429         }
4430         if (!hdw->state_pathway_ok) {
4431                 /* Don't run the encoder if we don't (yet) know what mode
4432                    we need to be in... */
4433                 return 0;
4434         }
4435
4436         switch (hdw->pathway_state) {
4437         case PVR2_PATHWAY_ANALOG:
4438                 if (hdw->state_decoder_run) {
4439                         /* In analog mode, if the decoder is running, then
4440                            run the encoder. */
4441                         return !0;
4442                 }
4443                 break;
4444         case PVR2_PATHWAY_DIGITAL:
4445                 if ((hdw->hdw_desc->digital_control_scheme ==
4446                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4447                     !hdw->state_encoder_runok) {
4448                         /* This is a quirk.  OnAir hardware won't stream
4449                            digital until the encoder has been run at least
4450                            once, for a minimal period of time (empiricially
4451                            measured to be 1/4 second).  So if we're on
4452                            OnAir hardware and the encoder has never been
4453                            run at all, then start the encoder.  Normal
4454                            state machine logic in the driver will
4455                            automatically handle the remaining bits. */
4456                         return !0;
4457                 }
4458                 break;
4459         default:
4460                 /* For completeness (unknown mode; encoder won't run ever) */
4461                 break;
4462         }
4463         /* If we get here, then we haven't found any reason to run the
4464            encoder, so don't run it. */
4465         return 0;
4466 }
4467
4468
4469 /* Evaluate whether or not state_encoder_run can change */
4470 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4471 {
4472         if (hdw->state_encoder_run) {
4473                 if (!state_check_disable_encoder_run(hdw)) return 0;
4474                 if (hdw->state_encoder_ok) {
4475                         del_timer_sync(&hdw->encoder_run_timer);
4476                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4477                 }
4478                 hdw->state_encoder_run = 0;
4479         } else {
4480                 if (!state_check_enable_encoder_run(hdw)) return 0;
4481                 if (pvr2_encoder_start(hdw) < 0) return !0;
4482                 hdw->state_encoder_run = !0;
4483                 if (!hdw->state_encoder_runok) {
4484                         hdw->encoder_run_timer.expires =
4485                                 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4486                         add_timer(&hdw->encoder_run_timer);
4487                 }
4488         }
4489         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4490         return !0;
4491 }
4492
4493
4494 /* Timeout function for quiescent timer. */
4495 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4496 {
4497         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4498         hdw->state_decoder_quiescent = !0;
4499         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4500         hdw->state_stale = !0;
4501         queue_work(hdw->workqueue,&hdw->workpoll);
4502 }
4503
4504
4505 /* Timeout function for encoder wait timer. */
4506 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4507 {
4508         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4509         hdw->state_encoder_waitok = !0;
4510         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4511         hdw->state_stale = !0;
4512         queue_work(hdw->workqueue,&hdw->workpoll);
4513 }
4514
4515
4516 /* Timeout function for encoder run timer. */
4517 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4518 {
4519         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4520         if (!hdw->state_encoder_runok) {
4521                 hdw->state_encoder_runok = !0;
4522                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4523                 hdw->state_stale = !0;
4524                 queue_work(hdw->workqueue,&hdw->workpoll);
4525         }
4526 }
4527
4528
4529 /* Evaluate whether or not state_decoder_run can change */
4530 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4531 {
4532         if (hdw->state_decoder_run) {
4533                 if (hdw->state_encoder_ok) {
4534                         if (hdw->state_pipeline_req &&
4535                             !hdw->state_pipeline_pause &&
4536                             hdw->state_pathway_ok) return 0;
4537                 }
4538                 if (!hdw->flag_decoder_missed) {
4539                         pvr2_decoder_enable(hdw,0);
4540                 }
4541                 hdw->state_decoder_quiescent = 0;
4542                 hdw->state_decoder_run = 0;
4543                 /* paranoia - solve race if timer just completed */
4544                 del_timer_sync(&hdw->quiescent_timer);
4545         } else {
4546                 if (!hdw->state_decoder_quiescent) {
4547                         if (!timer_pending(&hdw->quiescent_timer)) {
4548                                 /* We don't do something about the
4549                                    quiescent timer until right here because
4550                                    we also want to catch cases where the
4551                                    decoder was already not running (like
4552                                    after initialization) as opposed to
4553                                    knowing that we had just stopped it.
4554                                    The second flag check is here to cover a
4555                                    race - the timer could have run and set
4556                                    this flag just after the previous check
4557                                    but before we did the pending check. */
4558                                 if (!hdw->state_decoder_quiescent) {
4559                                         hdw->quiescent_timer.expires =
4560                                                 jiffies +
4561                                                 (HZ * TIME_MSEC_DECODER_WAIT
4562                                                  / 1000);
4563                                         add_timer(&hdw->quiescent_timer);
4564                                 }
4565                         }
4566                         /* Don't allow decoder to start again until it has
4567                            been quiesced first.  This little detail should
4568                            hopefully further stabilize the encoder. */
4569                         return 0;
4570                 }
4571                 if (!hdw->state_pathway_ok ||
4572                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4573                     !hdw->state_pipeline_req ||
4574                     hdw->state_pipeline_pause ||
4575                     !hdw->state_pipeline_config ||
4576                     !hdw->state_encoder_config ||
4577                     !hdw->state_encoder_ok) return 0;
4578                 del_timer_sync(&hdw->quiescent_timer);
4579                 if (hdw->flag_decoder_missed) return 0;
4580                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4581                 hdw->state_decoder_quiescent = 0;
4582                 hdw->state_decoder_run = !0;
4583         }
4584         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4585         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4586         return !0;
4587 }
4588
4589
4590 /* Evaluate whether or not state_usbstream_run can change */
4591 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4592 {
4593         if (hdw->state_usbstream_run) {
4594                 int fl = !0;
4595                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4596                         fl = (hdw->state_encoder_ok &&
4597                               hdw->state_encoder_run);
4598                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4599                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4600                         fl = hdw->state_encoder_ok;
4601                 }
4602                 if (fl &&
4603                     hdw->state_pipeline_req &&
4604                     !hdw->state_pipeline_pause &&
4605                     hdw->state_pathway_ok) {
4606                         return 0;
4607                 }
4608                 pvr2_hdw_cmd_usbstream(hdw,0);
4609                 hdw->state_usbstream_run = 0;
4610         } else {
4611                 if (!hdw->state_pipeline_req ||
4612                     hdw->state_pipeline_pause ||
4613                     !hdw->state_pathway_ok) return 0;
4614                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4615                         if (!hdw->state_encoder_ok ||
4616                             !hdw->state_encoder_run) return 0;
4617                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4618                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4619                         if (!hdw->state_encoder_ok) return 0;
4620                         if (hdw->state_encoder_run) return 0;
4621                         if (hdw->hdw_desc->digital_control_scheme ==
4622                             PVR2_DIGITAL_SCHEME_ONAIR) {
4623                                 /* OnAir digital receivers won't stream
4624                                    unless the analog encoder has run first.
4625                                    Why?  I have no idea.  But don't even
4626                                    try until we know the analog side is
4627                                    known to have run. */
4628                                 if (!hdw->state_encoder_runok) return 0;
4629                         }
4630                 }
4631                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4632                 hdw->state_usbstream_run = !0;
4633         }
4634         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4635         return !0;
4636 }
4637
4638
4639 /* Attempt to configure pipeline, if needed */
4640 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4641 {
4642         if (hdw->state_pipeline_config ||
4643             hdw->state_pipeline_pause) return 0;
4644         pvr2_hdw_commit_execute(hdw);
4645         return !0;
4646 }
4647
4648
4649 /* Update pipeline idle and pipeline pause tracking states based on other
4650    inputs.  This must be called whenever the other relevant inputs have
4651    changed. */
4652 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4653 {
4654         unsigned int st;
4655         int updatedFl = 0;
4656         /* Update pipeline state */
4657         st = !(hdw->state_encoder_run ||
4658                hdw->state_decoder_run ||
4659                hdw->state_usbstream_run ||
4660                (!hdw->state_decoder_quiescent));
4661         if (!st != !hdw->state_pipeline_idle) {
4662                 hdw->state_pipeline_idle = st;
4663                 updatedFl = !0;
4664         }
4665         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4666                 hdw->state_pipeline_pause = 0;
4667                 updatedFl = !0;
4668         }
4669         return updatedFl;
4670 }
4671
4672
4673 typedef int (*state_eval_func)(struct pvr2_hdw *);
4674
4675 /* Set of functions to be run to evaluate various states in the driver. */
4676 static const state_eval_func eval_funcs[] = {
4677         state_eval_pathway_ok,
4678         state_eval_pipeline_config,
4679         state_eval_encoder_ok,
4680         state_eval_encoder_config,
4681         state_eval_decoder_run,
4682         state_eval_encoder_run,
4683         state_eval_usbstream_run,
4684 };
4685
4686
4687 /* Process various states and return true if we did anything interesting. */
4688 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4689 {
4690         unsigned int i;
4691         int state_updated = 0;
4692         int check_flag;
4693
4694         if (!hdw->state_stale) return 0;
4695         if ((hdw->fw1_state != FW1_STATE_OK) ||
4696             !hdw->flag_ok) {
4697                 hdw->state_stale = 0;
4698                 return !0;
4699         }
4700         /* This loop is the heart of the entire driver.  It keeps trying to
4701            evaluate various bits of driver state until nothing changes for
4702            one full iteration.  Each "bit of state" tracks some global
4703            aspect of the driver, e.g. whether decoder should run, if
4704            pipeline is configured, usb streaming is on, etc.  We separately
4705            evaluate each of those questions based on other driver state to
4706            arrive at the correct running configuration. */
4707         do {
4708                 check_flag = 0;
4709                 state_update_pipeline_state(hdw);
4710                 /* Iterate over each bit of state */
4711                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4712                         if ((*eval_funcs[i])(hdw)) {
4713                                 check_flag = !0;
4714                                 state_updated = !0;
4715                                 state_update_pipeline_state(hdw);
4716                         }
4717                 }
4718         } while (check_flag && hdw->flag_ok);
4719         hdw->state_stale = 0;
4720         trace_stbit("state_stale",hdw->state_stale);
4721         return state_updated;
4722 }
4723
4724
4725 static unsigned int print_input_mask(unsigned int msk,
4726                                      char *buf,unsigned int acnt)
4727 {
4728         unsigned int idx,ccnt;
4729         unsigned int tcnt = 0;
4730         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4731                 if (!((1 << idx) & msk)) continue;
4732                 ccnt = scnprintf(buf+tcnt,
4733                                  acnt-tcnt,
4734                                  "%s%s",
4735                                  (tcnt ? ", " : ""),
4736                                  control_values_input[idx]);
4737                 tcnt += ccnt;
4738         }
4739         return tcnt;
4740 }
4741
4742
4743 static const char *pvr2_pathway_state_name(int id)
4744 {
4745         switch (id) {
4746         case PVR2_PATHWAY_ANALOG: return "analog";
4747         case PVR2_PATHWAY_DIGITAL: return "digital";
4748         default: return "unknown";
4749         }
4750 }
4751
4752
4753 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4754                                              char *buf,unsigned int acnt)
4755 {
4756         switch (which) {
4757         case 0:
4758                 return scnprintf(
4759                         buf,acnt,
4760                         "driver:%s%s%s%s%s <mode=%s>",
4761                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4762                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4763                         (hdw->flag_disconnected ? " <disconnected>" :
4764                          " <connected>"),
4765                         (hdw->flag_tripped ? " <tripped>" : ""),
4766                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4767                         pvr2_pathway_state_name(hdw->pathway_state));
4768
4769         case 1:
4770                 return scnprintf(
4771                         buf,acnt,
4772                         "pipeline:%s%s%s%s",
4773                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4774                         (hdw->state_pipeline_config ?
4775                          " <configok>" : " <stale>"),
4776                         (hdw->state_pipeline_req ? " <req>" : ""),
4777                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4778         case 2:
4779                 return scnprintf(
4780                         buf,acnt,
4781                         "worker:%s%s%s%s%s%s%s",
4782                         (hdw->state_decoder_run ?
4783                          " <decode:run>" :
4784                          (hdw->state_decoder_quiescent ?
4785                           "" : " <decode:stop>")),
4786                         (hdw->state_decoder_quiescent ?
4787                          " <decode:quiescent>" : ""),
4788                         (hdw->state_encoder_ok ?
4789                          "" : " <encode:init>"),
4790                         (hdw->state_encoder_run ?
4791                          (hdw->state_encoder_runok ?
4792                           " <encode:run>" :
4793                           " <encode:firstrun>") :
4794                          (hdw->state_encoder_runok ?
4795                           " <encode:stop>" :
4796                           " <encode:virgin>")),
4797                         (hdw->state_encoder_config ?
4798                          " <encode:configok>" :
4799                          (hdw->state_encoder_waitok ?
4800                           "" : " <encode:waitok>")),
4801                         (hdw->state_usbstream_run ?
4802                          " <usb:run>" : " <usb:stop>"),
4803                         (hdw->state_pathway_ok ?
4804                          " <pathway:ok>" : ""));
4805         case 3:
4806                 return scnprintf(
4807                         buf,acnt,
4808                         "state: %s",
4809                         pvr2_get_state_name(hdw->master_state));
4810         case 4: {
4811                 unsigned int tcnt = 0;
4812                 unsigned int ccnt;
4813
4814                 ccnt = scnprintf(buf,
4815                                  acnt,
4816                                  "Hardware supported inputs: ");
4817                 tcnt += ccnt;
4818                 tcnt += print_input_mask(hdw->input_avail_mask,
4819                                          buf+tcnt,
4820                                          acnt-tcnt);
4821                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4822                         ccnt = scnprintf(buf+tcnt,
4823                                          acnt-tcnt,
4824                                          "; allowed inputs: ");
4825                         tcnt += ccnt;
4826                         tcnt += print_input_mask(hdw->input_allowed_mask,
4827                                                  buf+tcnt,
4828                                                  acnt-tcnt);
4829                 }
4830                 return tcnt;
4831         }
4832         case 5: {
4833                 struct pvr2_stream_stats stats;
4834                 if (!hdw->vid_stream) break;
4835                 pvr2_stream_get_stats(hdw->vid_stream,
4836                                       &stats,
4837                                       0);
4838                 return scnprintf(
4839                         buf,acnt,
4840                         "Bytes streamed=%u"
4841                         " URBs: queued=%u idle=%u ready=%u"
4842                         " processed=%u failed=%u",
4843                         stats.bytes_processed,
4844                         stats.buffers_in_queue,
4845                         stats.buffers_in_idle,
4846                         stats.buffers_in_ready,
4847                         stats.buffers_processed,
4848                         stats.buffers_failed);
4849         }
4850         case 6: {
4851                 struct v4l2_subdev *sd;
4852                 unsigned int tcnt = 0;
4853                 unsigned int ccnt;
4854                 const char *p;
4855                 unsigned int id;
4856                 ccnt = scnprintf(buf,
4857                                  acnt,
4858                                  "Associted v4l2_subdev drivers:");
4859                 tcnt += ccnt;
4860                 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4861                         id = sd->grp_id;
4862                         p = NULL;
4863                         if (id < ARRAY_SIZE(module_names)) {
4864                                 p = module_names[id];
4865                         }
4866                         if (!p) p = "(unknown)";
4867                         ccnt = scnprintf(buf + tcnt,
4868                                          acnt - tcnt,
4869                                          " %s (%u)", p, id);
4870                 }
4871                 return tcnt;
4872         }
4873         default: break;
4874         }
4875         return 0;
4876 }
4877
4878
4879 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4880                                    char *buf,unsigned int acnt)
4881 {
4882         unsigned int bcnt,ccnt,idx;
4883         bcnt = 0;
4884         LOCK_TAKE(hdw->big_lock);
4885         for (idx = 0; ; idx++) {
4886                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4887                 if (!ccnt) break;
4888                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4889                 if (!acnt) break;
4890                 buf[0] = '\n'; ccnt = 1;
4891                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4892         }
4893         LOCK_GIVE(hdw->big_lock);
4894         return bcnt;
4895 }
4896
4897
4898 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4899 {
4900         char buf[128];
4901         unsigned int idx,ccnt;
4902
4903         for (idx = 0; ; idx++) {
4904                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4905                 if (!ccnt) break;
4906                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4907         }
4908 }
4909
4910
4911 /* Evaluate and update the driver's current state, taking various actions
4912    as appropriate for the update. */
4913 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4914 {
4915         unsigned int st;
4916         int state_updated = 0;
4917         int callback_flag = 0;
4918         int analog_mode;
4919
4920         pvr2_trace(PVR2_TRACE_STBITS,
4921                    "Drive state check START");
4922         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4923                 pvr2_hdw_state_log_state(hdw);
4924         }
4925
4926         /* Process all state and get back over disposition */
4927         state_updated = pvr2_hdw_state_update(hdw);
4928
4929         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4930
4931         /* Update master state based upon all other states. */
4932         if (!hdw->flag_ok) {
4933                 st = PVR2_STATE_DEAD;
4934         } else if (hdw->fw1_state != FW1_STATE_OK) {
4935                 st = PVR2_STATE_COLD;
4936         } else if ((analog_mode ||
4937                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4938                    !hdw->state_encoder_ok) {
4939                 st = PVR2_STATE_WARM;
4940         } else if (hdw->flag_tripped ||
4941                    (analog_mode && hdw->flag_decoder_missed)) {
4942                 st = PVR2_STATE_ERROR;
4943         } else if (hdw->state_usbstream_run &&
4944                    (!analog_mode ||
4945                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4946                 st = PVR2_STATE_RUN;
4947         } else {
4948                 st = PVR2_STATE_READY;
4949         }
4950         if (hdw->master_state != st) {
4951                 pvr2_trace(PVR2_TRACE_STATE,
4952                            "Device state change from %s to %s",
4953                            pvr2_get_state_name(hdw->master_state),
4954                            pvr2_get_state_name(st));
4955                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4956                 hdw->master_state = st;
4957                 state_updated = !0;
4958                 callback_flag = !0;
4959         }
4960         if (state_updated) {
4961                 /* Trigger anyone waiting on any state changes here. */
4962                 wake_up(&hdw->state_wait_data);
4963         }
4964
4965         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4966                 pvr2_hdw_state_log_state(hdw);
4967         }
4968         pvr2_trace(PVR2_TRACE_STBITS,
4969                    "Drive state check DONE callback=%d",callback_flag);
4970
4971         return callback_flag;
4972 }
4973
4974
4975 /* Cause kernel thread to check / update driver state */
4976 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4977 {
4978         if (hdw->state_stale) return;
4979         hdw->state_stale = !0;
4980         trace_stbit("state_stale",hdw->state_stale);
4981         queue_work(hdw->workqueue,&hdw->workpoll);
4982 }
4983
4984
4985 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4986 {
4987         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4988 }
4989
4990
4991 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4992 {
4993         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4994 }
4995
4996
4997 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4998 {
4999         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5000 }
5001
5002
5003 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5004 {
5005         u32 cval,nval;
5006         int ret;
5007         if (~msk) {
5008                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5009                 if (ret) return ret;
5010                 nval = (cval & ~msk) | (val & msk);
5011                 pvr2_trace(PVR2_TRACE_GPIO,
5012                            "GPIO direction changing 0x%x:0x%x"
5013                            " from 0x%x to 0x%x",
5014                            msk,val,cval,nval);
5015         } else {
5016                 nval = val;
5017                 pvr2_trace(PVR2_TRACE_GPIO,
5018                            "GPIO direction changing to 0x%x",nval);
5019         }
5020         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5021 }
5022
5023
5024 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5025 {
5026         u32 cval,nval;
5027         int ret;
5028         if (~msk) {
5029                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5030                 if (ret) return ret;
5031                 nval = (cval & ~msk) | (val & msk);
5032                 pvr2_trace(PVR2_TRACE_GPIO,
5033                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5034                            msk,val,cval,nval);
5035         } else {
5036                 nval = val;
5037                 pvr2_trace(PVR2_TRACE_GPIO,
5038                            "GPIO output changing to 0x%x",nval);
5039         }
5040         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5041 }
5042
5043
5044 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5045 {
5046         struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5047         memset(vtp, 0, sizeof(*vtp));
5048         hdw->tuner_signal_stale = 0;
5049         pvr2_i2c_core_status_poll(hdw);
5050         /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5051            using v4l2-subdev - therefore we can't support that AT ALL right
5052            now.  (Of course, no sub-drivers seem to implement it either.
5053            But now it's a a chicken and egg problem...) */
5054         v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
5055                              &hdw->tuner_signal_info);
5056         pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
5057                    " type=%u strength=%u audio=0x%x cap=0x%x"
5058                    " low=%u hi=%u",
5059                    vtp->type,
5060                    vtp->signal, vtp->rxsubchans, vtp->capability,
5061                    vtp->rangelow, vtp->rangehigh);
5062
5063         /* We have to do this to avoid getting into constant polling if
5064            there's nobody to answer a poll of cropcap info. */
5065         hdw->cropcap_stale = 0;
5066 }
5067
5068
5069 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5070 {
5071         return hdw->input_avail_mask;
5072 }
5073
5074
5075 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5076 {
5077         return hdw->input_allowed_mask;
5078 }
5079
5080
5081 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5082 {
5083         if (hdw->input_val != v) {
5084                 hdw->input_val = v;
5085                 hdw->input_dirty = !0;
5086         }
5087
5088         /* Handle side effects - if we switch to a mode that needs the RF
5089            tuner, then select the right frequency choice as well and mark
5090            it dirty. */
5091         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5092                 hdw->freqSelector = 0;
5093                 hdw->freqDirty = !0;
5094         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5095                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5096                 hdw->freqSelector = 1;
5097                 hdw->freqDirty = !0;
5098         }
5099         return 0;
5100 }
5101
5102
5103 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5104                                unsigned int change_mask,
5105                                unsigned int change_val)
5106 {
5107         int ret = 0;
5108         unsigned int nv,m,idx;
5109         LOCK_TAKE(hdw->big_lock);
5110         do {
5111                 nv = hdw->input_allowed_mask & ~change_mask;
5112                 nv |= (change_val & change_mask);
5113                 nv &= hdw->input_avail_mask;
5114                 if (!nv) {
5115                         /* No legal modes left; return error instead. */
5116                         ret = -EPERM;
5117                         break;
5118                 }
5119                 hdw->input_allowed_mask = nv;
5120                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5121                         /* Current mode is still in the allowed mask, so
5122                            we're done. */
5123                         break;
5124                 }
5125                 /* Select and switch to a mode that is still in the allowed
5126                    mask */
5127                 if (!hdw->input_allowed_mask) {
5128                         /* Nothing legal; give up */
5129                         break;
5130                 }
5131                 m = hdw->input_allowed_mask;
5132                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5133                         if (!((1 << idx) & m)) continue;
5134                         pvr2_hdw_set_input(hdw,idx);
5135                         break;
5136                 }
5137         } while (0);
5138         LOCK_GIVE(hdw->big_lock);
5139         return ret;
5140 }
5141
5142
5143 /* Find I2C address of eeprom */
5144 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5145 {
5146         int result;
5147         LOCK_TAKE(hdw->ctl_lock); do {
5148                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5149                 result = pvr2_send_request(hdw,
5150                                            hdw->cmd_buffer,1,
5151                                            hdw->cmd_buffer,1);
5152                 if (result < 0) break;
5153                 result = hdw->cmd_buffer[0];
5154         } while(0); LOCK_GIVE(hdw->ctl_lock);
5155         return result;
5156 }
5157
5158
5159 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
5160                              struct v4l2_dbg_match *match, u64 reg_id,
5161                              int setFl, u64 *val_ptr)
5162 {
5163 #ifdef CONFIG_VIDEO_ADV_DEBUG
5164         struct pvr2_i2c_client *cp;
5165         struct v4l2_dbg_register req;
5166         int stat = 0;
5167         int okFl = 0;
5168
5169         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5170
5171         req.match = *match;
5172         req.reg = reg_id;
5173         if (setFl) req.val = *val_ptr;
5174         /* It would be nice to know if a sub-device answered the request */
5175         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5176         if (!setFl) *val_ptr = req.val;
5177         if (!okFl) mutex_lock(&hdw->i2c_list_lock); do {
5178                 list_for_each_entry(cp, &hdw->i2c_clients, list) {
5179                         if (!v4l2_chip_match_i2c_client(
5180                                     cp->client,
5181                                     &req.match)) {
5182                                 continue;
5183                         }
5184                         stat = pvr2_i2c_client_cmd(
5185                                 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
5186                                     VIDIOC_DBG_G_REGISTER),&req);
5187                         if (!setFl) *val_ptr = req.val;
5188                         okFl = !0;
5189                         break;
5190                 }
5191         } while (0); mutex_unlock(&hdw->i2c_list_lock);
5192         if (okFl) {
5193                 return stat;
5194         }
5195         return -EINVAL;
5196 #else
5197         return -ENOSYS;
5198 #endif
5199 }
5200
5201
5202 /*
5203   Stuff for Emacs to see, in order to encourage consistent editing style:
5204   *** Local Variables: ***
5205   *** mode: c ***
5206   *** fill-column: 75 ***
5207   *** tab-width: 8 ***
5208   *** c-basic-offset: 8 ***
5209   *** End: ***
5210   */