Pileus Git - ~andy/linux/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/firmware.h>
  25 #include <linux/videodev2.h>
  26 #include <media/v4l2-common.h>
  27 #include "pvrusb2.h"
  28 #include "pvrusb2-std.h"
  29 #include "pvrusb2-util.h"
  30 #include "pvrusb2-hdw.h"
  31 #include "pvrusb2-i2c-core.h"
  32 #include "pvrusb2-i2c-track.h"
  33 #include "pvrusb2-tuner.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38 #include "pvrusb2-fx2-cmd.h"
  39
  40 #define TV_MIN_FREQ     55250000L
  41 #define TV_MAX_FREQ    850000000L
  42
  43 /* This defines a minimum interval that the decoder must remain quiet
  44    before we are allowed to start it running. */
  45 #define TIME_MSEC_DECODER_WAIT 50
  46
  47 /* This defines a minimum interval that the encoder must remain quiet
  48    before we are allowed to configure it.  I had this originally set to
  49    50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
  50    things work better when it's set to 100msec. */
  51 #define TIME_MSEC_ENCODER_WAIT 100
  52
  53 /* This defines the minimum interval that the encoder must successfully run
  54    before we consider that the encoder has run at least once since its
  55    firmware has been loaded.  This measurement is in important for cases
  56    where we can't do something until we know that the encoder has been run
  57    at least once. */
  58 #define TIME_MSEC_ENCODER_OK 250
  59
  60 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  61 static DEFINE_MUTEX(pvr2_unit_mtx);
  62
  63 static int ctlchg;
  64 static int procreload;
  65 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  66 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  67 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  68 static int init_pause_msec;
  69
  70 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  71 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  72 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  73 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  74 module_param(procreload, int, S_IRUGO|S_IWUSR);
  75 MODULE_PARM_DESC(procreload,
  76                  "Attempt init failure recovery with firmware reload");
  77 module_param_array(tuner,    int, NULL, 0444);
  78 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  79 module_param_array(video_std,    int, NULL, 0444);
  80 MODULE_PARM_DESC(video_std,"specify initial video standard");
  81 module_param_array(tolerance,    int, NULL, 0444);
  82 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  83
  84 /* US Broadcast channel 7 (175.25 MHz) */
  85 static int default_tv_freq    = 175250000L;
  86 /* 104.3 MHz, a usable FM station for my area */
  87 static int default_radio_freq = 104300000L;
  88
  89 module_param_named(tv_freq, default_tv_freq, int, 0444);
  90 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  91 module_param_named(radio_freq, default_radio_freq, int, 0444);
  92 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  93
  94 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  95 #define PVR2_CTL_READ_ENDPOINT   0x81
  96
  97 #define PVR2_GPIO_IN 0x9008
  98 #define PVR2_GPIO_OUT 0x900c
  99 #define PVR2_GPIO_DIR 0x9020
 100
 101 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 102
 103 #define PVR2_FIRMWARE_ENDPOINT   0x02
 104
 105 /* size of a firmware chunk */
 106 #define FIRMWARE_CHUNK_SIZE 0x2000
 107
 108 static const char *module_names[] = {
 109         [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 110         [PVR2_CLIENT_ID_CX25840] = "cx25840",
 111         [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 112         [PVR2_CLIENT_ID_TUNER] = "tuner",
 113         [PVR2_CLIENT_ID_CS53132A] = "cs53132a",
 114 };
 115
 116
 117 static const unsigned char *module_i2c_addresses[] = {
 118         [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 119 };
 120
 121
 122 /* Define the list of additional controls we'll dynamically construct based
 123    on query of the cx2341x module. */
 124 struct pvr2_mpeg_ids {
 125         const char *strid;
 126         int id;
 127 };
 128 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 129         {
 130                 .strid = "audio_layer",
 131                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 132         },{
 133                 .strid = "audio_bitrate",
 134                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 135         },{
 136                 /* Already using audio_mode elsewhere :-( */
 137                 .strid = "mpeg_audio_mode",
 138                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 139         },{
 140                 .strid = "mpeg_audio_mode_extension",
 141                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 142         },{
 143                 .strid = "audio_emphasis",
 144                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 145         },{
 146                 .strid = "audio_crc",
 147                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 148         },{
 149                 .strid = "video_aspect",
 150                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 151         },{
 152                 .strid = "video_b_frames",
 153                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 154         },{
 155                 .strid = "video_gop_size",
 156                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 157         },{
 158                 .strid = "video_gop_closure",
 159                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 160         },{
 161                 .strid = "video_bitrate_mode",
 162                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 163         },{
 164                 .strid = "video_bitrate",
 165                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 166         },{
 167                 .strid = "video_bitrate_peak",
 168                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 169         },{
 170                 .strid = "video_temporal_decimation",
 171                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 172         },{
 173                 .strid = "stream_type",
 174                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 175         },{
 176                 .strid = "video_spatial_filter_mode",
 177                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 178         },{
 179                 .strid = "video_spatial_filter",
 180                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 181         },{
 182                 .strid = "video_luma_spatial_filter_type",
 183                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 184         },{
 185                 .strid = "video_chroma_spatial_filter_type",
 186                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 187         },{
 188                 .strid = "video_temporal_filter_mode",
 189                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 190         },{
 191                 .strid = "video_temporal_filter",
 192                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 193         },{
 194                 .strid = "video_median_filter_type",
 195                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 196         },{
 197                 .strid = "video_luma_median_filter_top",
 198                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 199         },{
 200                 .strid = "video_luma_median_filter_bottom",
 201                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 202         },{
 203                 .strid = "video_chroma_median_filter_top",
 204                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 205         },{
 206                 .strid = "video_chroma_median_filter_bottom",
 207                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 208         }
 209 };
 210 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 211
 212
 213 static const char *control_values_srate[] = {
 214         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 215         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 216         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 217 };
 218
 219
 220
 221 static const char *control_values_input[] = {
 222         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 223         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 224         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 225         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 226         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 227 };
 228
 229
 230 static const char *control_values_audiomode[] = {
 231         [V4L2_TUNER_MODE_MONO]   = "Mono",
 232         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 233         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 234         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 235         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 236 };
 237
 238
 239 static const char *control_values_hsm[] = {
 240         [PVR2_CVAL_HSM_FAIL] = "Fail",
 241         [PVR2_CVAL_HSM_HIGH] = "High",
 242         [PVR2_CVAL_HSM_FULL] = "Full",
 243 };
 244
 245
 246 static const char *pvr2_state_names[] = {
 247         [PVR2_STATE_NONE] =    "none",
 248         [PVR2_STATE_DEAD] =    "dead",
 249         [PVR2_STATE_COLD] =    "cold",
 250         [PVR2_STATE_WARM] =    "warm",
 251         [PVR2_STATE_ERROR] =   "error",
 252         [PVR2_STATE_READY] =   "ready",
 253         [PVR2_STATE_RUN] =     "run",
 254 };
 255
 256
 257 struct pvr2_fx2cmd_descdef {
 258         unsigned char id;
 259         unsigned char *desc;
 260 };
 261
 262 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 263         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 264         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 265         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 266         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 267         {FX2CMD_REG_WRITE, "write encoder register"},
 268         {FX2CMD_REG_READ, "read encoder register"},
 269         {FX2CMD_MEMSEL, "encoder memsel"},
 270         {FX2CMD_I2C_WRITE, "i2c write"},
 271         {FX2CMD_I2C_READ, "i2c read"},
 272         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 273         {FX2CMD_STREAMING_ON, "stream on"},
 274         {FX2CMD_STREAMING_OFF, "stream off"},
 275         {FX2CMD_FWPOST1, "fwpost1"},
 276         {FX2CMD_POWER_OFF, "power off"},
 277         {FX2CMD_POWER_ON, "power on"},
 278         {FX2CMD_DEEP_RESET, "deep reset"},
 279         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 280         {FX2CMD_GET_IR_CODE, "get IR code"},
 281         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 282         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 283         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 284         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 285         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 286         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 287         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 288 };
 289
 290
 291 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 292 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 293 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 294 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 295 static void pvr2_hdw_worker_i2c(struct work_struct *work);
 296 static void pvr2_hdw_worker_poll(struct work_struct *work);
 297 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 298 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 299 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 300 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 301 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 302 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 303 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 304 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 305 static void pvr2_hdw_quiescent_timeout(unsigned long);
 306 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 307 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 308 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 309 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 310                                 unsigned int timeout,int probe_fl,
 311                                 void *write_data,unsigned int write_len,
 312                                 void *read_data,unsigned int read_len);
 313 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 314
 315
 316 static void trace_stbit(const char *name,int val)
 317 {
 318         pvr2_trace(PVR2_TRACE_STBITS,
 319                    "State bit %s <-- %s",
 320                    name,(val ? "true" : "false"));
 321 }
 322
 323 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 324 {
 325         struct pvr2_hdw *hdw = cptr->hdw;
 326         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 327                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 328         } else {
 329                 *vp = 0;
 330         }
 331         return 0;
 332 }
 333
 334 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 335 {
 336         struct pvr2_hdw *hdw = cptr->hdw;
 337         unsigned int slotId = hdw->freqProgSlot;
 338         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 339                 hdw->freqTable[slotId-1] = v;
 340                 /* Handle side effects correctly - if we're tuned to this
 341                    slot, then forgot the slot id relation since the stored
 342                    frequency has been changed. */
 343                 if (hdw->freqSelector) {
 344                         if (hdw->freqSlotRadio == slotId) {
 345                                 hdw->freqSlotRadio = 0;
 346                         }
 347                 } else {
 348                         if (hdw->freqSlotTelevision == slotId) {
 349                                 hdw->freqSlotTelevision = 0;
 350                         }
 351                 }
 352         }
 353         return 0;
 354 }
 355
 356 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 357 {
 358         *vp = cptr->hdw->freqProgSlot;
 359         return 0;
 360 }
 361
 362 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 363 {
 364         struct pvr2_hdw *hdw = cptr->hdw;
 365         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 366                 hdw->freqProgSlot = v;
 367         }
 368         return 0;
 369 }
 370
 371 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 372 {
 373         struct pvr2_hdw *hdw = cptr->hdw;
 374         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 375         return 0;
 376 }
 377
 378 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 379 {
 380         unsigned freq = 0;
 381         struct pvr2_hdw *hdw = cptr->hdw;
 382         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 383         if (slotId > 0) {
 384                 freq = hdw->freqTable[slotId-1];
 385                 if (!freq) return 0;
 386                 pvr2_hdw_set_cur_freq(hdw,freq);
 387         }
 388         if (hdw->freqSelector) {
 389                 hdw->freqSlotRadio = slotId;
 390         } else {
 391                 hdw->freqSlotTelevision = slotId;
 392         }
 393         return 0;
 394 }
 395
 396 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 397 {
 398         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 399         return 0;
 400 }
 401
 402 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 403 {
 404         return cptr->hdw->freqDirty != 0;
 405 }
 406
 407 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 408 {
 409         cptr->hdw->freqDirty = 0;
 410 }
 411
 412 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 413 {
 414         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 415         return 0;
 416 }
 417
 418 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 419 {
 420         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 421         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 422         if (stat != 0) {
 423                 return stat;
 424         }
 425         *left = cap->bounds.left;
 426         return 0;
 427 }
 428
 429 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 430 {
 431         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 432         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 433         if (stat != 0) {
 434                 return stat;
 435         }
 436         *left = cap->bounds.left;
 437         if (cap->bounds.width > cptr->hdw->cropw_val) {
 438                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 439         }
 440         return 0;
 441 }
 442
 443 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 444 {
 445         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 446         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 447         if (stat != 0) {
 448                 return stat;
 449         }
 450         *top = cap->bounds.top;
 451         return 0;
 452 }
 453
 454 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 455 {
 456         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 457         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 458         if (stat != 0) {
 459                 return stat;
 460         }
 461         *top = cap->bounds.top;
 462         if (cap->bounds.height > cptr->hdw->croph_val) {
 463                 *top += cap->bounds.height - cptr->hdw->croph_val;
 464         }
 465         return 0;
 466 }
 467
 468 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
 469 {
 470         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 471         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 472         if (stat != 0) {
 473                 return stat;
 474         }
 475         *val = 0;
 476         if (cap->bounds.width > cptr->hdw->cropl_val) {
 477                 *val = cap->bounds.width - cptr->hdw->cropl_val;
 478         }
 479         return 0;
 480 }
 481
 482 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
 483 {
 484         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 485         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 486         if (stat != 0) {
 487                 return stat;
 488         }
 489         *val = 0;
 490         if (cap->bounds.height > cptr->hdw->cropt_val) {
 491                 *val = cap->bounds.height - cptr->hdw->cropt_val;
 492         }
 493         return 0;
 494 }
 495
 496 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 497 {
 498         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 499         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 500         if (stat != 0) {
 501                 return stat;
 502         }
 503         *val = cap->bounds.left;
 504         return 0;
 505 }
 506
 507 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 508 {
 509         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 510         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 511         if (stat != 0) {
 512                 return stat;
 513         }
 514         *val = cap->bounds.top;
 515         return 0;
 516 }
 517
 518 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 519 {
 520         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 521         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 522         if (stat != 0) {
 523                 return stat;
 524         }
 525         *val = cap->bounds.width;
 526         return 0;
 527 }
 528
 529 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 530 {
 531         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 532         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 533         if (stat != 0) {
 534                 return stat;
 535         }
 536         *val = cap->bounds.height;
 537         return 0;
 538 }
 539
 540 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 541 {
 542         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 543         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 544         if (stat != 0) {
 545                 return stat;
 546         }
 547         *val = cap->defrect.left;
 548         return 0;
 549 }
 550
 551 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 552 {
 553         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 554         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 555         if (stat != 0) {
 556                 return stat;
 557         }
 558         *val = cap->defrect.top;
 559         return 0;
 560 }
 561
 562 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 563 {
 564         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 565         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 566         if (stat != 0) {
 567                 return stat;
 568         }
 569         *val = cap->defrect.width;
 570         return 0;
 571 }
 572
 573 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 574 {
 575         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 576         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 577         if (stat != 0) {
 578                 return stat;
 579         }
 580         *val = cap->defrect.height;
 581         return 0;
 582 }
 583
 584 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 585 {
 586         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 587         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 588         if (stat != 0) {
 589                 return stat;
 590         }
 591         *val = cap->pixelaspect.numerator;
 592         return 0;
 593 }
 594
 595 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 596 {
 597         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 598         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 599         if (stat != 0) {
 600                 return stat;
 601         }
 602         *val = cap->pixelaspect.denominator;
 603         return 0;
 604 }
 605
 606 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 607 {
 608         /* Actual maximum depends on the video standard in effect. */
 609         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 610                 *vp = 480;
 611         } else {
 612                 *vp = 576;
 613         }
 614         return 0;
 615 }
 616
 617 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 618 {
 619         /* Actual minimum depends on device digitizer type. */
 620         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 621                 *vp = 75;
 622         } else {
 623                 *vp = 17;
 624         }
 625         return 0;
 626 }
 627
 628 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 629 {
 630         *vp = cptr->hdw->input_val;
 631         return 0;
 632 }
 633
 634 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 635 {
 636         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 637 }
 638
 639 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 640 {
 641         return pvr2_hdw_set_input(cptr->hdw,v);
 642 }
 643
 644 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 645 {
 646         return cptr->hdw->input_dirty != 0;
 647 }
 648
 649 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 650 {
 651         cptr->hdw->input_dirty = 0;
 652 }
 653
 654
 655 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 656 {
 657         unsigned long fv;
 658         struct pvr2_hdw *hdw = cptr->hdw;
 659         if (hdw->tuner_signal_stale) {
 660                 pvr2_hdw_status_poll(hdw);
 661         }
 662         fv = hdw->tuner_signal_info.rangehigh;
 663         if (!fv) {
 664                 /* Safety fallback */
 665                 *vp = TV_MAX_FREQ;
 666                 return 0;
 667         }
 668         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 669                 fv = (fv * 125) / 2;
 670         } else {
 671                 fv = fv * 62500;
 672         }
 673         *vp = fv;
 674         return 0;
 675 }
 676
 677 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 678 {
 679         unsigned long fv;
 680         struct pvr2_hdw *hdw = cptr->hdw;
 681         if (hdw->tuner_signal_stale) {
 682                 pvr2_hdw_status_poll(hdw);
 683         }
 684         fv = hdw->tuner_signal_info.rangelow;
 685         if (!fv) {
 686                 /* Safety fallback */
 687                 *vp = TV_MIN_FREQ;
 688                 return 0;
 689         }
 690         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 691                 fv = (fv * 125) / 2;
 692         } else {
 693                 fv = fv * 62500;
 694         }
 695         *vp = fv;
 696         return 0;
 697 }
 698
 699 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 700 {
 701         return cptr->hdw->enc_stale != 0;
 702 }
 703
 704 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 705 {
 706         cptr->hdw->enc_stale = 0;
 707         cptr->hdw->enc_unsafe_stale = 0;
 708 }
 709
 710 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 711 {
 712         int ret;
 713         struct v4l2_ext_controls cs;
 714         struct v4l2_ext_control c1;
 715         memset(&cs,0,sizeof(cs));
 716         memset(&c1,0,sizeof(c1));
 717         cs.controls = &c1;
 718         cs.count = 1;
 719         c1.id = cptr->info->v4l_id;
 720         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 721                                 VIDIOC_G_EXT_CTRLS);
 722         if (ret) return ret;
 723         *vp = c1.value;
 724         return 0;
 725 }
 726
 727 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 728 {
 729         int ret;
 730         struct pvr2_hdw *hdw = cptr->hdw;
 731         struct v4l2_ext_controls cs;
 732         struct v4l2_ext_control c1;
 733         memset(&cs,0,sizeof(cs));
 734         memset(&c1,0,sizeof(c1));
 735         cs.controls = &c1;
 736         cs.count = 1;
 737         c1.id = cptr->info->v4l_id;
 738         c1.value = v;
 739         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 740                                 hdw->state_encoder_run, &cs,
 741                                 VIDIOC_S_EXT_CTRLS);
 742         if (ret == -EBUSY) {
 743                 /* Oops.  cx2341x is telling us it's not safe to change
 744                    this control while we're capturing.  Make a note of this
 745                    fact so that the pipeline will be stopped the next time
 746                    controls are committed.  Then go on ahead and store this
 747                    change anyway. */
 748                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 749                                         0, &cs,
 750                                         VIDIOC_S_EXT_CTRLS);
 751                 if (!ret) hdw->enc_unsafe_stale = !0;
 752         }
 753         if (ret) return ret;
 754         hdw->enc_stale = !0;
 755         return 0;
 756 }
 757
 758 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 759 {
 760         struct v4l2_queryctrl qctrl;
 761         struct pvr2_ctl_info *info;
 762         qctrl.id = cptr->info->v4l_id;
 763         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 764         /* Strip out the const so we can adjust a function pointer.  It's
 765            OK to do this here because we know this is a dynamically created
 766            control, so the underlying storage for the info pointer is (a)
 767            private to us, and (b) not in read-only storage.  Either we do
 768            this or we significantly complicate the underlying control
 769            implementation. */
 770         info = (struct pvr2_ctl_info *)(cptr->info);
 771         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 772                 if (info->set_value) {
 773                         info->set_value = NULL;
 774                 }
 775         } else {
 776                 if (!(info->set_value)) {
 777                         info->set_value = ctrl_cx2341x_set;
 778                 }
 779         }
 780         return qctrl.flags;
 781 }
 782
 783 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 784 {
 785         *vp = cptr->hdw->state_pipeline_req;
 786         return 0;
 787 }
 788
 789 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 790 {
 791         *vp = cptr->hdw->master_state;
 792         return 0;
 793 }
 794
 795 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 796 {
 797         int result = pvr2_hdw_is_hsm(cptr->hdw);
 798         *vp = PVR2_CVAL_HSM_FULL;
 799         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 800         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 801         return 0;
 802 }
 803
 804 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 805 {
 806         *vp = cptr->hdw->std_mask_avail;
 807         return 0;
 808 }
 809
 810 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 811 {
 812         struct pvr2_hdw *hdw = cptr->hdw;
 813         v4l2_std_id ns;
 814         ns = hdw->std_mask_avail;
 815         ns = (ns & ~m) | (v & m);
 816         if (ns == hdw->std_mask_avail) return 0;
 817         hdw->std_mask_avail = ns;
 818         pvr2_hdw_internal_set_std_avail(hdw);
 819         pvr2_hdw_internal_find_stdenum(hdw);
 820         return 0;
 821 }
 822
 823 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 824                                char *bufPtr,unsigned int bufSize,
 825                                unsigned int *len)
 826 {
 827         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 828         return 0;
 829 }
 830
 831 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 832                                const char *bufPtr,unsigned int bufSize,
 833                                int *mskp,int *valp)
 834 {
 835         int ret;
 836         v4l2_std_id id;
 837         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 838         if (ret < 0) return ret;
 839         if (mskp) *mskp = id;
 840         if (valp) *valp = id;
 841         return 0;
 842 }
 843
 844 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 845 {
 846         *vp = cptr->hdw->std_mask_cur;
 847         return 0;
 848 }
 849
 850 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 851 {
 852         struct pvr2_hdw *hdw = cptr->hdw;
 853         v4l2_std_id ns;
 854         ns = hdw->std_mask_cur;
 855         ns = (ns & ~m) | (v & m);
 856         if (ns == hdw->std_mask_cur) return 0;
 857         hdw->std_mask_cur = ns;
 858         hdw->std_dirty = !0;
 859         pvr2_hdw_internal_find_stdenum(hdw);
 860         return 0;
 861 }
 862
 863 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 864 {
 865         return cptr->hdw->std_dirty != 0;
 866 }
 867
 868 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 869 {
 870         cptr->hdw->std_dirty = 0;
 871 }
 872
 873 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 874 {
 875         struct pvr2_hdw *hdw = cptr->hdw;
 876         pvr2_hdw_status_poll(hdw);
 877         *vp = hdw->tuner_signal_info.signal;
 878         return 0;
 879 }
 880
 881 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 882 {
 883         int val = 0;
 884         unsigned int subchan;
 885         struct pvr2_hdw *hdw = cptr->hdw;
 886         pvr2_hdw_status_poll(hdw);
 887         subchan = hdw->tuner_signal_info.rxsubchans;
 888         if (subchan & V4L2_TUNER_SUB_MONO) {
 889                 val |= (1 << V4L2_TUNER_MODE_MONO);
 890         }
 891         if (subchan & V4L2_TUNER_SUB_STEREO) {
 892                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 893         }
 894         if (subchan & V4L2_TUNER_SUB_LANG1) {
 895                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 896         }
 897         if (subchan & V4L2_TUNER_SUB_LANG2) {
 898                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 899         }
 900         *vp = val;
 901         return 0;
 902 }
 903
 904
 905 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 906 {
 907         struct pvr2_hdw *hdw = cptr->hdw;
 908         if (v < 0) return -EINVAL;
 909         if (v > hdw->std_enum_cnt) return -EINVAL;
 910         hdw->std_enum_cur = v;
 911         if (!v) return 0;
 912         v--;
 913         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 914         hdw->std_mask_cur = hdw->std_defs[v].id;
 915         hdw->std_dirty = !0;
 916         return 0;
 917 }
 918
 919
 920 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 921 {
 922         *vp = cptr->hdw->std_enum_cur;
 923         return 0;
 924 }
 925
 926
 927 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 928 {
 929         return cptr->hdw->std_dirty != 0;
 930 }
 931
 932
 933 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 934 {
 935         cptr->hdw->std_dirty = 0;
 936 }
 937
 938
 939 #define DEFINT(vmin,vmax) \
 940         .type = pvr2_ctl_int, \
 941         .def.type_int.min_value = vmin, \
 942         .def.type_int.max_value = vmax
 943
 944 #define DEFENUM(tab) \
 945         .type = pvr2_ctl_enum, \
 946         .def.type_enum.count = ARRAY_SIZE(tab), \
 947         .def.type_enum.value_names = tab
 948
 949 #define DEFBOOL \
 950         .type = pvr2_ctl_bool
 951
 952 #define DEFMASK(msk,tab) \
 953         .type = pvr2_ctl_bitmask, \
 954         .def.type_bitmask.valid_bits = msk, \
 955         .def.type_bitmask.bit_names = tab
 956
 957 #define DEFREF(vname) \
 958         .set_value = ctrl_set_##vname, \
 959         .get_value = ctrl_get_##vname, \
 960         .is_dirty = ctrl_isdirty_##vname, \
 961         .clear_dirty = ctrl_cleardirty_##vname
 962
 963
 964 #define VCREATE_FUNCS(vname) \
 965 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 966 {*vp = cptr->hdw->vname##_val; return 0;} \
 967 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 968 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 969 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 970 {return cptr->hdw->vname##_dirty != 0;} \
 971 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 972 {cptr->hdw->vname##_dirty = 0;}
 973
 974 VCREATE_FUNCS(brightness)
 975 VCREATE_FUNCS(contrast)
 976 VCREATE_FUNCS(saturation)
 977 VCREATE_FUNCS(hue)
 978 VCREATE_FUNCS(volume)
 979 VCREATE_FUNCS(balance)
 980 VCREATE_FUNCS(bass)
 981 VCREATE_FUNCS(treble)
 982 VCREATE_FUNCS(mute)
 983 VCREATE_FUNCS(cropl)
 984 VCREATE_FUNCS(cropt)
 985 VCREATE_FUNCS(cropw)
 986 VCREATE_FUNCS(croph)
 987 VCREATE_FUNCS(audiomode)
 988 VCREATE_FUNCS(res_hor)
 989 VCREATE_FUNCS(res_ver)
 990 VCREATE_FUNCS(srate)
 991
 992 /* Table definition of all controls which can be manipulated */
 993 static const struct pvr2_ctl_info control_defs[] = {
 994         {
 995                 .v4l_id = V4L2_CID_BRIGHTNESS,
 996                 .desc = "Brightness",
 997                 .name = "brightness",
 998                 .default_value = 128,
 999                 DEFREF(brightness),
1000                 DEFINT(0,255),
1001         },{
1002                 .v4l_id = V4L2_CID_CONTRAST,
1003                 .desc = "Contrast",
1004                 .name = "contrast",
1005                 .default_value = 68,
1006                 DEFREF(contrast),
1007                 DEFINT(0,127),
1008         },{
1009                 .v4l_id = V4L2_CID_SATURATION,
1010                 .desc = "Saturation",
1011                 .name = "saturation",
1012                 .default_value = 64,
1013                 DEFREF(saturation),
1014                 DEFINT(0,127),
1015         },{
1016                 .v4l_id = V4L2_CID_HUE,
1017                 .desc = "Hue",
1018                 .name = "hue",
1019                 .default_value = 0,
1020                 DEFREF(hue),
1021                 DEFINT(-128,127),
1022         },{
1023                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1024                 .desc = "Volume",
1025                 .name = "volume",
1026                 .default_value = 62000,
1027                 DEFREF(volume),
1028                 DEFINT(0,65535),
1029         },{
1030                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1031                 .desc = "Balance",
1032                 .name = "balance",
1033                 .default_value = 0,
1034                 DEFREF(balance),
1035                 DEFINT(-32768,32767),
1036         },{
1037                 .v4l_id = V4L2_CID_AUDIO_BASS,
1038                 .desc = "Bass",
1039                 .name = "bass",
1040                 .default_value = 0,
1041                 DEFREF(bass),
1042                 DEFINT(-32768,32767),
1043         },{
1044                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1045                 .desc = "Treble",
1046                 .name = "treble",
1047                 .default_value = 0,
1048                 DEFREF(treble),
1049                 DEFINT(-32768,32767),
1050         },{
1051                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1052                 .desc = "Mute",
1053                 .name = "mute",
1054                 .default_value = 0,
1055                 DEFREF(mute),
1056                 DEFBOOL,
1057         }, {
1058                 .desc = "Capture crop left margin",
1059                 .name = "crop_left",
1060                 .internal_id = PVR2_CID_CROPL,
1061                 .default_value = 0,
1062                 DEFREF(cropl),
1063                 DEFINT(-129, 340),
1064                 .get_min_value = ctrl_cropl_min_get,
1065                 .get_max_value = ctrl_cropl_max_get,
1066                 .get_def_value = ctrl_get_cropcapdl,
1067         }, {
1068                 .desc = "Capture crop top margin",
1069                 .name = "crop_top",
1070                 .internal_id = PVR2_CID_CROPT,
1071                 .default_value = 0,
1072                 DEFREF(cropt),
1073                 DEFINT(-35, 544),
1074                 .get_min_value = ctrl_cropt_min_get,
1075                 .get_max_value = ctrl_cropt_max_get,
1076                 .get_def_value = ctrl_get_cropcapdt,
1077         }, {
1078                 .desc = "Capture crop width",
1079                 .name = "crop_width",
1080                 .internal_id = PVR2_CID_CROPW,
1081                 .default_value = 720,
1082                 DEFREF(cropw),
1083                 .get_max_value = ctrl_cropw_max_get,
1084                 .get_def_value = ctrl_get_cropcapdw,
1085         }, {
1086                 .desc = "Capture crop height",
1087                 .name = "crop_height",
1088                 .internal_id = PVR2_CID_CROPH,
1089                 .default_value = 480,
1090                 DEFREF(croph),
1091                 .get_max_value = ctrl_croph_max_get,
1092                 .get_def_value = ctrl_get_cropcapdh,
1093         }, {
1094                 .desc = "Capture capability pixel aspect numerator",
1095                 .name = "cropcap_pixel_numerator",
1096                 .internal_id = PVR2_CID_CROPCAPPAN,
1097                 .get_value = ctrl_get_cropcappan,
1098         }, {
1099                 .desc = "Capture capability pixel aspect denominator",
1100                 .name = "cropcap_pixel_denominator",
1101                 .internal_id = PVR2_CID_CROPCAPPAD,
1102                 .get_value = ctrl_get_cropcappad,
1103         }, {
1104                 .desc = "Capture capability bounds top",
1105                 .name = "cropcap_bounds_top",
1106                 .internal_id = PVR2_CID_CROPCAPBT,
1107                 .get_value = ctrl_get_cropcapbt,
1108         }, {
1109                 .desc = "Capture capability bounds left",
1110                 .name = "cropcap_bounds_left",
1111                 .internal_id = PVR2_CID_CROPCAPBL,
1112                 .get_value = ctrl_get_cropcapbl,
1113         }, {
1114                 .desc = "Capture capability bounds width",
1115                 .name = "cropcap_bounds_width",
1116                 .internal_id = PVR2_CID_CROPCAPBW,
1117                 .get_value = ctrl_get_cropcapbw,
1118         }, {
1119                 .desc = "Capture capability bounds height",
1120                 .name = "cropcap_bounds_height",
1121                 .internal_id = PVR2_CID_CROPCAPBH,
1122                 .get_value = ctrl_get_cropcapbh,
1123         },{
1124                 .desc = "Video Source",
1125                 .name = "input",
1126                 .internal_id = PVR2_CID_INPUT,
1127                 .default_value = PVR2_CVAL_INPUT_TV,
1128                 .check_value = ctrl_check_input,
1129                 DEFREF(input),
1130                 DEFENUM(control_values_input),
1131         },{
1132                 .desc = "Audio Mode",
1133                 .name = "audio_mode",
1134                 .internal_id = PVR2_CID_AUDIOMODE,
1135                 .default_value = V4L2_TUNER_MODE_STEREO,
1136                 DEFREF(audiomode),
1137                 DEFENUM(control_values_audiomode),
1138         },{
1139                 .desc = "Horizontal capture resolution",
1140                 .name = "resolution_hor",
1141                 .internal_id = PVR2_CID_HRES,
1142                 .default_value = 720,
1143                 DEFREF(res_hor),
1144                 DEFINT(19,720),
1145         },{
1146                 .desc = "Vertical capture resolution",
1147                 .name = "resolution_ver",
1148                 .internal_id = PVR2_CID_VRES,
1149                 .default_value = 480,
1150                 DEFREF(res_ver),
1151                 DEFINT(17,576),
1152                 /* Hook in check for video standard and adjust maximum
1153                    depending on the standard. */
1154                 .get_max_value = ctrl_vres_max_get,
1155                 .get_min_value = ctrl_vres_min_get,
1156         },{
1157                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1158                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1159                 .desc = "Audio Sampling Frequency",
1160                 .name = "srate",
1161                 DEFREF(srate),
1162                 DEFENUM(control_values_srate),
1163         },{
1164                 .desc = "Tuner Frequency (Hz)",
1165                 .name = "frequency",
1166                 .internal_id = PVR2_CID_FREQUENCY,
1167                 .default_value = 0,
1168                 .set_value = ctrl_freq_set,
1169                 .get_value = ctrl_freq_get,
1170                 .is_dirty = ctrl_freq_is_dirty,
1171                 .clear_dirty = ctrl_freq_clear_dirty,
1172                 DEFINT(0,0),
1173                 /* Hook in check for input value (tv/radio) and adjust
1174                    max/min values accordingly */
1175                 .get_max_value = ctrl_freq_max_get,
1176                 .get_min_value = ctrl_freq_min_get,
1177         },{
1178                 .desc = "Channel",
1179                 .name = "channel",
1180                 .set_value = ctrl_channel_set,
1181                 .get_value = ctrl_channel_get,
1182                 DEFINT(0,FREQTABLE_SIZE),
1183         },{
1184                 .desc = "Channel Program Frequency",
1185                 .name = "freq_table_value",
1186                 .set_value = ctrl_channelfreq_set,
1187                 .get_value = ctrl_channelfreq_get,
1188                 DEFINT(0,0),
1189                 /* Hook in check for input value (tv/radio) and adjust
1190                    max/min values accordingly */
1191                 .get_max_value = ctrl_freq_max_get,
1192                 .get_min_value = ctrl_freq_min_get,
1193         },{
1194                 .desc = "Channel Program ID",
1195                 .name = "freq_table_channel",
1196                 .set_value = ctrl_channelprog_set,
1197                 .get_value = ctrl_channelprog_get,
1198                 DEFINT(0,FREQTABLE_SIZE),
1199         },{
1200                 .desc = "Streaming Enabled",
1201                 .name = "streaming_enabled",
1202                 .get_value = ctrl_streamingenabled_get,
1203                 DEFBOOL,
1204         },{
1205                 .desc = "USB Speed",
1206                 .name = "usb_speed",
1207                 .get_value = ctrl_hsm_get,
1208                 DEFENUM(control_values_hsm),
1209         },{
1210                 .desc = "Master State",
1211                 .name = "master_state",
1212                 .get_value = ctrl_masterstate_get,
1213                 DEFENUM(pvr2_state_names),
1214         },{
1215                 .desc = "Signal Present",
1216                 .name = "signal_present",
1217                 .get_value = ctrl_signal_get,
1218                 DEFINT(0,65535),
1219         },{
1220                 .desc = "Audio Modes Present",
1221                 .name = "audio_modes_present",
1222                 .get_value = ctrl_audio_modes_present_get,
1223                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1224                    v4l.  Nothing outside of this module cares about this,
1225                    but I reuse it in order to also reuse the
1226                    control_values_audiomode string table. */
1227                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1228                          (1 << V4L2_TUNER_MODE_STEREO)|
1229                          (1 << V4L2_TUNER_MODE_LANG1)|
1230                          (1 << V4L2_TUNER_MODE_LANG2)),
1231                         control_values_audiomode),
1232         },{
1233                 .desc = "Video Standards Available Mask",
1234                 .name = "video_standard_mask_available",
1235                 .internal_id = PVR2_CID_STDAVAIL,
1236                 .skip_init = !0,
1237                 .get_value = ctrl_stdavail_get,
1238                 .set_value = ctrl_stdavail_set,
1239                 .val_to_sym = ctrl_std_val_to_sym,
1240                 .sym_to_val = ctrl_std_sym_to_val,
1241                 .type = pvr2_ctl_bitmask,
1242         },{
1243                 .desc = "Video Standards In Use Mask",
1244                 .name = "video_standard_mask_active",
1245                 .internal_id = PVR2_CID_STDCUR,
1246                 .skip_init = !0,
1247                 .get_value = ctrl_stdcur_get,
1248                 .set_value = ctrl_stdcur_set,
1249                 .is_dirty = ctrl_stdcur_is_dirty,
1250                 .clear_dirty = ctrl_stdcur_clear_dirty,
1251                 .val_to_sym = ctrl_std_val_to_sym,
1252                 .sym_to_val = ctrl_std_sym_to_val,
1253                 .type = pvr2_ctl_bitmask,
1254         },{
1255                 .desc = "Video Standard Name",
1256                 .name = "video_standard",
1257                 .internal_id = PVR2_CID_STDENUM,
1258                 .skip_init = !0,
1259                 .get_value = ctrl_stdenumcur_get,
1260                 .set_value = ctrl_stdenumcur_set,
1261                 .is_dirty = ctrl_stdenumcur_is_dirty,
1262                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1263                 .type = pvr2_ctl_enum,
1264         }
1265 };
1266
1267 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1268
1269
1270 const char *pvr2_config_get_name(enum pvr2_config cfg)
1271 {
1272         switch (cfg) {
1273         case pvr2_config_empty: return "empty";
1274         case pvr2_config_mpeg: return "mpeg";
1275         case pvr2_config_vbi: return "vbi";
1276         case pvr2_config_pcm: return "pcm";
1277         case pvr2_config_rawvideo: return "raw video";
1278         }
1279         return "<unknown>";
1280 }
1281
1282
1283 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1284 {
1285         return hdw->usb_dev;
1286 }
1287
1288
1289 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1290 {
1291         return hdw->serial_number;
1292 }
1293
1294
1295 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1296 {
1297         return hdw->bus_info;
1298 }
1299
1300
1301 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1302 {
1303         return hdw->identifier;
1304 }
1305
1306
1307 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1308 {
1309         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1310 }
1311
1312 /* Set the currently tuned frequency and account for all possible
1313    driver-core side effects of this action. */
1314 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1315 {
1316         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1317                 if (hdw->freqSelector) {
1318                         /* Swing over to radio frequency selection */
1319                         hdw->freqSelector = 0;
1320                         hdw->freqDirty = !0;
1321                 }
1322                 if (hdw->freqValRadio != val) {
1323                         hdw->freqValRadio = val;
1324                         hdw->freqSlotRadio = 0;
1325                         hdw->freqDirty = !0;
1326                 }
1327         } else {
1328                 if (!(hdw->freqSelector)) {
1329                         /* Swing over to television frequency selection */
1330                         hdw->freqSelector = 1;
1331                         hdw->freqDirty = !0;
1332                 }
1333                 if (hdw->freqValTelevision != val) {
1334                         hdw->freqValTelevision = val;
1335                         hdw->freqSlotTelevision = 0;
1336                         hdw->freqDirty = !0;
1337                 }
1338         }
1339 }
1340
1341 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1342 {
1343         return hdw->unit_number;
1344 }
1345
1346
1347 /* Attempt to locate one of the given set of files.  Messages are logged
1348    appropriate to what has been found.  The return value will be 0 or
1349    greater on success (it will be the index of the file name found) and
1350    fw_entry will be filled in.  Otherwise a negative error is returned on
1351    failure.  If the return value is -ENOENT then no viable firmware file
1352    could be located. */
1353 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1354                                 const struct firmware **fw_entry,
1355                                 const char *fwtypename,
1356                                 unsigned int fwcount,
1357                                 const char *fwnames[])
1358 {
1359         unsigned int idx;
1360         int ret = -EINVAL;
1361         for (idx = 0; idx < fwcount; idx++) {
1362                 ret = request_firmware(fw_entry,
1363                                        fwnames[idx],
1364                                        &hdw->usb_dev->dev);
1365                 if (!ret) {
1366                         trace_firmware("Located %s firmware: %s;"
1367                                        " uploading...",
1368                                        fwtypename,
1369                                        fwnames[idx]);
1370                         return idx;
1371                 }
1372                 if (ret == -ENOENT) continue;
1373                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1374                            "request_firmware fatal error with code=%d",ret);
1375                 return ret;
1376         }
1377         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1378                    "***WARNING***"
1379                    " Device %s firmware"
1380                    " seems to be missing.",
1381                    fwtypename);
1382         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1383                    "Did you install the pvrusb2 firmware files"
1384                    " in their proper location?");
1385         if (fwcount == 1) {
1386                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1387                            "request_firmware unable to locate %s file %s",
1388                            fwtypename,fwnames[0]);
1389         } else {
1390                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1391                            "request_firmware unable to locate"
1392                            " one of the following %s files:",
1393                            fwtypename);
1394                 for (idx = 0; idx < fwcount; idx++) {
1395                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1396                                    "request_firmware: Failed to find %s",
1397                                    fwnames[idx]);
1398                 }
1399         }
1400         return ret;
1401 }
1402
1403
1404 /*
1405  * pvr2_upload_firmware1().
1406  *
1407  * Send the 8051 firmware to the device.  After the upload, arrange for
1408  * device to re-enumerate.
1409  *
1410  * NOTE : the pointer to the firmware data given by request_firmware()
1411  * is not suitable for an usb transaction.
1412  *
1413  */
1414 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1415 {
1416         const struct firmware *fw_entry = NULL;
1417         void  *fw_ptr;
1418         unsigned int pipe;
1419         int ret;
1420         u16 address;
1421
1422         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1423                 hdw->fw1_state = FW1_STATE_OK;
1424                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1425                            "Connected device type defines"
1426                            " no firmware to upload; ignoring firmware");
1427                 return -ENOTTY;
1428         }
1429
1430         hdw->fw1_state = FW1_STATE_FAILED; // default result
1431
1432         trace_firmware("pvr2_upload_firmware1");
1433
1434         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1435                                    hdw->hdw_desc->fx2_firmware.cnt,
1436                                    hdw->hdw_desc->fx2_firmware.lst);
1437         if (ret < 0) {
1438                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1439                 return ret;
1440         }
1441
1442         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1443         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1444
1445         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1446
1447         if (fw_entry->size != 0x2000){
1448                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1449                 release_firmware(fw_entry);
1450                 return -ENOMEM;
1451         }
1452
1453         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1454         if (fw_ptr == NULL){
1455                 release_firmware(fw_entry);
1456                 return -ENOMEM;
1457         }
1458
1459         /* We have to hold the CPU during firmware upload. */
1460         pvr2_hdw_cpureset_assert(hdw,1);
1461
1462         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1463            chunk. */
1464
1465         ret = 0;
1466         for(address = 0; address < fw_entry->size; address += 0x800) {
1467                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1468                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1469                                        0, fw_ptr, 0x800, HZ);
1470         }
1471
1472         trace_firmware("Upload done, releasing device's CPU");
1473
1474         /* Now release the CPU.  It will disconnect and reconnect later. */
1475         pvr2_hdw_cpureset_assert(hdw,0);
1476
1477         kfree(fw_ptr);
1478         release_firmware(fw_entry);
1479
1480         trace_firmware("Upload done (%d bytes sent)",ret);
1481
1482         /* We should have written 8192 bytes */
1483         if (ret == 8192) {
1484                 hdw->fw1_state = FW1_STATE_RELOAD;
1485                 return 0;
1486         }
1487
1488         return -EIO;
1489 }
1490
1491
1492 /*
1493  * pvr2_upload_firmware2()
1494  *
1495  * This uploads encoder firmware on endpoint 2.
1496  *
1497  */
1498
1499 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1500 {
1501         const struct firmware *fw_entry = NULL;
1502         void  *fw_ptr;
1503         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1504         int actual_length;
1505         int ret = 0;
1506         int fwidx;
1507         static const char *fw_files[] = {
1508                 CX2341X_FIRM_ENC_FILENAME,
1509         };
1510
1511         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1512                 return 0;
1513         }
1514
1515         trace_firmware("pvr2_upload_firmware2");
1516
1517         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1518                                    ARRAY_SIZE(fw_files), fw_files);
1519         if (ret < 0) return ret;
1520         fwidx = ret;
1521         ret = 0;
1522         /* Since we're about to completely reinitialize the encoder,
1523            invalidate our cached copy of its configuration state.  Next
1524            time we configure the encoder, then we'll fully configure it. */
1525         hdw->enc_cur_valid = 0;
1526
1527         /* Encoder is about to be reset so note that as far as we're
1528            concerned now, the encoder has never been run. */
1529         del_timer_sync(&hdw->encoder_run_timer);
1530         if (hdw->state_encoder_runok) {
1531                 hdw->state_encoder_runok = 0;
1532                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1533         }
1534
1535         /* First prepare firmware loading */
1536         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1537         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1538         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1539         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1540         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1541         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1542         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1543         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1544         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1545         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1546         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1547         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1548         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1549         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1550         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1551         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1552         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1553         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1554
1555         if (ret) {
1556                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1557                            "firmware2 upload prep failed, ret=%d",ret);
1558                 release_firmware(fw_entry);
1559                 goto done;
1560         }
1561
1562         /* Now send firmware */
1563
1564         fw_len = fw_entry->size;
1565
1566         if (fw_len % sizeof(u32)) {
1567                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1568                            "size of %s firmware"
1569                            " must be a multiple of %zu bytes",
1570                            fw_files[fwidx],sizeof(u32));
1571                 release_firmware(fw_entry);
1572                 ret = -EINVAL;
1573                 goto done;
1574         }
1575
1576         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1577         if (fw_ptr == NULL){
1578                 release_firmware(fw_entry);
1579                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1580                            "failed to allocate memory for firmware2 upload");
1581                 ret = -ENOMEM;
1582                 goto done;
1583         }
1584
1585         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1586
1587         fw_done = 0;
1588         for (fw_done = 0; fw_done < fw_len;) {
1589                 bcnt = fw_len - fw_done;
1590                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1591                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1592                 /* Usbsnoop log shows that we must swap bytes... */
1593                 /* Some background info: The data being swapped here is a
1594                    firmware image destined for the mpeg encoder chip that
1595                    lives at the other end of a USB endpoint.  The encoder
1596                    chip always talks in 32 bit chunks and its storage is
1597                    organized into 32 bit words.  However from the file
1598                    system to the encoder chip everything is purely a byte
1599                    stream.  The firmware file's contents are always 32 bit
1600                    swapped from what the encoder expects.  Thus the need
1601                    always exists to swap the bytes regardless of the endian
1602                    type of the host processor and therefore swab32() makes
1603                    the most sense. */
1604                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1605                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1606
1607                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1608                                     &actual_length, HZ);
1609                 ret |= (actual_length != bcnt);
1610                 if (ret) break;
1611                 fw_done += bcnt;
1612         }
1613
1614         trace_firmware("upload of %s : %i / %i ",
1615                        fw_files[fwidx],fw_done,fw_len);
1616
1617         kfree(fw_ptr);
1618         release_firmware(fw_entry);
1619
1620         if (ret) {
1621                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1622                            "firmware2 upload transfer failure");
1623                 goto done;
1624         }
1625
1626         /* Finish upload */
1627
1628         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1629         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1630         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1631
1632         if (ret) {
1633                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1634                            "firmware2 upload post-proc failure");
1635         }
1636
1637  done:
1638         if (hdw->hdw_desc->signal_routing_scheme ==
1639             PVR2_ROUTING_SCHEME_GOTVIEW) {
1640                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1641                    hardware. */
1642                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1643         }
1644         return ret;
1645 }
1646
1647
1648 static const char *pvr2_get_state_name(unsigned int st)
1649 {
1650         if (st < ARRAY_SIZE(pvr2_state_names)) {
1651                 return pvr2_state_names[st];
1652         }
1653         return "???";
1654 }
1655
1656 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1657 {
1658         if (!hdw->decoder_ctrl) {
1659                 if (!hdw->flag_decoder_missed) {
1660                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1661                                    "WARNING: No decoder present");
1662                         hdw->flag_decoder_missed = !0;
1663                         trace_stbit("flag_decoder_missed",
1664                                     hdw->flag_decoder_missed);
1665                 }
1666                 return -EIO;
1667         }
1668         hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1669         return 0;
1670 }
1671
1672
1673 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1674 {
1675         if (hdw->decoder_ctrl == ptr) return;
1676         hdw->decoder_ctrl = ptr;
1677         if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1678                 hdw->flag_decoder_missed = 0;
1679                 trace_stbit("flag_decoder_missed",
1680                             hdw->flag_decoder_missed);
1681                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1682                            "Decoder has appeared");
1683                 pvr2_hdw_state_sched(hdw);
1684         }
1685 }
1686
1687
1688 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1689 {
1690         return hdw->master_state;
1691 }
1692
1693
1694 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1695 {
1696         if (!hdw->flag_tripped) return 0;
1697         hdw->flag_tripped = 0;
1698         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1699                    "Clearing driver error statuss");
1700         return !0;
1701 }
1702
1703
1704 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1705 {
1706         int fl;
1707         LOCK_TAKE(hdw->big_lock); do {
1708                 fl = pvr2_hdw_untrip_unlocked(hdw);
1709         } while (0); LOCK_GIVE(hdw->big_lock);
1710         if (fl) pvr2_hdw_state_sched(hdw);
1711         return 0;
1712 }
1713
1714
1715
1716
1717 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1718 {
1719         return hdw->state_pipeline_req != 0;
1720 }
1721
1722
1723 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1724 {
1725         int ret,st;
1726         LOCK_TAKE(hdw->big_lock); do {
1727                 pvr2_hdw_untrip_unlocked(hdw);
1728                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1729                         hdw->state_pipeline_req = enable_flag != 0;
1730                         pvr2_trace(PVR2_TRACE_START_STOP,
1731                                    "/*--TRACE_STREAM--*/ %s",
1732                                    enable_flag ? "enable" : "disable");
1733                 }
1734                 pvr2_hdw_state_sched(hdw);
1735         } while (0); LOCK_GIVE(hdw->big_lock);
1736         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1737         if (enable_flag) {
1738                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1739                         if (st != PVR2_STATE_READY) return -EIO;
1740                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1741                 }
1742         }
1743         return 0;
1744 }
1745
1746
1747 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1748 {
1749         int fl;
1750         LOCK_TAKE(hdw->big_lock);
1751         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1752                 hdw->desired_stream_type = config;
1753                 hdw->state_pipeline_config = 0;
1754                 trace_stbit("state_pipeline_config",
1755                             hdw->state_pipeline_config);
1756                 pvr2_hdw_state_sched(hdw);
1757         }
1758         LOCK_GIVE(hdw->big_lock);
1759         if (fl) return 0;
1760         return pvr2_hdw_wait(hdw,0);
1761 }
1762
1763
1764 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1765 {
1766         int unit_number = hdw->unit_number;
1767         int tp = -1;
1768         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1769                 tp = tuner[unit_number];
1770         }
1771         if (tp < 0) return -EINVAL;
1772         hdw->tuner_type = tp;
1773         hdw->tuner_updated = !0;
1774         return 0;
1775 }
1776
1777
1778 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1779 {
1780         int unit_number = hdw->unit_number;
1781         int tp = 0;
1782         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1783                 tp = video_std[unit_number];
1784                 if (tp) return tp;
1785         }
1786         return 0;
1787 }
1788
1789
1790 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1791 {
1792         int unit_number = hdw->unit_number;
1793         int tp = 0;
1794         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1795                 tp = tolerance[unit_number];
1796         }
1797         return tp;
1798 }
1799
1800
1801 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1802 {
1803         /* Try a harmless request to fetch the eeprom's address over
1804            endpoint 1.  See what happens.  Only the full FX2 image can
1805            respond to this.  If this probe fails then likely the FX2
1806            firmware needs be loaded. */
1807         int result;
1808         LOCK_TAKE(hdw->ctl_lock); do {
1809                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1810                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1811                                            hdw->cmd_buffer,1,
1812                                            hdw->cmd_buffer,1);
1813                 if (result < 0) break;
1814         } while(0); LOCK_GIVE(hdw->ctl_lock);
1815         if (result) {
1816                 pvr2_trace(PVR2_TRACE_INIT,
1817                            "Probe of device endpoint 1 result status %d",
1818                            result);
1819         } else {
1820                 pvr2_trace(PVR2_TRACE_INIT,
1821                            "Probe of device endpoint 1 succeeded");
1822         }
1823         return result == 0;
1824 }
1825
1826 struct pvr2_std_hack {
1827         v4l2_std_id pat;  /* Pattern to match */
1828         v4l2_std_id msk;  /* Which bits we care about */
1829         v4l2_std_id std;  /* What additional standards or default to set */
1830 };
1831
1832 /* This data structure labels specific combinations of standards from
1833    tveeprom that we'll try to recognize.  If we recognize one, then assume
1834    a specified default standard to use.  This is here because tveeprom only
1835    tells us about available standards not the intended default standard (if
1836    any) for the device in question.  We guess the default based on what has
1837    been reported as available.  Note that this is only for guessing a
1838    default - which can always be overridden explicitly - and if the user
1839    has otherwise named a default then that default will always be used in
1840    place of this table. */
1841 static const struct pvr2_std_hack std_eeprom_maps[] = {
1842         {       /* PAL(B/G) */
1843                 .pat = V4L2_STD_B|V4L2_STD_GH,
1844                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1845         },
1846         {       /* NTSC(M) */
1847                 .pat = V4L2_STD_MN,
1848                 .std = V4L2_STD_NTSC_M,
1849         },
1850         {       /* PAL(I) */
1851                 .pat = V4L2_STD_PAL_I,
1852                 .std = V4L2_STD_PAL_I,
1853         },
1854         {       /* SECAM(L/L') */
1855                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1856                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1857         },
1858         {       /* PAL(D/D1/K) */
1859                 .pat = V4L2_STD_DK,
1860                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1861         },
1862 };
1863
1864 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1865 {
1866         char buf[40];
1867         unsigned int bcnt;
1868         v4l2_std_id std1,std2,std3;
1869
1870         std1 = get_default_standard(hdw);
1871         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1872
1873         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1874         pvr2_trace(PVR2_TRACE_STD,
1875                    "Supported video standard(s) reported available"
1876                    " in hardware: %.*s",
1877                    bcnt,buf);
1878
1879         hdw->std_mask_avail = hdw->std_mask_eeprom;
1880
1881         std2 = (std1|std3) & ~hdw->std_mask_avail;
1882         if (std2) {
1883                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1884                 pvr2_trace(PVR2_TRACE_STD,
1885                            "Expanding supported video standards"
1886                            " to include: %.*s",
1887                            bcnt,buf);
1888                 hdw->std_mask_avail |= std2;
1889         }
1890
1891         pvr2_hdw_internal_set_std_avail(hdw);
1892
1893         if (std1) {
1894                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1895                 pvr2_trace(PVR2_TRACE_STD,
1896                            "Initial video standard forced to %.*s",
1897                            bcnt,buf);
1898                 hdw->std_mask_cur = std1;
1899                 hdw->std_dirty = !0;
1900                 pvr2_hdw_internal_find_stdenum(hdw);
1901                 return;
1902         }
1903         if (std3) {
1904                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1905                 pvr2_trace(PVR2_TRACE_STD,
1906                            "Initial video standard"
1907                            " (determined by device type): %.*s",bcnt,buf);
1908                 hdw->std_mask_cur = std3;
1909                 hdw->std_dirty = !0;
1910                 pvr2_hdw_internal_find_stdenum(hdw);
1911                 return;
1912         }
1913
1914         {
1915                 unsigned int idx;
1916                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1917                         if (std_eeprom_maps[idx].msk ?
1918                             ((std_eeprom_maps[idx].pat ^
1919                              hdw->std_mask_eeprom) &
1920                              std_eeprom_maps[idx].msk) :
1921                             (std_eeprom_maps[idx].pat !=
1922                              hdw->std_mask_eeprom)) continue;
1923                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1924                                                   std_eeprom_maps[idx].std);
1925                         pvr2_trace(PVR2_TRACE_STD,
1926                                    "Initial video standard guessed as %.*s",
1927                                    bcnt,buf);
1928                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1929                         hdw->std_dirty = !0;
1930                         pvr2_hdw_internal_find_stdenum(hdw);
1931                         return;
1932                 }
1933         }
1934
1935         if (hdw->std_enum_cnt > 1) {
1936                 // Autoselect the first listed standard
1937                 hdw->std_enum_cur = 1;
1938                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1939                 hdw->std_dirty = !0;
1940                 pvr2_trace(PVR2_TRACE_STD,
1941                            "Initial video standard auto-selected to %s",
1942                            hdw->std_defs[hdw->std_enum_cur-1].name);
1943                 return;
1944         }
1945
1946         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1947                    "Unable to select a viable initial video standard");
1948 }
1949
1950
1951 static unsigned int pvr2_copy_i2c_addr_list(
1952         unsigned short *dst, const unsigned char *src,
1953         unsigned int dst_max)
1954 {
1955         unsigned int cnt;
1956         if (!src) return 0;
1957         while (src[cnt] && (cnt + 1) < dst_max) {
1958                 dst[cnt] = src[cnt];
1959                 cnt++;
1960         }
1961         dst[cnt] = I2C_CLIENT_END;
1962         return cnt;
1963 }
1964
1965
1966 static void pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1967                                  const struct pvr2_device_client_desc *cd)
1968 {
1969         const char *fname;
1970         unsigned char mid;
1971         struct v4l2_subdev *sd;
1972         unsigned int i2ccnt;
1973         const unsigned char *p;
1974         /* Arbitrary count - max # i2c addresses we will probe */
1975         unsigned short i2caddr[25];
1976
1977         mid = cd->module_id;
1978         fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
1979         if (!fname) {
1980                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1981                            "Module ID %u for device %s is unknown"
1982                            " (this is probably a bad thing...)",
1983                            mid,
1984                            hdw->hdw_desc->description);
1985                 return;
1986         }
1987
1988         i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
1989                                          ARRAY_SIZE(i2caddr));
1990         if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
1991                          module_i2c_addresses[mid] : NULL) != NULL)) {
1992                 /* Second chance: Try default i2c address list */
1993                 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
1994                                                  ARRAY_SIZE(i2caddr));
1995         }
1996
1997         if (!i2ccnt) {
1998                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1999                            "Module ID %u for device %s:"
2000                            " No i2c addresses"
2001                            " (this is probably a bad thing...)",
2002                            mid, hdw->hdw_desc->description);
2003                 return;
2004         }
2005
2006         /* Note how the 2nd and 3rd arguments are the same for both
2007          * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev().  Why?
2008          * Well the 2nd argument is the module name to load, while the 3rd
2009          * argument is documented in the framework as being the "chipid" -
2010          * and every other place where I can find examples of this, the
2011          * "chipid" appears to just be the module name again.  So here we
2012          * just do the same thing. */
2013         if (i2ccnt == 1) {
2014                 sd = v4l2_i2c_new_subdev(&hdw->i2c_adap,
2015                                          fname, fname,
2016                                          i2caddr[0]);
2017         } else {
2018                 sd = v4l2_i2c_new_probed_subdev(&hdw->i2c_adap,
2019                                                 fname, fname,
2020                                                 i2caddr);
2021         }
2022
2023         if (!sd) {
2024                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2025                            "Module ID %u for device %s failed to load"
2026                            " (this is probably a bad thing...)",
2027                            mid, hdw->hdw_desc->description);
2028                 return;
2029         }
2030
2031         /* Tag this sub-device instance with the module ID we know about.
2032            In other places we'll use that tag to determine if the instance
2033            requires special handling. */
2034         sd->grp_id = mid;
2035
2036         /* If we have both old and new i2c layers enabled, make sure that
2037            old layer isn't also tracking this module.  This is a debugging
2038            aid, in normal situations there's no reason for both mechanisms
2039            to be enabled. */
2040         pvr2_i2c_untrack_subdev(hdw, sd);
2041         pvr2_trace(PVR2_TRACE_INIT, "Attached sub-driver %s", fname);
2042
2043
2044 }
2045
2046
2047 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2048 {
2049         unsigned int idx;
2050         const struct pvr2_string_table *cm;
2051         const struct pvr2_device_client_table *ct;
2052
2053         cm = &hdw->hdw_desc->client_modules;
2054         for (idx = 0; idx < cm->cnt; idx++) {
2055                 request_module(cm->lst[idx]);
2056         }
2057
2058         ct = &hdw->hdw_desc->client_table;
2059         for (idx = 0; idx < ct->cnt; idx++) {
2060                 pvr2_hdw_load_subdev(hdw,&ct->lst[idx]);
2061         }
2062 }
2063
2064
2065 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2066 {
2067         int ret;
2068         unsigned int idx;
2069         struct pvr2_ctrl *cptr;
2070         int reloadFl = 0;
2071         if (hdw->hdw_desc->fx2_firmware.cnt) {
2072                 if (!reloadFl) {
2073                         reloadFl =
2074                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2075                                  == 0);
2076                         if (reloadFl) {
2077                                 pvr2_trace(PVR2_TRACE_INIT,
2078                                            "USB endpoint config looks strange"
2079                                            "; possibly firmware needs to be"
2080                                            " loaded");
2081                         }
2082                 }
2083                 if (!reloadFl) {
2084                         reloadFl = !pvr2_hdw_check_firmware(hdw);
2085                         if (reloadFl) {
2086                                 pvr2_trace(PVR2_TRACE_INIT,
2087                                            "Check for FX2 firmware failed"
2088                                            "; possibly firmware needs to be"
2089                                            " loaded");
2090                         }
2091                 }
2092                 if (reloadFl) {
2093                         if (pvr2_upload_firmware1(hdw) != 0) {
2094                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2095                                            "Failure uploading firmware1");
2096                         }
2097                         return;
2098                 }
2099         }
2100         hdw->fw1_state = FW1_STATE_OK;
2101
2102         if (!pvr2_hdw_dev_ok(hdw)) return;
2103
2104         if (!hdw->hdw_desc->flag_no_powerup) {
2105                 pvr2_hdw_cmd_powerup(hdw);
2106                 if (!pvr2_hdw_dev_ok(hdw)) return;
2107         }
2108
2109         /* Take the IR chip out of reset, if appropriate */
2110         if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
2111                 pvr2_issue_simple_cmd(hdw,
2112                                       FX2CMD_HCW_ZILOG_RESET |
2113                                       (1 << 8) |
2114                                       ((0) << 16));
2115         }
2116
2117         // This step MUST happen after the earlier powerup step.
2118         pvr2_i2c_track_init(hdw);
2119         pvr2_i2c_core_init(hdw);
2120         if (!pvr2_hdw_dev_ok(hdw)) return;
2121
2122         pvr2_hdw_load_modules(hdw);
2123
2124         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2125                 cptr = hdw->controls + idx;
2126                 if (cptr->info->skip_init) continue;
2127                 if (!cptr->info->set_value) continue;
2128                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2129         }
2130
2131         /* Set up special default values for the television and radio
2132            frequencies here.  It's not really important what these defaults
2133            are, but I set them to something usable in the Chicago area just
2134            to make driver testing a little easier. */
2135
2136         hdw->freqValTelevision = default_tv_freq;
2137         hdw->freqValRadio = default_radio_freq;
2138
2139         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2140         // thread-safe against the normal pvr2_send_request() mechanism.
2141         // (We should make it thread safe).
2142
2143         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2144                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2145                 if (!pvr2_hdw_dev_ok(hdw)) return;
2146                 if (ret < 0) {
2147                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2148                                    "Unable to determine location of eeprom,"
2149                                    " skipping");
2150                 } else {
2151                         hdw->eeprom_addr = ret;
2152                         pvr2_eeprom_analyze(hdw);
2153                         if (!pvr2_hdw_dev_ok(hdw)) return;
2154                 }
2155         } else {
2156                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2157                 hdw->tuner_updated = !0;
2158                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2159         }
2160
2161         if (hdw->serial_number) {
2162                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2163                                 "sn-%lu", hdw->serial_number);
2164         } else if (hdw->unit_number >= 0) {
2165                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2166                                 "unit-%c",
2167                                 hdw->unit_number + 'a');
2168         } else {
2169                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2170                                 "unit-??");
2171         }
2172         hdw->identifier[idx] = 0;
2173
2174         pvr2_hdw_setup_std(hdw);
2175
2176         if (!get_default_tuner_type(hdw)) {
2177                 pvr2_trace(PVR2_TRACE_INIT,
2178                            "pvr2_hdw_setup: Tuner type overridden to %d",
2179                            hdw->tuner_type);
2180         }
2181
2182         pvr2_i2c_core_check_stale(hdw);
2183         hdw->tuner_updated = 0;
2184
2185         if (!pvr2_hdw_dev_ok(hdw)) return;
2186
2187         if (hdw->hdw_desc->signal_routing_scheme ==
2188             PVR2_ROUTING_SCHEME_GOTVIEW) {
2189                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2190                    hardware. */
2191                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2192         }
2193
2194         pvr2_hdw_commit_setup(hdw);
2195
2196         hdw->vid_stream = pvr2_stream_create();
2197         if (!pvr2_hdw_dev_ok(hdw)) return;
2198         pvr2_trace(PVR2_TRACE_INIT,
2199                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2200         if (hdw->vid_stream) {
2201                 idx = get_default_error_tolerance(hdw);
2202                 if (idx) {
2203                         pvr2_trace(PVR2_TRACE_INIT,
2204                                    "pvr2_hdw_setup: video stream %p"
2205                                    " setting tolerance %u",
2206                                    hdw->vid_stream,idx);
2207                 }
2208                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2209                                   PVR2_VID_ENDPOINT,idx);
2210         }
2211
2212         if (!pvr2_hdw_dev_ok(hdw)) return;
2213
2214         hdw->flag_init_ok = !0;
2215
2216         pvr2_hdw_state_sched(hdw);
2217 }
2218
2219
2220 /* Set up the structure and attempt to put the device into a usable state.
2221    This can be a time-consuming operation, which is why it is not done
2222    internally as part of the create() step. */
2223 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2224 {
2225         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2226         do {
2227                 pvr2_hdw_setup_low(hdw);
2228                 pvr2_trace(PVR2_TRACE_INIT,
2229                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2230                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2231                 if (pvr2_hdw_dev_ok(hdw)) {
2232                         if (hdw->flag_init_ok) {
2233                                 pvr2_trace(
2234                                         PVR2_TRACE_INFO,
2235                                         "Device initialization"
2236                                         " completed successfully.");
2237                                 break;
2238                         }
2239                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2240                                 pvr2_trace(
2241                                         PVR2_TRACE_INFO,
2242                                         "Device microcontroller firmware"
2243                                         " (re)loaded; it should now reset"
2244                                         " and reconnect.");
2245                                 break;
2246                         }
2247                         pvr2_trace(
2248                                 PVR2_TRACE_ERROR_LEGS,
2249                                 "Device initialization was not successful.");
2250                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2251                                 pvr2_trace(
2252                                         PVR2_TRACE_ERROR_LEGS,
2253                                         "Giving up since device"
2254                                         " microcontroller firmware"
2255                                         " appears to be missing.");
2256                                 break;
2257                         }
2258                 }
2259                 if (procreload) {
2260                         pvr2_trace(
2261                                 PVR2_TRACE_ERROR_LEGS,
2262                                 "Attempting pvrusb2 recovery by reloading"
2263                                 " primary firmware.");
2264                         pvr2_trace(
2265                                 PVR2_TRACE_ERROR_LEGS,
2266                                 "If this works, device should disconnect"
2267                                 " and reconnect in a sane state.");
2268                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2269                         pvr2_upload_firmware1(hdw);
2270                 } else {
2271                         pvr2_trace(
2272                                 PVR2_TRACE_ERROR_LEGS,
2273                                 "***WARNING*** pvrusb2 device hardware"
2274                                 " appears to be jammed"
2275                                 " and I can't clear it.");
2276                         pvr2_trace(
2277                                 PVR2_TRACE_ERROR_LEGS,
2278                                 "You might need to power cycle"
2279                                 " the pvrusb2 device"
2280                                 " in order to recover.");
2281                 }
2282         } while (0);
2283         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2284 }
2285
2286
2287 /* Perform second stage initialization.  Set callback pointer first so that
2288    we can avoid a possible initialization race (if the kernel thread runs
2289    before the callback has been set). */
2290 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2291                         void (*callback_func)(void *),
2292                         void *callback_data)
2293 {
2294         LOCK_TAKE(hdw->big_lock); do {
2295                 if (hdw->flag_disconnected) {
2296                         /* Handle a race here: If we're already
2297                            disconnected by this point, then give up.  If we
2298                            get past this then we'll remain connected for
2299                            the duration of initialization since the entire
2300                            initialization sequence is now protected by the
2301                            big_lock. */
2302                         break;
2303                 }
2304                 hdw->state_data = callback_data;
2305                 hdw->state_func = callback_func;
2306                 pvr2_hdw_setup(hdw);
2307         } while (0); LOCK_GIVE(hdw->big_lock);
2308         return hdw->flag_init_ok;
2309 }
2310
2311
2312 /* Create, set up, and return a structure for interacting with the
2313    underlying hardware.  */
2314 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2315                                  const struct usb_device_id *devid)
2316 {
2317         unsigned int idx,cnt1,cnt2,m;
2318         struct pvr2_hdw *hdw = NULL;
2319         int valid_std_mask;
2320         struct pvr2_ctrl *cptr;
2321         struct usb_device *usb_dev;
2322         const struct pvr2_device_desc *hdw_desc;
2323         __u8 ifnum;
2324         struct v4l2_queryctrl qctrl;
2325         struct pvr2_ctl_info *ciptr;
2326
2327         usb_dev = interface_to_usbdev(intf);
2328
2329         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2330
2331         if (hdw_desc == NULL) {
2332                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2333                            " No device description pointer,"
2334                            " unable to continue.");
2335                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2336                            " please contact Mike Isely <isely@pobox.com>"
2337                            " to get it included in the driver\n");
2338                 goto fail;
2339         }
2340
2341         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2342         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2343                    hdw,hdw_desc->description);
2344         if (!hdw) goto fail;
2345
2346         init_timer(&hdw->quiescent_timer);
2347         hdw->quiescent_timer.data = (unsigned long)hdw;
2348         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2349
2350         init_timer(&hdw->encoder_wait_timer);
2351         hdw->encoder_wait_timer.data = (unsigned long)hdw;
2352         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2353
2354         init_timer(&hdw->encoder_run_timer);
2355         hdw->encoder_run_timer.data = (unsigned long)hdw;
2356         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2357
2358         hdw->master_state = PVR2_STATE_DEAD;
2359
2360         init_waitqueue_head(&hdw->state_wait_data);
2361
2362         hdw->tuner_signal_stale = !0;
2363         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2364
2365         /* Calculate which inputs are OK */
2366         m = 0;
2367         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2368         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2369                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2370         }
2371         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2372         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2373         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2374         hdw->input_avail_mask = m;
2375         hdw->input_allowed_mask = hdw->input_avail_mask;
2376
2377         /* If not a hybrid device, pathway_state never changes.  So
2378            initialize it here to what it should forever be. */
2379         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2380                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2381         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2382                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2383         }
2384
2385         hdw->control_cnt = CTRLDEF_COUNT;
2386         hdw->control_cnt += MPEGDEF_COUNT;
2387         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2388                                 GFP_KERNEL);
2389         if (!hdw->controls) goto fail;
2390         hdw->hdw_desc = hdw_desc;
2391         for (idx = 0; idx < hdw->control_cnt; idx++) {
2392                 cptr = hdw->controls + idx;
2393                 cptr->hdw = hdw;
2394         }
2395         for (idx = 0; idx < 32; idx++) {
2396                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2397         }
2398         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2399                 cptr = hdw->controls + idx;
2400                 cptr->info = control_defs+idx;
2401         }
2402
2403         /* Ensure that default input choice is a valid one. */
2404         m = hdw->input_avail_mask;
2405         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2406                 if (!((1 << idx) & m)) continue;
2407                 hdw->input_val = idx;
2408                 break;
2409         }
2410
2411         /* Define and configure additional controls from cx2341x module. */
2412         hdw->mpeg_ctrl_info = kzalloc(
2413                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2414         if (!hdw->mpeg_ctrl_info) goto fail;
2415         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2416                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2417                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2418                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2419                 ciptr->name = mpeg_ids[idx].strid;
2420                 ciptr->v4l_id = mpeg_ids[idx].id;
2421                 ciptr->skip_init = !0;
2422                 ciptr->get_value = ctrl_cx2341x_get;
2423                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2424                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2425                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2426                 qctrl.id = ciptr->v4l_id;
2427                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2428                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2429                         ciptr->set_value = ctrl_cx2341x_set;
2430                 }
2431                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2432                         PVR2_CTLD_INFO_DESC_SIZE);
2433                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2434                 ciptr->default_value = qctrl.default_value;
2435                 switch (qctrl.type) {
2436                 default:
2437                 case V4L2_CTRL_TYPE_INTEGER:
2438                         ciptr->type = pvr2_ctl_int;
2439                         ciptr->def.type_int.min_value = qctrl.minimum;
2440                         ciptr->def.type_int.max_value = qctrl.maximum;
2441                         break;
2442                 case V4L2_CTRL_TYPE_BOOLEAN:
2443                         ciptr->type = pvr2_ctl_bool;
2444                         break;
2445                 case V4L2_CTRL_TYPE_MENU:
2446                         ciptr->type = pvr2_ctl_enum;
2447                         ciptr->def.type_enum.value_names =
2448                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2449                                                                 ciptr->v4l_id);
2450                         for (cnt1 = 0;
2451                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2452                              cnt1++) { }
2453                         ciptr->def.type_enum.count = cnt1;
2454                         break;
2455                 }
2456                 cptr->info = ciptr;
2457         }
2458
2459         // Initialize video standard enum dynamic control
2460         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2461         if (cptr) {
2462                 memcpy(&hdw->std_info_enum,cptr->info,
2463                        sizeof(hdw->std_info_enum));
2464                 cptr->info = &hdw->std_info_enum;
2465
2466         }
2467         // Initialize control data regarding video standard masks
2468         valid_std_mask = pvr2_std_get_usable();
2469         for (idx = 0; idx < 32; idx++) {
2470                 if (!(valid_std_mask & (1 << idx))) continue;
2471                 cnt1 = pvr2_std_id_to_str(
2472                         hdw->std_mask_names[idx],
2473                         sizeof(hdw->std_mask_names[idx])-1,
2474                         1 << idx);
2475                 hdw->std_mask_names[idx][cnt1] = 0;
2476         }
2477         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2478         if (cptr) {
2479                 memcpy(&hdw->std_info_avail,cptr->info,
2480                        sizeof(hdw->std_info_avail));
2481                 cptr->info = &hdw->std_info_avail;
2482                 hdw->std_info_avail.def.type_bitmask.bit_names =
2483                         hdw->std_mask_ptrs;
2484                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2485                         valid_std_mask;
2486         }
2487         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2488         if (cptr) {
2489                 memcpy(&hdw->std_info_cur,cptr->info,
2490                        sizeof(hdw->std_info_cur));
2491                 cptr->info = &hdw->std_info_cur;
2492                 hdw->std_info_cur.def.type_bitmask.bit_names =
2493                         hdw->std_mask_ptrs;
2494                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2495                         valid_std_mask;
2496         }
2497
2498         hdw->cropcap_stale = !0;
2499         hdw->eeprom_addr = -1;
2500         hdw->unit_number = -1;
2501         hdw->v4l_minor_number_video = -1;
2502         hdw->v4l_minor_number_vbi = -1;
2503         hdw->v4l_minor_number_radio = -1;
2504         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2505         if (!hdw->ctl_write_buffer) goto fail;
2506         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2507         if (!hdw->ctl_read_buffer) goto fail;
2508         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2509         if (!hdw->ctl_write_urb) goto fail;
2510         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2511         if (!hdw->ctl_read_urb) goto fail;
2512
2513         if (v4l2_device_register(&usb_dev->dev, &hdw->v4l2_dev) != 0) {
2514                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2515                            "Error registering with v4l core, giving up");
2516                 goto fail;
2517         }
2518         mutex_lock(&pvr2_unit_mtx); do {
2519                 for (idx = 0; idx < PVR_NUM; idx++) {
2520                         if (unit_pointers[idx]) continue;
2521                         hdw->unit_number = idx;
2522                         unit_pointers[idx] = hdw;
2523                         break;
2524                 }
2525         } while (0); mutex_unlock(&pvr2_unit_mtx);
2526
2527         cnt1 = 0;
2528         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2529         cnt1 += cnt2;
2530         if (hdw->unit_number >= 0) {
2531                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2532                                  ('a' + hdw->unit_number));
2533                 cnt1 += cnt2;
2534         }
2535         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2536         hdw->name[cnt1] = 0;
2537
2538         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2539         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2540         INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2541
2542         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2543                    hdw->unit_number,hdw->name);
2544
2545         hdw->tuner_type = -1;
2546         hdw->flag_ok = !0;
2547
2548         hdw->usb_intf = intf;
2549         hdw->usb_dev = usb_dev;
2550
2551         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2552
2553         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2554         usb_set_interface(hdw->usb_dev,ifnum,0);
2555
2556         mutex_init(&hdw->ctl_lock_mutex);
2557         mutex_init(&hdw->big_lock_mutex);
2558
2559         return hdw;
2560  fail:
2561         if (hdw) {
2562                 del_timer_sync(&hdw->quiescent_timer);
2563                 del_timer_sync(&hdw->encoder_run_timer);
2564                 del_timer_sync(&hdw->encoder_wait_timer);
2565                 if (hdw->workqueue) {
2566                         flush_workqueue(hdw->workqueue);
2567                         destroy_workqueue(hdw->workqueue);
2568                         hdw->workqueue = NULL;
2569                 }
2570                 usb_free_urb(hdw->ctl_read_urb);
2571                 usb_free_urb(hdw->ctl_write_urb);
2572                 kfree(hdw->ctl_read_buffer);
2573                 kfree(hdw->ctl_write_buffer);
2574                 kfree(hdw->controls);
2575                 kfree(hdw->mpeg_ctrl_info);
2576                 kfree(hdw->std_defs);
2577                 kfree(hdw->std_enum_names);
2578                 kfree(hdw);
2579         }
2580         return NULL;
2581 }
2582
2583
2584 /* Remove _all_ associations between this driver and the underlying USB
2585    layer. */
2586 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2587 {
2588         if (hdw->flag_disconnected) return;
2589         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2590         if (hdw->ctl_read_urb) {
2591                 usb_kill_urb(hdw->ctl_read_urb);
2592                 usb_free_urb(hdw->ctl_read_urb);
2593                 hdw->ctl_read_urb = NULL;
2594         }
2595         if (hdw->ctl_write_urb) {
2596                 usb_kill_urb(hdw->ctl_write_urb);
2597                 usb_free_urb(hdw->ctl_write_urb);
2598                 hdw->ctl_write_urb = NULL;
2599         }
2600         if (hdw->ctl_read_buffer) {
2601                 kfree(hdw->ctl_read_buffer);
2602                 hdw->ctl_read_buffer = NULL;
2603         }
2604         if (hdw->ctl_write_buffer) {
2605                 kfree(hdw->ctl_write_buffer);
2606                 hdw->ctl_write_buffer = NULL;
2607         }
2608         hdw->flag_disconnected = !0;
2609         /* If we don't do this, then there will be a dangling struct device
2610            reference to our disappearing device persisting inside the V4L
2611            core... */
2612         if (hdw->v4l2_dev.dev) {
2613                 dev_set_drvdata(hdw->v4l2_dev.dev, NULL);
2614                 hdw->v4l2_dev.dev = NULL;
2615         }
2616         hdw->usb_dev = NULL;
2617         hdw->usb_intf = NULL;
2618         pvr2_hdw_render_useless(hdw);
2619 }
2620
2621
2622 /* Destroy hardware interaction structure */
2623 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2624 {
2625         if (!hdw) return;
2626         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2627         if (hdw->workqueue) {
2628                 flush_workqueue(hdw->workqueue);
2629                 destroy_workqueue(hdw->workqueue);
2630                 hdw->workqueue = NULL;
2631         }
2632         del_timer_sync(&hdw->quiescent_timer);
2633         del_timer_sync(&hdw->encoder_run_timer);
2634         del_timer_sync(&hdw->encoder_wait_timer);
2635         if (hdw->fw_buffer) {
2636                 kfree(hdw->fw_buffer);
2637                 hdw->fw_buffer = NULL;
2638         }
2639         if (hdw->vid_stream) {
2640                 pvr2_stream_destroy(hdw->vid_stream);
2641                 hdw->vid_stream = NULL;
2642         }
2643         if (hdw->decoder_ctrl) {
2644                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2645         }
2646         pvr2_i2c_core_done(hdw);
2647         pvr2_i2c_track_done(hdw);
2648         v4l2_device_unregister(&hdw->v4l2_dev);
2649         pvr2_hdw_remove_usb_stuff(hdw);
2650         mutex_lock(&pvr2_unit_mtx); do {
2651                 if ((hdw->unit_number >= 0) &&
2652                     (hdw->unit_number < PVR_NUM) &&
2653                     (unit_pointers[hdw->unit_number] == hdw)) {
2654                         unit_pointers[hdw->unit_number] = NULL;
2655                 }
2656         } while (0); mutex_unlock(&pvr2_unit_mtx);
2657         kfree(hdw->controls);
2658         kfree(hdw->mpeg_ctrl_info);
2659         kfree(hdw->std_defs);
2660         kfree(hdw->std_enum_names);
2661         kfree(hdw);
2662 }
2663
2664
2665 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2666 {
2667         return (hdw && hdw->flag_ok);
2668 }
2669
2670
2671 /* Called when hardware has been unplugged */
2672 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2673 {
2674         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2675         LOCK_TAKE(hdw->big_lock);
2676         LOCK_TAKE(hdw->ctl_lock);
2677         pvr2_hdw_remove_usb_stuff(hdw);
2678         LOCK_GIVE(hdw->ctl_lock);
2679         LOCK_GIVE(hdw->big_lock);
2680 }
2681
2682
2683 // Attempt to autoselect an appropriate value for std_enum_cur given
2684 // whatever is currently in std_mask_cur
2685 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2686 {
2687         unsigned int idx;
2688         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2689                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2690                         hdw->std_enum_cur = idx;
2691                         return;
2692                 }
2693         }
2694         hdw->std_enum_cur = 0;
2695 }
2696
2697
2698 // Calculate correct set of enumerated standards based on currently known
2699 // set of available standards bits.
2700 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2701 {
2702         struct v4l2_standard *newstd;
2703         unsigned int std_cnt;
2704         unsigned int idx;
2705
2706         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2707
2708         if (hdw->std_defs) {
2709                 kfree(hdw->std_defs);
2710                 hdw->std_defs = NULL;
2711         }
2712         hdw->std_enum_cnt = 0;
2713         if (hdw->std_enum_names) {
2714                 kfree(hdw->std_enum_names);
2715                 hdw->std_enum_names = NULL;
2716         }
2717
2718         if (!std_cnt) {
2719                 pvr2_trace(
2720                         PVR2_TRACE_ERROR_LEGS,
2721                         "WARNING: Failed to identify any viable standards");
2722         }
2723         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2724         hdw->std_enum_names[0] = "none";
2725         for (idx = 0; idx < std_cnt; idx++) {
2726                 hdw->std_enum_names[idx+1] =
2727                         newstd[idx].name;
2728         }
2729         // Set up the dynamic control for this standard
2730         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2731         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2732         hdw->std_defs = newstd;
2733         hdw->std_enum_cnt = std_cnt+1;
2734         hdw->std_enum_cur = 0;
2735         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2736 }
2737
2738
2739 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2740                                struct v4l2_standard *std,
2741                                unsigned int idx)
2742 {
2743         int ret = -EINVAL;
2744         if (!idx) return ret;
2745         LOCK_TAKE(hdw->big_lock); do {
2746                 if (idx >= hdw->std_enum_cnt) break;
2747                 idx--;
2748                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2749                 ret = 0;
2750         } while (0); LOCK_GIVE(hdw->big_lock);
2751         return ret;
2752 }
2753
2754
2755 /* Get the number of defined controls */
2756 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2757 {
2758         return hdw->control_cnt;
2759 }
2760
2761
2762 /* Retrieve a control handle given its index (0..count-1) */
2763 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2764                                              unsigned int idx)
2765 {
2766         if (idx >= hdw->control_cnt) return NULL;
2767         return hdw->controls + idx;
2768 }
2769
2770
2771 /* Retrieve a control handle given its index (0..count-1) */
2772 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2773                                           unsigned int ctl_id)
2774 {
2775         struct pvr2_ctrl *cptr;
2776         unsigned int idx;
2777         int i;
2778
2779         /* This could be made a lot more efficient, but for now... */
2780         for (idx = 0; idx < hdw->control_cnt; idx++) {
2781                 cptr = hdw->controls + idx;
2782                 i = cptr->info->internal_id;
2783                 if (i && (i == ctl_id)) return cptr;
2784         }
2785         return NULL;
2786 }
2787
2788
2789 /* Given a V4L ID, retrieve the control structure associated with it. */
2790 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2791 {
2792         struct pvr2_ctrl *cptr;
2793         unsigned int idx;
2794         int i;
2795
2796         /* This could be made a lot more efficient, but for now... */
2797         for (idx = 0; idx < hdw->control_cnt; idx++) {
2798                 cptr = hdw->controls + idx;
2799                 i = cptr->info->v4l_id;
2800                 if (i && (i == ctl_id)) return cptr;
2801         }
2802         return NULL;
2803 }
2804
2805
2806 /* Given a V4L ID for its immediate predecessor, retrieve the control
2807    structure associated with it. */
2808 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2809                                             unsigned int ctl_id)
2810 {
2811         struct pvr2_ctrl *cptr,*cp2;
2812         unsigned int idx;
2813         int i;
2814
2815         /* This could be made a lot more efficient, but for now... */
2816         cp2 = NULL;
2817         for (idx = 0; idx < hdw->control_cnt; idx++) {
2818                 cptr = hdw->controls + idx;
2819                 i = cptr->info->v4l_id;
2820                 if (!i) continue;
2821                 if (i <= ctl_id) continue;
2822                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2823                 cp2 = cptr;
2824         }
2825         return cp2;
2826         return NULL;
2827 }
2828
2829
2830 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2831 {
2832         switch (tp) {
2833         case pvr2_ctl_int: return "integer";
2834         case pvr2_ctl_enum: return "enum";
2835         case pvr2_ctl_bool: return "boolean";
2836         case pvr2_ctl_bitmask: return "bitmask";
2837         }
2838         return "";
2839 }
2840
2841
2842 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2843                                     const char *name, int val)
2844 {
2845         struct v4l2_control ctrl;
2846         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2847         memset(&ctrl, 0, sizeof(ctrl));
2848         ctrl.id = id;
2849         ctrl.value = val;
2850         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2851 }
2852
2853 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2854         if ((hdw)->lab##_dirty) { \
2855                 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2856         }
2857
2858 /* Execute whatever commands are required to update the state of all the
2859    sub-devices so that they match our current control values. */
2860 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2861 {
2862         if (hdw->input_dirty || hdw->std_dirty) {
2863                 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_standard");
2864                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2865                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2866                                              tuner, s_radio);
2867                 } else {
2868                         v4l2_std_id vs;
2869                         vs = hdw->std_mask_cur;
2870                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2871                                              tuner, s_std, vs);
2872                 }
2873                 hdw->tuner_signal_stale = !0;
2874                 hdw->cropcap_stale = !0;
2875         }
2876
2877         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2878         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2879         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2880         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2881         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2882         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2883         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2884         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2885         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2886
2887         if (hdw->input_dirty || hdw->audiomode_dirty) {
2888                 struct v4l2_tuner vt;
2889                 memset(&vt, 0, sizeof(vt));
2890                 vt.audmode = hdw->audiomode_val;
2891                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2892         }
2893
2894         if (hdw->freqDirty) {
2895                 unsigned long fv;
2896                 struct v4l2_frequency freq;
2897                 fv = pvr2_hdw_get_cur_freq(hdw);
2898                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2899                 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2900                 memset(&freq, 0, sizeof(freq));
2901                 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2902                         /* ((fv * 1000) / 62500) */
2903                         freq.frequency = (fv * 2) / 125;
2904                 } else {
2905                         freq.frequency = fv / 62500;
2906                 }
2907                 /* tuner-core currently doesn't seem to care about this, but
2908                    let's set it anyway for completeness. */
2909                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2910                         freq.type = V4L2_TUNER_RADIO;
2911                 } else {
2912                         freq.type = V4L2_TUNER_ANALOG_TV;
2913                 }
2914                 freq.tuner = 0;
2915                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2916                                      s_frequency, &freq);
2917         }
2918
2919         if (hdw->res_hor_dirty || hdw->res_ver_dirty) {
2920                 struct v4l2_format fmt;
2921                 memset(&fmt, 0, sizeof(fmt));
2922                 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2923                 fmt.fmt.pix.width = hdw->res_hor_val;
2924                 fmt.fmt.pix.height = hdw->res_ver_val;
2925                 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_size(%dx%d)",
2926                            fmt.fmt.pix.width, fmt.fmt.pix.height);
2927                 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
2928         }
2929
2930         /* Unable to set crop parameters; there is apparently no equivalent
2931            for VIDIOC_S_CROP */
2932
2933         /* ????? Cover special cases for specific sub-devices. */
2934
2935         if (hdw->tuner_signal_stale && hdw->cropcap_stale) {
2936                 pvr2_hdw_status_poll(hdw);
2937         }
2938 }
2939
2940
2941 /* Figure out if we need to commit control changes.  If so, mark internal
2942    state flags to indicate this fact and return true.  Otherwise do nothing
2943    else and return false. */
2944 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2945 {
2946         unsigned int idx;
2947         struct pvr2_ctrl *cptr;
2948         int value;
2949         int commit_flag = 0;
2950         char buf[100];
2951         unsigned int bcnt,ccnt;
2952
2953         for (idx = 0; idx < hdw->control_cnt; idx++) {
2954                 cptr = hdw->controls + idx;
2955                 if (!cptr->info->is_dirty) continue;
2956                 if (!cptr->info->is_dirty(cptr)) continue;
2957                 commit_flag = !0;
2958
2959                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2960                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2961                                  cptr->info->name);
2962                 value = 0;
2963                 cptr->info->get_value(cptr,&value);
2964                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2965                                                 buf+bcnt,
2966                                                 sizeof(buf)-bcnt,&ccnt);
2967                 bcnt += ccnt;
2968                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2969                                   get_ctrl_typename(cptr->info->type));
2970                 pvr2_trace(PVR2_TRACE_CTL,
2971                            "/*--TRACE_COMMIT--*/ %.*s",
2972                            bcnt,buf);
2973         }
2974
2975         if (!commit_flag) {
2976                 /* Nothing has changed */
2977                 return 0;
2978         }
2979
2980         hdw->state_pipeline_config = 0;
2981         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2982         pvr2_hdw_state_sched(hdw);
2983
2984         return !0;
2985 }
2986
2987
2988 /* Perform all operations needed to commit all control changes.  This must
2989    be performed in synchronization with the pipeline state and is thus
2990    expected to be called as part of the driver's worker thread.  Return
2991    true if commit successful, otherwise return false to indicate that
2992    commit isn't possible at this time. */
2993 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2994 {
2995         unsigned int idx;
2996         struct pvr2_ctrl *cptr;
2997         int disruptive_change;
2998
2999         /* Handle some required side effects when the video standard is
3000            changed.... */
3001         if (hdw->std_dirty) {
3002                 int nvres;
3003                 int gop_size;
3004                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3005                         nvres = 480;
3006                         gop_size = 15;
3007                 } else {
3008                         nvres = 576;
3009                         gop_size = 12;
3010                 }
3011                 /* Rewrite the vertical resolution to be appropriate to the
3012                    video standard that has been selected. */
3013                 if (nvres != hdw->res_ver_val) {
3014                         hdw->res_ver_val = nvres;
3015                         hdw->res_ver_dirty = !0;
3016                 }
3017                 /* Rewrite the GOP size to be appropriate to the video
3018                    standard that has been selected. */
3019                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3020                         struct v4l2_ext_controls cs;
3021                         struct v4l2_ext_control c1;
3022                         memset(&cs, 0, sizeof(cs));
3023                         memset(&c1, 0, sizeof(c1));
3024                         cs.controls = &c1;
3025                         cs.count = 1;
3026                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3027                         c1.value = gop_size;
3028                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3029                                           VIDIOC_S_EXT_CTRLS);
3030                 }
3031         }
3032
3033         if (hdw->input_dirty && hdw->state_pathway_ok &&
3034             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3035               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3036              hdw->pathway_state)) {
3037                 /* Change of mode being asked for... */
3038                 hdw->state_pathway_ok = 0;
3039                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3040         }
3041         if (!hdw->state_pathway_ok) {
3042                 /* Can't commit anything until pathway is ok. */
3043                 return 0;
3044         }
3045         /* The broadcast decoder can only scale down, so if
3046          * res_*_dirty && crop window < output format ==> enlarge crop.
3047          *
3048          * The mpeg encoder receives fields of res_hor_val dots and
3049          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3050          */
3051         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3052                 hdw->cropw_val = hdw->res_hor_val;
3053                 hdw->cropw_dirty = !0;
3054         } else if (hdw->cropw_dirty) {
3055                 hdw->res_hor_dirty = !0;           /* must rescale */
3056                 hdw->res_hor_val = min(720, hdw->cropw_val);
3057         }
3058         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3059                 hdw->croph_val = hdw->res_ver_val;
3060                 hdw->croph_dirty = !0;
3061         } else if (hdw->croph_dirty) {
3062                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3063                 hdw->res_ver_dirty = !0;
3064                 hdw->res_ver_val = min(nvres, hdw->croph_val);
3065         }
3066
3067         /* If any of the below has changed, then we can't do the update
3068            while the pipeline is running.  Pipeline must be paused first
3069            and decoder -> encoder connection be made quiescent before we
3070            can proceed. */
3071         disruptive_change =
3072                 (hdw->std_dirty ||
3073                  hdw->enc_unsafe_stale ||
3074                  hdw->srate_dirty ||
3075                  hdw->res_ver_dirty ||
3076                  hdw->res_hor_dirty ||
3077                  hdw->cropw_dirty ||
3078                  hdw->croph_dirty ||
3079                  hdw->input_dirty ||
3080                  (hdw->active_stream_type != hdw->desired_stream_type));
3081         if (disruptive_change && !hdw->state_pipeline_idle) {
3082                 /* Pipeline is not idle; we can't proceed.  Arrange to
3083                    cause pipeline to stop so that we can try this again
3084                    later.... */
3085                 hdw->state_pipeline_pause = !0;
3086                 return 0;
3087         }
3088
3089         if (hdw->srate_dirty) {
3090                 /* Write new sample rate into control structure since
3091                  * the master copy is stale.  We must track srate
3092                  * separate from the mpeg control structure because
3093                  * other logic also uses this value. */
3094                 struct v4l2_ext_controls cs;
3095                 struct v4l2_ext_control c1;
3096                 memset(&cs,0,sizeof(cs));
3097                 memset(&c1,0,sizeof(c1));
3098                 cs.controls = &c1;
3099                 cs.count = 1;
3100                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3101                 c1.value = hdw->srate_val;
3102                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3103         }
3104
3105         /* Scan i2c core at this point - before we clear all the dirty
3106            bits.  Various parts of the i2c core will notice dirty bits as
3107            appropriate and arrange to broadcast or directly send updates to
3108            the client drivers in order to keep everything in sync */
3109         pvr2_i2c_core_check_stale(hdw);
3110
3111         if (hdw->active_stream_type != hdw->desired_stream_type) {
3112                 /* Handle any side effects of stream config here */
3113                 hdw->active_stream_type = hdw->desired_stream_type;
3114         }
3115
3116         if (hdw->hdw_desc->signal_routing_scheme ==
3117             PVR2_ROUTING_SCHEME_GOTVIEW) {
3118                 u32 b;
3119                 /* Handle GOTVIEW audio switching */
3120                 pvr2_hdw_gpio_get_out(hdw,&b);
3121                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3122                         /* Set GPIO 11 */
3123                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3124                 } else {
3125                         /* Clear GPIO 11 */
3126                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3127                 }
3128         }
3129
3130         for (idx = 0; idx < hdw->control_cnt; idx++) {
3131                 cptr = hdw->controls + idx;
3132                 if (!cptr->info->clear_dirty) continue;
3133                 cptr->info->clear_dirty(cptr);
3134         }
3135
3136         /* Check and update state for all sub-devices. */
3137         pvr2_subdev_update(hdw);
3138
3139         /* Now execute i2c core update */
3140         pvr2_i2c_core_sync(hdw);
3141
3142         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3143             hdw->state_encoder_run) {
3144                 /* If encoder isn't running or it can't be touched, then
3145                    this will get worked out later when we start the
3146                    encoder. */
3147                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3148         }
3149
3150         hdw->state_pipeline_config = !0;
3151         /* Hardware state may have changed in a way to cause the cropping
3152            capabilities to have changed.  So mark it stale, which will
3153            cause a later re-fetch. */
3154         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3155         return !0;
3156 }
3157
3158
3159 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3160 {
3161         int fl;
3162         LOCK_TAKE(hdw->big_lock);
3163         fl = pvr2_hdw_commit_setup(hdw);
3164         LOCK_GIVE(hdw->big_lock);
3165         if (!fl) return 0;
3166         return pvr2_hdw_wait(hdw,0);
3167 }
3168
3169
3170 static void pvr2_hdw_worker_i2c(struct work_struct *work)
3171 {
3172         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
3173         LOCK_TAKE(hdw->big_lock); do {
3174                 pvr2_i2c_core_sync(hdw);
3175         } while (0); LOCK_GIVE(hdw->big_lock);
3176 }
3177
3178
3179 static void pvr2_hdw_worker_poll(struct work_struct *work)
3180 {
3181         int fl = 0;
3182         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3183         LOCK_TAKE(hdw->big_lock); do {
3184                 fl = pvr2_hdw_state_eval(hdw);
3185         } while (0); LOCK_GIVE(hdw->big_lock);
3186         if (fl && hdw->state_func) {
3187                 hdw->state_func(hdw->state_data);
3188         }
3189 }
3190
3191
3192 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3193 {
3194         return wait_event_interruptible(
3195                 hdw->state_wait_data,
3196                 (hdw->state_stale == 0) &&
3197                 (!state || (hdw->master_state != state)));
3198 }
3199
3200
3201 /* Return name for this driver instance */
3202 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3203 {
3204         return hdw->name;
3205 }
3206
3207
3208 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3209 {
3210         return hdw->hdw_desc->description;
3211 }
3212
3213
3214 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3215 {
3216         return hdw->hdw_desc->shortname;
3217 }
3218
3219
3220 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3221 {
3222         int result;
3223         LOCK_TAKE(hdw->ctl_lock); do {
3224                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3225                 result = pvr2_send_request(hdw,
3226                                            hdw->cmd_buffer,1,
3227                                            hdw->cmd_buffer,1);
3228                 if (result < 0) break;
3229                 result = (hdw->cmd_buffer[0] != 0);
3230         } while(0); LOCK_GIVE(hdw->ctl_lock);
3231         return result;
3232 }
3233
3234
3235 /* Execute poll of tuner status */
3236 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3237 {
3238         LOCK_TAKE(hdw->big_lock); do {
3239                 pvr2_hdw_status_poll(hdw);
3240         } while (0); LOCK_GIVE(hdw->big_lock);
3241 }
3242
3243
3244 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3245 {
3246         if (!hdw->cropcap_stale) {
3247                 return 0;
3248         }
3249         pvr2_hdw_status_poll(hdw);
3250         if (hdw->cropcap_stale) {
3251                 return -EIO;
3252         }
3253         return 0;
3254 }
3255
3256
3257 /* Return information about cropping capabilities */
3258 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3259 {
3260         int stat = 0;
3261         LOCK_TAKE(hdw->big_lock);
3262         stat = pvr2_hdw_check_cropcap(hdw);
3263         if (!stat) {
3264                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3265         }
3266         LOCK_GIVE(hdw->big_lock);
3267         return stat;
3268 }
3269
3270
3271 /* Return information about the tuner */
3272 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3273 {
3274         LOCK_TAKE(hdw->big_lock); do {
3275                 if (hdw->tuner_signal_stale) {
3276                         pvr2_hdw_status_poll(hdw);
3277                 }
3278                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3279         } while (0); LOCK_GIVE(hdw->big_lock);
3280         return 0;
3281 }
3282
3283
3284 /* Get handle to video output stream */
3285 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3286 {
3287         return hp->vid_stream;
3288 }
3289
3290
3291 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3292 {
3293         int nr = pvr2_hdw_get_unit_number(hdw);
3294         LOCK_TAKE(hdw->big_lock); do {
3295                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3296                 hdw->log_requested = !0;
3297                 pvr2_i2c_core_check_stale(hdw);
3298                 pvr2_i2c_core_sync(hdw);
3299                 hdw->log_requested = 0;
3300                 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3301                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3302                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3303                 pvr2_hdw_state_log_state(hdw);
3304                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3305         } while (0); LOCK_GIVE(hdw->big_lock);
3306 }
3307
3308
3309 /* Grab EEPROM contents, needed for direct method. */
3310 #define EEPROM_SIZE 8192
3311 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3312 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3313 {
3314         struct i2c_msg msg[2];
3315         u8 *eeprom;
3316         u8 iadd[2];
3317         u8 addr;
3318         u16 eepromSize;
3319         unsigned int offs;
3320         int ret;
3321         int mode16 = 0;
3322         unsigned pcnt,tcnt;
3323         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3324         if (!eeprom) {
3325                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3326                            "Failed to allocate memory"
3327                            " required to read eeprom");
3328                 return NULL;
3329         }
3330
3331         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3332                      hdw->eeprom_addr);
3333         addr = hdw->eeprom_addr;
3334         /* Seems that if the high bit is set, then the *real* eeprom
3335            address is shifted right now bit position (noticed this in
3336            newer PVR USB2 hardware) */
3337         if (addr & 0x80) addr >>= 1;
3338
3339         /* FX2 documentation states that a 16bit-addressed eeprom is
3340            expected if the I2C address is an odd number (yeah, this is
3341            strange but it's what they do) */
3342         mode16 = (addr & 1);
3343         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3344         trace_eeprom("Examining %d byte eeprom at location 0x%x"
3345                      " using %d bit addressing",eepromSize,addr,
3346                      mode16 ? 16 : 8);
3347
3348         msg[0].addr = addr;
3349         msg[0].flags = 0;
3350         msg[0].len = mode16 ? 2 : 1;
3351         msg[0].buf = iadd;
3352         msg[1].addr = addr;
3353         msg[1].flags = I2C_M_RD;
3354
3355         /* We have to do the actual eeprom data fetch ourselves, because
3356            (1) we're only fetching part of the eeprom, and (2) if we were
3357            getting the whole thing our I2C driver can't grab it in one
3358            pass - which is what tveeprom is otherwise going to attempt */
3359         memset(eeprom,0,EEPROM_SIZE);
3360         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3361                 pcnt = 16;
3362                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3363                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3364                 if (mode16) {
3365                         iadd[0] = offs >> 8;
3366                         iadd[1] = offs;
3367                 } else {
3368                         iadd[0] = offs;
3369                 }
3370                 msg[1].len = pcnt;
3371                 msg[1].buf = eeprom+tcnt;
3372                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3373                                         msg,ARRAY_SIZE(msg))) != 2) {
3374                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3375                                    "eeprom fetch set offs err=%d",ret);
3376                         kfree(eeprom);
3377                         return NULL;
3378                 }
3379         }
3380         return eeprom;
3381 }
3382
3383
3384 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3385                                 int prom_flag,
3386                                 int enable_flag)
3387 {
3388         int ret;
3389         u16 address;
3390         unsigned int pipe;
3391         LOCK_TAKE(hdw->big_lock); do {
3392                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3393
3394                 if (!enable_flag) {
3395                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3396                                    "Cleaning up after CPU firmware fetch");
3397                         kfree(hdw->fw_buffer);
3398                         hdw->fw_buffer = NULL;
3399                         hdw->fw_size = 0;
3400                         if (hdw->fw_cpu_flag) {
3401                                 /* Now release the CPU.  It will disconnect
3402                                    and reconnect later. */
3403                                 pvr2_hdw_cpureset_assert(hdw,0);
3404                         }
3405                         break;
3406                 }
3407
3408                 hdw->fw_cpu_flag = (prom_flag == 0);
3409                 if (hdw->fw_cpu_flag) {
3410                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3411                                    "Preparing to suck out CPU firmware");
3412                         hdw->fw_size = 0x2000;
3413                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3414                         if (!hdw->fw_buffer) {
3415                                 hdw->fw_size = 0;
3416                                 break;
3417                         }
3418
3419                         /* We have to hold the CPU during firmware upload. */
3420                         pvr2_hdw_cpureset_assert(hdw,1);
3421
3422                         /* download the firmware from address 0000-1fff in 2048
3423                            (=0x800) bytes chunk. */
3424
3425                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3426                                    "Grabbing CPU firmware");
3427                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3428                         for(address = 0; address < hdw->fw_size;
3429                             address += 0x800) {
3430                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3431                                                       0xa0,0xc0,
3432                                                       address,0,
3433                                                       hdw->fw_buffer+address,
3434                                                       0x800,HZ);
3435                                 if (ret < 0) break;
3436                         }
3437
3438                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3439                                    "Done grabbing CPU firmware");
3440                 } else {
3441                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3442                                    "Sucking down EEPROM contents");
3443                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3444                         if (!hdw->fw_buffer) {
3445                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3446                                            "EEPROM content suck failed.");
3447                                 break;
3448                         }
3449                         hdw->fw_size = EEPROM_SIZE;
3450                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3451                                    "Done sucking down EEPROM contents");
3452                 }
3453
3454         } while (0); LOCK_GIVE(hdw->big_lock);
3455 }
3456
3457
3458 /* Return true if we're in a mode for retrieval CPU firmware */
3459 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3460 {
3461         return hdw->fw_buffer != NULL;
3462 }
3463
3464
3465 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3466                        char *buf,unsigned int cnt)
3467 {
3468         int ret = -EINVAL;
3469         LOCK_TAKE(hdw->big_lock); do {
3470                 if (!buf) break;
3471                 if (!cnt) break;
3472
3473                 if (!hdw->fw_buffer) {
3474                         ret = -EIO;
3475                         break;
3476                 }
3477
3478                 if (offs >= hdw->fw_size) {
3479                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3480                                    "Read firmware data offs=%d EOF",
3481                                    offs);
3482                         ret = 0;
3483                         break;
3484                 }
3485
3486                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3487
3488                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3489
3490                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3491                            "Read firmware data offs=%d cnt=%d",
3492                            offs,cnt);
3493                 ret = cnt;
3494         } while (0); LOCK_GIVE(hdw->big_lock);
3495
3496         return ret;
3497 }
3498
3499
3500 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3501                                   enum pvr2_v4l_type index)
3502 {
3503         switch (index) {
3504         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3505         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3506         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3507         default: return -1;
3508         }
3509 }
3510
3511
3512 /* Store a v4l minor device number */
3513 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3514                                      enum pvr2_v4l_type index,int v)
3515 {
3516         switch (index) {
3517         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3518         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3519         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3520         default: break;
3521         }
3522 }
3523
3524
3525 static void pvr2_ctl_write_complete(struct urb *urb)
3526 {
3527         struct pvr2_hdw *hdw = urb->context;
3528         hdw->ctl_write_pend_flag = 0;
3529         if (hdw->ctl_read_pend_flag) return;
3530         complete(&hdw->ctl_done);
3531 }
3532
3533
3534 static void pvr2_ctl_read_complete(struct urb *urb)
3535 {
3536         struct pvr2_hdw *hdw = urb->context;
3537         hdw->ctl_read_pend_flag = 0;
3538         if (hdw->ctl_write_pend_flag) return;
3539         complete(&hdw->ctl_done);
3540 }
3541
3542
3543 static void pvr2_ctl_timeout(unsigned long data)
3544 {
3545         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3546         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3547                 hdw->ctl_timeout_flag = !0;
3548                 if (hdw->ctl_write_pend_flag)
3549                         usb_unlink_urb(hdw->ctl_write_urb);
3550                 if (hdw->ctl_read_pend_flag)
3551                         usb_unlink_urb(hdw->ctl_read_urb);
3552         }
3553 }
3554
3555
3556 /* Issue a command and get a response from the device.  This extended
3557    version includes a probe flag (which if set means that device errors
3558    should not be logged or treated as fatal) and a timeout in jiffies.
3559    This can be used to non-lethally probe the health of endpoint 1. */
3560 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3561                                 unsigned int timeout,int probe_fl,
3562                                 void *write_data,unsigned int write_len,
3563                                 void *read_data,unsigned int read_len)
3564 {
3565         unsigned int idx;
3566         int status = 0;
3567         struct timer_list timer;
3568         if (!hdw->ctl_lock_held) {
3569                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3570                            "Attempted to execute control transfer"
3571                            " without lock!!");
3572                 return -EDEADLK;
3573         }
3574         if (!hdw->flag_ok && !probe_fl) {
3575                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3576                            "Attempted to execute control transfer"
3577                            " when device not ok");
3578                 return -EIO;
3579         }
3580         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3581                 if (!probe_fl) {
3582                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3583                                    "Attempted to execute control transfer"
3584                                    " when USB is disconnected");
3585                 }
3586                 return -ENOTTY;
3587         }
3588
3589         /* Ensure that we have sane parameters */
3590         if (!write_data) write_len = 0;
3591         if (!read_data) read_len = 0;
3592         if (write_len > PVR2_CTL_BUFFSIZE) {
3593                 pvr2_trace(
3594                         PVR2_TRACE_ERROR_LEGS,
3595                         "Attempted to execute %d byte"
3596                         " control-write transfer (limit=%d)",
3597                         write_len,PVR2_CTL_BUFFSIZE);
3598                 return -EINVAL;
3599         }
3600         if (read_len > PVR2_CTL_BUFFSIZE) {
3601                 pvr2_trace(
3602                         PVR2_TRACE_ERROR_LEGS,
3603                         "Attempted to execute %d byte"
3604                         " control-read transfer (limit=%d)",
3605                         write_len,PVR2_CTL_BUFFSIZE);
3606                 return -EINVAL;
3607         }
3608         if ((!write_len) && (!read_len)) {
3609                 pvr2_trace(
3610                         PVR2_TRACE_ERROR_LEGS,
3611                         "Attempted to execute null control transfer?");
3612                 return -EINVAL;
3613         }
3614
3615
3616         hdw->cmd_debug_state = 1;
3617         if (write_len) {
3618                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3619         } else {
3620                 hdw->cmd_debug_code = 0;
3621         }
3622         hdw->cmd_debug_write_len = write_len;
3623         hdw->cmd_debug_read_len = read_len;
3624
3625         /* Initialize common stuff */
3626         init_completion(&hdw->ctl_done);
3627         hdw->ctl_timeout_flag = 0;
3628         hdw->ctl_write_pend_flag = 0;
3629         hdw->ctl_read_pend_flag = 0;
3630         init_timer(&timer);
3631         timer.expires = jiffies + timeout;
3632         timer.data = (unsigned long)hdw;
3633         timer.function = pvr2_ctl_timeout;
3634
3635         if (write_len) {
3636                 hdw->cmd_debug_state = 2;
3637                 /* Transfer write data to internal buffer */
3638                 for (idx = 0; idx < write_len; idx++) {
3639                         hdw->ctl_write_buffer[idx] =
3640                                 ((unsigned char *)write_data)[idx];
3641                 }
3642                 /* Initiate a write request */
3643                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3644                                   hdw->usb_dev,
3645                                   usb_sndbulkpipe(hdw->usb_dev,
3646                                                   PVR2_CTL_WRITE_ENDPOINT),
3647                                   hdw->ctl_write_buffer,
3648                                   write_len,
3649                                   pvr2_ctl_write_complete,
3650                                   hdw);
3651                 hdw->ctl_write_urb->actual_length = 0;
3652                 hdw->ctl_write_pend_flag = !0;
3653                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3654                 if (status < 0) {
3655                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3656                                    "Failed to submit write-control"
3657                                    " URB status=%d",status);
3658                         hdw->ctl_write_pend_flag = 0;
3659                         goto done;
3660                 }
3661         }
3662
3663         if (read_len) {
3664                 hdw->cmd_debug_state = 3;
3665                 memset(hdw->ctl_read_buffer,0x43,read_len);
3666                 /* Initiate a read request */
3667                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3668                                   hdw->usb_dev,
3669                                   usb_rcvbulkpipe(hdw->usb_dev,
3670                                                   PVR2_CTL_READ_ENDPOINT),
3671                                   hdw->ctl_read_buffer,
3672                                   read_len,
3673                                   pvr2_ctl_read_complete,
3674                                   hdw);
3675                 hdw->ctl_read_urb->actual_length = 0;
3676                 hdw->ctl_read_pend_flag = !0;
3677                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3678                 if (status < 0) {
3679                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3680                                    "Failed to submit read-control"
3681                                    " URB status=%d",status);
3682                         hdw->ctl_read_pend_flag = 0;
3683                         goto done;
3684                 }
3685         }
3686
3687         /* Start timer */
3688         add_timer(&timer);
3689
3690         /* Now wait for all I/O to complete */
3691         hdw->cmd_debug_state = 4;
3692         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3693                 wait_for_completion(&hdw->ctl_done);
3694         }
3695         hdw->cmd_debug_state = 5;
3696
3697         /* Stop timer */
3698         del_timer_sync(&timer);
3699
3700         hdw->cmd_debug_state = 6;
3701         status = 0;
3702
3703         if (hdw->ctl_timeout_flag) {
3704                 status = -ETIMEDOUT;
3705                 if (!probe_fl) {
3706                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3707                                    "Timed out control-write");
3708                 }
3709                 goto done;
3710         }
3711
3712         if (write_len) {
3713                 /* Validate results of write request */
3714                 if ((hdw->ctl_write_urb->status != 0) &&
3715                     (hdw->ctl_write_urb->status != -ENOENT) &&
3716                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3717                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3718                         /* USB subsystem is reporting some kind of failure
3719                            on the write */
3720                         status = hdw->ctl_write_urb->status;
3721                         if (!probe_fl) {
3722                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3723                                            "control-write URB failure,"
3724                                            " status=%d",
3725                                            status);
3726                         }
3727                         goto done;
3728                 }
3729                 if (hdw->ctl_write_urb->actual_length < write_len) {
3730                         /* Failed to write enough data */
3731                         status = -EIO;
3732                         if (!probe_fl) {
3733                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3734                                            "control-write URB short,"
3735                                            " expected=%d got=%d",
3736                                            write_len,
3737                                            hdw->ctl_write_urb->actual_length);
3738                         }
3739                         goto done;
3740                 }
3741         }
3742         if (read_len) {
3743                 /* Validate results of read request */
3744                 if ((hdw->ctl_read_urb->status != 0) &&
3745                     (hdw->ctl_read_urb->status != -ENOENT) &&
3746                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3747                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3748                         /* USB subsystem is reporting some kind of failure
3749                            on the read */
3750                         status = hdw->ctl_read_urb->status;
3751                         if (!probe_fl) {
3752                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3753                                            "control-read URB failure,"
3754                                            " status=%d",
3755                                            status);
3756                         }
3757                         goto done;
3758                 }
3759                 if (hdw->ctl_read_urb->actual_length < read_len) {
3760                         /* Failed to read enough data */
3761                         status = -EIO;
3762                         if (!probe_fl) {
3763                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3764                                            "control-read URB short,"
3765                                            " expected=%d got=%d",
3766                                            read_len,
3767                                            hdw->ctl_read_urb->actual_length);
3768                         }
3769                         goto done;
3770                 }
3771                 /* Transfer retrieved data out from internal buffer */
3772                 for (idx = 0; idx < read_len; idx++) {
3773                         ((unsigned char *)read_data)[idx] =
3774                                 hdw->ctl_read_buffer[idx];
3775                 }
3776         }
3777
3778  done:
3779
3780         hdw->cmd_debug_state = 0;
3781         if ((status < 0) && (!probe_fl)) {
3782                 pvr2_hdw_render_useless(hdw);
3783         }
3784         return status;
3785 }
3786
3787
3788 int pvr2_send_request(struct pvr2_hdw *hdw,
3789                       void *write_data,unsigned int write_len,
3790                       void *read_data,unsigned int read_len)
3791 {
3792         return pvr2_send_request_ex(hdw,HZ*4,0,
3793                                     write_data,write_len,
3794                                     read_data,read_len);
3795 }
3796
3797
3798 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3799 {
3800         int ret;
3801         unsigned int cnt = 1;
3802         unsigned int args = 0;
3803         LOCK_TAKE(hdw->ctl_lock);
3804         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3805         args = (cmdcode >> 8) & 0xffu;
3806         args = (args > 2) ? 2 : args;
3807         if (args) {
3808                 cnt += args;
3809                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3810                 if (args > 1) {
3811                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3812                 }
3813         }
3814         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3815                 unsigned int idx;
3816                 unsigned int ccnt,bcnt;
3817                 char tbuf[50];
3818                 cmdcode &= 0xffu;
3819                 bcnt = 0;
3820                 ccnt = scnprintf(tbuf+bcnt,
3821                                  sizeof(tbuf)-bcnt,
3822                                  "Sending FX2 command 0x%x",cmdcode);
3823                 bcnt += ccnt;
3824                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3825                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3826                                 ccnt = scnprintf(tbuf+bcnt,
3827                                                  sizeof(tbuf)-bcnt,
3828                                                  " \"%s\"",
3829                                                  pvr2_fx2cmd_desc[idx].desc);
3830                                 bcnt += ccnt;
3831                                 break;
3832                         }
3833                 }
3834                 if (args) {
3835                         ccnt = scnprintf(tbuf+bcnt,
3836                                          sizeof(tbuf)-bcnt,
3837                                          " (%u",hdw->cmd_buffer[1]);
3838                         bcnt += ccnt;
3839                         if (args > 1) {
3840                                 ccnt = scnprintf(tbuf+bcnt,
3841                                                  sizeof(tbuf)-bcnt,
3842                                                  ",%u",hdw->cmd_buffer[2]);
3843                                 bcnt += ccnt;
3844                         }
3845                         ccnt = scnprintf(tbuf+bcnt,
3846                                          sizeof(tbuf)-bcnt,
3847                                          ")");
3848                         bcnt += ccnt;
3849                 }
3850                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3851         }
3852         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3853         LOCK_GIVE(hdw->ctl_lock);
3854         return ret;
3855 }
3856
3857
3858 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3859 {
3860         int ret;
3861
3862         LOCK_TAKE(hdw->ctl_lock);
3863
3864         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3865         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3866         hdw->cmd_buffer[5] = 0;
3867         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3868         hdw->cmd_buffer[7] = reg & 0xff;
3869
3870
3871         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3872
3873         LOCK_GIVE(hdw->ctl_lock);
3874
3875         return ret;
3876 }
3877
3878
3879 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3880 {
3881         int ret = 0;
3882
3883         LOCK_TAKE(hdw->ctl_lock);
3884
3885         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3886         hdw->cmd_buffer[1] = 0;
3887         hdw->cmd_buffer[2] = 0;
3888         hdw->cmd_buffer[3] = 0;
3889         hdw->cmd_buffer[4] = 0;
3890         hdw->cmd_buffer[5] = 0;
3891         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3892         hdw->cmd_buffer[7] = reg & 0xff;
3893
3894         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3895         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3896
3897         LOCK_GIVE(hdw->ctl_lock);
3898
3899         return ret;
3900 }
3901
3902
3903 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3904 {
3905         if (!hdw->flag_ok) return;
3906         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3907                    "Device being rendered inoperable");
3908         if (hdw->vid_stream) {
3909                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3910         }
3911         hdw->flag_ok = 0;
3912         trace_stbit("flag_ok",hdw->flag_ok);
3913         pvr2_hdw_state_sched(hdw);
3914 }
3915
3916
3917 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3918 {
3919         int ret;
3920         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3921         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3922         if (ret == 0) {
3923                 ret = usb_reset_device(hdw->usb_dev);
3924                 usb_unlock_device(hdw->usb_dev);
3925         } else {
3926                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3927                            "Failed to lock USB device ret=%d",ret);
3928         }
3929         if (init_pause_msec) {
3930                 pvr2_trace(PVR2_TRACE_INFO,
3931                            "Waiting %u msec for hardware to settle",
3932                            init_pause_msec);
3933                 msleep(init_pause_msec);
3934         }
3935
3936 }
3937
3938
3939 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3940 {
3941         char da[1];
3942         unsigned int pipe;
3943         int ret;
3944
3945         if (!hdw->usb_dev) return;
3946
3947         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3948
3949         da[0] = val ? 0x01 : 0x00;
3950
3951         /* Write the CPUCS register on the 8051.  The lsb of the register
3952            is the reset bit; a 1 asserts reset while a 0 clears it. */
3953         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3954         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3955         if (ret < 0) {
3956                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3957                            "cpureset_assert(%d) error=%d",val,ret);
3958                 pvr2_hdw_render_useless(hdw);
3959         }
3960 }
3961
3962
3963 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3964 {
3965         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
3966 }
3967
3968
3969 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3970 {
3971         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
3972 }
3973
3974
3975 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
3976 {
3977         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
3978 }
3979
3980
3981 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3982 {
3983         if (!hdw->decoder_ctrl) {
3984                 pvr2_trace(PVR2_TRACE_INIT,
3985                            "Unable to reset decoder: nothing attached");
3986                 return -ENOTTY;
3987         }
3988
3989         if (!hdw->decoder_ctrl->force_reset) {
3990                 pvr2_trace(PVR2_TRACE_INIT,
3991                            "Unable to reset decoder: not implemented");
3992                 return -ENOTTY;
3993         }
3994
3995         pvr2_trace(PVR2_TRACE_INIT,
3996                    "Requesting decoder reset");
3997         hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3998         return 0;
3999 }
4000
4001
4002 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4003 {
4004         hdw->flag_ok = !0;
4005         return pvr2_issue_simple_cmd(hdw,
4006                                      FX2CMD_HCW_DEMOD_RESETIN |
4007                                      (1 << 8) |
4008                                      ((onoff ? 1 : 0) << 16));
4009 }
4010
4011
4012 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4013 {
4014         hdw->flag_ok = !0;
4015         return pvr2_issue_simple_cmd(hdw,(onoff ?
4016                                           FX2CMD_ONAIR_DTV_POWER_ON :
4017                                           FX2CMD_ONAIR_DTV_POWER_OFF));
4018 }
4019
4020
4021 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4022                                                 int onoff)
4023 {
4024         return pvr2_issue_simple_cmd(hdw,(onoff ?
4025                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
4026                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
4027 }
4028
4029
4030 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4031 {
4032         int cmode;
4033         /* Compare digital/analog desired setting with current setting.  If
4034            they don't match, fix it... */
4035         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4036         if (cmode == hdw->pathway_state) {
4037                 /* They match; nothing to do */
4038                 return;
4039         }
4040
4041         switch (hdw->hdw_desc->digital_control_scheme) {
4042         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4043                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4044                 if (cmode == PVR2_PATHWAY_ANALOG) {
4045                         /* If moving to analog mode, also force the decoder
4046                            to reset.  If no decoder is attached, then it's
4047                            ok to ignore this because if/when the decoder
4048                            attaches, it will reset itself at that time. */
4049                         pvr2_hdw_cmd_decoder_reset(hdw);
4050                 }
4051                 break;
4052         case PVR2_DIGITAL_SCHEME_ONAIR:
4053                 /* Supposedly we should always have the power on whether in
4054                    digital or analog mode.  But for now do what appears to
4055                    work... */
4056                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4057                 break;
4058         default: break;
4059         }
4060
4061         pvr2_hdw_untrip_unlocked(hdw);
4062         hdw->pathway_state = cmode;
4063 }
4064
4065
4066 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4067 {
4068         /* change some GPIO data
4069          *
4070          * note: bit d7 of dir appears to control the LED,
4071          * so we shut it off here.
4072          *
4073          */
4074         if (onoff) {
4075                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4076         } else {
4077                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4078         }
4079         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4080 }
4081
4082
4083 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4084
4085 static led_method_func led_methods[] = {
4086         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4087 };
4088
4089
4090 /* Toggle LED */
4091 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4092 {
4093         unsigned int scheme_id;
4094         led_method_func fp;
4095
4096         if ((!onoff) == (!hdw->led_on)) return;
4097
4098         hdw->led_on = onoff != 0;
4099
4100         scheme_id = hdw->hdw_desc->led_scheme;
4101         if (scheme_id < ARRAY_SIZE(led_methods)) {
4102                 fp = led_methods[scheme_id];
4103         } else {
4104                 fp = NULL;
4105         }
4106
4107         if (fp) (*fp)(hdw,onoff);
4108 }
4109
4110
4111 /* Stop / start video stream transport */
4112 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4113 {
4114         int ret;
4115
4116         /* If we're in analog mode, then just issue the usual analog
4117            command. */
4118         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4119                 return pvr2_issue_simple_cmd(hdw,
4120                                              (runFl ?
4121                                               FX2CMD_STREAMING_ON :
4122                                               FX2CMD_STREAMING_OFF));
4123                 /*Note: Not reached */
4124         }
4125
4126         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4127                 /* Whoops, we don't know what mode we're in... */
4128                 return -EINVAL;
4129         }
4130
4131         /* To get here we have to be in digital mode.  The mechanism here
4132            is unfortunately different for different vendors.  So we switch
4133            on the device's digital scheme attribute in order to figure out
4134            what to do. */
4135         switch (hdw->hdw_desc->digital_control_scheme) {
4136         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4137                 return pvr2_issue_simple_cmd(hdw,
4138                                              (runFl ?
4139                                               FX2CMD_HCW_DTV_STREAMING_ON :
4140                                               FX2CMD_HCW_DTV_STREAMING_OFF));
4141         case PVR2_DIGITAL_SCHEME_ONAIR:
4142                 ret = pvr2_issue_simple_cmd(hdw,
4143                                             (runFl ?
4144                                              FX2CMD_STREAMING_ON :
4145                                              FX2CMD_STREAMING_OFF));
4146                 if (ret) return ret;
4147                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4148         default:
4149                 return -EINVAL;
4150         }
4151 }
4152
4153
4154 /* Evaluate whether or not state_pathway_ok can change */
4155 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4156 {
4157         if (hdw->state_pathway_ok) {
4158                 /* Nothing to do if pathway is already ok */
4159                 return 0;
4160         }
4161         if (!hdw->state_pipeline_idle) {
4162                 /* Not allowed to change anything if pipeline is not idle */
4163                 return 0;
4164         }
4165         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4166         hdw->state_pathway_ok = !0;
4167         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4168         return !0;
4169 }
4170
4171
4172 /* Evaluate whether or not state_encoder_ok can change */
4173 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4174 {
4175         if (hdw->state_encoder_ok) return 0;
4176         if (hdw->flag_tripped) return 0;
4177         if (hdw->state_encoder_run) return 0;
4178         if (hdw->state_encoder_config) return 0;
4179         if (hdw->state_decoder_run) return 0;
4180         if (hdw->state_usbstream_run) return 0;
4181         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4182                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4183         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4184                 return 0;
4185         }
4186
4187         if (pvr2_upload_firmware2(hdw) < 0) {
4188                 hdw->flag_tripped = !0;
4189                 trace_stbit("flag_tripped",hdw->flag_tripped);
4190                 return !0;
4191         }
4192         hdw->state_encoder_ok = !0;
4193         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4194         return !0;
4195 }
4196
4197
4198 /* Evaluate whether or not state_encoder_config can change */
4199 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4200 {
4201         if (hdw->state_encoder_config) {
4202                 if (hdw->state_encoder_ok) {
4203                         if (hdw->state_pipeline_req &&
4204                             !hdw->state_pipeline_pause) return 0;
4205                 }
4206                 hdw->state_encoder_config = 0;
4207                 hdw->state_encoder_waitok = 0;
4208                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4209                 /* paranoia - solve race if timer just completed */
4210                 del_timer_sync(&hdw->encoder_wait_timer);
4211         } else {
4212                 if (!hdw->state_pathway_ok ||
4213                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4214                     !hdw->state_encoder_ok ||
4215                     !hdw->state_pipeline_idle ||
4216                     hdw->state_pipeline_pause ||
4217                     !hdw->state_pipeline_req ||
4218                     !hdw->state_pipeline_config) {
4219                         /* We must reset the enforced wait interval if
4220                            anything has happened that might have disturbed
4221                            the encoder.  This should be a rare case. */
4222                         if (timer_pending(&hdw->encoder_wait_timer)) {
4223                                 del_timer_sync(&hdw->encoder_wait_timer);
4224                         }
4225                         if (hdw->state_encoder_waitok) {
4226                                 /* Must clear the state - therefore we did
4227                                    something to a state bit and must also
4228                                    return true. */
4229                                 hdw->state_encoder_waitok = 0;
4230                                 trace_stbit("state_encoder_waitok",
4231                                             hdw->state_encoder_waitok);
4232                                 return !0;
4233                         }
4234                         return 0;
4235                 }
4236                 if (!hdw->state_encoder_waitok) {
4237                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4238                                 /* waitok flag wasn't set and timer isn't
4239                                    running.  Check flag once more to avoid
4240                                    a race then start the timer.  This is
4241                                    the point when we measure out a minimal
4242                                    quiet interval before doing something to
4243                                    the encoder. */
4244                                 if (!hdw->state_encoder_waitok) {
4245                                         hdw->encoder_wait_timer.expires =
4246                                                 jiffies +
4247                                                 (HZ * TIME_MSEC_ENCODER_WAIT
4248                                                  / 1000);
4249                                         add_timer(&hdw->encoder_wait_timer);
4250                                 }
4251                         }
4252                         /* We can't continue until we know we have been
4253                            quiet for the interval measured by this
4254                            timer. */
4255                         return 0;
4256                 }
4257                 pvr2_encoder_configure(hdw);
4258                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4259         }
4260         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4261         return !0;
4262 }
4263
4264
4265 /* Return true if the encoder should not be running. */
4266 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4267 {
4268         if (!hdw->state_encoder_ok) {
4269                 /* Encoder isn't healthy at the moment, so stop it. */
4270                 return !0;
4271         }
4272         if (!hdw->state_pathway_ok) {
4273                 /* Mode is not understood at the moment (i.e. it wants to
4274                    change), so encoder must be stopped. */
4275                 return !0;
4276         }
4277
4278         switch (hdw->pathway_state) {
4279         case PVR2_PATHWAY_ANALOG:
4280                 if (!hdw->state_decoder_run) {
4281                         /* We're in analog mode and the decoder is not
4282                            running; thus the encoder should be stopped as
4283                            well. */
4284                         return !0;
4285                 }
4286                 break;
4287         case PVR2_PATHWAY_DIGITAL:
4288                 if (hdw->state_encoder_runok) {
4289                         /* This is a funny case.  We're in digital mode so
4290                            really the encoder should be stopped.  However
4291                            if it really is running, only kill it after
4292                            runok has been set.  This gives a chance for the
4293                            onair quirk to function (encoder must run
4294                            briefly first, at least once, before onair
4295                            digital streaming can work). */
4296                         return !0;
4297                 }
4298                 break;
4299         default:
4300                 /* Unknown mode; so encoder should be stopped. */
4301                 return !0;
4302         }
4303
4304         /* If we get here, we haven't found a reason to stop the
4305            encoder. */
4306         return 0;
4307 }
4308
4309
4310 /* Return true if the encoder should be running. */
4311 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4312 {
4313         if (!hdw->state_encoder_ok) {
4314                 /* Don't run the encoder if it isn't healthy... */
4315                 return 0;
4316         }
4317         if (!hdw->state_pathway_ok) {
4318                 /* Don't run the encoder if we don't (yet) know what mode
4319                    we need to be in... */
4320                 return 0;
4321         }
4322
4323         switch (hdw->pathway_state) {
4324         case PVR2_PATHWAY_ANALOG:
4325                 if (hdw->state_decoder_run) {
4326                         /* In analog mode, if the decoder is running, then
4327                            run the encoder. */
4328                         return !0;
4329                 }
4330                 break;
4331         case PVR2_PATHWAY_DIGITAL:
4332                 if ((hdw->hdw_desc->digital_control_scheme ==
4333                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4334                     !hdw->state_encoder_runok) {
4335                         /* This is a quirk.  OnAir hardware won't stream
4336                            digital until the encoder has been run at least
4337                            once, for a minimal period of time (empiricially
4338                            measured to be 1/4 second).  So if we're on
4339                            OnAir hardware and the encoder has never been
4340                            run at all, then start the encoder.  Normal
4341                            state machine logic in the driver will
4342                            automatically handle the remaining bits. */
4343                         return !0;
4344                 }
4345                 break;
4346         default:
4347                 /* For completeness (unknown mode; encoder won't run ever) */
4348                 break;
4349         }
4350         /* If we get here, then we haven't found any reason to run the
4351            encoder, so don't run it. */
4352         return 0;
4353 }
4354
4355
4356 /* Evaluate whether or not state_encoder_run can change */
4357 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4358 {
4359         if (hdw->state_encoder_run) {
4360                 if (!state_check_disable_encoder_run(hdw)) return 0;
4361                 if (hdw->state_encoder_ok) {
4362                         del_timer_sync(&hdw->encoder_run_timer);
4363                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4364                 }
4365                 hdw->state_encoder_run = 0;
4366         } else {
4367                 if (!state_check_enable_encoder_run(hdw)) return 0;
4368                 if (pvr2_encoder_start(hdw) < 0) return !0;
4369                 hdw->state_encoder_run = !0;
4370                 if (!hdw->state_encoder_runok) {
4371                         hdw->encoder_run_timer.expires =
4372                                 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4373                         add_timer(&hdw->encoder_run_timer);
4374                 }
4375         }
4376         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4377         return !0;
4378 }
4379
4380
4381 /* Timeout function for quiescent timer. */
4382 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4383 {
4384         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4385         hdw->state_decoder_quiescent = !0;
4386         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4387         hdw->state_stale = !0;
4388         queue_work(hdw->workqueue,&hdw->workpoll);
4389 }
4390
4391
4392 /* Timeout function for encoder wait timer. */
4393 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4394 {
4395         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4396         hdw->state_encoder_waitok = !0;
4397         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4398         hdw->state_stale = !0;
4399         queue_work(hdw->workqueue,&hdw->workpoll);
4400 }
4401
4402
4403 /* Timeout function for encoder run timer. */
4404 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4405 {
4406         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4407         if (!hdw->state_encoder_runok) {
4408                 hdw->state_encoder_runok = !0;
4409                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4410                 hdw->state_stale = !0;
4411                 queue_work(hdw->workqueue,&hdw->workpoll);
4412         }
4413 }
4414
4415
4416 /* Evaluate whether or not state_decoder_run can change */
4417 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4418 {
4419         if (hdw->state_decoder_run) {
4420                 if (hdw->state_encoder_ok) {
4421                         if (hdw->state_pipeline_req &&
4422                             !hdw->state_pipeline_pause &&
4423                             hdw->state_pathway_ok) return 0;
4424                 }
4425                 if (!hdw->flag_decoder_missed) {
4426                         pvr2_decoder_enable(hdw,0);
4427                 }
4428                 hdw->state_decoder_quiescent = 0;
4429                 hdw->state_decoder_run = 0;
4430                 /* paranoia - solve race if timer just completed */
4431                 del_timer_sync(&hdw->quiescent_timer);
4432         } else {
4433                 if (!hdw->state_decoder_quiescent) {
4434                         if (!timer_pending(&hdw->quiescent_timer)) {
4435                                 /* We don't do something about the
4436                                    quiescent timer until right here because
4437                                    we also want to catch cases where the
4438                                    decoder was already not running (like
4439                                    after initialization) as opposed to
4440                                    knowing that we had just stopped it.
4441                                    The second flag check is here to cover a
4442                                    race - the timer could have run and set
4443                                    this flag just after the previous check
4444                                    but before we did the pending check. */
4445                                 if (!hdw->state_decoder_quiescent) {
4446                                         hdw->quiescent_timer.expires =
4447                                                 jiffies +
4448                                                 (HZ * TIME_MSEC_DECODER_WAIT
4449                                                  / 1000);
4450                                         add_timer(&hdw->quiescent_timer);
4451                                 }
4452                         }
4453                         /* Don't allow decoder to start again until it has
4454                            been quiesced first.  This little detail should
4455                            hopefully further stabilize the encoder. */
4456                         return 0;
4457                 }
4458                 if (!hdw->state_pathway_ok ||
4459                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4460                     !hdw->state_pipeline_req ||
4461                     hdw->state_pipeline_pause ||
4462                     !hdw->state_pipeline_config ||
4463                     !hdw->state_encoder_config ||
4464                     !hdw->state_encoder_ok) return 0;
4465                 del_timer_sync(&hdw->quiescent_timer);
4466                 if (hdw->flag_decoder_missed) return 0;
4467                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4468                 hdw->state_decoder_quiescent = 0;
4469                 hdw->state_decoder_run = !0;
4470         }
4471         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4472         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4473         return !0;
4474 }
4475
4476
4477 /* Evaluate whether or not state_usbstream_run can change */
4478 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4479 {
4480         if (hdw->state_usbstream_run) {
4481                 int fl = !0;
4482                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4483                         fl = (hdw->state_encoder_ok &&
4484                               hdw->state_encoder_run);
4485                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4486                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4487                         fl = hdw->state_encoder_ok;
4488                 }
4489                 if (fl &&
4490                     hdw->state_pipeline_req &&
4491                     !hdw->state_pipeline_pause &&
4492                     hdw->state_pathway_ok) {
4493                         return 0;
4494                 }
4495                 pvr2_hdw_cmd_usbstream(hdw,0);
4496                 hdw->state_usbstream_run = 0;
4497         } else {
4498                 if (!hdw->state_pipeline_req ||
4499                     hdw->state_pipeline_pause ||
4500                     !hdw->state_pathway_ok) return 0;
4501                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4502                         if (!hdw->state_encoder_ok ||
4503                             !hdw->state_encoder_run) return 0;
4504                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4505                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4506                         if (!hdw->state_encoder_ok) return 0;
4507                         if (hdw->state_encoder_run) return 0;
4508                         if (hdw->hdw_desc->digital_control_scheme ==
4509                             PVR2_DIGITAL_SCHEME_ONAIR) {
4510                                 /* OnAir digital receivers won't stream
4511                                    unless the analog encoder has run first.
4512                                    Why?  I have no idea.  But don't even
4513                                    try until we know the analog side is
4514                                    known to have run. */
4515                                 if (!hdw->state_encoder_runok) return 0;
4516                         }
4517                 }
4518                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4519                 hdw->state_usbstream_run = !0;
4520         }
4521         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4522         return !0;
4523 }
4524
4525
4526 /* Attempt to configure pipeline, if needed */
4527 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4528 {
4529         if (hdw->state_pipeline_config ||
4530             hdw->state_pipeline_pause) return 0;
4531         pvr2_hdw_commit_execute(hdw);
4532         return !0;
4533 }
4534
4535
4536 /* Update pipeline idle and pipeline pause tracking states based on other
4537    inputs.  This must be called whenever the other relevant inputs have
4538    changed. */
4539 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4540 {
4541         unsigned int st;
4542         int updatedFl = 0;
4543         /* Update pipeline state */
4544         st = !(hdw->state_encoder_run ||
4545                hdw->state_decoder_run ||
4546                hdw->state_usbstream_run ||
4547                (!hdw->state_decoder_quiescent));
4548         if (!st != !hdw->state_pipeline_idle) {
4549                 hdw->state_pipeline_idle = st;
4550                 updatedFl = !0;
4551         }
4552         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4553                 hdw->state_pipeline_pause = 0;
4554                 updatedFl = !0;
4555         }
4556         return updatedFl;
4557 }
4558
4559
4560 typedef int (*state_eval_func)(struct pvr2_hdw *);
4561
4562 /* Set of functions to be run to evaluate various states in the driver. */
4563 static const state_eval_func eval_funcs[] = {
4564         state_eval_pathway_ok,
4565         state_eval_pipeline_config,
4566         state_eval_encoder_ok,
4567         state_eval_encoder_config,
4568         state_eval_decoder_run,
4569         state_eval_encoder_run,
4570         state_eval_usbstream_run,
4571 };
4572
4573
4574 /* Process various states and return true if we did anything interesting. */
4575 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4576 {
4577         unsigned int i;
4578         int state_updated = 0;
4579         int check_flag;
4580
4581         if (!hdw->state_stale) return 0;
4582         if ((hdw->fw1_state != FW1_STATE_OK) ||
4583             !hdw->flag_ok) {
4584                 hdw->state_stale = 0;
4585                 return !0;
4586         }
4587         /* This loop is the heart of the entire driver.  It keeps trying to
4588            evaluate various bits of driver state until nothing changes for
4589            one full iteration.  Each "bit of state" tracks some global
4590            aspect of the driver, e.g. whether decoder should run, if
4591            pipeline is configured, usb streaming is on, etc.  We separately
4592            evaluate each of those questions based on other driver state to
4593            arrive at the correct running configuration. */
4594         do {
4595                 check_flag = 0;
4596                 state_update_pipeline_state(hdw);
4597                 /* Iterate over each bit of state */
4598                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4599                         if ((*eval_funcs[i])(hdw)) {
4600                                 check_flag = !0;
4601                                 state_updated = !0;
4602                                 state_update_pipeline_state(hdw);
4603                         }
4604                 }
4605         } while (check_flag && hdw->flag_ok);
4606         hdw->state_stale = 0;
4607         trace_stbit("state_stale",hdw->state_stale);
4608         return state_updated;
4609 }
4610
4611
4612 static unsigned int print_input_mask(unsigned int msk,
4613                                      char *buf,unsigned int acnt)
4614 {
4615         unsigned int idx,ccnt;
4616         unsigned int tcnt = 0;
4617         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4618                 if (!((1 << idx) & msk)) continue;
4619                 ccnt = scnprintf(buf+tcnt,
4620                                  acnt-tcnt,
4621                                  "%s%s",
4622                                  (tcnt ? ", " : ""),
4623                                  control_values_input[idx]);
4624                 tcnt += ccnt;
4625         }
4626         return tcnt;
4627 }
4628
4629
4630 static const char *pvr2_pathway_state_name(int id)
4631 {
4632         switch (id) {
4633         case PVR2_PATHWAY_ANALOG: return "analog";
4634         case PVR2_PATHWAY_DIGITAL: return "digital";
4635         default: return "unknown";
4636         }
4637 }
4638
4639
4640 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4641                                              char *buf,unsigned int acnt)
4642 {
4643         switch (which) {
4644         case 0:
4645                 return scnprintf(
4646                         buf,acnt,
4647                         "driver:%s%s%s%s%s <mode=%s>",
4648                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4649                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4650                         (hdw->flag_disconnected ? " <disconnected>" :
4651                          " <connected>"),
4652                         (hdw->flag_tripped ? " <tripped>" : ""),
4653                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4654                         pvr2_pathway_state_name(hdw->pathway_state));
4655
4656         case 1:
4657                 return scnprintf(
4658                         buf,acnt,
4659                         "pipeline:%s%s%s%s",
4660                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4661                         (hdw->state_pipeline_config ?
4662                          " <configok>" : " <stale>"),
4663                         (hdw->state_pipeline_req ? " <req>" : ""),
4664                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4665         case 2:
4666                 return scnprintf(
4667                         buf,acnt,
4668                         "worker:%s%s%s%s%s%s%s",
4669                         (hdw->state_decoder_run ?
4670                          " <decode:run>" :
4671                          (hdw->state_decoder_quiescent ?
4672                           "" : " <decode:stop>")),
4673                         (hdw->state_decoder_quiescent ?
4674                          " <decode:quiescent>" : ""),
4675                         (hdw->state_encoder_ok ?
4676                          "" : " <encode:init>"),
4677                         (hdw->state_encoder_run ?
4678                          (hdw->state_encoder_runok ?
4679                           " <encode:run>" :
4680                           " <encode:firstrun>") :
4681                          (hdw->state_encoder_runok ?
4682                           " <encode:stop>" :
4683                           " <encode:virgin>")),
4684                         (hdw->state_encoder_config ?
4685                          " <encode:configok>" :
4686                          (hdw->state_encoder_waitok ?
4687                           "" : " <encode:waitok>")),
4688                         (hdw->state_usbstream_run ?
4689                          " <usb:run>" : " <usb:stop>"),
4690                         (hdw->state_pathway_ok ?
4691                          " <pathway:ok>" : ""));
4692         case 3:
4693                 return scnprintf(
4694                         buf,acnt,
4695                         "state: %s",
4696                         pvr2_get_state_name(hdw->master_state));
4697         case 4: {
4698                 unsigned int tcnt = 0;
4699                 unsigned int ccnt;
4700
4701                 ccnt = scnprintf(buf,
4702                                  acnt,
4703                                  "Hardware supported inputs: ");
4704                 tcnt += ccnt;
4705                 tcnt += print_input_mask(hdw->input_avail_mask,
4706                                          buf+tcnt,
4707                                          acnt-tcnt);
4708                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4709                         ccnt = scnprintf(buf+tcnt,
4710                                          acnt-tcnt,
4711                                          "; allowed inputs: ");
4712                         tcnt += ccnt;
4713                         tcnt += print_input_mask(hdw->input_allowed_mask,
4714                                                  buf+tcnt,
4715                                                  acnt-tcnt);
4716                 }
4717                 return tcnt;
4718         }
4719         case 5: {
4720                 struct pvr2_stream_stats stats;
4721                 if (!hdw->vid_stream) break;
4722                 pvr2_stream_get_stats(hdw->vid_stream,
4723                                       &stats,
4724                                       0);
4725                 return scnprintf(
4726                         buf,acnt,
4727                         "Bytes streamed=%u"
4728                         " URBs: queued=%u idle=%u ready=%u"
4729                         " processed=%u failed=%u",
4730                         stats.bytes_processed,
4731                         stats.buffers_in_queue,
4732                         stats.buffers_in_idle,
4733                         stats.buffers_in_ready,
4734                         stats.buffers_processed,
4735                         stats.buffers_failed);
4736         }
4737         default: break;
4738         }
4739         return 0;
4740 }
4741
4742
4743 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4744                                    char *buf,unsigned int acnt)
4745 {
4746         unsigned int bcnt,ccnt,idx;
4747         bcnt = 0;
4748         LOCK_TAKE(hdw->big_lock);
4749         for (idx = 0; ; idx++) {
4750                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4751                 if (!ccnt) break;
4752                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4753                 if (!acnt) break;
4754                 buf[0] = '\n'; ccnt = 1;
4755                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4756         }
4757         LOCK_GIVE(hdw->big_lock);
4758         return bcnt;
4759 }
4760
4761
4762 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4763 {
4764         char buf[128];
4765         unsigned int idx,ccnt;
4766
4767         for (idx = 0; ; idx++) {
4768                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4769                 if (!ccnt) break;
4770                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4771         }
4772 }
4773
4774
4775 /* Evaluate and update the driver's current state, taking various actions
4776    as appropriate for the update. */
4777 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4778 {
4779         unsigned int st;
4780         int state_updated = 0;
4781         int callback_flag = 0;
4782         int analog_mode;
4783
4784         pvr2_trace(PVR2_TRACE_STBITS,
4785                    "Drive state check START");
4786         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4787                 pvr2_hdw_state_log_state(hdw);
4788         }
4789
4790         /* Process all state and get back over disposition */
4791         state_updated = pvr2_hdw_state_update(hdw);
4792
4793         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4794
4795         /* Update master state based upon all other states. */
4796         if (!hdw->flag_ok) {
4797                 st = PVR2_STATE_DEAD;
4798         } else if (hdw->fw1_state != FW1_STATE_OK) {
4799                 st = PVR2_STATE_COLD;
4800         } else if ((analog_mode ||
4801                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4802                    !hdw->state_encoder_ok) {
4803                 st = PVR2_STATE_WARM;
4804         } else if (hdw->flag_tripped ||
4805                    (analog_mode && hdw->flag_decoder_missed)) {
4806                 st = PVR2_STATE_ERROR;
4807         } else if (hdw->state_usbstream_run &&
4808                    (!analog_mode ||
4809                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4810                 st = PVR2_STATE_RUN;
4811         } else {
4812                 st = PVR2_STATE_READY;
4813         }
4814         if (hdw->master_state != st) {
4815                 pvr2_trace(PVR2_TRACE_STATE,
4816                            "Device state change from %s to %s",
4817                            pvr2_get_state_name(hdw->master_state),
4818                            pvr2_get_state_name(st));
4819                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4820                 hdw->master_state = st;
4821                 state_updated = !0;
4822                 callback_flag = !0;
4823         }
4824         if (state_updated) {
4825                 /* Trigger anyone waiting on any state changes here. */
4826                 wake_up(&hdw->state_wait_data);
4827         }
4828
4829         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4830                 pvr2_hdw_state_log_state(hdw);
4831         }
4832         pvr2_trace(PVR2_TRACE_STBITS,
4833                    "Drive state check DONE callback=%d",callback_flag);
4834
4835         return callback_flag;
4836 }
4837
4838
4839 /* Cause kernel thread to check / update driver state */
4840 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4841 {
4842         if (hdw->state_stale) return;
4843         hdw->state_stale = !0;
4844         trace_stbit("state_stale",hdw->state_stale);
4845         queue_work(hdw->workqueue,&hdw->workpoll);
4846 }
4847
4848
4849 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4850 {
4851         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4852 }
4853
4854
4855 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4856 {
4857         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4858 }
4859
4860
4861 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4862 {
4863         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4864 }
4865
4866
4867 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4868 {
4869         u32 cval,nval;
4870         int ret;
4871         if (~msk) {
4872                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4873                 if (ret) return ret;
4874                 nval = (cval & ~msk) | (val & msk);
4875                 pvr2_trace(PVR2_TRACE_GPIO,
4876                            "GPIO direction changing 0x%x:0x%x"
4877                            " from 0x%x to 0x%x",
4878                            msk,val,cval,nval);
4879         } else {
4880                 nval = val;
4881                 pvr2_trace(PVR2_TRACE_GPIO,
4882                            "GPIO direction changing to 0x%x",nval);
4883         }
4884         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4885 }
4886
4887
4888 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4889 {
4890         u32 cval,nval;
4891         int ret;
4892         if (~msk) {
4893                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4894                 if (ret) return ret;
4895                 nval = (cval & ~msk) | (val & msk);
4896                 pvr2_trace(PVR2_TRACE_GPIO,
4897                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4898                            msk,val,cval,nval);
4899         } else {
4900                 nval = val;
4901                 pvr2_trace(PVR2_TRACE_GPIO,
4902                            "GPIO output changing to 0x%x",nval);
4903         }
4904         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4905 }
4906
4907
4908 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
4909 {
4910         struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
4911         memset(vtp, 0, sizeof(*vtp));
4912         hdw->tuner_signal_stale = 0;
4913         pvr2_i2c_core_status_poll(hdw);
4914         /* Note: There apparently is no replacement for VIDIOC_CROPCAP
4915            using v4l2-subdev - therefore we can't support that AT ALL right
4916            now.  (Of course, no sub-drivers seem to implement it either.
4917            But now it's a a chicken and egg problem...) */
4918         v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
4919                              &hdw->tuner_signal_info);
4920         pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
4921                    " type=%u strength=%u audio=0x%x cap=0x%x"
4922                    " low=%u hi=%u",
4923                    vtp->type,
4924                    vtp->signal, vtp->rxsubchans, vtp->capability,
4925                    vtp->rangelow, vtp->rangehigh);
4926
4927         /* We have to do this to avoid getting into constant polling if
4928            there's nobody to answer a poll of cropcap info. */
4929         hdw->cropcap_stale = 0;
4930 }
4931
4932
4933 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
4934 {
4935         return hdw->input_avail_mask;
4936 }
4937
4938
4939 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
4940 {
4941         return hdw->input_allowed_mask;
4942 }
4943
4944
4945 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
4946 {
4947         if (hdw->input_val != v) {
4948                 hdw->input_val = v;
4949                 hdw->input_dirty = !0;
4950         }
4951
4952         /* Handle side effects - if we switch to a mode that needs the RF
4953            tuner, then select the right frequency choice as well and mark
4954            it dirty. */
4955         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
4956                 hdw->freqSelector = 0;
4957                 hdw->freqDirty = !0;
4958         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
4959                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
4960                 hdw->freqSelector = 1;
4961                 hdw->freqDirty = !0;
4962         }
4963         return 0;
4964 }
4965
4966
4967 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
4968                                unsigned int change_mask,
4969                                unsigned int change_val)
4970 {
4971         int ret = 0;
4972         unsigned int nv,m,idx;
4973         LOCK_TAKE(hdw->big_lock);
4974         do {
4975                 nv = hdw->input_allowed_mask & ~change_mask;
4976                 nv |= (change_val & change_mask);
4977                 nv &= hdw->input_avail_mask;
4978                 if (!nv) {
4979                         /* No legal modes left; return error instead. */
4980                         ret = -EPERM;
4981                         break;
4982                 }
4983                 hdw->input_allowed_mask = nv;
4984                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
4985                         /* Current mode is still in the allowed mask, so
4986                            we're done. */
4987                         break;
4988                 }
4989                 /* Select and switch to a mode that is still in the allowed
4990                    mask */
4991                 if (!hdw->input_allowed_mask) {
4992                         /* Nothing legal; give up */
4993                         break;
4994                 }
4995                 m = hdw->input_allowed_mask;
4996                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
4997                         if (!((1 << idx) & m)) continue;
4998                         pvr2_hdw_set_input(hdw,idx);
4999                         break;
5000                 }
5001         } while (0);
5002         LOCK_GIVE(hdw->big_lock);
5003         return ret;
5004 }
5005
5006
5007 /* Find I2C address of eeprom */
5008 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5009 {
5010         int result;
5011         LOCK_TAKE(hdw->ctl_lock); do {
5012                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5013                 result = pvr2_send_request(hdw,
5014                                            hdw->cmd_buffer,1,
5015                                            hdw->cmd_buffer,1);
5016                 if (result < 0) break;
5017                 result = hdw->cmd_buffer[0];
5018         } while(0); LOCK_GIVE(hdw->ctl_lock);
5019         return result;
5020 }
5021
5022
5023 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
5024                              struct v4l2_dbg_match *match, u64 reg_id,
5025                              int setFl, u64 *val_ptr)
5026 {
5027 #ifdef CONFIG_VIDEO_ADV_DEBUG
5028         struct pvr2_i2c_client *cp;
5029         struct v4l2_dbg_register req;
5030         int stat = 0;
5031         int okFl = 0;
5032
5033         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5034
5035         req.match = *match;
5036         req.reg = reg_id;
5037         if (setFl) req.val = *val_ptr;
5038         /* It would be nice to know if a sub-device answered the request */
5039         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5040         if (!setFl) *val_ptr = req.val;
5041         if (!okFl) mutex_lock(&hdw->i2c_list_lock); do {
5042                 list_for_each_entry(cp, &hdw->i2c_clients, list) {
5043                         if (!v4l2_chip_match_i2c_client(
5044                                     cp->client,
5045                                     &req.match)) {
5046                                 continue;
5047                         }
5048                         stat = pvr2_i2c_client_cmd(
5049                                 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
5050                                     VIDIOC_DBG_G_REGISTER),&req);
5051                         if (!setFl) *val_ptr = req.val;
5052                         okFl = !0;
5053                         break;
5054                 }
5055         } while (0); mutex_unlock(&hdw->i2c_list_lock);
5056         if (okFl) {
5057                 return stat;
5058         }
5059         return -EINVAL;
5060 #else
5061         return -ENOSYS;
5062 #endif
5063 }
5064
5065
5066 /*
5067   Stuff for Emacs to see, in order to encourage consistent editing style:
5068   *** Local Variables: ***
5069   *** mode: c ***
5070   *** fill-column: 75 ***
5071   *** tab-width: 8 ***
5072   *** c-basic-offset: 8 ***
5073   *** End: ***
5074   */