Pileus Git - ~andy/linux/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/firmware.h>
  25 #include <linux/videodev2.h>
  26 #include <media/v4l2-common.h>
  27 #include "pvrusb2.h"
  28 #include "pvrusb2-std.h"
  29 #include "pvrusb2-util.h"
  30 #include "pvrusb2-hdw.h"
  31 #include "pvrusb2-i2c-core.h"
  32 #include "pvrusb2-i2c-track.h"
  33 #include "pvrusb2-tuner.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38 #include "pvrusb2-fx2-cmd.h"
  39
  40 #define TV_MIN_FREQ     55250000L
  41 #define TV_MAX_FREQ    850000000L
  42
  43 /* This defines a minimum interval that the decoder must remain quiet
  44    before we are allowed to start it running. */
  45 #define TIME_MSEC_DECODER_WAIT 50
  46
  47 /* This defines a minimum interval that the encoder must remain quiet
  48    before we are allowed to configure it.  I had this originally set to
  49    50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
  50    things work better when it's set to 100msec. */
  51 #define TIME_MSEC_ENCODER_WAIT 100
  52
  53 /* This defines the minimum interval that the encoder must successfully run
  54    before we consider that the encoder has run at least once since its
  55    firmware has been loaded.  This measurement is in important for cases
  56    where we can't do something until we know that the encoder has been run
  57    at least once. */
  58 #define TIME_MSEC_ENCODER_OK 250
  59
  60 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  61 static DEFINE_MUTEX(pvr2_unit_mtx);
  62
  63 static int ctlchg;
  64 static int procreload;
  65 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  66 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  67 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  68 static int init_pause_msec;
  69
  70 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  71 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  72 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  73 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  74 module_param(procreload, int, S_IRUGO|S_IWUSR);
  75 MODULE_PARM_DESC(procreload,
  76                  "Attempt init failure recovery with firmware reload");
  77 module_param_array(tuner,    int, NULL, 0444);
  78 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  79 module_param_array(video_std,    int, NULL, 0444);
  80 MODULE_PARM_DESC(video_std,"specify initial video standard");
  81 module_param_array(tolerance,    int, NULL, 0444);
  82 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  83
  84 /* US Broadcast channel 7 (175.25 MHz) */
  85 static int default_tv_freq    = 175250000L;
  86 /* 104.3 MHz, a usable FM station for my area */
  87 static int default_radio_freq = 104300000L;
  88
  89 module_param_named(tv_freq, default_tv_freq, int, 0444);
  90 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  91 module_param_named(radio_freq, default_radio_freq, int, 0444);
  92 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  93
  94 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  95 #define PVR2_CTL_READ_ENDPOINT   0x81
  96
  97 #define PVR2_GPIO_IN 0x9008
  98 #define PVR2_GPIO_OUT 0x900c
  99 #define PVR2_GPIO_DIR 0x9020
 100
 101 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 102
 103 #define PVR2_FIRMWARE_ENDPOINT   0x02
 104
 105 /* size of a firmware chunk */
 106 #define FIRMWARE_CHUNK_SIZE 0x2000
 107
 108 static const char *module_names[] = {
 109         [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 110         [PVR2_CLIENT_ID_CX25840] = "cx25840",
 111         [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 112         [PVR2_CLIENT_ID_TUNER] = "tuner",
 113         [PVR2_CLIENT_ID_CS53132A] = "cs53132a",
 114 };
 115
 116
 117 static const unsigned char *module_i2c_addresses[] = {
 118         [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 119 };
 120
 121
 122 /* Define the list of additional controls we'll dynamically construct based
 123    on query of the cx2341x module. */
 124 struct pvr2_mpeg_ids {
 125         const char *strid;
 126         int id;
 127 };
 128 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 129         {
 130                 .strid = "audio_layer",
 131                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 132         },{
 133                 .strid = "audio_bitrate",
 134                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 135         },{
 136                 /* Already using audio_mode elsewhere :-( */
 137                 .strid = "mpeg_audio_mode",
 138                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 139         },{
 140                 .strid = "mpeg_audio_mode_extension",
 141                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 142         },{
 143                 .strid = "audio_emphasis",
 144                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 145         },{
 146                 .strid = "audio_crc",
 147                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 148         },{
 149                 .strid = "video_aspect",
 150                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 151         },{
 152                 .strid = "video_b_frames",
 153                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 154         },{
 155                 .strid = "video_gop_size",
 156                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 157         },{
 158                 .strid = "video_gop_closure",
 159                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 160         },{
 161                 .strid = "video_bitrate_mode",
 162                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 163         },{
 164                 .strid = "video_bitrate",
 165                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 166         },{
 167                 .strid = "video_bitrate_peak",
 168                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 169         },{
 170                 .strid = "video_temporal_decimation",
 171                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 172         },{
 173                 .strid = "stream_type",
 174                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 175         },{
 176                 .strid = "video_spatial_filter_mode",
 177                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 178         },{
 179                 .strid = "video_spatial_filter",
 180                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 181         },{
 182                 .strid = "video_luma_spatial_filter_type",
 183                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 184         },{
 185                 .strid = "video_chroma_spatial_filter_type",
 186                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 187         },{
 188                 .strid = "video_temporal_filter_mode",
 189                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 190         },{
 191                 .strid = "video_temporal_filter",
 192                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 193         },{
 194                 .strid = "video_median_filter_type",
 195                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 196         },{
 197                 .strid = "video_luma_median_filter_top",
 198                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 199         },{
 200                 .strid = "video_luma_median_filter_bottom",
 201                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 202         },{
 203                 .strid = "video_chroma_median_filter_top",
 204                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 205         },{
 206                 .strid = "video_chroma_median_filter_bottom",
 207                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 208         }
 209 };
 210 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 211
 212
 213 static const char *control_values_srate[] = {
 214         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 215         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 216         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 217 };
 218
 219
 220
 221 static const char *control_values_input[] = {
 222         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 223         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 224         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 225         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 226         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 227 };
 228
 229
 230 static const char *control_values_audiomode[] = {
 231         [V4L2_TUNER_MODE_MONO]   = "Mono",
 232         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 233         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 234         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 235         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 236 };
 237
 238
 239 static const char *control_values_hsm[] = {
 240         [PVR2_CVAL_HSM_FAIL] = "Fail",
 241         [PVR2_CVAL_HSM_HIGH] = "High",
 242         [PVR2_CVAL_HSM_FULL] = "Full",
 243 };
 244
 245
 246 static const char *pvr2_state_names[] = {
 247         [PVR2_STATE_NONE] =    "none",
 248         [PVR2_STATE_DEAD] =    "dead",
 249         [PVR2_STATE_COLD] =    "cold",
 250         [PVR2_STATE_WARM] =    "warm",
 251         [PVR2_STATE_ERROR] =   "error",
 252         [PVR2_STATE_READY] =   "ready",
 253         [PVR2_STATE_RUN] =     "run",
 254 };
 255
 256
 257 struct pvr2_fx2cmd_descdef {
 258         unsigned char id;
 259         unsigned char *desc;
 260 };
 261
 262 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 263         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 264         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 265         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 266         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 267         {FX2CMD_REG_WRITE, "write encoder register"},
 268         {FX2CMD_REG_READ, "read encoder register"},
 269         {FX2CMD_MEMSEL, "encoder memsel"},
 270         {FX2CMD_I2C_WRITE, "i2c write"},
 271         {FX2CMD_I2C_READ, "i2c read"},
 272         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 273         {FX2CMD_STREAMING_ON, "stream on"},
 274         {FX2CMD_STREAMING_OFF, "stream off"},
 275         {FX2CMD_FWPOST1, "fwpost1"},
 276         {FX2CMD_POWER_OFF, "power off"},
 277         {FX2CMD_POWER_ON, "power on"},
 278         {FX2CMD_DEEP_RESET, "deep reset"},
 279         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 280         {FX2CMD_GET_IR_CODE, "get IR code"},
 281         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 282         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 283         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 284         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 285         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 286         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 287         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 288 };
 289
 290
 291 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 292 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 293 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 294 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 295 static void pvr2_hdw_worker_i2c(struct work_struct *work);
 296 static void pvr2_hdw_worker_poll(struct work_struct *work);
 297 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 298 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 299 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 300 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 301 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 302 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 303 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 304 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 305 static void pvr2_hdw_quiescent_timeout(unsigned long);
 306 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 307 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 308 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 309 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 310                                 unsigned int timeout,int probe_fl,
 311                                 void *write_data,unsigned int write_len,
 312                                 void *read_data,unsigned int read_len);
 313 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 314
 315
 316 static void trace_stbit(const char *name,int val)
 317 {
 318         pvr2_trace(PVR2_TRACE_STBITS,
 319                    "State bit %s <-- %s",
 320                    name,(val ? "true" : "false"));
 321 }
 322
 323 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 324 {
 325         struct pvr2_hdw *hdw = cptr->hdw;
 326         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 327                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 328         } else {
 329                 *vp = 0;
 330         }
 331         return 0;
 332 }
 333
 334 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 335 {
 336         struct pvr2_hdw *hdw = cptr->hdw;
 337         unsigned int slotId = hdw->freqProgSlot;
 338         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 339                 hdw->freqTable[slotId-1] = v;
 340                 /* Handle side effects correctly - if we're tuned to this
 341                    slot, then forgot the slot id relation since the stored
 342                    frequency has been changed. */
 343                 if (hdw->freqSelector) {
 344                         if (hdw->freqSlotRadio == slotId) {
 345                                 hdw->freqSlotRadio = 0;
 346                         }
 347                 } else {
 348                         if (hdw->freqSlotTelevision == slotId) {
 349                                 hdw->freqSlotTelevision = 0;
 350                         }
 351                 }
 352         }
 353         return 0;
 354 }
 355
 356 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 357 {
 358         *vp = cptr->hdw->freqProgSlot;
 359         return 0;
 360 }
 361
 362 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 363 {
 364         struct pvr2_hdw *hdw = cptr->hdw;
 365         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 366                 hdw->freqProgSlot = v;
 367         }
 368         return 0;
 369 }
 370
 371 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 372 {
 373         struct pvr2_hdw *hdw = cptr->hdw;
 374         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 375         return 0;
 376 }
 377
 378 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 379 {
 380         unsigned freq = 0;
 381         struct pvr2_hdw *hdw = cptr->hdw;
 382         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 383         if (slotId > 0) {
 384                 freq = hdw->freqTable[slotId-1];
 385                 if (!freq) return 0;
 386                 pvr2_hdw_set_cur_freq(hdw,freq);
 387         }
 388         if (hdw->freqSelector) {
 389                 hdw->freqSlotRadio = slotId;
 390         } else {
 391                 hdw->freqSlotTelevision = slotId;
 392         }
 393         return 0;
 394 }
 395
 396 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 397 {
 398         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 399         return 0;
 400 }
 401
 402 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 403 {
 404         return cptr->hdw->freqDirty != 0;
 405 }
 406
 407 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 408 {
 409         cptr->hdw->freqDirty = 0;
 410 }
 411
 412 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 413 {
 414         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 415         return 0;
 416 }
 417
 418 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 419 {
 420         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 421         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 422         if (stat != 0) {
 423                 return stat;
 424         }
 425         *left = cap->bounds.left;
 426         return 0;
 427 }
 428
 429 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 430 {
 431         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 432         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 433         if (stat != 0) {
 434                 return stat;
 435         }
 436         *left = cap->bounds.left;
 437         if (cap->bounds.width > cptr->hdw->cropw_val) {
 438                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 439         }
 440         return 0;
 441 }
 442
 443 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 444 {
 445         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 446         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 447         if (stat != 0) {
 448                 return stat;
 449         }
 450         *top = cap->bounds.top;
 451         return 0;
 452 }
 453
 454 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 455 {
 456         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 457         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 458         if (stat != 0) {
 459                 return stat;
 460         }
 461         *top = cap->bounds.top;
 462         if (cap->bounds.height > cptr->hdw->croph_val) {
 463                 *top += cap->bounds.height - cptr->hdw->croph_val;
 464         }
 465         return 0;
 466 }
 467
 468 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
 469 {
 470         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 471         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 472         if (stat != 0) {
 473                 return stat;
 474         }
 475         *val = 0;
 476         if (cap->bounds.width > cptr->hdw->cropl_val) {
 477                 *val = cap->bounds.width - cptr->hdw->cropl_val;
 478         }
 479         return 0;
 480 }
 481
 482 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
 483 {
 484         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 485         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 486         if (stat != 0) {
 487                 return stat;
 488         }
 489         *val = 0;
 490         if (cap->bounds.height > cptr->hdw->cropt_val) {
 491                 *val = cap->bounds.height - cptr->hdw->cropt_val;
 492         }
 493         return 0;
 494 }
 495
 496 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 497 {
 498         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 499         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 500         if (stat != 0) {
 501                 return stat;
 502         }
 503         *val = cap->bounds.left;
 504         return 0;
 505 }
 506
 507 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 508 {
 509         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 510         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 511         if (stat != 0) {
 512                 return stat;
 513         }
 514         *val = cap->bounds.top;
 515         return 0;
 516 }
 517
 518 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 519 {
 520         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 521         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 522         if (stat != 0) {
 523                 return stat;
 524         }
 525         *val = cap->bounds.width;
 526         return 0;
 527 }
 528
 529 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 530 {
 531         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 532         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 533         if (stat != 0) {
 534                 return stat;
 535         }
 536         *val = cap->bounds.height;
 537         return 0;
 538 }
 539
 540 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 541 {
 542         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 543         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 544         if (stat != 0) {
 545                 return stat;
 546         }
 547         *val = cap->defrect.left;
 548         return 0;
 549 }
 550
 551 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 552 {
 553         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 554         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 555         if (stat != 0) {
 556                 return stat;
 557         }
 558         *val = cap->defrect.top;
 559         return 0;
 560 }
 561
 562 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 563 {
 564         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 565         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 566         if (stat != 0) {
 567                 return stat;
 568         }
 569         *val = cap->defrect.width;
 570         return 0;
 571 }
 572
 573 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 574 {
 575         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 576         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 577         if (stat != 0) {
 578                 return stat;
 579         }
 580         *val = cap->defrect.height;
 581         return 0;
 582 }
 583
 584 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 585 {
 586         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 587         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 588         if (stat != 0) {
 589                 return stat;
 590         }
 591         *val = cap->pixelaspect.numerator;
 592         return 0;
 593 }
 594
 595 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 596 {
 597         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 598         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 599         if (stat != 0) {
 600                 return stat;
 601         }
 602         *val = cap->pixelaspect.denominator;
 603         return 0;
 604 }
 605
 606 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 607 {
 608         /* Actual maximum depends on the video standard in effect. */
 609         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 610                 *vp = 480;
 611         } else {
 612                 *vp = 576;
 613         }
 614         return 0;
 615 }
 616
 617 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 618 {
 619         /* Actual minimum depends on device digitizer type. */
 620         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 621                 *vp = 75;
 622         } else {
 623                 *vp = 17;
 624         }
 625         return 0;
 626 }
 627
 628 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 629 {
 630         *vp = cptr->hdw->input_val;
 631         return 0;
 632 }
 633
 634 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 635 {
 636         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 637 }
 638
 639 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 640 {
 641         return pvr2_hdw_set_input(cptr->hdw,v);
 642 }
 643
 644 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 645 {
 646         return cptr->hdw->input_dirty != 0;
 647 }
 648
 649 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 650 {
 651         cptr->hdw->input_dirty = 0;
 652 }
 653
 654
 655 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 656 {
 657         unsigned long fv;
 658         struct pvr2_hdw *hdw = cptr->hdw;
 659         if (hdw->tuner_signal_stale) {
 660                 pvr2_hdw_status_poll(hdw);
 661         }
 662         fv = hdw->tuner_signal_info.rangehigh;
 663         if (!fv) {
 664                 /* Safety fallback */
 665                 *vp = TV_MAX_FREQ;
 666                 return 0;
 667         }
 668         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 669                 fv = (fv * 125) / 2;
 670         } else {
 671                 fv = fv * 62500;
 672         }
 673         *vp = fv;
 674         return 0;
 675 }
 676
 677 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 678 {
 679         unsigned long fv;
 680         struct pvr2_hdw *hdw = cptr->hdw;
 681         if (hdw->tuner_signal_stale) {
 682                 pvr2_hdw_status_poll(hdw);
 683         }
 684         fv = hdw->tuner_signal_info.rangelow;
 685         if (!fv) {
 686                 /* Safety fallback */
 687                 *vp = TV_MIN_FREQ;
 688                 return 0;
 689         }
 690         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 691                 fv = (fv * 125) / 2;
 692         } else {
 693                 fv = fv * 62500;
 694         }
 695         *vp = fv;
 696         return 0;
 697 }
 698
 699 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 700 {
 701         return cptr->hdw->enc_stale != 0;
 702 }
 703
 704 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 705 {
 706         cptr->hdw->enc_stale = 0;
 707         cptr->hdw->enc_unsafe_stale = 0;
 708 }
 709
 710 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 711 {
 712         int ret;
 713         struct v4l2_ext_controls cs;
 714         struct v4l2_ext_control c1;
 715         memset(&cs,0,sizeof(cs));
 716         memset(&c1,0,sizeof(c1));
 717         cs.controls = &c1;
 718         cs.count = 1;
 719         c1.id = cptr->info->v4l_id;
 720         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 721                                 VIDIOC_G_EXT_CTRLS);
 722         if (ret) return ret;
 723         *vp = c1.value;
 724         return 0;
 725 }
 726
 727 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 728 {
 729         int ret;
 730         struct pvr2_hdw *hdw = cptr->hdw;
 731         struct v4l2_ext_controls cs;
 732         struct v4l2_ext_control c1;
 733         memset(&cs,0,sizeof(cs));
 734         memset(&c1,0,sizeof(c1));
 735         cs.controls = &c1;
 736         cs.count = 1;
 737         c1.id = cptr->info->v4l_id;
 738         c1.value = v;
 739         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 740                                 hdw->state_encoder_run, &cs,
 741                                 VIDIOC_S_EXT_CTRLS);
 742         if (ret == -EBUSY) {
 743                 /* Oops.  cx2341x is telling us it's not safe to change
 744                    this control while we're capturing.  Make a note of this
 745                    fact so that the pipeline will be stopped the next time
 746                    controls are committed.  Then go on ahead and store this
 747                    change anyway. */
 748                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 749                                         0, &cs,
 750                                         VIDIOC_S_EXT_CTRLS);
 751                 if (!ret) hdw->enc_unsafe_stale = !0;
 752         }
 753         if (ret) return ret;
 754         hdw->enc_stale = !0;
 755         return 0;
 756 }
 757
 758 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 759 {
 760         struct v4l2_queryctrl qctrl;
 761         struct pvr2_ctl_info *info;
 762         qctrl.id = cptr->info->v4l_id;
 763         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 764         /* Strip out the const so we can adjust a function pointer.  It's
 765            OK to do this here because we know this is a dynamically created
 766            control, so the underlying storage for the info pointer is (a)
 767            private to us, and (b) not in read-only storage.  Either we do
 768            this or we significantly complicate the underlying control
 769            implementation. */
 770         info = (struct pvr2_ctl_info *)(cptr->info);
 771         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 772                 if (info->set_value) {
 773                         info->set_value = NULL;
 774                 }
 775         } else {
 776                 if (!(info->set_value)) {
 777                         info->set_value = ctrl_cx2341x_set;
 778                 }
 779         }
 780         return qctrl.flags;
 781 }
 782
 783 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 784 {
 785         *vp = cptr->hdw->state_pipeline_req;
 786         return 0;
 787 }
 788
 789 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 790 {
 791         *vp = cptr->hdw->master_state;
 792         return 0;
 793 }
 794
 795 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 796 {
 797         int result = pvr2_hdw_is_hsm(cptr->hdw);
 798         *vp = PVR2_CVAL_HSM_FULL;
 799         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 800         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 801         return 0;
 802 }
 803
 804 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 805 {
 806         *vp = cptr->hdw->std_mask_avail;
 807         return 0;
 808 }
 809
 810 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 811 {
 812         struct pvr2_hdw *hdw = cptr->hdw;
 813         v4l2_std_id ns;
 814         ns = hdw->std_mask_avail;
 815         ns = (ns & ~m) | (v & m);
 816         if (ns == hdw->std_mask_avail) return 0;
 817         hdw->std_mask_avail = ns;
 818         pvr2_hdw_internal_set_std_avail(hdw);
 819         pvr2_hdw_internal_find_stdenum(hdw);
 820         return 0;
 821 }
 822
 823 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 824                                char *bufPtr,unsigned int bufSize,
 825                                unsigned int *len)
 826 {
 827         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 828         return 0;
 829 }
 830
 831 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 832                                const char *bufPtr,unsigned int bufSize,
 833                                int *mskp,int *valp)
 834 {
 835         int ret;
 836         v4l2_std_id id;
 837         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 838         if (ret < 0) return ret;
 839         if (mskp) *mskp = id;
 840         if (valp) *valp = id;
 841         return 0;
 842 }
 843
 844 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 845 {
 846         *vp = cptr->hdw->std_mask_cur;
 847         return 0;
 848 }
 849
 850 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 851 {
 852         struct pvr2_hdw *hdw = cptr->hdw;
 853         v4l2_std_id ns;
 854         ns = hdw->std_mask_cur;
 855         ns = (ns & ~m) | (v & m);
 856         if (ns == hdw->std_mask_cur) return 0;
 857         hdw->std_mask_cur = ns;
 858         hdw->std_dirty = !0;
 859         pvr2_hdw_internal_find_stdenum(hdw);
 860         return 0;
 861 }
 862
 863 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 864 {
 865         return cptr->hdw->std_dirty != 0;
 866 }
 867
 868 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 869 {
 870         cptr->hdw->std_dirty = 0;
 871 }
 872
 873 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 874 {
 875         struct pvr2_hdw *hdw = cptr->hdw;
 876         pvr2_hdw_status_poll(hdw);
 877         *vp = hdw->tuner_signal_info.signal;
 878         return 0;
 879 }
 880
 881 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 882 {
 883         int val = 0;
 884         unsigned int subchan;
 885         struct pvr2_hdw *hdw = cptr->hdw;
 886         pvr2_hdw_status_poll(hdw);
 887         subchan = hdw->tuner_signal_info.rxsubchans;
 888         if (subchan & V4L2_TUNER_SUB_MONO) {
 889                 val |= (1 << V4L2_TUNER_MODE_MONO);
 890         }
 891         if (subchan & V4L2_TUNER_SUB_STEREO) {
 892                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 893         }
 894         if (subchan & V4L2_TUNER_SUB_LANG1) {
 895                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 896         }
 897         if (subchan & V4L2_TUNER_SUB_LANG2) {
 898                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 899         }
 900         *vp = val;
 901         return 0;
 902 }
 903
 904
 905 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 906 {
 907         struct pvr2_hdw *hdw = cptr->hdw;
 908         if (v < 0) return -EINVAL;
 909         if (v > hdw->std_enum_cnt) return -EINVAL;
 910         hdw->std_enum_cur = v;
 911         if (!v) return 0;
 912         v--;
 913         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 914         hdw->std_mask_cur = hdw->std_defs[v].id;
 915         hdw->std_dirty = !0;
 916         return 0;
 917 }
 918
 919
 920 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 921 {
 922         *vp = cptr->hdw->std_enum_cur;
 923         return 0;
 924 }
 925
 926
 927 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 928 {
 929         return cptr->hdw->std_dirty != 0;
 930 }
 931
 932
 933 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 934 {
 935         cptr->hdw->std_dirty = 0;
 936 }
 937
 938
 939 #define DEFINT(vmin,vmax) \
 940         .type = pvr2_ctl_int, \
 941         .def.type_int.min_value = vmin, \
 942         .def.type_int.max_value = vmax
 943
 944 #define DEFENUM(tab) \
 945         .type = pvr2_ctl_enum, \
 946         .def.type_enum.count = ARRAY_SIZE(tab), \
 947         .def.type_enum.value_names = tab
 948
 949 #define DEFBOOL \
 950         .type = pvr2_ctl_bool
 951
 952 #define DEFMASK(msk,tab) \
 953         .type = pvr2_ctl_bitmask, \
 954         .def.type_bitmask.valid_bits = msk, \
 955         .def.type_bitmask.bit_names = tab
 956
 957 #define DEFREF(vname) \
 958         .set_value = ctrl_set_##vname, \
 959         .get_value = ctrl_get_##vname, \
 960         .is_dirty = ctrl_isdirty_##vname, \
 961         .clear_dirty = ctrl_cleardirty_##vname
 962
 963
 964 #define VCREATE_FUNCS(vname) \
 965 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 966 {*vp = cptr->hdw->vname##_val; return 0;} \
 967 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 968 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 969 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 970 {return cptr->hdw->vname##_dirty != 0;} \
 971 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 972 {cptr->hdw->vname##_dirty = 0;}
 973
 974 VCREATE_FUNCS(brightness)
 975 VCREATE_FUNCS(contrast)
 976 VCREATE_FUNCS(saturation)
 977 VCREATE_FUNCS(hue)
 978 VCREATE_FUNCS(volume)
 979 VCREATE_FUNCS(balance)
 980 VCREATE_FUNCS(bass)
 981 VCREATE_FUNCS(treble)
 982 VCREATE_FUNCS(mute)
 983 VCREATE_FUNCS(cropl)
 984 VCREATE_FUNCS(cropt)
 985 VCREATE_FUNCS(cropw)
 986 VCREATE_FUNCS(croph)
 987 VCREATE_FUNCS(audiomode)
 988 VCREATE_FUNCS(res_hor)
 989 VCREATE_FUNCS(res_ver)
 990 VCREATE_FUNCS(srate)
 991
 992 /* Table definition of all controls which can be manipulated */
 993 static const struct pvr2_ctl_info control_defs[] = {
 994         {
 995                 .v4l_id = V4L2_CID_BRIGHTNESS,
 996                 .desc = "Brightness",
 997                 .name = "brightness",
 998                 .default_value = 128,
 999                 DEFREF(brightness),
1000                 DEFINT(0,255),
1001         },{
1002                 .v4l_id = V4L2_CID_CONTRAST,
1003                 .desc = "Contrast",
1004                 .name = "contrast",
1005                 .default_value = 68,
1006                 DEFREF(contrast),
1007                 DEFINT(0,127),
1008         },{
1009                 .v4l_id = V4L2_CID_SATURATION,
1010                 .desc = "Saturation",
1011                 .name = "saturation",
1012                 .default_value = 64,
1013                 DEFREF(saturation),
1014                 DEFINT(0,127),
1015         },{
1016                 .v4l_id = V4L2_CID_HUE,
1017                 .desc = "Hue",
1018                 .name = "hue",
1019                 .default_value = 0,
1020                 DEFREF(hue),
1021                 DEFINT(-128,127),
1022         },{
1023                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1024                 .desc = "Volume",
1025                 .name = "volume",
1026                 .default_value = 62000,
1027                 DEFREF(volume),
1028                 DEFINT(0,65535),
1029         },{
1030                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1031                 .desc = "Balance",
1032                 .name = "balance",
1033                 .default_value = 0,
1034                 DEFREF(balance),
1035                 DEFINT(-32768,32767),
1036         },{
1037                 .v4l_id = V4L2_CID_AUDIO_BASS,
1038                 .desc = "Bass",
1039                 .name = "bass",
1040                 .default_value = 0,
1041                 DEFREF(bass),
1042                 DEFINT(-32768,32767),
1043         },{
1044                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1045                 .desc = "Treble",
1046                 .name = "treble",
1047                 .default_value = 0,
1048                 DEFREF(treble),
1049                 DEFINT(-32768,32767),
1050         },{
1051                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1052                 .desc = "Mute",
1053                 .name = "mute",
1054                 .default_value = 0,
1055                 DEFREF(mute),
1056                 DEFBOOL,
1057         }, {
1058                 .desc = "Capture crop left margin",
1059                 .name = "crop_left",
1060                 .internal_id = PVR2_CID_CROPL,
1061                 .default_value = 0,
1062                 DEFREF(cropl),
1063                 DEFINT(-129, 340),
1064                 .get_min_value = ctrl_cropl_min_get,
1065                 .get_max_value = ctrl_cropl_max_get,
1066                 .get_def_value = ctrl_get_cropcapdl,
1067         }, {
1068                 .desc = "Capture crop top margin",
1069                 .name = "crop_top",
1070                 .internal_id = PVR2_CID_CROPT,
1071                 .default_value = 0,
1072                 DEFREF(cropt),
1073                 DEFINT(-35, 544),
1074                 .get_min_value = ctrl_cropt_min_get,
1075                 .get_max_value = ctrl_cropt_max_get,
1076                 .get_def_value = ctrl_get_cropcapdt,
1077         }, {
1078                 .desc = "Capture crop width",
1079                 .name = "crop_width",
1080                 .internal_id = PVR2_CID_CROPW,
1081                 .default_value = 720,
1082                 DEFREF(cropw),
1083                 .get_max_value = ctrl_cropw_max_get,
1084                 .get_def_value = ctrl_get_cropcapdw,
1085         }, {
1086                 .desc = "Capture crop height",
1087                 .name = "crop_height",
1088                 .internal_id = PVR2_CID_CROPH,
1089                 .default_value = 480,
1090                 DEFREF(croph),
1091                 .get_max_value = ctrl_croph_max_get,
1092                 .get_def_value = ctrl_get_cropcapdh,
1093         }, {
1094                 .desc = "Capture capability pixel aspect numerator",
1095                 .name = "cropcap_pixel_numerator",
1096                 .internal_id = PVR2_CID_CROPCAPPAN,
1097                 .get_value = ctrl_get_cropcappan,
1098         }, {
1099                 .desc = "Capture capability pixel aspect denominator",
1100                 .name = "cropcap_pixel_denominator",
1101                 .internal_id = PVR2_CID_CROPCAPPAD,
1102                 .get_value = ctrl_get_cropcappad,
1103         }, {
1104                 .desc = "Capture capability bounds top",
1105                 .name = "cropcap_bounds_top",
1106                 .internal_id = PVR2_CID_CROPCAPBT,
1107                 .get_value = ctrl_get_cropcapbt,
1108         }, {
1109                 .desc = "Capture capability bounds left",
1110                 .name = "cropcap_bounds_left",
1111                 .internal_id = PVR2_CID_CROPCAPBL,
1112                 .get_value = ctrl_get_cropcapbl,
1113         }, {
1114                 .desc = "Capture capability bounds width",
1115                 .name = "cropcap_bounds_width",
1116                 .internal_id = PVR2_CID_CROPCAPBW,
1117                 .get_value = ctrl_get_cropcapbw,
1118         }, {
1119                 .desc = "Capture capability bounds height",
1120                 .name = "cropcap_bounds_height",
1121                 .internal_id = PVR2_CID_CROPCAPBH,
1122                 .get_value = ctrl_get_cropcapbh,
1123         },{
1124                 .desc = "Video Source",
1125                 .name = "input",
1126                 .internal_id = PVR2_CID_INPUT,
1127                 .default_value = PVR2_CVAL_INPUT_TV,
1128                 .check_value = ctrl_check_input,
1129                 DEFREF(input),
1130                 DEFENUM(control_values_input),
1131         },{
1132                 .desc = "Audio Mode",
1133                 .name = "audio_mode",
1134                 .internal_id = PVR2_CID_AUDIOMODE,
1135                 .default_value = V4L2_TUNER_MODE_STEREO,
1136                 DEFREF(audiomode),
1137                 DEFENUM(control_values_audiomode),
1138         },{
1139                 .desc = "Horizontal capture resolution",
1140                 .name = "resolution_hor",
1141                 .internal_id = PVR2_CID_HRES,
1142                 .default_value = 720,
1143                 DEFREF(res_hor),
1144                 DEFINT(19,720),
1145         },{
1146                 .desc = "Vertical capture resolution",
1147                 .name = "resolution_ver",
1148                 .internal_id = PVR2_CID_VRES,
1149                 .default_value = 480,
1150                 DEFREF(res_ver),
1151                 DEFINT(17,576),
1152                 /* Hook in check for video standard and adjust maximum
1153                    depending on the standard. */
1154                 .get_max_value = ctrl_vres_max_get,
1155                 .get_min_value = ctrl_vres_min_get,
1156         },{
1157                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1158                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1159                 .desc = "Audio Sampling Frequency",
1160                 .name = "srate",
1161                 DEFREF(srate),
1162                 DEFENUM(control_values_srate),
1163         },{
1164                 .desc = "Tuner Frequency (Hz)",
1165                 .name = "frequency",
1166                 .internal_id = PVR2_CID_FREQUENCY,
1167                 .default_value = 0,
1168                 .set_value = ctrl_freq_set,
1169                 .get_value = ctrl_freq_get,
1170                 .is_dirty = ctrl_freq_is_dirty,
1171                 .clear_dirty = ctrl_freq_clear_dirty,
1172                 DEFINT(0,0),
1173                 /* Hook in check for input value (tv/radio) and adjust
1174                    max/min values accordingly */
1175                 .get_max_value = ctrl_freq_max_get,
1176                 .get_min_value = ctrl_freq_min_get,
1177         },{
1178                 .desc = "Channel",
1179                 .name = "channel",
1180                 .set_value = ctrl_channel_set,
1181                 .get_value = ctrl_channel_get,
1182                 DEFINT(0,FREQTABLE_SIZE),
1183         },{
1184                 .desc = "Channel Program Frequency",
1185                 .name = "freq_table_value",
1186                 .set_value = ctrl_channelfreq_set,
1187                 .get_value = ctrl_channelfreq_get,
1188                 DEFINT(0,0),
1189                 /* Hook in check for input value (tv/radio) and adjust
1190                    max/min values accordingly */
1191                 .get_max_value = ctrl_freq_max_get,
1192                 .get_min_value = ctrl_freq_min_get,
1193         },{
1194                 .desc = "Channel Program ID",
1195                 .name = "freq_table_channel",
1196                 .set_value = ctrl_channelprog_set,
1197                 .get_value = ctrl_channelprog_get,
1198                 DEFINT(0,FREQTABLE_SIZE),
1199         },{
1200                 .desc = "Streaming Enabled",
1201                 .name = "streaming_enabled",
1202                 .get_value = ctrl_streamingenabled_get,
1203                 DEFBOOL,
1204         },{
1205                 .desc = "USB Speed",
1206                 .name = "usb_speed",
1207                 .get_value = ctrl_hsm_get,
1208                 DEFENUM(control_values_hsm),
1209         },{
1210                 .desc = "Master State",
1211                 .name = "master_state",
1212                 .get_value = ctrl_masterstate_get,
1213                 DEFENUM(pvr2_state_names),
1214         },{
1215                 .desc = "Signal Present",
1216                 .name = "signal_present",
1217                 .get_value = ctrl_signal_get,
1218                 DEFINT(0,65535),
1219         },{
1220                 .desc = "Audio Modes Present",
1221                 .name = "audio_modes_present",
1222                 .get_value = ctrl_audio_modes_present_get,
1223                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1224                    v4l.  Nothing outside of this module cares about this,
1225                    but I reuse it in order to also reuse the
1226                    control_values_audiomode string table. */
1227                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1228                          (1 << V4L2_TUNER_MODE_STEREO)|
1229                          (1 << V4L2_TUNER_MODE_LANG1)|
1230                          (1 << V4L2_TUNER_MODE_LANG2)),
1231                         control_values_audiomode),
1232         },{
1233                 .desc = "Video Standards Available Mask",
1234                 .name = "video_standard_mask_available",
1235                 .internal_id = PVR2_CID_STDAVAIL,
1236                 .skip_init = !0,
1237                 .get_value = ctrl_stdavail_get,
1238                 .set_value = ctrl_stdavail_set,
1239                 .val_to_sym = ctrl_std_val_to_sym,
1240                 .sym_to_val = ctrl_std_sym_to_val,
1241                 .type = pvr2_ctl_bitmask,
1242         },{
1243                 .desc = "Video Standards In Use Mask",
1244                 .name = "video_standard_mask_active",
1245                 .internal_id = PVR2_CID_STDCUR,
1246                 .skip_init = !0,
1247                 .get_value = ctrl_stdcur_get,
1248                 .set_value = ctrl_stdcur_set,
1249                 .is_dirty = ctrl_stdcur_is_dirty,
1250                 .clear_dirty = ctrl_stdcur_clear_dirty,
1251                 .val_to_sym = ctrl_std_val_to_sym,
1252                 .sym_to_val = ctrl_std_sym_to_val,
1253                 .type = pvr2_ctl_bitmask,
1254         },{
1255                 .desc = "Video Standard Name",
1256                 .name = "video_standard",
1257                 .internal_id = PVR2_CID_STDENUM,
1258                 .skip_init = !0,
1259                 .get_value = ctrl_stdenumcur_get,
1260                 .set_value = ctrl_stdenumcur_set,
1261                 .is_dirty = ctrl_stdenumcur_is_dirty,
1262                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1263                 .type = pvr2_ctl_enum,
1264         }
1265 };
1266
1267 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1268
1269
1270 const char *pvr2_config_get_name(enum pvr2_config cfg)
1271 {
1272         switch (cfg) {
1273         case pvr2_config_empty: return "empty";
1274         case pvr2_config_mpeg: return "mpeg";
1275         case pvr2_config_vbi: return "vbi";
1276         case pvr2_config_pcm: return "pcm";
1277         case pvr2_config_rawvideo: return "raw video";
1278         }
1279         return "<unknown>";
1280 }
1281
1282
1283 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1284 {
1285         return hdw->usb_dev;
1286 }
1287
1288
1289 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1290 {
1291         return hdw->serial_number;
1292 }
1293
1294
1295 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1296 {
1297         return hdw->bus_info;
1298 }
1299
1300
1301 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1302 {
1303         return hdw->identifier;
1304 }
1305
1306
1307 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1308 {
1309         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1310 }
1311
1312 /* Set the currently tuned frequency and account for all possible
1313    driver-core side effects of this action. */
1314 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1315 {
1316         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1317                 if (hdw->freqSelector) {
1318                         /* Swing over to radio frequency selection */
1319                         hdw->freqSelector = 0;
1320                         hdw->freqDirty = !0;
1321                 }
1322                 if (hdw->freqValRadio != val) {
1323                         hdw->freqValRadio = val;
1324                         hdw->freqSlotRadio = 0;
1325                         hdw->freqDirty = !0;
1326                 }
1327         } else {
1328                 if (!(hdw->freqSelector)) {
1329                         /* Swing over to television frequency selection */
1330                         hdw->freqSelector = 1;
1331                         hdw->freqDirty = !0;
1332                 }
1333                 if (hdw->freqValTelevision != val) {
1334                         hdw->freqValTelevision = val;
1335                         hdw->freqSlotTelevision = 0;
1336                         hdw->freqDirty = !0;
1337                 }
1338         }
1339 }
1340
1341 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1342 {
1343         return hdw->unit_number;
1344 }
1345
1346
1347 /* Attempt to locate one of the given set of files.  Messages are logged
1348    appropriate to what has been found.  The return value will be 0 or
1349    greater on success (it will be the index of the file name found) and
1350    fw_entry will be filled in.  Otherwise a negative error is returned on
1351    failure.  If the return value is -ENOENT then no viable firmware file
1352    could be located. */
1353 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1354                                 const struct firmware **fw_entry,
1355                                 const char *fwtypename,
1356                                 unsigned int fwcount,
1357                                 const char *fwnames[])
1358 {
1359         unsigned int idx;
1360         int ret = -EINVAL;
1361         for (idx = 0; idx < fwcount; idx++) {
1362                 ret = request_firmware(fw_entry,
1363                                        fwnames[idx],
1364                                        &hdw->usb_dev->dev);
1365                 if (!ret) {
1366                         trace_firmware("Located %s firmware: %s;"
1367                                        " uploading...",
1368                                        fwtypename,
1369                                        fwnames[idx]);
1370                         return idx;
1371                 }
1372                 if (ret == -ENOENT) continue;
1373                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1374                            "request_firmware fatal error with code=%d",ret);
1375                 return ret;
1376         }
1377         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1378                    "***WARNING***"
1379                    " Device %s firmware"
1380                    " seems to be missing.",
1381                    fwtypename);
1382         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1383                    "Did you install the pvrusb2 firmware files"
1384                    " in their proper location?");
1385         if (fwcount == 1) {
1386                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1387                            "request_firmware unable to locate %s file %s",
1388                            fwtypename,fwnames[0]);
1389         } else {
1390                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1391                            "request_firmware unable to locate"
1392                            " one of the following %s files:",
1393                            fwtypename);
1394                 for (idx = 0; idx < fwcount; idx++) {
1395                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1396                                    "request_firmware: Failed to find %s",
1397                                    fwnames[idx]);
1398                 }
1399         }
1400         return ret;
1401 }
1402
1403
1404 /*
1405  * pvr2_upload_firmware1().
1406  *
1407  * Send the 8051 firmware to the device.  After the upload, arrange for
1408  * device to re-enumerate.
1409  *
1410  * NOTE : the pointer to the firmware data given by request_firmware()
1411  * is not suitable for an usb transaction.
1412  *
1413  */
1414 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1415 {
1416         const struct firmware *fw_entry = NULL;
1417         void  *fw_ptr;
1418         unsigned int pipe;
1419         int ret;
1420         u16 address;
1421
1422         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1423                 hdw->fw1_state = FW1_STATE_OK;
1424                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1425                            "Connected device type defines"
1426                            " no firmware to upload; ignoring firmware");
1427                 return -ENOTTY;
1428         }
1429
1430         hdw->fw1_state = FW1_STATE_FAILED; // default result
1431
1432         trace_firmware("pvr2_upload_firmware1");
1433
1434         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1435                                    hdw->hdw_desc->fx2_firmware.cnt,
1436                                    hdw->hdw_desc->fx2_firmware.lst);
1437         if (ret < 0) {
1438                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1439                 return ret;
1440         }
1441
1442         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1443         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1444
1445         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1446
1447         if (fw_entry->size != 0x2000){
1448                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1449                 release_firmware(fw_entry);
1450                 return -ENOMEM;
1451         }
1452
1453         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1454         if (fw_ptr == NULL){
1455                 release_firmware(fw_entry);
1456                 return -ENOMEM;
1457         }
1458
1459         /* We have to hold the CPU during firmware upload. */
1460         pvr2_hdw_cpureset_assert(hdw,1);
1461
1462         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1463            chunk. */
1464
1465         ret = 0;
1466         for(address = 0; address < fw_entry->size; address += 0x800) {
1467                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1468                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1469                                        0, fw_ptr, 0x800, HZ);
1470         }
1471
1472         trace_firmware("Upload done, releasing device's CPU");
1473
1474         /* Now release the CPU.  It will disconnect and reconnect later. */
1475         pvr2_hdw_cpureset_assert(hdw,0);
1476
1477         kfree(fw_ptr);
1478         release_firmware(fw_entry);
1479
1480         trace_firmware("Upload done (%d bytes sent)",ret);
1481
1482         /* We should have written 8192 bytes */
1483         if (ret == 8192) {
1484                 hdw->fw1_state = FW1_STATE_RELOAD;
1485                 return 0;
1486         }
1487
1488         return -EIO;
1489 }
1490
1491
1492 /*
1493  * pvr2_upload_firmware2()
1494  *
1495  * This uploads encoder firmware on endpoint 2.
1496  *
1497  */
1498
1499 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1500 {
1501         const struct firmware *fw_entry = NULL;
1502         void  *fw_ptr;
1503         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1504         int actual_length;
1505         int ret = 0;
1506         int fwidx;
1507         static const char *fw_files[] = {
1508                 CX2341X_FIRM_ENC_FILENAME,
1509         };
1510
1511         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1512                 return 0;
1513         }
1514
1515         trace_firmware("pvr2_upload_firmware2");
1516
1517         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1518                                    ARRAY_SIZE(fw_files), fw_files);
1519         if (ret < 0) return ret;
1520         fwidx = ret;
1521         ret = 0;
1522         /* Since we're about to completely reinitialize the encoder,
1523            invalidate our cached copy of its configuration state.  Next
1524            time we configure the encoder, then we'll fully configure it. */
1525         hdw->enc_cur_valid = 0;
1526
1527         /* Encoder is about to be reset so note that as far as we're
1528            concerned now, the encoder has never been run. */
1529         del_timer_sync(&hdw->encoder_run_timer);
1530         if (hdw->state_encoder_runok) {
1531                 hdw->state_encoder_runok = 0;
1532                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1533         }
1534
1535         /* First prepare firmware loading */
1536         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1537         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1538         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1539         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1540         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1541         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1542         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1543         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1544         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1545         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1546         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1547         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1548         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1549         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1550         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1551         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1552         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1553         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1554
1555         if (ret) {
1556                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1557                            "firmware2 upload prep failed, ret=%d",ret);
1558                 release_firmware(fw_entry);
1559                 goto done;
1560         }
1561
1562         /* Now send firmware */
1563
1564         fw_len = fw_entry->size;
1565
1566         if (fw_len % sizeof(u32)) {
1567                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1568                            "size of %s firmware"
1569                            " must be a multiple of %zu bytes",
1570                            fw_files[fwidx],sizeof(u32));
1571                 release_firmware(fw_entry);
1572                 ret = -EINVAL;
1573                 goto done;
1574         }
1575
1576         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1577         if (fw_ptr == NULL){
1578                 release_firmware(fw_entry);
1579                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1580                            "failed to allocate memory for firmware2 upload");
1581                 ret = -ENOMEM;
1582                 goto done;
1583         }
1584
1585         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1586
1587         fw_done = 0;
1588         for (fw_done = 0; fw_done < fw_len;) {
1589                 bcnt = fw_len - fw_done;
1590                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1591                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1592                 /* Usbsnoop log shows that we must swap bytes... */
1593                 /* Some background info: The data being swapped here is a
1594                    firmware image destined for the mpeg encoder chip that
1595                    lives at the other end of a USB endpoint.  The encoder
1596                    chip always talks in 32 bit chunks and its storage is
1597                    organized into 32 bit words.  However from the file
1598                    system to the encoder chip everything is purely a byte
1599                    stream.  The firmware file's contents are always 32 bit
1600                    swapped from what the encoder expects.  Thus the need
1601                    always exists to swap the bytes regardless of the endian
1602                    type of the host processor and therefore swab32() makes
1603                    the most sense. */
1604                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1605                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1606
1607                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1608                                     &actual_length, HZ);
1609                 ret |= (actual_length != bcnt);
1610                 if (ret) break;
1611                 fw_done += bcnt;
1612         }
1613
1614         trace_firmware("upload of %s : %i / %i ",
1615                        fw_files[fwidx],fw_done,fw_len);
1616
1617         kfree(fw_ptr);
1618         release_firmware(fw_entry);
1619
1620         if (ret) {
1621                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1622                            "firmware2 upload transfer failure");
1623                 goto done;
1624         }
1625
1626         /* Finish upload */
1627
1628         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1629         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1630         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1631
1632         if (ret) {
1633                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1634                            "firmware2 upload post-proc failure");
1635         }
1636
1637  done:
1638         if (hdw->hdw_desc->signal_routing_scheme ==
1639             PVR2_ROUTING_SCHEME_GOTVIEW) {
1640                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1641                    hardware. */
1642                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1643         }
1644         return ret;
1645 }
1646
1647
1648 static const char *pvr2_get_state_name(unsigned int st)
1649 {
1650         if (st < ARRAY_SIZE(pvr2_state_names)) {
1651                 return pvr2_state_names[st];
1652         }
1653         return "???";
1654 }
1655
1656 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1657 {
1658         if (hdw->decoder_ctrl) {
1659                 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt, enablefl);
1660                 return 0;
1661         }
1662         /* Even though we really only care about the video decoder chip at
1663            this point, we'll broadcast stream on/off to all sub-devices
1664            anyway, just in case somebody else wants to hear the
1665            command... */
1666         v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1667         if (hdw->decoder_client_id) {
1668                 /* We get here if the encoder has been noticed.  Otherwise
1669                    we'll issue a warning to the user (which should
1670                    normally never happen). */
1671                 return 0;
1672         }
1673         if (!hdw->flag_decoder_missed) {
1674                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1675                            "WARNING: No decoder present");
1676                 hdw->flag_decoder_missed = !0;
1677                 trace_stbit("flag_decoder_missed",
1678                             hdw->flag_decoder_missed);
1679         }
1680         return -EIO;
1681 }
1682
1683
1684 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1685 {
1686         if (hdw->decoder_ctrl == ptr) return;
1687         hdw->decoder_ctrl = ptr;
1688         if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1689                 hdw->flag_decoder_missed = 0;
1690                 trace_stbit("flag_decoder_missed",
1691                             hdw->flag_decoder_missed);
1692                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1693                            "Decoder has appeared");
1694                 pvr2_hdw_state_sched(hdw);
1695         }
1696 }
1697
1698
1699 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1700 {
1701         return hdw->master_state;
1702 }
1703
1704
1705 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1706 {
1707         if (!hdw->flag_tripped) return 0;
1708         hdw->flag_tripped = 0;
1709         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1710                    "Clearing driver error statuss");
1711         return !0;
1712 }
1713
1714
1715 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1716 {
1717         int fl;
1718         LOCK_TAKE(hdw->big_lock); do {
1719                 fl = pvr2_hdw_untrip_unlocked(hdw);
1720         } while (0); LOCK_GIVE(hdw->big_lock);
1721         if (fl) pvr2_hdw_state_sched(hdw);
1722         return 0;
1723 }
1724
1725
1726
1727
1728 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1729 {
1730         return hdw->state_pipeline_req != 0;
1731 }
1732
1733
1734 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1735 {
1736         int ret,st;
1737         LOCK_TAKE(hdw->big_lock); do {
1738                 pvr2_hdw_untrip_unlocked(hdw);
1739                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1740                         hdw->state_pipeline_req = enable_flag != 0;
1741                         pvr2_trace(PVR2_TRACE_START_STOP,
1742                                    "/*--TRACE_STREAM--*/ %s",
1743                                    enable_flag ? "enable" : "disable");
1744                 }
1745                 pvr2_hdw_state_sched(hdw);
1746         } while (0); LOCK_GIVE(hdw->big_lock);
1747         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1748         if (enable_flag) {
1749                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1750                         if (st != PVR2_STATE_READY) return -EIO;
1751                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1752                 }
1753         }
1754         return 0;
1755 }
1756
1757
1758 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1759 {
1760         int fl;
1761         LOCK_TAKE(hdw->big_lock);
1762         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1763                 hdw->desired_stream_type = config;
1764                 hdw->state_pipeline_config = 0;
1765                 trace_stbit("state_pipeline_config",
1766                             hdw->state_pipeline_config);
1767                 pvr2_hdw_state_sched(hdw);
1768         }
1769         LOCK_GIVE(hdw->big_lock);
1770         if (fl) return 0;
1771         return pvr2_hdw_wait(hdw,0);
1772 }
1773
1774
1775 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1776 {
1777         int unit_number = hdw->unit_number;
1778         int tp = -1;
1779         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1780                 tp = tuner[unit_number];
1781         }
1782         if (tp < 0) return -EINVAL;
1783         hdw->tuner_type = tp;
1784         hdw->tuner_updated = !0;
1785         return 0;
1786 }
1787
1788
1789 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1790 {
1791         int unit_number = hdw->unit_number;
1792         int tp = 0;
1793         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1794                 tp = video_std[unit_number];
1795                 if (tp) return tp;
1796         }
1797         return 0;
1798 }
1799
1800
1801 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1802 {
1803         int unit_number = hdw->unit_number;
1804         int tp = 0;
1805         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1806                 tp = tolerance[unit_number];
1807         }
1808         return tp;
1809 }
1810
1811
1812 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1813 {
1814         /* Try a harmless request to fetch the eeprom's address over
1815            endpoint 1.  See what happens.  Only the full FX2 image can
1816            respond to this.  If this probe fails then likely the FX2
1817            firmware needs be loaded. */
1818         int result;
1819         LOCK_TAKE(hdw->ctl_lock); do {
1820                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1821                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1822                                            hdw->cmd_buffer,1,
1823                                            hdw->cmd_buffer,1);
1824                 if (result < 0) break;
1825         } while(0); LOCK_GIVE(hdw->ctl_lock);
1826         if (result) {
1827                 pvr2_trace(PVR2_TRACE_INIT,
1828                            "Probe of device endpoint 1 result status %d",
1829                            result);
1830         } else {
1831                 pvr2_trace(PVR2_TRACE_INIT,
1832                            "Probe of device endpoint 1 succeeded");
1833         }
1834         return result == 0;
1835 }
1836
1837 struct pvr2_std_hack {
1838         v4l2_std_id pat;  /* Pattern to match */
1839         v4l2_std_id msk;  /* Which bits we care about */
1840         v4l2_std_id std;  /* What additional standards or default to set */
1841 };
1842
1843 /* This data structure labels specific combinations of standards from
1844    tveeprom that we'll try to recognize.  If we recognize one, then assume
1845    a specified default standard to use.  This is here because tveeprom only
1846    tells us about available standards not the intended default standard (if
1847    any) for the device in question.  We guess the default based on what has
1848    been reported as available.  Note that this is only for guessing a
1849    default - which can always be overridden explicitly - and if the user
1850    has otherwise named a default then that default will always be used in
1851    place of this table. */
1852 static const struct pvr2_std_hack std_eeprom_maps[] = {
1853         {       /* PAL(B/G) */
1854                 .pat = V4L2_STD_B|V4L2_STD_GH,
1855                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1856         },
1857         {       /* NTSC(M) */
1858                 .pat = V4L2_STD_MN,
1859                 .std = V4L2_STD_NTSC_M,
1860         },
1861         {       /* PAL(I) */
1862                 .pat = V4L2_STD_PAL_I,
1863                 .std = V4L2_STD_PAL_I,
1864         },
1865         {       /* SECAM(L/L') */
1866                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1867                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1868         },
1869         {       /* PAL(D/D1/K) */
1870                 .pat = V4L2_STD_DK,
1871                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1872         },
1873 };
1874
1875 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1876 {
1877         char buf[40];
1878         unsigned int bcnt;
1879         v4l2_std_id std1,std2,std3;
1880
1881         std1 = get_default_standard(hdw);
1882         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1883
1884         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1885         pvr2_trace(PVR2_TRACE_STD,
1886                    "Supported video standard(s) reported available"
1887                    " in hardware: %.*s",
1888                    bcnt,buf);
1889
1890         hdw->std_mask_avail = hdw->std_mask_eeprom;
1891
1892         std2 = (std1|std3) & ~hdw->std_mask_avail;
1893         if (std2) {
1894                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1895                 pvr2_trace(PVR2_TRACE_STD,
1896                            "Expanding supported video standards"
1897                            " to include: %.*s",
1898                            bcnt,buf);
1899                 hdw->std_mask_avail |= std2;
1900         }
1901
1902         pvr2_hdw_internal_set_std_avail(hdw);
1903
1904         if (std1) {
1905                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1906                 pvr2_trace(PVR2_TRACE_STD,
1907                            "Initial video standard forced to %.*s",
1908                            bcnt,buf);
1909                 hdw->std_mask_cur = std1;
1910                 hdw->std_dirty = !0;
1911                 pvr2_hdw_internal_find_stdenum(hdw);
1912                 return;
1913         }
1914         if (std3) {
1915                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1916                 pvr2_trace(PVR2_TRACE_STD,
1917                            "Initial video standard"
1918                            " (determined by device type): %.*s",bcnt,buf);
1919                 hdw->std_mask_cur = std3;
1920                 hdw->std_dirty = !0;
1921                 pvr2_hdw_internal_find_stdenum(hdw);
1922                 return;
1923         }
1924
1925         {
1926                 unsigned int idx;
1927                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1928                         if (std_eeprom_maps[idx].msk ?
1929                             ((std_eeprom_maps[idx].pat ^
1930                              hdw->std_mask_eeprom) &
1931                              std_eeprom_maps[idx].msk) :
1932                             (std_eeprom_maps[idx].pat !=
1933                              hdw->std_mask_eeprom)) continue;
1934                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1935                                                   std_eeprom_maps[idx].std);
1936                         pvr2_trace(PVR2_TRACE_STD,
1937                                    "Initial video standard guessed as %.*s",
1938                                    bcnt,buf);
1939                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1940                         hdw->std_dirty = !0;
1941                         pvr2_hdw_internal_find_stdenum(hdw);
1942                         return;
1943                 }
1944         }
1945
1946         if (hdw->std_enum_cnt > 1) {
1947                 // Autoselect the first listed standard
1948                 hdw->std_enum_cur = 1;
1949                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1950                 hdw->std_dirty = !0;
1951                 pvr2_trace(PVR2_TRACE_STD,
1952                            "Initial video standard auto-selected to %s",
1953                            hdw->std_defs[hdw->std_enum_cur-1].name);
1954                 return;
1955         }
1956
1957         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1958                    "Unable to select a viable initial video standard");
1959 }
1960
1961
1962 static unsigned int pvr2_copy_i2c_addr_list(
1963         unsigned short *dst, const unsigned char *src,
1964         unsigned int dst_max)
1965 {
1966         unsigned int cnt;
1967         if (!src) return 0;
1968         while (src[cnt] && (cnt + 1) < dst_max) {
1969                 dst[cnt] = src[cnt];
1970                 cnt++;
1971         }
1972         dst[cnt] = I2C_CLIENT_END;
1973         return cnt;
1974 }
1975
1976
1977 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1978                                 const struct pvr2_device_client_desc *cd)
1979 {
1980         const char *fname;
1981         unsigned char mid;
1982         struct v4l2_subdev *sd;
1983         unsigned int i2ccnt;
1984         const unsigned char *p;
1985         /* Arbitrary count - max # i2c addresses we will probe */
1986         unsigned short i2caddr[25];
1987
1988         mid = cd->module_id;
1989         fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
1990         if (!fname) {
1991                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1992                            "Module ID %u for device %s has no name",
1993                            mid,
1994                            hdw->hdw_desc->description);
1995                 return -EINVAL;
1996         }
1997
1998         i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
1999                                          ARRAY_SIZE(i2caddr));
2000         if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2001                          module_i2c_addresses[mid] : NULL) != NULL)) {
2002                 /* Second chance: Try default i2c address list */
2003                 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2004                                                  ARRAY_SIZE(i2caddr));
2005         }
2006
2007         if (!i2ccnt) {
2008                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2009                            "Module ID %u (%s) for device %s:"
2010                            " No i2c addresses",
2011                            mid, fname, hdw->hdw_desc->description);
2012                 return -EINVAL;
2013         }
2014
2015         /* Note how the 2nd and 3rd arguments are the same for both
2016          * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev().  Why?
2017          * Well the 2nd argument is the module name to load, while the 3rd
2018          * argument is documented in the framework as being the "chipid" -
2019          * and every other place where I can find examples of this, the
2020          * "chipid" appears to just be the module name again.  So here we
2021          * just do the same thing. */
2022         if (i2ccnt == 1) {
2023                 sd = v4l2_i2c_new_subdev(&hdw->i2c_adap,
2024                                          fname, fname,
2025                                          i2caddr[0]);
2026         } else {
2027                 sd = v4l2_i2c_new_probed_subdev(&hdw->i2c_adap,
2028                                                 fname, fname,
2029                                                 i2caddr);
2030         }
2031
2032         if (!sd) {
2033                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2034                            "Module ID %u (%s) for device %s failed to load",
2035                            mid, fname, hdw->hdw_desc->description);
2036                 return -EIO;
2037         }
2038
2039         /* Tag this sub-device instance with the module ID we know about.
2040            In other places we'll use that tag to determine if the instance
2041            requires special handling. */
2042         sd->grp_id = mid;
2043
2044         /* If we have both old and new i2c layers enabled, make sure that
2045            old layer isn't also tracking this module.  This is a debugging
2046            aid, in normal situations there's no reason for both mechanisms
2047            to be enabled. */
2048         pvr2_i2c_untrack_subdev(hdw, sd);
2049         pvr2_trace(PVR2_TRACE_INIT, "Attached sub-driver %s", fname);
2050
2051
2052         /* client-specific setup... */
2053         switch (mid) {
2054         case PVR2_CLIENT_ID_CX25840:
2055                 hdw->decoder_client_id = mid;
2056                 {
2057                         /*
2058                           Mike Isely <isely@pobox.com> 19-Nov-2006 - This
2059                           bit of nuttiness for cx25840 causes that module
2060                           to correctly set up its video scaling.  This is
2061                           really a problem in the cx25840 module itself,
2062                           but we work around it here.  The problem has not
2063                           been seen in ivtv because there VBI is supported
2064                           and set up.  We don't do VBI here (at least not
2065                           yet) and thus we never attempted to even set it
2066                           up.
2067                         */
2068                         struct v4l2_format fmt;
2069                         memset(&fmt, 0, sizeof(fmt));
2070                         fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2071                         v4l2_device_call_all(&hdw->v4l2_dev, mid,
2072                                              video, s_fmt, &fmt);
2073                 }
2074                 break;
2075         case PVR2_CLIENT_ID_SAA7115:
2076                 hdw->decoder_client_id = mid;
2077                 break;
2078         default: break;
2079         }
2080
2081         return 0;
2082 }
2083
2084
2085 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2086 {
2087         unsigned int idx;
2088         const struct pvr2_string_table *cm;
2089         const struct pvr2_device_client_table *ct;
2090         int okFl = !0;
2091
2092         cm = &hdw->hdw_desc->client_modules;
2093         for (idx = 0; idx < cm->cnt; idx++) {
2094                 request_module(cm->lst[idx]);
2095         }
2096
2097         ct = &hdw->hdw_desc->client_table;
2098         for (idx = 0; idx < ct->cnt; idx++) {
2099                 if (!pvr2_hdw_load_subdev(hdw, &ct->lst[idx])) okFl = 0;
2100         }
2101         if (!okFl) pvr2_hdw_render_useless(hdw);
2102 }
2103
2104
2105 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2106 {
2107         int ret;
2108         unsigned int idx;
2109         struct pvr2_ctrl *cptr;
2110         int reloadFl = 0;
2111         if (hdw->hdw_desc->fx2_firmware.cnt) {
2112                 if (!reloadFl) {
2113                         reloadFl =
2114                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2115                                  == 0);
2116                         if (reloadFl) {
2117                                 pvr2_trace(PVR2_TRACE_INIT,
2118                                            "USB endpoint config looks strange"
2119                                            "; possibly firmware needs to be"
2120                                            " loaded");
2121                         }
2122                 }
2123                 if (!reloadFl) {
2124                         reloadFl = !pvr2_hdw_check_firmware(hdw);
2125                         if (reloadFl) {
2126                                 pvr2_trace(PVR2_TRACE_INIT,
2127                                            "Check for FX2 firmware failed"
2128                                            "; possibly firmware needs to be"
2129                                            " loaded");
2130                         }
2131                 }
2132                 if (reloadFl) {
2133                         if (pvr2_upload_firmware1(hdw) != 0) {
2134                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2135                                            "Failure uploading firmware1");
2136                         }
2137                         return;
2138                 }
2139         }
2140         hdw->fw1_state = FW1_STATE_OK;
2141
2142         if (!pvr2_hdw_dev_ok(hdw)) return;
2143
2144         if (!hdw->hdw_desc->flag_no_powerup) {
2145                 pvr2_hdw_cmd_powerup(hdw);
2146                 if (!pvr2_hdw_dev_ok(hdw)) return;
2147         }
2148
2149         /* Take the IR chip out of reset, if appropriate */
2150         if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
2151                 pvr2_issue_simple_cmd(hdw,
2152                                       FX2CMD_HCW_ZILOG_RESET |
2153                                       (1 << 8) |
2154                                       ((0) << 16));
2155         }
2156
2157         // This step MUST happen after the earlier powerup step.
2158         pvr2_i2c_track_init(hdw);
2159         pvr2_i2c_core_init(hdw);
2160         if (!pvr2_hdw_dev_ok(hdw)) return;
2161
2162         pvr2_hdw_load_modules(hdw);
2163         if (!pvr2_hdw_dev_ok(hdw)) return;
2164
2165         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2166                 cptr = hdw->controls + idx;
2167                 if (cptr->info->skip_init) continue;
2168                 if (!cptr->info->set_value) continue;
2169                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2170         }
2171
2172         /* Set up special default values for the television and radio
2173            frequencies here.  It's not really important what these defaults
2174            are, but I set them to something usable in the Chicago area just
2175            to make driver testing a little easier. */
2176
2177         hdw->freqValTelevision = default_tv_freq;
2178         hdw->freqValRadio = default_radio_freq;
2179
2180         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2181         // thread-safe against the normal pvr2_send_request() mechanism.
2182         // (We should make it thread safe).
2183
2184         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2185                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2186                 if (!pvr2_hdw_dev_ok(hdw)) return;
2187                 if (ret < 0) {
2188                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2189                                    "Unable to determine location of eeprom,"
2190                                    " skipping");
2191                 } else {
2192                         hdw->eeprom_addr = ret;
2193                         pvr2_eeprom_analyze(hdw);
2194                         if (!pvr2_hdw_dev_ok(hdw)) return;
2195                 }
2196         } else {
2197                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2198                 hdw->tuner_updated = !0;
2199                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2200         }
2201
2202         if (hdw->serial_number) {
2203                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2204                                 "sn-%lu", hdw->serial_number);
2205         } else if (hdw->unit_number >= 0) {
2206                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2207                                 "unit-%c",
2208                                 hdw->unit_number + 'a');
2209         } else {
2210                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2211                                 "unit-??");
2212         }
2213         hdw->identifier[idx] = 0;
2214
2215         pvr2_hdw_setup_std(hdw);
2216
2217         if (!get_default_tuner_type(hdw)) {
2218                 pvr2_trace(PVR2_TRACE_INIT,
2219                            "pvr2_hdw_setup: Tuner type overridden to %d",
2220                            hdw->tuner_type);
2221         }
2222
2223         pvr2_i2c_core_check_stale(hdw);
2224         hdw->tuner_updated = 0;
2225
2226         if (!pvr2_hdw_dev_ok(hdw)) return;
2227
2228         if (hdw->hdw_desc->signal_routing_scheme ==
2229             PVR2_ROUTING_SCHEME_GOTVIEW) {
2230                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2231                    hardware. */
2232                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2233         }
2234
2235         pvr2_hdw_commit_setup(hdw);
2236
2237         hdw->vid_stream = pvr2_stream_create();
2238         if (!pvr2_hdw_dev_ok(hdw)) return;
2239         pvr2_trace(PVR2_TRACE_INIT,
2240                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2241         if (hdw->vid_stream) {
2242                 idx = get_default_error_tolerance(hdw);
2243                 if (idx) {
2244                         pvr2_trace(PVR2_TRACE_INIT,
2245                                    "pvr2_hdw_setup: video stream %p"
2246                                    " setting tolerance %u",
2247                                    hdw->vid_stream,idx);
2248                 }
2249                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2250                                   PVR2_VID_ENDPOINT,idx);
2251         }
2252
2253         if (!pvr2_hdw_dev_ok(hdw)) return;
2254
2255         hdw->flag_init_ok = !0;
2256
2257         pvr2_hdw_state_sched(hdw);
2258 }
2259
2260
2261 /* Set up the structure and attempt to put the device into a usable state.
2262    This can be a time-consuming operation, which is why it is not done
2263    internally as part of the create() step. */
2264 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2265 {
2266         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2267         do {
2268                 pvr2_hdw_setup_low(hdw);
2269                 pvr2_trace(PVR2_TRACE_INIT,
2270                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2271                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2272                 if (pvr2_hdw_dev_ok(hdw)) {
2273                         if (hdw->flag_init_ok) {
2274                                 pvr2_trace(
2275                                         PVR2_TRACE_INFO,
2276                                         "Device initialization"
2277                                         " completed successfully.");
2278                                 break;
2279                         }
2280                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2281                                 pvr2_trace(
2282                                         PVR2_TRACE_INFO,
2283                                         "Device microcontroller firmware"
2284                                         " (re)loaded; it should now reset"
2285                                         " and reconnect.");
2286                                 break;
2287                         }
2288                         pvr2_trace(
2289                                 PVR2_TRACE_ERROR_LEGS,
2290                                 "Device initialization was not successful.");
2291                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2292                                 pvr2_trace(
2293                                         PVR2_TRACE_ERROR_LEGS,
2294                                         "Giving up since device"
2295                                         " microcontroller firmware"
2296                                         " appears to be missing.");
2297                                 break;
2298                         }
2299                 }
2300                 if (procreload) {
2301                         pvr2_trace(
2302                                 PVR2_TRACE_ERROR_LEGS,
2303                                 "Attempting pvrusb2 recovery by reloading"
2304                                 " primary firmware.");
2305                         pvr2_trace(
2306                                 PVR2_TRACE_ERROR_LEGS,
2307                                 "If this works, device should disconnect"
2308                                 " and reconnect in a sane state.");
2309                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2310                         pvr2_upload_firmware1(hdw);
2311                 } else {
2312                         pvr2_trace(
2313                                 PVR2_TRACE_ERROR_LEGS,
2314                                 "***WARNING*** pvrusb2 device hardware"
2315                                 " appears to be jammed"
2316                                 " and I can't clear it.");
2317                         pvr2_trace(
2318                                 PVR2_TRACE_ERROR_LEGS,
2319                                 "You might need to power cycle"
2320                                 " the pvrusb2 device"
2321                                 " in order to recover.");
2322                 }
2323         } while (0);
2324         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2325 }
2326
2327
2328 /* Perform second stage initialization.  Set callback pointer first so that
2329    we can avoid a possible initialization race (if the kernel thread runs
2330    before the callback has been set). */
2331 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2332                         void (*callback_func)(void *),
2333                         void *callback_data)
2334 {
2335         LOCK_TAKE(hdw->big_lock); do {
2336                 if (hdw->flag_disconnected) {
2337                         /* Handle a race here: If we're already
2338                            disconnected by this point, then give up.  If we
2339                            get past this then we'll remain connected for
2340                            the duration of initialization since the entire
2341                            initialization sequence is now protected by the
2342                            big_lock. */
2343                         break;
2344                 }
2345                 hdw->state_data = callback_data;
2346                 hdw->state_func = callback_func;
2347                 pvr2_hdw_setup(hdw);
2348         } while (0); LOCK_GIVE(hdw->big_lock);
2349         return hdw->flag_init_ok;
2350 }
2351
2352
2353 /* Create, set up, and return a structure for interacting with the
2354    underlying hardware.  */
2355 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2356                                  const struct usb_device_id *devid)
2357 {
2358         unsigned int idx,cnt1,cnt2,m;
2359         struct pvr2_hdw *hdw = NULL;
2360         int valid_std_mask;
2361         struct pvr2_ctrl *cptr;
2362         struct usb_device *usb_dev;
2363         const struct pvr2_device_desc *hdw_desc;
2364         __u8 ifnum;
2365         struct v4l2_queryctrl qctrl;
2366         struct pvr2_ctl_info *ciptr;
2367
2368         usb_dev = interface_to_usbdev(intf);
2369
2370         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2371
2372         if (hdw_desc == NULL) {
2373                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2374                            " No device description pointer,"
2375                            " unable to continue.");
2376                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2377                            " please contact Mike Isely <isely@pobox.com>"
2378                            " to get it included in the driver\n");
2379                 goto fail;
2380         }
2381
2382         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2383         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2384                    hdw,hdw_desc->description);
2385         if (!hdw) goto fail;
2386
2387         init_timer(&hdw->quiescent_timer);
2388         hdw->quiescent_timer.data = (unsigned long)hdw;
2389         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2390
2391         init_timer(&hdw->encoder_wait_timer);
2392         hdw->encoder_wait_timer.data = (unsigned long)hdw;
2393         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2394
2395         init_timer(&hdw->encoder_run_timer);
2396         hdw->encoder_run_timer.data = (unsigned long)hdw;
2397         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2398
2399         hdw->master_state = PVR2_STATE_DEAD;
2400
2401         init_waitqueue_head(&hdw->state_wait_data);
2402
2403         hdw->tuner_signal_stale = !0;
2404         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2405
2406         /* Calculate which inputs are OK */
2407         m = 0;
2408         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2409         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2410                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2411         }
2412         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2413         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2414         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2415         hdw->input_avail_mask = m;
2416         hdw->input_allowed_mask = hdw->input_avail_mask;
2417
2418         /* If not a hybrid device, pathway_state never changes.  So
2419            initialize it here to what it should forever be. */
2420         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2421                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2422         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2423                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2424         }
2425
2426         hdw->control_cnt = CTRLDEF_COUNT;
2427         hdw->control_cnt += MPEGDEF_COUNT;
2428         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2429                                 GFP_KERNEL);
2430         if (!hdw->controls) goto fail;
2431         hdw->hdw_desc = hdw_desc;
2432         for (idx = 0; idx < hdw->control_cnt; idx++) {
2433                 cptr = hdw->controls + idx;
2434                 cptr->hdw = hdw;
2435         }
2436         for (idx = 0; idx < 32; idx++) {
2437                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2438         }
2439         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2440                 cptr = hdw->controls + idx;
2441                 cptr->info = control_defs+idx;
2442         }
2443
2444         /* Ensure that default input choice is a valid one. */
2445         m = hdw->input_avail_mask;
2446         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2447                 if (!((1 << idx) & m)) continue;
2448                 hdw->input_val = idx;
2449                 break;
2450         }
2451
2452         /* Define and configure additional controls from cx2341x module. */
2453         hdw->mpeg_ctrl_info = kzalloc(
2454                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2455         if (!hdw->mpeg_ctrl_info) goto fail;
2456         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2457                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2458                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2459                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2460                 ciptr->name = mpeg_ids[idx].strid;
2461                 ciptr->v4l_id = mpeg_ids[idx].id;
2462                 ciptr->skip_init = !0;
2463                 ciptr->get_value = ctrl_cx2341x_get;
2464                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2465                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2466                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2467                 qctrl.id = ciptr->v4l_id;
2468                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2469                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2470                         ciptr->set_value = ctrl_cx2341x_set;
2471                 }
2472                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2473                         PVR2_CTLD_INFO_DESC_SIZE);
2474                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2475                 ciptr->default_value = qctrl.default_value;
2476                 switch (qctrl.type) {
2477                 default:
2478                 case V4L2_CTRL_TYPE_INTEGER:
2479                         ciptr->type = pvr2_ctl_int;
2480                         ciptr->def.type_int.min_value = qctrl.minimum;
2481                         ciptr->def.type_int.max_value = qctrl.maximum;
2482                         break;
2483                 case V4L2_CTRL_TYPE_BOOLEAN:
2484                         ciptr->type = pvr2_ctl_bool;
2485                         break;
2486                 case V4L2_CTRL_TYPE_MENU:
2487                         ciptr->type = pvr2_ctl_enum;
2488                         ciptr->def.type_enum.value_names =
2489                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2490                                                                 ciptr->v4l_id);
2491                         for (cnt1 = 0;
2492                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2493                              cnt1++) { }
2494                         ciptr->def.type_enum.count = cnt1;
2495                         break;
2496                 }
2497                 cptr->info = ciptr;
2498         }
2499
2500         // Initialize video standard enum dynamic control
2501         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2502         if (cptr) {
2503                 memcpy(&hdw->std_info_enum,cptr->info,
2504                        sizeof(hdw->std_info_enum));
2505                 cptr->info = &hdw->std_info_enum;
2506
2507         }
2508         // Initialize control data regarding video standard masks
2509         valid_std_mask = pvr2_std_get_usable();
2510         for (idx = 0; idx < 32; idx++) {
2511                 if (!(valid_std_mask & (1 << idx))) continue;
2512                 cnt1 = pvr2_std_id_to_str(
2513                         hdw->std_mask_names[idx],
2514                         sizeof(hdw->std_mask_names[idx])-1,
2515                         1 << idx);
2516                 hdw->std_mask_names[idx][cnt1] = 0;
2517         }
2518         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2519         if (cptr) {
2520                 memcpy(&hdw->std_info_avail,cptr->info,
2521                        sizeof(hdw->std_info_avail));
2522                 cptr->info = &hdw->std_info_avail;
2523                 hdw->std_info_avail.def.type_bitmask.bit_names =
2524                         hdw->std_mask_ptrs;
2525                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2526                         valid_std_mask;
2527         }
2528         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2529         if (cptr) {
2530                 memcpy(&hdw->std_info_cur,cptr->info,
2531                        sizeof(hdw->std_info_cur));
2532                 cptr->info = &hdw->std_info_cur;
2533                 hdw->std_info_cur.def.type_bitmask.bit_names =
2534                         hdw->std_mask_ptrs;
2535                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2536                         valid_std_mask;
2537         }
2538
2539         hdw->cropcap_stale = !0;
2540         hdw->eeprom_addr = -1;
2541         hdw->unit_number = -1;
2542         hdw->v4l_minor_number_video = -1;
2543         hdw->v4l_minor_number_vbi = -1;
2544         hdw->v4l_minor_number_radio = -1;
2545         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2546         if (!hdw->ctl_write_buffer) goto fail;
2547         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2548         if (!hdw->ctl_read_buffer) goto fail;
2549         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2550         if (!hdw->ctl_write_urb) goto fail;
2551         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2552         if (!hdw->ctl_read_urb) goto fail;
2553
2554         if (v4l2_device_register(&usb_dev->dev, &hdw->v4l2_dev) != 0) {
2555                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2556                            "Error registering with v4l core, giving up");
2557                 goto fail;
2558         }
2559         mutex_lock(&pvr2_unit_mtx); do {
2560                 for (idx = 0; idx < PVR_NUM; idx++) {
2561                         if (unit_pointers[idx]) continue;
2562                         hdw->unit_number = idx;
2563                         unit_pointers[idx] = hdw;
2564                         break;
2565                 }
2566         } while (0); mutex_unlock(&pvr2_unit_mtx);
2567
2568         cnt1 = 0;
2569         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2570         cnt1 += cnt2;
2571         if (hdw->unit_number >= 0) {
2572                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2573                                  ('a' + hdw->unit_number));
2574                 cnt1 += cnt2;
2575         }
2576         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2577         hdw->name[cnt1] = 0;
2578
2579         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2580         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2581         INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2582
2583         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2584                    hdw->unit_number,hdw->name);
2585
2586         hdw->tuner_type = -1;
2587         hdw->flag_ok = !0;
2588
2589         hdw->usb_intf = intf;
2590         hdw->usb_dev = usb_dev;
2591
2592         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2593
2594         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2595         usb_set_interface(hdw->usb_dev,ifnum,0);
2596
2597         mutex_init(&hdw->ctl_lock_mutex);
2598         mutex_init(&hdw->big_lock_mutex);
2599
2600         return hdw;
2601  fail:
2602         if (hdw) {
2603                 del_timer_sync(&hdw->quiescent_timer);
2604                 del_timer_sync(&hdw->encoder_run_timer);
2605                 del_timer_sync(&hdw->encoder_wait_timer);
2606                 if (hdw->workqueue) {
2607                         flush_workqueue(hdw->workqueue);
2608                         destroy_workqueue(hdw->workqueue);
2609                         hdw->workqueue = NULL;
2610                 }
2611                 usb_free_urb(hdw->ctl_read_urb);
2612                 usb_free_urb(hdw->ctl_write_urb);
2613                 kfree(hdw->ctl_read_buffer);
2614                 kfree(hdw->ctl_write_buffer);
2615                 kfree(hdw->controls);
2616                 kfree(hdw->mpeg_ctrl_info);
2617                 kfree(hdw->std_defs);
2618                 kfree(hdw->std_enum_names);
2619                 kfree(hdw);
2620         }
2621         return NULL;
2622 }
2623
2624
2625 /* Remove _all_ associations between this driver and the underlying USB
2626    layer. */
2627 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2628 {
2629         if (hdw->flag_disconnected) return;
2630         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2631         if (hdw->ctl_read_urb) {
2632                 usb_kill_urb(hdw->ctl_read_urb);
2633                 usb_free_urb(hdw->ctl_read_urb);
2634                 hdw->ctl_read_urb = NULL;
2635         }
2636         if (hdw->ctl_write_urb) {
2637                 usb_kill_urb(hdw->ctl_write_urb);
2638                 usb_free_urb(hdw->ctl_write_urb);
2639                 hdw->ctl_write_urb = NULL;
2640         }
2641         if (hdw->ctl_read_buffer) {
2642                 kfree(hdw->ctl_read_buffer);
2643                 hdw->ctl_read_buffer = NULL;
2644         }
2645         if (hdw->ctl_write_buffer) {
2646                 kfree(hdw->ctl_write_buffer);
2647                 hdw->ctl_write_buffer = NULL;
2648         }
2649         hdw->flag_disconnected = !0;
2650         /* If we don't do this, then there will be a dangling struct device
2651            reference to our disappearing device persisting inside the V4L
2652            core... */
2653         if (hdw->v4l2_dev.dev) {
2654                 dev_set_drvdata(hdw->v4l2_dev.dev, NULL);
2655                 hdw->v4l2_dev.dev = NULL;
2656         }
2657         hdw->usb_dev = NULL;
2658         hdw->usb_intf = NULL;
2659         pvr2_hdw_render_useless(hdw);
2660 }
2661
2662
2663 /* Destroy hardware interaction structure */
2664 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2665 {
2666         if (!hdw) return;
2667         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2668         if (hdw->workqueue) {
2669                 flush_workqueue(hdw->workqueue);
2670                 destroy_workqueue(hdw->workqueue);
2671                 hdw->workqueue = NULL;
2672         }
2673         del_timer_sync(&hdw->quiescent_timer);
2674         del_timer_sync(&hdw->encoder_run_timer);
2675         del_timer_sync(&hdw->encoder_wait_timer);
2676         if (hdw->fw_buffer) {
2677                 kfree(hdw->fw_buffer);
2678                 hdw->fw_buffer = NULL;
2679         }
2680         if (hdw->vid_stream) {
2681                 pvr2_stream_destroy(hdw->vid_stream);
2682                 hdw->vid_stream = NULL;
2683         }
2684         if (hdw->decoder_ctrl) {
2685                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2686         }
2687         pvr2_i2c_core_done(hdw);
2688         pvr2_i2c_track_done(hdw);
2689         v4l2_device_unregister(&hdw->v4l2_dev);
2690         pvr2_hdw_remove_usb_stuff(hdw);
2691         mutex_lock(&pvr2_unit_mtx); do {
2692                 if ((hdw->unit_number >= 0) &&
2693                     (hdw->unit_number < PVR_NUM) &&
2694                     (unit_pointers[hdw->unit_number] == hdw)) {
2695                         unit_pointers[hdw->unit_number] = NULL;
2696                 }
2697         } while (0); mutex_unlock(&pvr2_unit_mtx);
2698         kfree(hdw->controls);
2699         kfree(hdw->mpeg_ctrl_info);
2700         kfree(hdw->std_defs);
2701         kfree(hdw->std_enum_names);
2702         kfree(hdw);
2703 }
2704
2705
2706 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2707 {
2708         return (hdw && hdw->flag_ok);
2709 }
2710
2711
2712 /* Called when hardware has been unplugged */
2713 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2714 {
2715         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2716         LOCK_TAKE(hdw->big_lock);
2717         LOCK_TAKE(hdw->ctl_lock);
2718         pvr2_hdw_remove_usb_stuff(hdw);
2719         LOCK_GIVE(hdw->ctl_lock);
2720         LOCK_GIVE(hdw->big_lock);
2721 }
2722
2723
2724 // Attempt to autoselect an appropriate value for std_enum_cur given
2725 // whatever is currently in std_mask_cur
2726 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2727 {
2728         unsigned int idx;
2729         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2730                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2731                         hdw->std_enum_cur = idx;
2732                         return;
2733                 }
2734         }
2735         hdw->std_enum_cur = 0;
2736 }
2737
2738
2739 // Calculate correct set of enumerated standards based on currently known
2740 // set of available standards bits.
2741 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2742 {
2743         struct v4l2_standard *newstd;
2744         unsigned int std_cnt;
2745         unsigned int idx;
2746
2747         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2748
2749         if (hdw->std_defs) {
2750                 kfree(hdw->std_defs);
2751                 hdw->std_defs = NULL;
2752         }
2753         hdw->std_enum_cnt = 0;
2754         if (hdw->std_enum_names) {
2755                 kfree(hdw->std_enum_names);
2756                 hdw->std_enum_names = NULL;
2757         }
2758
2759         if (!std_cnt) {
2760                 pvr2_trace(
2761                         PVR2_TRACE_ERROR_LEGS,
2762                         "WARNING: Failed to identify any viable standards");
2763         }
2764         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2765         hdw->std_enum_names[0] = "none";
2766         for (idx = 0; idx < std_cnt; idx++) {
2767                 hdw->std_enum_names[idx+1] =
2768                         newstd[idx].name;
2769         }
2770         // Set up the dynamic control for this standard
2771         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2772         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2773         hdw->std_defs = newstd;
2774         hdw->std_enum_cnt = std_cnt+1;
2775         hdw->std_enum_cur = 0;
2776         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2777 }
2778
2779
2780 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2781                                struct v4l2_standard *std,
2782                                unsigned int idx)
2783 {
2784         int ret = -EINVAL;
2785         if (!idx) return ret;
2786         LOCK_TAKE(hdw->big_lock); do {
2787                 if (idx >= hdw->std_enum_cnt) break;
2788                 idx--;
2789                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2790                 ret = 0;
2791         } while (0); LOCK_GIVE(hdw->big_lock);
2792         return ret;
2793 }
2794
2795
2796 /* Get the number of defined controls */
2797 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2798 {
2799         return hdw->control_cnt;
2800 }
2801
2802
2803 /* Retrieve a control handle given its index (0..count-1) */
2804 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2805                                              unsigned int idx)
2806 {
2807         if (idx >= hdw->control_cnt) return NULL;
2808         return hdw->controls + idx;
2809 }
2810
2811
2812 /* Retrieve a control handle given its index (0..count-1) */
2813 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2814                                           unsigned int ctl_id)
2815 {
2816         struct pvr2_ctrl *cptr;
2817         unsigned int idx;
2818         int i;
2819
2820         /* This could be made a lot more efficient, but for now... */
2821         for (idx = 0; idx < hdw->control_cnt; idx++) {
2822                 cptr = hdw->controls + idx;
2823                 i = cptr->info->internal_id;
2824                 if (i && (i == ctl_id)) return cptr;
2825         }
2826         return NULL;
2827 }
2828
2829
2830 /* Given a V4L ID, retrieve the control structure associated with it. */
2831 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2832 {
2833         struct pvr2_ctrl *cptr;
2834         unsigned int idx;
2835         int i;
2836
2837         /* This could be made a lot more efficient, but for now... */
2838         for (idx = 0; idx < hdw->control_cnt; idx++) {
2839                 cptr = hdw->controls + idx;
2840                 i = cptr->info->v4l_id;
2841                 if (i && (i == ctl_id)) return cptr;
2842         }
2843         return NULL;
2844 }
2845
2846
2847 /* Given a V4L ID for its immediate predecessor, retrieve the control
2848    structure associated with it. */
2849 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2850                                             unsigned int ctl_id)
2851 {
2852         struct pvr2_ctrl *cptr,*cp2;
2853         unsigned int idx;
2854         int i;
2855
2856         /* This could be made a lot more efficient, but for now... */
2857         cp2 = NULL;
2858         for (idx = 0; idx < hdw->control_cnt; idx++) {
2859                 cptr = hdw->controls + idx;
2860                 i = cptr->info->v4l_id;
2861                 if (!i) continue;
2862                 if (i <= ctl_id) continue;
2863                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2864                 cp2 = cptr;
2865         }
2866         return cp2;
2867         return NULL;
2868 }
2869
2870
2871 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2872 {
2873         switch (tp) {
2874         case pvr2_ctl_int: return "integer";
2875         case pvr2_ctl_enum: return "enum";
2876         case pvr2_ctl_bool: return "boolean";
2877         case pvr2_ctl_bitmask: return "bitmask";
2878         }
2879         return "";
2880 }
2881
2882
2883 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2884                                     const char *name, int val)
2885 {
2886         struct v4l2_control ctrl;
2887         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2888         memset(&ctrl, 0, sizeof(ctrl));
2889         ctrl.id = id;
2890         ctrl.value = val;
2891         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2892 }
2893
2894 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2895         if ((hdw)->lab##_dirty) { \
2896                 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2897         }
2898
2899 /* Execute whatever commands are required to update the state of all the
2900    sub-devices so that they match our current control values. */
2901 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2902 {
2903         if (hdw->input_dirty || hdw->std_dirty) {
2904                 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_standard");
2905                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2906                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2907                                              tuner, s_radio);
2908                 } else {
2909                         v4l2_std_id vs;
2910                         vs = hdw->std_mask_cur;
2911                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2912                                              tuner, s_std, vs);
2913                 }
2914                 hdw->tuner_signal_stale = !0;
2915                 hdw->cropcap_stale = !0;
2916         }
2917
2918         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2919         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2920         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2921         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2922         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2923         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2924         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2925         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2926         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2927
2928         if (hdw->input_dirty || hdw->audiomode_dirty) {
2929                 struct v4l2_tuner vt;
2930                 memset(&vt, 0, sizeof(vt));
2931                 vt.audmode = hdw->audiomode_val;
2932                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2933         }
2934
2935         if (hdw->freqDirty) {
2936                 unsigned long fv;
2937                 struct v4l2_frequency freq;
2938                 fv = pvr2_hdw_get_cur_freq(hdw);
2939                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2940                 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2941                 memset(&freq, 0, sizeof(freq));
2942                 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2943                         /* ((fv * 1000) / 62500) */
2944                         freq.frequency = (fv * 2) / 125;
2945                 } else {
2946                         freq.frequency = fv / 62500;
2947                 }
2948                 /* tuner-core currently doesn't seem to care about this, but
2949                    let's set it anyway for completeness. */
2950                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2951                         freq.type = V4L2_TUNER_RADIO;
2952                 } else {
2953                         freq.type = V4L2_TUNER_ANALOG_TV;
2954                 }
2955                 freq.tuner = 0;
2956                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2957                                      s_frequency, &freq);
2958         }
2959
2960         if (hdw->res_hor_dirty || hdw->res_ver_dirty) {
2961                 struct v4l2_format fmt;
2962                 memset(&fmt, 0, sizeof(fmt));
2963                 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2964                 fmt.fmt.pix.width = hdw->res_hor_val;
2965                 fmt.fmt.pix.height = hdw->res_ver_val;
2966                 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_size(%dx%d)",
2967                            fmt.fmt.pix.width, fmt.fmt.pix.height);
2968                 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
2969         }
2970
2971         /* Unable to set crop parameters; there is apparently no equivalent
2972            for VIDIOC_S_CROP */
2973
2974         /* ????? Cover special cases for specific sub-devices. */
2975
2976         if (hdw->tuner_signal_stale && hdw->cropcap_stale) {
2977                 pvr2_hdw_status_poll(hdw);
2978         }
2979 }
2980
2981
2982 /* Figure out if we need to commit control changes.  If so, mark internal
2983    state flags to indicate this fact and return true.  Otherwise do nothing
2984    else and return false. */
2985 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2986 {
2987         unsigned int idx;
2988         struct pvr2_ctrl *cptr;
2989         int value;
2990         int commit_flag = 0;
2991         char buf[100];
2992         unsigned int bcnt,ccnt;
2993
2994         for (idx = 0; idx < hdw->control_cnt; idx++) {
2995                 cptr = hdw->controls + idx;
2996                 if (!cptr->info->is_dirty) continue;
2997                 if (!cptr->info->is_dirty(cptr)) continue;
2998                 commit_flag = !0;
2999
3000                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
3001                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3002                                  cptr->info->name);
3003                 value = 0;
3004                 cptr->info->get_value(cptr,&value);
3005                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3006                                                 buf+bcnt,
3007                                                 sizeof(buf)-bcnt,&ccnt);
3008                 bcnt += ccnt;
3009                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3010                                   get_ctrl_typename(cptr->info->type));
3011                 pvr2_trace(PVR2_TRACE_CTL,
3012                            "/*--TRACE_COMMIT--*/ %.*s",
3013                            bcnt,buf);
3014         }
3015
3016         if (!commit_flag) {
3017                 /* Nothing has changed */
3018                 return 0;
3019         }
3020
3021         hdw->state_pipeline_config = 0;
3022         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3023         pvr2_hdw_state_sched(hdw);
3024
3025         return !0;
3026 }
3027
3028
3029 /* Perform all operations needed to commit all control changes.  This must
3030    be performed in synchronization with the pipeline state and is thus
3031    expected to be called as part of the driver's worker thread.  Return
3032    true if commit successful, otherwise return false to indicate that
3033    commit isn't possible at this time. */
3034 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3035 {
3036         unsigned int idx;
3037         struct pvr2_ctrl *cptr;
3038         int disruptive_change;
3039
3040         /* Handle some required side effects when the video standard is
3041            changed.... */
3042         if (hdw->std_dirty) {
3043                 int nvres;
3044                 int gop_size;
3045                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3046                         nvres = 480;
3047                         gop_size = 15;
3048                 } else {
3049                         nvres = 576;
3050                         gop_size = 12;
3051                 }
3052                 /* Rewrite the vertical resolution to be appropriate to the
3053                    video standard that has been selected. */
3054                 if (nvres != hdw->res_ver_val) {
3055                         hdw->res_ver_val = nvres;
3056                         hdw->res_ver_dirty = !0;
3057                 }
3058                 /* Rewrite the GOP size to be appropriate to the video
3059                    standard that has been selected. */
3060                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3061                         struct v4l2_ext_controls cs;
3062                         struct v4l2_ext_control c1;
3063                         memset(&cs, 0, sizeof(cs));
3064                         memset(&c1, 0, sizeof(c1));
3065                         cs.controls = &c1;
3066                         cs.count = 1;
3067                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3068                         c1.value = gop_size;
3069                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3070                                           VIDIOC_S_EXT_CTRLS);
3071                 }
3072         }
3073
3074         if (hdw->input_dirty && hdw->state_pathway_ok &&
3075             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3076               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3077              hdw->pathway_state)) {
3078                 /* Change of mode being asked for... */
3079                 hdw->state_pathway_ok = 0;
3080                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3081         }
3082         if (!hdw->state_pathway_ok) {
3083                 /* Can't commit anything until pathway is ok. */
3084                 return 0;
3085         }
3086         /* The broadcast decoder can only scale down, so if
3087          * res_*_dirty && crop window < output format ==> enlarge crop.
3088          *
3089          * The mpeg encoder receives fields of res_hor_val dots and
3090          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3091          */
3092         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3093                 hdw->cropw_val = hdw->res_hor_val;
3094                 hdw->cropw_dirty = !0;
3095         } else if (hdw->cropw_dirty) {
3096                 hdw->res_hor_dirty = !0;           /* must rescale */
3097                 hdw->res_hor_val = min(720, hdw->cropw_val);
3098         }
3099         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3100                 hdw->croph_val = hdw->res_ver_val;
3101                 hdw->croph_dirty = !0;
3102         } else if (hdw->croph_dirty) {
3103                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3104                 hdw->res_ver_dirty = !0;
3105                 hdw->res_ver_val = min(nvres, hdw->croph_val);
3106         }
3107
3108         /* If any of the below has changed, then we can't do the update
3109            while the pipeline is running.  Pipeline must be paused first
3110            and decoder -> encoder connection be made quiescent before we
3111            can proceed. */
3112         disruptive_change =
3113                 (hdw->std_dirty ||
3114                  hdw->enc_unsafe_stale ||
3115                  hdw->srate_dirty ||
3116                  hdw->res_ver_dirty ||
3117                  hdw->res_hor_dirty ||
3118                  hdw->cropw_dirty ||
3119                  hdw->croph_dirty ||
3120                  hdw->input_dirty ||
3121                  (hdw->active_stream_type != hdw->desired_stream_type));
3122         if (disruptive_change && !hdw->state_pipeline_idle) {
3123                 /* Pipeline is not idle; we can't proceed.  Arrange to
3124                    cause pipeline to stop so that we can try this again
3125                    later.... */
3126                 hdw->state_pipeline_pause = !0;
3127                 return 0;
3128         }
3129
3130         if (hdw->srate_dirty) {
3131                 /* Write new sample rate into control structure since
3132                  * the master copy is stale.  We must track srate
3133                  * separate from the mpeg control structure because
3134                  * other logic also uses this value. */
3135                 struct v4l2_ext_controls cs;
3136                 struct v4l2_ext_control c1;
3137                 memset(&cs,0,sizeof(cs));
3138                 memset(&c1,0,sizeof(c1));
3139                 cs.controls = &c1;
3140                 cs.count = 1;
3141                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3142                 c1.value = hdw->srate_val;
3143                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3144         }
3145
3146         /* Scan i2c core at this point - before we clear all the dirty
3147            bits.  Various parts of the i2c core will notice dirty bits as
3148            appropriate and arrange to broadcast or directly send updates to
3149            the client drivers in order to keep everything in sync */
3150         pvr2_i2c_core_check_stale(hdw);
3151
3152         if (hdw->active_stream_type != hdw->desired_stream_type) {
3153                 /* Handle any side effects of stream config here */
3154                 hdw->active_stream_type = hdw->desired_stream_type;
3155         }
3156
3157         if (hdw->hdw_desc->signal_routing_scheme ==
3158             PVR2_ROUTING_SCHEME_GOTVIEW) {
3159                 u32 b;
3160                 /* Handle GOTVIEW audio switching */
3161                 pvr2_hdw_gpio_get_out(hdw,&b);
3162                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3163                         /* Set GPIO 11 */
3164                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3165                 } else {
3166                         /* Clear GPIO 11 */
3167                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3168                 }
3169         }
3170
3171         for (idx = 0; idx < hdw->control_cnt; idx++) {
3172                 cptr = hdw->controls + idx;
3173                 if (!cptr->info->clear_dirty) continue;
3174                 cptr->info->clear_dirty(cptr);
3175         }
3176
3177         /* Check and update state for all sub-devices. */
3178         pvr2_subdev_update(hdw);
3179
3180         /* Now execute i2c core update */
3181         pvr2_i2c_core_sync(hdw);
3182
3183         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3184             hdw->state_encoder_run) {
3185                 /* If encoder isn't running or it can't be touched, then
3186                    this will get worked out later when we start the
3187                    encoder. */
3188                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3189         }
3190
3191         hdw->state_pipeline_config = !0;
3192         /* Hardware state may have changed in a way to cause the cropping
3193            capabilities to have changed.  So mark it stale, which will
3194            cause a later re-fetch. */
3195         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3196         return !0;
3197 }
3198
3199
3200 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3201 {
3202         int fl;
3203         LOCK_TAKE(hdw->big_lock);
3204         fl = pvr2_hdw_commit_setup(hdw);
3205         LOCK_GIVE(hdw->big_lock);
3206         if (!fl) return 0;
3207         return pvr2_hdw_wait(hdw,0);
3208 }
3209
3210
3211 static void pvr2_hdw_worker_i2c(struct work_struct *work)
3212 {
3213         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
3214         LOCK_TAKE(hdw->big_lock); do {
3215                 pvr2_i2c_core_sync(hdw);
3216         } while (0); LOCK_GIVE(hdw->big_lock);
3217 }
3218
3219
3220 static void pvr2_hdw_worker_poll(struct work_struct *work)
3221 {
3222         int fl = 0;
3223         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3224         LOCK_TAKE(hdw->big_lock); do {
3225                 fl = pvr2_hdw_state_eval(hdw);
3226         } while (0); LOCK_GIVE(hdw->big_lock);
3227         if (fl && hdw->state_func) {
3228                 hdw->state_func(hdw->state_data);
3229         }
3230 }
3231
3232
3233 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3234 {
3235         return wait_event_interruptible(
3236                 hdw->state_wait_data,
3237                 (hdw->state_stale == 0) &&
3238                 (!state || (hdw->master_state != state)));
3239 }
3240
3241
3242 /* Return name for this driver instance */
3243 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3244 {
3245         return hdw->name;
3246 }
3247
3248
3249 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3250 {
3251         return hdw->hdw_desc->description;
3252 }
3253
3254
3255 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3256 {
3257         return hdw->hdw_desc->shortname;
3258 }
3259
3260
3261 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3262 {
3263         int result;
3264         LOCK_TAKE(hdw->ctl_lock); do {
3265                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3266                 result = pvr2_send_request(hdw,
3267                                            hdw->cmd_buffer,1,
3268                                            hdw->cmd_buffer,1);
3269                 if (result < 0) break;
3270                 result = (hdw->cmd_buffer[0] != 0);
3271         } while(0); LOCK_GIVE(hdw->ctl_lock);
3272         return result;
3273 }
3274
3275
3276 /* Execute poll of tuner status */
3277 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3278 {
3279         LOCK_TAKE(hdw->big_lock); do {
3280                 pvr2_hdw_status_poll(hdw);
3281         } while (0); LOCK_GIVE(hdw->big_lock);
3282 }
3283
3284
3285 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3286 {
3287         if (!hdw->cropcap_stale) {
3288                 return 0;
3289         }
3290         pvr2_hdw_status_poll(hdw);
3291         if (hdw->cropcap_stale) {
3292                 return -EIO;
3293         }
3294         return 0;
3295 }
3296
3297
3298 /* Return information about cropping capabilities */
3299 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3300 {
3301         int stat = 0;
3302         LOCK_TAKE(hdw->big_lock);
3303         stat = pvr2_hdw_check_cropcap(hdw);
3304         if (!stat) {
3305                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3306         }
3307         LOCK_GIVE(hdw->big_lock);
3308         return stat;
3309 }
3310
3311
3312 /* Return information about the tuner */
3313 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3314 {
3315         LOCK_TAKE(hdw->big_lock); do {
3316                 if (hdw->tuner_signal_stale) {
3317                         pvr2_hdw_status_poll(hdw);
3318                 }
3319                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3320         } while (0); LOCK_GIVE(hdw->big_lock);
3321         return 0;
3322 }
3323
3324
3325 /* Get handle to video output stream */
3326 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3327 {
3328         return hp->vid_stream;
3329 }
3330
3331
3332 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3333 {
3334         int nr = pvr2_hdw_get_unit_number(hdw);
3335         LOCK_TAKE(hdw->big_lock); do {
3336                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3337                 hdw->log_requested = !0;
3338                 pvr2_i2c_core_check_stale(hdw);
3339                 pvr2_i2c_core_sync(hdw);
3340                 hdw->log_requested = 0;
3341                 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3342                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3343                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3344                 pvr2_hdw_state_log_state(hdw);
3345                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3346         } while (0); LOCK_GIVE(hdw->big_lock);
3347 }
3348
3349
3350 /* Grab EEPROM contents, needed for direct method. */
3351 #define EEPROM_SIZE 8192
3352 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3353 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3354 {
3355         struct i2c_msg msg[2];
3356         u8 *eeprom;
3357         u8 iadd[2];
3358         u8 addr;
3359         u16 eepromSize;
3360         unsigned int offs;
3361         int ret;
3362         int mode16 = 0;
3363         unsigned pcnt,tcnt;
3364         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3365         if (!eeprom) {
3366                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3367                            "Failed to allocate memory"
3368                            " required to read eeprom");
3369                 return NULL;
3370         }
3371
3372         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3373                      hdw->eeprom_addr);
3374         addr = hdw->eeprom_addr;
3375         /* Seems that if the high bit is set, then the *real* eeprom
3376            address is shifted right now bit position (noticed this in
3377            newer PVR USB2 hardware) */
3378         if (addr & 0x80) addr >>= 1;
3379
3380         /* FX2 documentation states that a 16bit-addressed eeprom is
3381            expected if the I2C address is an odd number (yeah, this is
3382            strange but it's what they do) */
3383         mode16 = (addr & 1);
3384         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3385         trace_eeprom("Examining %d byte eeprom at location 0x%x"
3386                      " using %d bit addressing",eepromSize,addr,
3387                      mode16 ? 16 : 8);
3388
3389         msg[0].addr = addr;
3390         msg[0].flags = 0;
3391         msg[0].len = mode16 ? 2 : 1;
3392         msg[0].buf = iadd;
3393         msg[1].addr = addr;
3394         msg[1].flags = I2C_M_RD;
3395
3396         /* We have to do the actual eeprom data fetch ourselves, because
3397            (1) we're only fetching part of the eeprom, and (2) if we were
3398            getting the whole thing our I2C driver can't grab it in one
3399            pass - which is what tveeprom is otherwise going to attempt */
3400         memset(eeprom,0,EEPROM_SIZE);
3401         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3402                 pcnt = 16;
3403                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3404                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3405                 if (mode16) {
3406                         iadd[0] = offs >> 8;
3407                         iadd[1] = offs;
3408                 } else {
3409                         iadd[0] = offs;
3410                 }
3411                 msg[1].len = pcnt;
3412                 msg[1].buf = eeprom+tcnt;
3413                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3414                                         msg,ARRAY_SIZE(msg))) != 2) {
3415                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3416                                    "eeprom fetch set offs err=%d",ret);
3417                         kfree(eeprom);
3418                         return NULL;
3419                 }
3420         }
3421         return eeprom;
3422 }
3423
3424
3425 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3426                                 int prom_flag,
3427                                 int enable_flag)
3428 {
3429         int ret;
3430         u16 address;
3431         unsigned int pipe;
3432         LOCK_TAKE(hdw->big_lock); do {
3433                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3434
3435                 if (!enable_flag) {
3436                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3437                                    "Cleaning up after CPU firmware fetch");
3438                         kfree(hdw->fw_buffer);
3439                         hdw->fw_buffer = NULL;
3440                         hdw->fw_size = 0;
3441                         if (hdw->fw_cpu_flag) {
3442                                 /* Now release the CPU.  It will disconnect
3443                                    and reconnect later. */
3444                                 pvr2_hdw_cpureset_assert(hdw,0);
3445                         }
3446                         break;
3447                 }
3448
3449                 hdw->fw_cpu_flag = (prom_flag == 0);
3450                 if (hdw->fw_cpu_flag) {
3451                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3452                                    "Preparing to suck out CPU firmware");
3453                         hdw->fw_size = 0x2000;
3454                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3455                         if (!hdw->fw_buffer) {
3456                                 hdw->fw_size = 0;
3457                                 break;
3458                         }
3459
3460                         /* We have to hold the CPU during firmware upload. */
3461                         pvr2_hdw_cpureset_assert(hdw,1);
3462
3463                         /* download the firmware from address 0000-1fff in 2048
3464                            (=0x800) bytes chunk. */
3465
3466                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3467                                    "Grabbing CPU firmware");
3468                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3469                         for(address = 0; address < hdw->fw_size;
3470                             address += 0x800) {
3471                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3472                                                       0xa0,0xc0,
3473                                                       address,0,
3474                                                       hdw->fw_buffer+address,
3475                                                       0x800,HZ);
3476                                 if (ret < 0) break;
3477                         }
3478
3479                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3480                                    "Done grabbing CPU firmware");
3481                 } else {
3482                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3483                                    "Sucking down EEPROM contents");
3484                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3485                         if (!hdw->fw_buffer) {
3486                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3487                                            "EEPROM content suck failed.");
3488                                 break;
3489                         }
3490                         hdw->fw_size = EEPROM_SIZE;
3491                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3492                                    "Done sucking down EEPROM contents");
3493                 }
3494
3495         } while (0); LOCK_GIVE(hdw->big_lock);
3496 }
3497
3498
3499 /* Return true if we're in a mode for retrieval CPU firmware */
3500 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3501 {
3502         return hdw->fw_buffer != NULL;
3503 }
3504
3505
3506 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3507                        char *buf,unsigned int cnt)
3508 {
3509         int ret = -EINVAL;
3510         LOCK_TAKE(hdw->big_lock); do {
3511                 if (!buf) break;
3512                 if (!cnt) break;
3513
3514                 if (!hdw->fw_buffer) {
3515                         ret = -EIO;
3516                         break;
3517                 }
3518
3519                 if (offs >= hdw->fw_size) {
3520                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3521                                    "Read firmware data offs=%d EOF",
3522                                    offs);
3523                         ret = 0;
3524                         break;
3525                 }
3526
3527                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3528
3529                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3530
3531                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3532                            "Read firmware data offs=%d cnt=%d",
3533                            offs,cnt);
3534                 ret = cnt;
3535         } while (0); LOCK_GIVE(hdw->big_lock);
3536
3537         return ret;
3538 }
3539
3540
3541 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3542                                   enum pvr2_v4l_type index)
3543 {
3544         switch (index) {
3545         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3546         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3547         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3548         default: return -1;
3549         }
3550 }
3551
3552
3553 /* Store a v4l minor device number */
3554 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3555                                      enum pvr2_v4l_type index,int v)
3556 {
3557         switch (index) {
3558         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3559         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3560         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3561         default: break;
3562         }
3563 }
3564
3565
3566 static void pvr2_ctl_write_complete(struct urb *urb)
3567 {
3568         struct pvr2_hdw *hdw = urb->context;
3569         hdw->ctl_write_pend_flag = 0;
3570         if (hdw->ctl_read_pend_flag) return;
3571         complete(&hdw->ctl_done);
3572 }
3573
3574
3575 static void pvr2_ctl_read_complete(struct urb *urb)
3576 {
3577         struct pvr2_hdw *hdw = urb->context;
3578         hdw->ctl_read_pend_flag = 0;
3579         if (hdw->ctl_write_pend_flag) return;
3580         complete(&hdw->ctl_done);
3581 }
3582
3583
3584 static void pvr2_ctl_timeout(unsigned long data)
3585 {
3586         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3587         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3588                 hdw->ctl_timeout_flag = !0;
3589                 if (hdw->ctl_write_pend_flag)
3590                         usb_unlink_urb(hdw->ctl_write_urb);
3591                 if (hdw->ctl_read_pend_flag)
3592                         usb_unlink_urb(hdw->ctl_read_urb);
3593         }
3594 }
3595
3596
3597 /* Issue a command and get a response from the device.  This extended
3598    version includes a probe flag (which if set means that device errors
3599    should not be logged or treated as fatal) and a timeout in jiffies.
3600    This can be used to non-lethally probe the health of endpoint 1. */
3601 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3602                                 unsigned int timeout,int probe_fl,
3603                                 void *write_data,unsigned int write_len,
3604                                 void *read_data,unsigned int read_len)
3605 {
3606         unsigned int idx;
3607         int status = 0;
3608         struct timer_list timer;
3609         if (!hdw->ctl_lock_held) {
3610                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3611                            "Attempted to execute control transfer"
3612                            " without lock!!");
3613                 return -EDEADLK;
3614         }
3615         if (!hdw->flag_ok && !probe_fl) {
3616                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3617                            "Attempted to execute control transfer"
3618                            " when device not ok");
3619                 return -EIO;
3620         }
3621         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3622                 if (!probe_fl) {
3623                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3624                                    "Attempted to execute control transfer"
3625                                    " when USB is disconnected");
3626                 }
3627                 return -ENOTTY;
3628         }
3629
3630         /* Ensure that we have sane parameters */
3631         if (!write_data) write_len = 0;
3632         if (!read_data) read_len = 0;
3633         if (write_len > PVR2_CTL_BUFFSIZE) {
3634                 pvr2_trace(
3635                         PVR2_TRACE_ERROR_LEGS,
3636                         "Attempted to execute %d byte"
3637                         " control-write transfer (limit=%d)",
3638                         write_len,PVR2_CTL_BUFFSIZE);
3639                 return -EINVAL;
3640         }
3641         if (read_len > PVR2_CTL_BUFFSIZE) {
3642                 pvr2_trace(
3643                         PVR2_TRACE_ERROR_LEGS,
3644                         "Attempted to execute %d byte"
3645                         " control-read transfer (limit=%d)",
3646                         write_len,PVR2_CTL_BUFFSIZE);
3647                 return -EINVAL;
3648         }
3649         if ((!write_len) && (!read_len)) {
3650                 pvr2_trace(
3651                         PVR2_TRACE_ERROR_LEGS,
3652                         "Attempted to execute null control transfer?");
3653                 return -EINVAL;
3654         }
3655
3656
3657         hdw->cmd_debug_state = 1;
3658         if (write_len) {
3659                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3660         } else {
3661                 hdw->cmd_debug_code = 0;
3662         }
3663         hdw->cmd_debug_write_len = write_len;
3664         hdw->cmd_debug_read_len = read_len;
3665
3666         /* Initialize common stuff */
3667         init_completion(&hdw->ctl_done);
3668         hdw->ctl_timeout_flag = 0;
3669         hdw->ctl_write_pend_flag = 0;
3670         hdw->ctl_read_pend_flag = 0;
3671         init_timer(&timer);
3672         timer.expires = jiffies + timeout;
3673         timer.data = (unsigned long)hdw;
3674         timer.function = pvr2_ctl_timeout;
3675
3676         if (write_len) {
3677                 hdw->cmd_debug_state = 2;
3678                 /* Transfer write data to internal buffer */
3679                 for (idx = 0; idx < write_len; idx++) {
3680                         hdw->ctl_write_buffer[idx] =
3681                                 ((unsigned char *)write_data)[idx];
3682                 }
3683                 /* Initiate a write request */
3684                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3685                                   hdw->usb_dev,
3686                                   usb_sndbulkpipe(hdw->usb_dev,
3687                                                   PVR2_CTL_WRITE_ENDPOINT),
3688                                   hdw->ctl_write_buffer,
3689                                   write_len,
3690                                   pvr2_ctl_write_complete,
3691                                   hdw);
3692                 hdw->ctl_write_urb->actual_length = 0;
3693                 hdw->ctl_write_pend_flag = !0;
3694                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3695                 if (status < 0) {
3696                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3697                                    "Failed to submit write-control"
3698                                    " URB status=%d",status);
3699                         hdw->ctl_write_pend_flag = 0;
3700                         goto done;
3701                 }
3702         }
3703
3704         if (read_len) {
3705                 hdw->cmd_debug_state = 3;
3706                 memset(hdw->ctl_read_buffer,0x43,read_len);
3707                 /* Initiate a read request */
3708                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3709                                   hdw->usb_dev,
3710                                   usb_rcvbulkpipe(hdw->usb_dev,
3711                                                   PVR2_CTL_READ_ENDPOINT),
3712                                   hdw->ctl_read_buffer,
3713                                   read_len,
3714                                   pvr2_ctl_read_complete,
3715                                   hdw);
3716                 hdw->ctl_read_urb->actual_length = 0;
3717                 hdw->ctl_read_pend_flag = !0;
3718                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3719                 if (status < 0) {
3720                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3721                                    "Failed to submit read-control"
3722                                    " URB status=%d",status);
3723                         hdw->ctl_read_pend_flag = 0;
3724                         goto done;
3725                 }
3726         }
3727
3728         /* Start timer */
3729         add_timer(&timer);
3730
3731         /* Now wait for all I/O to complete */
3732         hdw->cmd_debug_state = 4;
3733         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3734                 wait_for_completion(&hdw->ctl_done);
3735         }
3736         hdw->cmd_debug_state = 5;
3737
3738         /* Stop timer */
3739         del_timer_sync(&timer);
3740
3741         hdw->cmd_debug_state = 6;
3742         status = 0;
3743
3744         if (hdw->ctl_timeout_flag) {
3745                 status = -ETIMEDOUT;
3746                 if (!probe_fl) {
3747                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3748                                    "Timed out control-write");
3749                 }
3750                 goto done;
3751         }
3752
3753         if (write_len) {
3754                 /* Validate results of write request */
3755                 if ((hdw->ctl_write_urb->status != 0) &&
3756                     (hdw->ctl_write_urb->status != -ENOENT) &&
3757                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3758                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3759                         /* USB subsystem is reporting some kind of failure
3760                            on the write */
3761                         status = hdw->ctl_write_urb->status;
3762                         if (!probe_fl) {
3763                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3764                                            "control-write URB failure,"
3765                                            " status=%d",
3766                                            status);
3767                         }
3768                         goto done;
3769                 }
3770                 if (hdw->ctl_write_urb->actual_length < write_len) {
3771                         /* Failed to write enough data */
3772                         status = -EIO;
3773                         if (!probe_fl) {
3774                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3775                                            "control-write URB short,"
3776                                            " expected=%d got=%d",
3777                                            write_len,
3778                                            hdw->ctl_write_urb->actual_length);
3779                         }
3780                         goto done;
3781                 }
3782         }
3783         if (read_len) {
3784                 /* Validate results of read request */
3785                 if ((hdw->ctl_read_urb->status != 0) &&
3786                     (hdw->ctl_read_urb->status != -ENOENT) &&
3787                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3788                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3789                         /* USB subsystem is reporting some kind of failure
3790                            on the read */
3791                         status = hdw->ctl_read_urb->status;
3792                         if (!probe_fl) {
3793                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3794                                            "control-read URB failure,"
3795                                            " status=%d",
3796                                            status);
3797                         }
3798                         goto done;
3799                 }
3800                 if (hdw->ctl_read_urb->actual_length < read_len) {
3801                         /* Failed to read enough data */
3802                         status = -EIO;
3803                         if (!probe_fl) {
3804                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3805                                            "control-read URB short,"
3806                                            " expected=%d got=%d",
3807                                            read_len,
3808                                            hdw->ctl_read_urb->actual_length);
3809                         }
3810                         goto done;
3811                 }
3812                 /* Transfer retrieved data out from internal buffer */
3813                 for (idx = 0; idx < read_len; idx++) {
3814                         ((unsigned char *)read_data)[idx] =
3815                                 hdw->ctl_read_buffer[idx];
3816                 }
3817         }
3818
3819  done:
3820
3821         hdw->cmd_debug_state = 0;
3822         if ((status < 0) && (!probe_fl)) {
3823                 pvr2_hdw_render_useless(hdw);
3824         }
3825         return status;
3826 }
3827
3828
3829 int pvr2_send_request(struct pvr2_hdw *hdw,
3830                       void *write_data,unsigned int write_len,
3831                       void *read_data,unsigned int read_len)
3832 {
3833         return pvr2_send_request_ex(hdw,HZ*4,0,
3834                                     write_data,write_len,
3835                                     read_data,read_len);
3836 }
3837
3838
3839 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3840 {
3841         int ret;
3842         unsigned int cnt = 1;
3843         unsigned int args = 0;
3844         LOCK_TAKE(hdw->ctl_lock);
3845         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3846         args = (cmdcode >> 8) & 0xffu;
3847         args = (args > 2) ? 2 : args;
3848         if (args) {
3849                 cnt += args;
3850                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3851                 if (args > 1) {
3852                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3853                 }
3854         }
3855         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3856                 unsigned int idx;
3857                 unsigned int ccnt,bcnt;
3858                 char tbuf[50];
3859                 cmdcode &= 0xffu;
3860                 bcnt = 0;
3861                 ccnt = scnprintf(tbuf+bcnt,
3862                                  sizeof(tbuf)-bcnt,
3863                                  "Sending FX2 command 0x%x",cmdcode);
3864                 bcnt += ccnt;
3865                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3866                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3867                                 ccnt = scnprintf(tbuf+bcnt,
3868                                                  sizeof(tbuf)-bcnt,
3869                                                  " \"%s\"",
3870                                                  pvr2_fx2cmd_desc[idx].desc);
3871                                 bcnt += ccnt;
3872                                 break;
3873                         }
3874                 }
3875                 if (args) {
3876                         ccnt = scnprintf(tbuf+bcnt,
3877                                          sizeof(tbuf)-bcnt,
3878                                          " (%u",hdw->cmd_buffer[1]);
3879                         bcnt += ccnt;
3880                         if (args > 1) {
3881                                 ccnt = scnprintf(tbuf+bcnt,
3882                                                  sizeof(tbuf)-bcnt,
3883                                                  ",%u",hdw->cmd_buffer[2]);
3884                                 bcnt += ccnt;
3885                         }
3886                         ccnt = scnprintf(tbuf+bcnt,
3887                                          sizeof(tbuf)-bcnt,
3888                                          ")");
3889                         bcnt += ccnt;
3890                 }
3891                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3892         }
3893         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3894         LOCK_GIVE(hdw->ctl_lock);
3895         return ret;
3896 }
3897
3898
3899 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3900 {
3901         int ret;
3902
3903         LOCK_TAKE(hdw->ctl_lock);
3904
3905         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3906         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3907         hdw->cmd_buffer[5] = 0;
3908         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3909         hdw->cmd_buffer[7] = reg & 0xff;
3910
3911
3912         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3913
3914         LOCK_GIVE(hdw->ctl_lock);
3915
3916         return ret;
3917 }
3918
3919
3920 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3921 {
3922         int ret = 0;
3923
3924         LOCK_TAKE(hdw->ctl_lock);
3925
3926         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3927         hdw->cmd_buffer[1] = 0;
3928         hdw->cmd_buffer[2] = 0;
3929         hdw->cmd_buffer[3] = 0;
3930         hdw->cmd_buffer[4] = 0;
3931         hdw->cmd_buffer[5] = 0;
3932         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3933         hdw->cmd_buffer[7] = reg & 0xff;
3934
3935         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3936         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3937
3938         LOCK_GIVE(hdw->ctl_lock);
3939
3940         return ret;
3941 }
3942
3943
3944 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3945 {
3946         if (!hdw->flag_ok) return;
3947         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3948                    "Device being rendered inoperable");
3949         if (hdw->vid_stream) {
3950                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3951         }
3952         hdw->flag_ok = 0;
3953         trace_stbit("flag_ok",hdw->flag_ok);
3954         pvr2_hdw_state_sched(hdw);
3955 }
3956
3957
3958 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3959 {
3960         int ret;
3961         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3962         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3963         if (ret == 0) {
3964                 ret = usb_reset_device(hdw->usb_dev);
3965                 usb_unlock_device(hdw->usb_dev);
3966         } else {
3967                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3968                            "Failed to lock USB device ret=%d",ret);
3969         }
3970         if (init_pause_msec) {
3971                 pvr2_trace(PVR2_TRACE_INFO,
3972                            "Waiting %u msec for hardware to settle",
3973                            init_pause_msec);
3974                 msleep(init_pause_msec);
3975         }
3976
3977 }
3978
3979
3980 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3981 {
3982         char da[1];
3983         unsigned int pipe;
3984         int ret;
3985
3986         if (!hdw->usb_dev) return;
3987
3988         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3989
3990         da[0] = val ? 0x01 : 0x00;
3991
3992         /* Write the CPUCS register on the 8051.  The lsb of the register
3993            is the reset bit; a 1 asserts reset while a 0 clears it. */
3994         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3995         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3996         if (ret < 0) {
3997                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3998                            "cpureset_assert(%d) error=%d",val,ret);
3999                 pvr2_hdw_render_useless(hdw);
4000         }
4001 }
4002
4003
4004 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4005 {
4006         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4007 }
4008
4009
4010 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4011 {
4012         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4013 }
4014
4015
4016 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4017 {
4018         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
4019 }
4020
4021
4022 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4023 {
4024         pvr2_trace(PVR2_TRACE_INIT,
4025                    "Requesting decoder reset");
4026         if (hdw->decoder_ctrl) {
4027                 if (!hdw->decoder_ctrl->force_reset) {
4028                         pvr2_trace(PVR2_TRACE_INIT,
4029                                    "Unable to reset decoder: not implemented");
4030                         return -ENOTTY;
4031                 }
4032                 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
4033                 return 0;
4034         } else {
4035         }
4036         if (hdw->decoder_client_id) {
4037                 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4038                                      core, reset, 0);
4039                 return 0;
4040         }
4041         pvr2_trace(PVR2_TRACE_INIT,
4042                    "Unable to reset decoder: nothing attached");
4043         return -ENOTTY;
4044 }
4045
4046
4047 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4048 {
4049         hdw->flag_ok = !0;
4050         return pvr2_issue_simple_cmd(hdw,
4051                                      FX2CMD_HCW_DEMOD_RESETIN |
4052                                      (1 << 8) |
4053                                      ((onoff ? 1 : 0) << 16));
4054 }
4055
4056
4057 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4058 {
4059         hdw->flag_ok = !0;
4060         return pvr2_issue_simple_cmd(hdw,(onoff ?
4061                                           FX2CMD_ONAIR_DTV_POWER_ON :
4062                                           FX2CMD_ONAIR_DTV_POWER_OFF));
4063 }
4064
4065
4066 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4067                                                 int onoff)
4068 {
4069         return pvr2_issue_simple_cmd(hdw,(onoff ?
4070                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
4071                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
4072 }
4073
4074
4075 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4076 {
4077         int cmode;
4078         /* Compare digital/analog desired setting with current setting.  If
4079            they don't match, fix it... */
4080         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4081         if (cmode == hdw->pathway_state) {
4082                 /* They match; nothing to do */
4083                 return;
4084         }
4085
4086         switch (hdw->hdw_desc->digital_control_scheme) {
4087         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4088                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4089                 if (cmode == PVR2_PATHWAY_ANALOG) {
4090                         /* If moving to analog mode, also force the decoder
4091                            to reset.  If no decoder is attached, then it's
4092                            ok to ignore this because if/when the decoder
4093                            attaches, it will reset itself at that time. */
4094                         pvr2_hdw_cmd_decoder_reset(hdw);
4095                 }
4096                 break;
4097         case PVR2_DIGITAL_SCHEME_ONAIR:
4098                 /* Supposedly we should always have the power on whether in
4099                    digital or analog mode.  But for now do what appears to
4100                    work... */
4101                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4102                 break;
4103         default: break;
4104         }
4105
4106         pvr2_hdw_untrip_unlocked(hdw);
4107         hdw->pathway_state = cmode;
4108 }
4109
4110
4111 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4112 {
4113         /* change some GPIO data
4114          *
4115          * note: bit d7 of dir appears to control the LED,
4116          * so we shut it off here.
4117          *
4118          */
4119         if (onoff) {
4120                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4121         } else {
4122                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4123         }
4124         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4125 }
4126
4127
4128 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4129
4130 static led_method_func led_methods[] = {
4131         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4132 };
4133
4134
4135 /* Toggle LED */
4136 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4137 {
4138         unsigned int scheme_id;
4139         led_method_func fp;
4140
4141         if ((!onoff) == (!hdw->led_on)) return;
4142
4143         hdw->led_on = onoff != 0;
4144
4145         scheme_id = hdw->hdw_desc->led_scheme;
4146         if (scheme_id < ARRAY_SIZE(led_methods)) {
4147                 fp = led_methods[scheme_id];
4148         } else {
4149                 fp = NULL;
4150         }
4151
4152         if (fp) (*fp)(hdw,onoff);
4153 }
4154
4155
4156 /* Stop / start video stream transport */
4157 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4158 {
4159         int ret;
4160
4161         /* If we're in analog mode, then just issue the usual analog
4162            command. */
4163         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4164                 return pvr2_issue_simple_cmd(hdw,
4165                                              (runFl ?
4166                                               FX2CMD_STREAMING_ON :
4167                                               FX2CMD_STREAMING_OFF));
4168                 /*Note: Not reached */
4169         }
4170
4171         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4172                 /* Whoops, we don't know what mode we're in... */
4173                 return -EINVAL;
4174         }
4175
4176         /* To get here we have to be in digital mode.  The mechanism here
4177            is unfortunately different for different vendors.  So we switch
4178            on the device's digital scheme attribute in order to figure out
4179            what to do. */
4180         switch (hdw->hdw_desc->digital_control_scheme) {
4181         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4182                 return pvr2_issue_simple_cmd(hdw,
4183                                              (runFl ?
4184                                               FX2CMD_HCW_DTV_STREAMING_ON :
4185                                               FX2CMD_HCW_DTV_STREAMING_OFF));
4186         case PVR2_DIGITAL_SCHEME_ONAIR:
4187                 ret = pvr2_issue_simple_cmd(hdw,
4188                                             (runFl ?
4189                                              FX2CMD_STREAMING_ON :
4190                                              FX2CMD_STREAMING_OFF));
4191                 if (ret) return ret;
4192                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4193         default:
4194                 return -EINVAL;
4195         }
4196 }
4197
4198
4199 /* Evaluate whether or not state_pathway_ok can change */
4200 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4201 {
4202         if (hdw->state_pathway_ok) {
4203                 /* Nothing to do if pathway is already ok */
4204                 return 0;
4205         }
4206         if (!hdw->state_pipeline_idle) {
4207                 /* Not allowed to change anything if pipeline is not idle */
4208                 return 0;
4209         }
4210         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4211         hdw->state_pathway_ok = !0;
4212         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4213         return !0;
4214 }
4215
4216
4217 /* Evaluate whether or not state_encoder_ok can change */
4218 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4219 {
4220         if (hdw->state_encoder_ok) return 0;
4221         if (hdw->flag_tripped) return 0;
4222         if (hdw->state_encoder_run) return 0;
4223         if (hdw->state_encoder_config) return 0;
4224         if (hdw->state_decoder_run) return 0;
4225         if (hdw->state_usbstream_run) return 0;
4226         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4227                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4228         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4229                 return 0;
4230         }
4231
4232         if (pvr2_upload_firmware2(hdw) < 0) {
4233                 hdw->flag_tripped = !0;
4234                 trace_stbit("flag_tripped",hdw->flag_tripped);
4235                 return !0;
4236         }
4237         hdw->state_encoder_ok = !0;
4238         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4239         return !0;
4240 }
4241
4242
4243 /* Evaluate whether or not state_encoder_config can change */
4244 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4245 {
4246         if (hdw->state_encoder_config) {
4247                 if (hdw->state_encoder_ok) {
4248                         if (hdw->state_pipeline_req &&
4249                             !hdw->state_pipeline_pause) return 0;
4250                 }
4251                 hdw->state_encoder_config = 0;
4252                 hdw->state_encoder_waitok = 0;
4253                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4254                 /* paranoia - solve race if timer just completed */
4255                 del_timer_sync(&hdw->encoder_wait_timer);
4256         } else {
4257                 if (!hdw->state_pathway_ok ||
4258                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4259                     !hdw->state_encoder_ok ||
4260                     !hdw->state_pipeline_idle ||
4261                     hdw->state_pipeline_pause ||
4262                     !hdw->state_pipeline_req ||
4263                     !hdw->state_pipeline_config) {
4264                         /* We must reset the enforced wait interval if
4265                            anything has happened that might have disturbed
4266                            the encoder.  This should be a rare case. */
4267                         if (timer_pending(&hdw->encoder_wait_timer)) {
4268                                 del_timer_sync(&hdw->encoder_wait_timer);
4269                         }
4270                         if (hdw->state_encoder_waitok) {
4271                                 /* Must clear the state - therefore we did
4272                                    something to a state bit and must also
4273                                    return true. */
4274                                 hdw->state_encoder_waitok = 0;
4275                                 trace_stbit("state_encoder_waitok",
4276                                             hdw->state_encoder_waitok);
4277                                 return !0;
4278                         }
4279                         return 0;
4280                 }
4281                 if (!hdw->state_encoder_waitok) {
4282                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4283                                 /* waitok flag wasn't set and timer isn't
4284                                    running.  Check flag once more to avoid
4285                                    a race then start the timer.  This is
4286                                    the point when we measure out a minimal
4287                                    quiet interval before doing something to
4288                                    the encoder. */
4289                                 if (!hdw->state_encoder_waitok) {
4290                                         hdw->encoder_wait_timer.expires =
4291                                                 jiffies +
4292                                                 (HZ * TIME_MSEC_ENCODER_WAIT
4293                                                  / 1000);
4294                                         add_timer(&hdw->encoder_wait_timer);
4295                                 }
4296                         }
4297                         /* We can't continue until we know we have been
4298                            quiet for the interval measured by this
4299                            timer. */
4300                         return 0;
4301                 }
4302                 pvr2_encoder_configure(hdw);
4303                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4304         }
4305         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4306         return !0;
4307 }
4308
4309
4310 /* Return true if the encoder should not be running. */
4311 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4312 {
4313         if (!hdw->state_encoder_ok) {
4314                 /* Encoder isn't healthy at the moment, so stop it. */
4315                 return !0;
4316         }
4317         if (!hdw->state_pathway_ok) {
4318                 /* Mode is not understood at the moment (i.e. it wants to
4319                    change), so encoder must be stopped. */
4320                 return !0;
4321         }
4322
4323         switch (hdw->pathway_state) {
4324         case PVR2_PATHWAY_ANALOG:
4325                 if (!hdw->state_decoder_run) {
4326                         /* We're in analog mode and the decoder is not
4327                            running; thus the encoder should be stopped as
4328                            well. */
4329                         return !0;
4330                 }
4331                 break;
4332         case PVR2_PATHWAY_DIGITAL:
4333                 if (hdw->state_encoder_runok) {
4334                         /* This is a funny case.  We're in digital mode so
4335                            really the encoder should be stopped.  However
4336                            if it really is running, only kill it after
4337                            runok has been set.  This gives a chance for the
4338                            onair quirk to function (encoder must run
4339                            briefly first, at least once, before onair
4340                            digital streaming can work). */
4341                         return !0;
4342                 }
4343                 break;
4344         default:
4345                 /* Unknown mode; so encoder should be stopped. */
4346                 return !0;
4347         }
4348
4349         /* If we get here, we haven't found a reason to stop the
4350            encoder. */
4351         return 0;
4352 }
4353
4354
4355 /* Return true if the encoder should be running. */
4356 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4357 {
4358         if (!hdw->state_encoder_ok) {
4359                 /* Don't run the encoder if it isn't healthy... */
4360                 return 0;
4361         }
4362         if (!hdw->state_pathway_ok) {
4363                 /* Don't run the encoder if we don't (yet) know what mode
4364                    we need to be in... */
4365                 return 0;
4366         }
4367
4368         switch (hdw->pathway_state) {
4369         case PVR2_PATHWAY_ANALOG:
4370                 if (hdw->state_decoder_run) {
4371                         /* In analog mode, if the decoder is running, then
4372                            run the encoder. */
4373                         return !0;
4374                 }
4375                 break;
4376         case PVR2_PATHWAY_DIGITAL:
4377                 if ((hdw->hdw_desc->digital_control_scheme ==
4378                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4379                     !hdw->state_encoder_runok) {
4380                         /* This is a quirk.  OnAir hardware won't stream
4381                            digital until the encoder has been run at least
4382                            once, for a minimal period of time (empiricially
4383                            measured to be 1/4 second).  So if we're on
4384                            OnAir hardware and the encoder has never been
4385                            run at all, then start the encoder.  Normal
4386                            state machine logic in the driver will
4387                            automatically handle the remaining bits. */
4388                         return !0;
4389                 }
4390                 break;
4391         default:
4392                 /* For completeness (unknown mode; encoder won't run ever) */
4393                 break;
4394         }
4395         /* If we get here, then we haven't found any reason to run the
4396            encoder, so don't run it. */
4397         return 0;
4398 }
4399
4400
4401 /* Evaluate whether or not state_encoder_run can change */
4402 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4403 {
4404         if (hdw->state_encoder_run) {
4405                 if (!state_check_disable_encoder_run(hdw)) return 0;
4406                 if (hdw->state_encoder_ok) {
4407                         del_timer_sync(&hdw->encoder_run_timer);
4408                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4409                 }
4410                 hdw->state_encoder_run = 0;
4411         } else {
4412                 if (!state_check_enable_encoder_run(hdw)) return 0;
4413                 if (pvr2_encoder_start(hdw) < 0) return !0;
4414                 hdw->state_encoder_run = !0;
4415                 if (!hdw->state_encoder_runok) {
4416                         hdw->encoder_run_timer.expires =
4417                                 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4418                         add_timer(&hdw->encoder_run_timer);
4419                 }
4420         }
4421         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4422         return !0;
4423 }
4424
4425
4426 /* Timeout function for quiescent timer. */
4427 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4428 {
4429         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4430         hdw->state_decoder_quiescent = !0;
4431         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4432         hdw->state_stale = !0;
4433         queue_work(hdw->workqueue,&hdw->workpoll);
4434 }
4435
4436
4437 /* Timeout function for encoder wait timer. */
4438 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4439 {
4440         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4441         hdw->state_encoder_waitok = !0;
4442         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4443         hdw->state_stale = !0;
4444         queue_work(hdw->workqueue,&hdw->workpoll);
4445 }
4446
4447
4448 /* Timeout function for encoder run timer. */
4449 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4450 {
4451         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4452         if (!hdw->state_encoder_runok) {
4453                 hdw->state_encoder_runok = !0;
4454                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4455                 hdw->state_stale = !0;
4456                 queue_work(hdw->workqueue,&hdw->workpoll);
4457         }
4458 }
4459
4460
4461 /* Evaluate whether or not state_decoder_run can change */
4462 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4463 {
4464         if (hdw->state_decoder_run) {
4465                 if (hdw->state_encoder_ok) {
4466                         if (hdw->state_pipeline_req &&
4467                             !hdw->state_pipeline_pause &&
4468                             hdw->state_pathway_ok) return 0;
4469                 }
4470                 if (!hdw->flag_decoder_missed) {
4471                         pvr2_decoder_enable(hdw,0);
4472                 }
4473                 hdw->state_decoder_quiescent = 0;
4474                 hdw->state_decoder_run = 0;
4475                 /* paranoia - solve race if timer just completed */
4476                 del_timer_sync(&hdw->quiescent_timer);
4477         } else {
4478                 if (!hdw->state_decoder_quiescent) {
4479                         if (!timer_pending(&hdw->quiescent_timer)) {
4480                                 /* We don't do something about the
4481                                    quiescent timer until right here because
4482                                    we also want to catch cases where the
4483                                    decoder was already not running (like
4484                                    after initialization) as opposed to
4485                                    knowing that we had just stopped it.
4486                                    The second flag check is here to cover a
4487                                    race - the timer could have run and set
4488                                    this flag just after the previous check
4489                                    but before we did the pending check. */
4490                                 if (!hdw->state_decoder_quiescent) {
4491                                         hdw->quiescent_timer.expires =
4492                                                 jiffies +
4493                                                 (HZ * TIME_MSEC_DECODER_WAIT
4494                                                  / 1000);
4495                                         add_timer(&hdw->quiescent_timer);
4496                                 }
4497                         }
4498                         /* Don't allow decoder to start again until it has
4499                            been quiesced first.  This little detail should
4500                            hopefully further stabilize the encoder. */
4501                         return 0;
4502                 }
4503                 if (!hdw->state_pathway_ok ||
4504                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4505                     !hdw->state_pipeline_req ||
4506                     hdw->state_pipeline_pause ||
4507                     !hdw->state_pipeline_config ||
4508                     !hdw->state_encoder_config ||
4509                     !hdw->state_encoder_ok) return 0;
4510                 del_timer_sync(&hdw->quiescent_timer);
4511                 if (hdw->flag_decoder_missed) return 0;
4512                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4513                 hdw->state_decoder_quiescent = 0;
4514                 hdw->state_decoder_run = !0;
4515         }
4516         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4517         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4518         return !0;
4519 }
4520
4521
4522 /* Evaluate whether or not state_usbstream_run can change */
4523 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4524 {
4525         if (hdw->state_usbstream_run) {
4526                 int fl = !0;
4527                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4528                         fl = (hdw->state_encoder_ok &&
4529                               hdw->state_encoder_run);
4530                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4531                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4532                         fl = hdw->state_encoder_ok;
4533                 }
4534                 if (fl &&
4535                     hdw->state_pipeline_req &&
4536                     !hdw->state_pipeline_pause &&
4537                     hdw->state_pathway_ok) {
4538                         return 0;
4539                 }
4540                 pvr2_hdw_cmd_usbstream(hdw,0);
4541                 hdw->state_usbstream_run = 0;
4542         } else {
4543                 if (!hdw->state_pipeline_req ||
4544                     hdw->state_pipeline_pause ||
4545                     !hdw->state_pathway_ok) return 0;
4546                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4547                         if (!hdw->state_encoder_ok ||
4548                             !hdw->state_encoder_run) return 0;
4549                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4550                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4551                         if (!hdw->state_encoder_ok) return 0;
4552                         if (hdw->state_encoder_run) return 0;
4553                         if (hdw->hdw_desc->digital_control_scheme ==
4554                             PVR2_DIGITAL_SCHEME_ONAIR) {
4555                                 /* OnAir digital receivers won't stream
4556                                    unless the analog encoder has run first.
4557                                    Why?  I have no idea.  But don't even
4558                                    try until we know the analog side is
4559                                    known to have run. */
4560                                 if (!hdw->state_encoder_runok) return 0;
4561                         }
4562                 }
4563                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4564                 hdw->state_usbstream_run = !0;
4565         }
4566         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4567         return !0;
4568 }
4569
4570
4571 /* Attempt to configure pipeline, if needed */
4572 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4573 {
4574         if (hdw->state_pipeline_config ||
4575             hdw->state_pipeline_pause) return 0;
4576         pvr2_hdw_commit_execute(hdw);
4577         return !0;
4578 }
4579
4580
4581 /* Update pipeline idle and pipeline pause tracking states based on other
4582    inputs.  This must be called whenever the other relevant inputs have
4583    changed. */
4584 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4585 {
4586         unsigned int st;
4587         int updatedFl = 0;
4588         /* Update pipeline state */
4589         st = !(hdw->state_encoder_run ||
4590                hdw->state_decoder_run ||
4591                hdw->state_usbstream_run ||
4592                (!hdw->state_decoder_quiescent));
4593         if (!st != !hdw->state_pipeline_idle) {
4594                 hdw->state_pipeline_idle = st;
4595                 updatedFl = !0;
4596         }
4597         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4598                 hdw->state_pipeline_pause = 0;
4599                 updatedFl = !0;
4600         }
4601         return updatedFl;
4602 }
4603
4604
4605 typedef int (*state_eval_func)(struct pvr2_hdw *);
4606
4607 /* Set of functions to be run to evaluate various states in the driver. */
4608 static const state_eval_func eval_funcs[] = {
4609         state_eval_pathway_ok,
4610         state_eval_pipeline_config,
4611         state_eval_encoder_ok,
4612         state_eval_encoder_config,
4613         state_eval_decoder_run,
4614         state_eval_encoder_run,
4615         state_eval_usbstream_run,
4616 };
4617
4618
4619 /* Process various states and return true if we did anything interesting. */
4620 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4621 {
4622         unsigned int i;
4623         int state_updated = 0;
4624         int check_flag;
4625
4626         if (!hdw->state_stale) return 0;
4627         if ((hdw->fw1_state != FW1_STATE_OK) ||
4628             !hdw->flag_ok) {
4629                 hdw->state_stale = 0;
4630                 return !0;
4631         }
4632         /* This loop is the heart of the entire driver.  It keeps trying to
4633            evaluate various bits of driver state until nothing changes for
4634            one full iteration.  Each "bit of state" tracks some global
4635            aspect of the driver, e.g. whether decoder should run, if
4636            pipeline is configured, usb streaming is on, etc.  We separately
4637            evaluate each of those questions based on other driver state to
4638            arrive at the correct running configuration. */
4639         do {
4640                 check_flag = 0;
4641                 state_update_pipeline_state(hdw);
4642                 /* Iterate over each bit of state */
4643                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4644                         if ((*eval_funcs[i])(hdw)) {
4645                                 check_flag = !0;
4646                                 state_updated = !0;
4647                                 state_update_pipeline_state(hdw);
4648                         }
4649                 }
4650         } while (check_flag && hdw->flag_ok);
4651         hdw->state_stale = 0;
4652         trace_stbit("state_stale",hdw->state_stale);
4653         return state_updated;
4654 }
4655
4656
4657 static unsigned int print_input_mask(unsigned int msk,
4658                                      char *buf,unsigned int acnt)
4659 {
4660         unsigned int idx,ccnt;
4661         unsigned int tcnt = 0;
4662         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4663                 if (!((1 << idx) & msk)) continue;
4664                 ccnt = scnprintf(buf+tcnt,
4665                                  acnt-tcnt,
4666                                  "%s%s",
4667                                  (tcnt ? ", " : ""),
4668                                  control_values_input[idx]);
4669                 tcnt += ccnt;
4670         }
4671         return tcnt;
4672 }
4673
4674
4675 static const char *pvr2_pathway_state_name(int id)
4676 {
4677         switch (id) {
4678         case PVR2_PATHWAY_ANALOG: return "analog";
4679         case PVR2_PATHWAY_DIGITAL: return "digital";
4680         default: return "unknown";
4681         }
4682 }
4683
4684
4685 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4686                                              char *buf,unsigned int acnt)
4687 {
4688         switch (which) {
4689         case 0:
4690                 return scnprintf(
4691                         buf,acnt,
4692                         "driver:%s%s%s%s%s <mode=%s>",
4693                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4694                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4695                         (hdw->flag_disconnected ? " <disconnected>" :
4696                          " <connected>"),
4697                         (hdw->flag_tripped ? " <tripped>" : ""),
4698                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4699                         pvr2_pathway_state_name(hdw->pathway_state));
4700
4701         case 1:
4702                 return scnprintf(
4703                         buf,acnt,
4704                         "pipeline:%s%s%s%s",
4705                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4706                         (hdw->state_pipeline_config ?
4707                          " <configok>" : " <stale>"),
4708                         (hdw->state_pipeline_req ? " <req>" : ""),
4709                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4710         case 2:
4711                 return scnprintf(
4712                         buf,acnt,
4713                         "worker:%s%s%s%s%s%s%s",
4714                         (hdw->state_decoder_run ?
4715                          " <decode:run>" :
4716                          (hdw->state_decoder_quiescent ?
4717                           "" : " <decode:stop>")),
4718                         (hdw->state_decoder_quiescent ?
4719                          " <decode:quiescent>" : ""),
4720                         (hdw->state_encoder_ok ?
4721                          "" : " <encode:init>"),
4722                         (hdw->state_encoder_run ?
4723                          (hdw->state_encoder_runok ?
4724                           " <encode:run>" :
4725                           " <encode:firstrun>") :
4726                          (hdw->state_encoder_runok ?
4727                           " <encode:stop>" :
4728                           " <encode:virgin>")),
4729                         (hdw->state_encoder_config ?
4730                          " <encode:configok>" :
4731                          (hdw->state_encoder_waitok ?
4732                           "" : " <encode:waitok>")),
4733                         (hdw->state_usbstream_run ?
4734                          " <usb:run>" : " <usb:stop>"),
4735                         (hdw->state_pathway_ok ?
4736                          " <pathway:ok>" : ""));
4737         case 3:
4738                 return scnprintf(
4739                         buf,acnt,
4740                         "state: %s",
4741                         pvr2_get_state_name(hdw->master_state));
4742         case 4: {
4743                 unsigned int tcnt = 0;
4744                 unsigned int ccnt;
4745
4746                 ccnt = scnprintf(buf,
4747                                  acnt,
4748                                  "Hardware supported inputs: ");
4749                 tcnt += ccnt;
4750                 tcnt += print_input_mask(hdw->input_avail_mask,
4751                                          buf+tcnt,
4752                                          acnt-tcnt);
4753                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4754                         ccnt = scnprintf(buf+tcnt,
4755                                          acnt-tcnt,
4756                                          "; allowed inputs: ");
4757                         tcnt += ccnt;
4758                         tcnt += print_input_mask(hdw->input_allowed_mask,
4759                                                  buf+tcnt,
4760                                                  acnt-tcnt);
4761                 }
4762                 return tcnt;
4763         }
4764         case 5: {
4765                 struct pvr2_stream_stats stats;
4766                 if (!hdw->vid_stream) break;
4767                 pvr2_stream_get_stats(hdw->vid_stream,
4768                                       &stats,
4769                                       0);
4770                 return scnprintf(
4771                         buf,acnt,
4772                         "Bytes streamed=%u"
4773                         " URBs: queued=%u idle=%u ready=%u"
4774                         " processed=%u failed=%u",
4775                         stats.bytes_processed,
4776                         stats.buffers_in_queue,
4777                         stats.buffers_in_idle,
4778                         stats.buffers_in_ready,
4779                         stats.buffers_processed,
4780                         stats.buffers_failed);
4781         }
4782         default: break;
4783         }
4784         return 0;
4785 }
4786
4787
4788 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4789                                    char *buf,unsigned int acnt)
4790 {
4791         unsigned int bcnt,ccnt,idx;
4792         bcnt = 0;
4793         LOCK_TAKE(hdw->big_lock);
4794         for (idx = 0; ; idx++) {
4795                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4796                 if (!ccnt) break;
4797                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4798                 if (!acnt) break;
4799                 buf[0] = '\n'; ccnt = 1;
4800                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4801         }
4802         LOCK_GIVE(hdw->big_lock);
4803         return bcnt;
4804 }
4805
4806
4807 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4808 {
4809         char buf[128];
4810         unsigned int idx,ccnt;
4811
4812         for (idx = 0; ; idx++) {
4813                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4814                 if (!ccnt) break;
4815                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4816         }
4817 }
4818
4819
4820 /* Evaluate and update the driver's current state, taking various actions
4821    as appropriate for the update. */
4822 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4823 {
4824         unsigned int st;
4825         int state_updated = 0;
4826         int callback_flag = 0;
4827         int analog_mode;
4828
4829         pvr2_trace(PVR2_TRACE_STBITS,
4830                    "Drive state check START");
4831         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4832                 pvr2_hdw_state_log_state(hdw);
4833         }
4834
4835         /* Process all state and get back over disposition */
4836         state_updated = pvr2_hdw_state_update(hdw);
4837
4838         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4839
4840         /* Update master state based upon all other states. */
4841         if (!hdw->flag_ok) {
4842                 st = PVR2_STATE_DEAD;
4843         } else if (hdw->fw1_state != FW1_STATE_OK) {
4844                 st = PVR2_STATE_COLD;
4845         } else if ((analog_mode ||
4846                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4847                    !hdw->state_encoder_ok) {
4848                 st = PVR2_STATE_WARM;
4849         } else if (hdw->flag_tripped ||
4850                    (analog_mode && hdw->flag_decoder_missed)) {
4851                 st = PVR2_STATE_ERROR;
4852         } else if (hdw->state_usbstream_run &&
4853                    (!analog_mode ||
4854                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4855                 st = PVR2_STATE_RUN;
4856         } else {
4857                 st = PVR2_STATE_READY;
4858         }
4859         if (hdw->master_state != st) {
4860                 pvr2_trace(PVR2_TRACE_STATE,
4861                            "Device state change from %s to %s",
4862                            pvr2_get_state_name(hdw->master_state),
4863                            pvr2_get_state_name(st));
4864                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4865                 hdw->master_state = st;
4866                 state_updated = !0;
4867                 callback_flag = !0;
4868         }
4869         if (state_updated) {
4870                 /* Trigger anyone waiting on any state changes here. */
4871                 wake_up(&hdw->state_wait_data);
4872         }
4873
4874         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4875                 pvr2_hdw_state_log_state(hdw);
4876         }
4877         pvr2_trace(PVR2_TRACE_STBITS,
4878                    "Drive state check DONE callback=%d",callback_flag);
4879
4880         return callback_flag;
4881 }
4882
4883
4884 /* Cause kernel thread to check / update driver state */
4885 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4886 {
4887         if (hdw->state_stale) return;
4888         hdw->state_stale = !0;
4889         trace_stbit("state_stale",hdw->state_stale);
4890         queue_work(hdw->workqueue,&hdw->workpoll);
4891 }
4892
4893
4894 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4895 {
4896         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4897 }
4898
4899
4900 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4901 {
4902         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4903 }
4904
4905
4906 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4907 {
4908         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4909 }
4910
4911
4912 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4913 {
4914         u32 cval,nval;
4915         int ret;
4916         if (~msk) {
4917                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4918                 if (ret) return ret;
4919                 nval = (cval & ~msk) | (val & msk);
4920                 pvr2_trace(PVR2_TRACE_GPIO,
4921                            "GPIO direction changing 0x%x:0x%x"
4922                            " from 0x%x to 0x%x",
4923                            msk,val,cval,nval);
4924         } else {
4925                 nval = val;
4926                 pvr2_trace(PVR2_TRACE_GPIO,
4927                            "GPIO direction changing to 0x%x",nval);
4928         }
4929         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4930 }
4931
4932
4933 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4934 {
4935         u32 cval,nval;
4936         int ret;
4937         if (~msk) {
4938                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4939                 if (ret) return ret;
4940                 nval = (cval & ~msk) | (val & msk);
4941                 pvr2_trace(PVR2_TRACE_GPIO,
4942                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4943                            msk,val,cval,nval);
4944         } else {
4945                 nval = val;
4946                 pvr2_trace(PVR2_TRACE_GPIO,
4947                            "GPIO output changing to 0x%x",nval);
4948         }
4949         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4950 }
4951
4952
4953 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
4954 {
4955         struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
4956         memset(vtp, 0, sizeof(*vtp));
4957         hdw->tuner_signal_stale = 0;
4958         pvr2_i2c_core_status_poll(hdw);
4959         /* Note: There apparently is no replacement for VIDIOC_CROPCAP
4960            using v4l2-subdev - therefore we can't support that AT ALL right
4961            now.  (Of course, no sub-drivers seem to implement it either.
4962            But now it's a a chicken and egg problem...) */
4963         v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
4964                              &hdw->tuner_signal_info);
4965         pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
4966                    " type=%u strength=%u audio=0x%x cap=0x%x"
4967                    " low=%u hi=%u",
4968                    vtp->type,
4969                    vtp->signal, vtp->rxsubchans, vtp->capability,
4970                    vtp->rangelow, vtp->rangehigh);
4971
4972         /* We have to do this to avoid getting into constant polling if
4973            there's nobody to answer a poll of cropcap info. */
4974         hdw->cropcap_stale = 0;
4975 }
4976
4977
4978 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
4979 {
4980         return hdw->input_avail_mask;
4981 }
4982
4983
4984 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
4985 {
4986         return hdw->input_allowed_mask;
4987 }
4988
4989
4990 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
4991 {
4992         if (hdw->input_val != v) {
4993                 hdw->input_val = v;
4994                 hdw->input_dirty = !0;
4995         }
4996
4997         /* Handle side effects - if we switch to a mode that needs the RF
4998            tuner, then select the right frequency choice as well and mark
4999            it dirty. */
5000         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5001                 hdw->freqSelector = 0;
5002                 hdw->freqDirty = !0;
5003         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5004                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5005                 hdw->freqSelector = 1;
5006                 hdw->freqDirty = !0;
5007         }
5008         return 0;
5009 }
5010
5011
5012 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5013                                unsigned int change_mask,
5014                                unsigned int change_val)
5015 {
5016         int ret = 0;
5017         unsigned int nv,m,idx;
5018         LOCK_TAKE(hdw->big_lock);
5019         do {
5020                 nv = hdw->input_allowed_mask & ~change_mask;
5021                 nv |= (change_val & change_mask);
5022                 nv &= hdw->input_avail_mask;
5023                 if (!nv) {
5024                         /* No legal modes left; return error instead. */
5025                         ret = -EPERM;
5026                         break;
5027                 }
5028                 hdw->input_allowed_mask = nv;
5029                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5030                         /* Current mode is still in the allowed mask, so
5031                            we're done. */
5032                         break;
5033                 }
5034                 /* Select and switch to a mode that is still in the allowed
5035                    mask */
5036                 if (!hdw->input_allowed_mask) {
5037                         /* Nothing legal; give up */
5038                         break;
5039                 }
5040                 m = hdw->input_allowed_mask;
5041                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5042                         if (!((1 << idx) & m)) continue;
5043                         pvr2_hdw_set_input(hdw,idx);
5044                         break;
5045                 }
5046         } while (0);
5047         LOCK_GIVE(hdw->big_lock);
5048         return ret;
5049 }
5050
5051
5052 /* Find I2C address of eeprom */
5053 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5054 {
5055         int result;
5056         LOCK_TAKE(hdw->ctl_lock); do {
5057                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5058                 result = pvr2_send_request(hdw,
5059                                            hdw->cmd_buffer,1,
5060                                            hdw->cmd_buffer,1);
5061                 if (result < 0) break;
5062                 result = hdw->cmd_buffer[0];
5063         } while(0); LOCK_GIVE(hdw->ctl_lock);
5064         return result;
5065 }
5066
5067
5068 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
5069                              struct v4l2_dbg_match *match, u64 reg_id,
5070                              int setFl, u64 *val_ptr)
5071 {
5072 #ifdef CONFIG_VIDEO_ADV_DEBUG
5073         struct pvr2_i2c_client *cp;
5074         struct v4l2_dbg_register req;
5075         int stat = 0;
5076         int okFl = 0;
5077
5078         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5079
5080         req.match = *match;
5081         req.reg = reg_id;
5082         if (setFl) req.val = *val_ptr;
5083         /* It would be nice to know if a sub-device answered the request */
5084         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5085         if (!setFl) *val_ptr = req.val;
5086         if (!okFl) mutex_lock(&hdw->i2c_list_lock); do {
5087                 list_for_each_entry(cp, &hdw->i2c_clients, list) {
5088                         if (!v4l2_chip_match_i2c_client(
5089                                     cp->client,
5090                                     &req.match)) {
5091                                 continue;
5092                         }
5093                         stat = pvr2_i2c_client_cmd(
5094                                 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
5095                                     VIDIOC_DBG_G_REGISTER),&req);
5096                         if (!setFl) *val_ptr = req.val;
5097                         okFl = !0;
5098                         break;
5099                 }
5100         } while (0); mutex_unlock(&hdw->i2c_list_lock);
5101         if (okFl) {
5102                 return stat;
5103         }
5104         return -EINVAL;
5105 #else
5106         return -ENOSYS;
5107 #endif
5108 }
5109
5110
5111 /*
5112   Stuff for Emacs to see, in order to encourage consistent editing style:
5113   *** Local Variables: ***
5114   *** mode: c ***
5115   *** fill-column: 75 ***
5116   *** tab-width: 8 ***
5117   *** c-basic-offset: 8 ***
5118   *** End: ***
5119   */