Pileus Git - ~andy/linux/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/firmware.h>
  25 #include <linux/videodev2.h>
  26 #include <media/v4l2-common.h>
  27 #include "pvrusb2.h"
  28 #include "pvrusb2-std.h"
  29 #include "pvrusb2-util.h"
  30 #include "pvrusb2-hdw.h"
  31 #include "pvrusb2-i2c-core.h"
  32 #include "pvrusb2-tuner.h"
  33 #include "pvrusb2-eeprom.h"
  34 #include "pvrusb2-hdw-internal.h"
  35 #include "pvrusb2-encoder.h"
  36 #include "pvrusb2-debug.h"
  37 #include "pvrusb2-fx2-cmd.h"
  38
  39 #define TV_MIN_FREQ     55250000L
  40 #define TV_MAX_FREQ    850000000L
  41
  42 /* This defines a minimum interval that the decoder must remain quiet
  43    before we are allowed to start it running. */
  44 #define TIME_MSEC_DECODER_WAIT 50
  45
  46 /* This defines a minimum interval that the encoder must remain quiet
  47    before we are allowed to configure it.  I had this originally set to
  48    50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
  49    things work better when it's set to 100msec. */
  50 #define TIME_MSEC_ENCODER_WAIT 100
  51
  52 /* This defines the minimum interval that the encoder must successfully run
  53    before we consider that the encoder has run at least once since its
  54    firmware has been loaded.  This measurement is in important for cases
  55    where we can't do something until we know that the encoder has been run
  56    at least once. */
  57 #define TIME_MSEC_ENCODER_OK 250
  58
  59 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  60 static DEFINE_MUTEX(pvr2_unit_mtx);
  61
  62 static int ctlchg;
  63 static int procreload;
  64 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  65 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  66 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  67 static int init_pause_msec;
  68
  69 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  70 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  71 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  72 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  73 module_param(procreload, int, S_IRUGO|S_IWUSR);
  74 MODULE_PARM_DESC(procreload,
  75                  "Attempt init failure recovery with firmware reload");
  76 module_param_array(tuner,    int, NULL, 0444);
  77 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  78 module_param_array(video_std,    int, NULL, 0444);
  79 MODULE_PARM_DESC(video_std,"specify initial video standard");
  80 module_param_array(tolerance,    int, NULL, 0444);
  81 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  82
  83 /* US Broadcast channel 7 (175.25 MHz) */
  84 static int default_tv_freq    = 175250000L;
  85 /* 104.3 MHz, a usable FM station for my area */
  86 static int default_radio_freq = 104300000L;
  87
  88 module_param_named(tv_freq, default_tv_freq, int, 0444);
  89 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  90 module_param_named(radio_freq, default_radio_freq, int, 0444);
  91 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  92
  93 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  94 #define PVR2_CTL_READ_ENDPOINT   0x81
  95
  96 #define PVR2_GPIO_IN 0x9008
  97 #define PVR2_GPIO_OUT 0x900c
  98 #define PVR2_GPIO_DIR 0x9020
  99
 100 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 101
 102 #define PVR2_FIRMWARE_ENDPOINT   0x02
 103
 104 /* size of a firmware chunk */
 105 #define FIRMWARE_CHUNK_SIZE 0x2000
 106
 107 /* Define the list of additional controls we'll dynamically construct based
 108    on query of the cx2341x module. */
 109 struct pvr2_mpeg_ids {
 110         const char *strid;
 111         int id;
 112 };
 113 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 114         {
 115                 .strid = "audio_layer",
 116                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 117         },{
 118                 .strid = "audio_bitrate",
 119                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 120         },{
 121                 /* Already using audio_mode elsewhere :-( */
 122                 .strid = "mpeg_audio_mode",
 123                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 124         },{
 125                 .strid = "mpeg_audio_mode_extension",
 126                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 127         },{
 128                 .strid = "audio_emphasis",
 129                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 130         },{
 131                 .strid = "audio_crc",
 132                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 133         },{
 134                 .strid = "video_aspect",
 135                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 136         },{
 137                 .strid = "video_b_frames",
 138                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 139         },{
 140                 .strid = "video_gop_size",
 141                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 142         },{
 143                 .strid = "video_gop_closure",
 144                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 145         },{
 146                 .strid = "video_bitrate_mode",
 147                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 148         },{
 149                 .strid = "video_bitrate",
 150                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 151         },{
 152                 .strid = "video_bitrate_peak",
 153                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 154         },{
 155                 .strid = "video_temporal_decimation",
 156                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 157         },{
 158                 .strid = "stream_type",
 159                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 160         },{
 161                 .strid = "video_spatial_filter_mode",
 162                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 163         },{
 164                 .strid = "video_spatial_filter",
 165                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 166         },{
 167                 .strid = "video_luma_spatial_filter_type",
 168                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 169         },{
 170                 .strid = "video_chroma_spatial_filter_type",
 171                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 172         },{
 173                 .strid = "video_temporal_filter_mode",
 174                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 175         },{
 176                 .strid = "video_temporal_filter",
 177                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 178         },{
 179                 .strid = "video_median_filter_type",
 180                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 181         },{
 182                 .strid = "video_luma_median_filter_top",
 183                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 184         },{
 185                 .strid = "video_luma_median_filter_bottom",
 186                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 187         },{
 188                 .strid = "video_chroma_median_filter_top",
 189                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 190         },{
 191                 .strid = "video_chroma_median_filter_bottom",
 192                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 193         }
 194 };
 195 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 196
 197
 198 static const char *control_values_srate[] = {
 199         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 200         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 201         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 202 };
 203
 204
 205
 206 static const char *control_values_input[] = {
 207         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 208         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 209         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 210         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 211         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 212 };
 213
 214
 215 static const char *control_values_audiomode[] = {
 216         [V4L2_TUNER_MODE_MONO]   = "Mono",
 217         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 218         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 219         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 220         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 221 };
 222
 223
 224 static const char *control_values_hsm[] = {
 225         [PVR2_CVAL_HSM_FAIL] = "Fail",
 226         [PVR2_CVAL_HSM_HIGH] = "High",
 227         [PVR2_CVAL_HSM_FULL] = "Full",
 228 };
 229
 230
 231 static const char *pvr2_state_names[] = {
 232         [PVR2_STATE_NONE] =    "none",
 233         [PVR2_STATE_DEAD] =    "dead",
 234         [PVR2_STATE_COLD] =    "cold",
 235         [PVR2_STATE_WARM] =    "warm",
 236         [PVR2_STATE_ERROR] =   "error",
 237         [PVR2_STATE_READY] =   "ready",
 238         [PVR2_STATE_RUN] =     "run",
 239 };
 240
 241
 242 struct pvr2_fx2cmd_descdef {
 243         unsigned char id;
 244         unsigned char *desc;
 245 };
 246
 247 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 248         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 249         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 250         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 251         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 252         {FX2CMD_REG_WRITE, "write encoder register"},
 253         {FX2CMD_REG_READ, "read encoder register"},
 254         {FX2CMD_MEMSEL, "encoder memsel"},
 255         {FX2CMD_I2C_WRITE, "i2c write"},
 256         {FX2CMD_I2C_READ, "i2c read"},
 257         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 258         {FX2CMD_STREAMING_ON, "stream on"},
 259         {FX2CMD_STREAMING_OFF, "stream off"},
 260         {FX2CMD_FWPOST1, "fwpost1"},
 261         {FX2CMD_POWER_OFF, "power off"},
 262         {FX2CMD_POWER_ON, "power on"},
 263         {FX2CMD_DEEP_RESET, "deep reset"},
 264         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 265         {FX2CMD_GET_IR_CODE, "get IR code"},
 266         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 267         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 268         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 269         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 270         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 271         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 272         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 273 };
 274
 275
 276 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 277 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 278 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 279 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 280 static void pvr2_hdw_worker_i2c(struct work_struct *work);
 281 static void pvr2_hdw_worker_poll(struct work_struct *work);
 282 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 283 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 284 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 285 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 286 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 287 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 288 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 289 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 290 static void pvr2_hdw_quiescent_timeout(unsigned long);
 291 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 292 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 293 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 294 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 295                                 unsigned int timeout,int probe_fl,
 296                                 void *write_data,unsigned int write_len,
 297                                 void *read_data,unsigned int read_len);
 298 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 299
 300
 301 static void trace_stbit(const char *name,int val)
 302 {
 303         pvr2_trace(PVR2_TRACE_STBITS,
 304                    "State bit %s <-- %s",
 305                    name,(val ? "true" : "false"));
 306 }
 307
 308 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 309 {
 310         struct pvr2_hdw *hdw = cptr->hdw;
 311         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 312                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 313         } else {
 314                 *vp = 0;
 315         }
 316         return 0;
 317 }
 318
 319 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 320 {
 321         struct pvr2_hdw *hdw = cptr->hdw;
 322         unsigned int slotId = hdw->freqProgSlot;
 323         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 324                 hdw->freqTable[slotId-1] = v;
 325                 /* Handle side effects correctly - if we're tuned to this
 326                    slot, then forgot the slot id relation since the stored
 327                    frequency has been changed. */
 328                 if (hdw->freqSelector) {
 329                         if (hdw->freqSlotRadio == slotId) {
 330                                 hdw->freqSlotRadio = 0;
 331                         }
 332                 } else {
 333                         if (hdw->freqSlotTelevision == slotId) {
 334                                 hdw->freqSlotTelevision = 0;
 335                         }
 336                 }
 337         }
 338         return 0;
 339 }
 340
 341 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 342 {
 343         *vp = cptr->hdw->freqProgSlot;
 344         return 0;
 345 }
 346
 347 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 348 {
 349         struct pvr2_hdw *hdw = cptr->hdw;
 350         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 351                 hdw->freqProgSlot = v;
 352         }
 353         return 0;
 354 }
 355
 356 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 357 {
 358         struct pvr2_hdw *hdw = cptr->hdw;
 359         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 360         return 0;
 361 }
 362
 363 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 364 {
 365         unsigned freq = 0;
 366         struct pvr2_hdw *hdw = cptr->hdw;
 367         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 368         if (slotId > 0) {
 369                 freq = hdw->freqTable[slotId-1];
 370                 if (!freq) return 0;
 371                 pvr2_hdw_set_cur_freq(hdw,freq);
 372         }
 373         if (hdw->freqSelector) {
 374                 hdw->freqSlotRadio = slotId;
 375         } else {
 376                 hdw->freqSlotTelevision = slotId;
 377         }
 378         return 0;
 379 }
 380
 381 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 382 {
 383         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 384         return 0;
 385 }
 386
 387 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 388 {
 389         return cptr->hdw->freqDirty != 0;
 390 }
 391
 392 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 393 {
 394         cptr->hdw->freqDirty = 0;
 395 }
 396
 397 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 398 {
 399         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 400         return 0;
 401 }
 402
 403 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 404 {
 405         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 406         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 407         if (stat != 0) {
 408                 return stat;
 409         }
 410         *left = cap->bounds.left;
 411         return 0;
 412 }
 413
 414 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 415 {
 416         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 417         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 418         if (stat != 0) {
 419                 return stat;
 420         }
 421         *left = cap->bounds.left;
 422         if (cap->bounds.width > cptr->hdw->cropw_val) {
 423                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 424         }
 425         return 0;
 426 }
 427
 428 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 429 {
 430         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 431         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 432         if (stat != 0) {
 433                 return stat;
 434         }
 435         *top = cap->bounds.top;
 436         return 0;
 437 }
 438
 439 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 440 {
 441         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 442         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 443         if (stat != 0) {
 444                 return stat;
 445         }
 446         *top = cap->bounds.top;
 447         if (cap->bounds.height > cptr->hdw->croph_val) {
 448                 *top += cap->bounds.height - cptr->hdw->croph_val;
 449         }
 450         return 0;
 451 }
 452
 453 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
 454 {
 455         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 456         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 457         if (stat != 0) {
 458                 return stat;
 459         }
 460         *val = 0;
 461         if (cap->bounds.width > cptr->hdw->cropl_val) {
 462                 *val = cap->bounds.width - cptr->hdw->cropl_val;
 463         }
 464         return 0;
 465 }
 466
 467 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
 468 {
 469         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 470         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 471         if (stat != 0) {
 472                 return stat;
 473         }
 474         *val = 0;
 475         if (cap->bounds.height > cptr->hdw->cropt_val) {
 476                 *val = cap->bounds.height - cptr->hdw->cropt_val;
 477         }
 478         return 0;
 479 }
 480
 481 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 482 {
 483         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 484         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 485         if (stat != 0) {
 486                 return stat;
 487         }
 488         *val = cap->bounds.left;
 489         return 0;
 490 }
 491
 492 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 493 {
 494         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 495         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 496         if (stat != 0) {
 497                 return stat;
 498         }
 499         *val = cap->bounds.top;
 500         return 0;
 501 }
 502
 503 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 504 {
 505         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 506         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 507         if (stat != 0) {
 508                 return stat;
 509         }
 510         *val = cap->bounds.width;
 511         return 0;
 512 }
 513
 514 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 515 {
 516         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 517         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 518         if (stat != 0) {
 519                 return stat;
 520         }
 521         *val = cap->bounds.height;
 522         return 0;
 523 }
 524
 525 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 526 {
 527         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 528         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 529         if (stat != 0) {
 530                 return stat;
 531         }
 532         *val = cap->defrect.left;
 533         return 0;
 534 }
 535
 536 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 537 {
 538         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 539         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 540         if (stat != 0) {
 541                 return stat;
 542         }
 543         *val = cap->defrect.top;
 544         return 0;
 545 }
 546
 547 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 548 {
 549         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 550         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 551         if (stat != 0) {
 552                 return stat;
 553         }
 554         *val = cap->defrect.width;
 555         return 0;
 556 }
 557
 558 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 559 {
 560         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 561         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 562         if (stat != 0) {
 563                 return stat;
 564         }
 565         *val = cap->defrect.height;
 566         return 0;
 567 }
 568
 569 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 570 {
 571         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 572         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 573         if (stat != 0) {
 574                 return stat;
 575         }
 576         *val = cap->pixelaspect.numerator;
 577         return 0;
 578 }
 579
 580 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 581 {
 582         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 583         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 584         if (stat != 0) {
 585                 return stat;
 586         }
 587         *val = cap->pixelaspect.denominator;
 588         return 0;
 589 }
 590
 591 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 592 {
 593         /* Actual maximum depends on the video standard in effect. */
 594         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 595                 *vp = 480;
 596         } else {
 597                 *vp = 576;
 598         }
 599         return 0;
 600 }
 601
 602 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 603 {
 604         /* Actual minimum depends on device digitizer type. */
 605         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 606                 *vp = 75;
 607         } else {
 608                 *vp = 17;
 609         }
 610         return 0;
 611 }
 612
 613 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 614 {
 615         *vp = cptr->hdw->input_val;
 616         return 0;
 617 }
 618
 619 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 620 {
 621         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 622 }
 623
 624 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 625 {
 626         return pvr2_hdw_set_input(cptr->hdw,v);
 627 }
 628
 629 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 630 {
 631         return cptr->hdw->input_dirty != 0;
 632 }
 633
 634 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 635 {
 636         cptr->hdw->input_dirty = 0;
 637 }
 638
 639
 640 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 641 {
 642         unsigned long fv;
 643         struct pvr2_hdw *hdw = cptr->hdw;
 644         if (hdw->tuner_signal_stale) {
 645                 pvr2_i2c_core_status_poll(hdw);
 646         }
 647         fv = hdw->tuner_signal_info.rangehigh;
 648         if (!fv) {
 649                 /* Safety fallback */
 650                 *vp = TV_MAX_FREQ;
 651                 return 0;
 652         }
 653         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 654                 fv = (fv * 125) / 2;
 655         } else {
 656                 fv = fv * 62500;
 657         }
 658         *vp = fv;
 659         return 0;
 660 }
 661
 662 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 663 {
 664         unsigned long fv;
 665         struct pvr2_hdw *hdw = cptr->hdw;
 666         if (hdw->tuner_signal_stale) {
 667                 pvr2_i2c_core_status_poll(hdw);
 668         }
 669         fv = hdw->tuner_signal_info.rangelow;
 670         if (!fv) {
 671                 /* Safety fallback */
 672                 *vp = TV_MIN_FREQ;
 673                 return 0;
 674         }
 675         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 676                 fv = (fv * 125) / 2;
 677         } else {
 678                 fv = fv * 62500;
 679         }
 680         *vp = fv;
 681         return 0;
 682 }
 683
 684 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 685 {
 686         return cptr->hdw->enc_stale != 0;
 687 }
 688
 689 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 690 {
 691         cptr->hdw->enc_stale = 0;
 692         cptr->hdw->enc_unsafe_stale = 0;
 693 }
 694
 695 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 696 {
 697         int ret;
 698         struct v4l2_ext_controls cs;
 699         struct v4l2_ext_control c1;
 700         memset(&cs,0,sizeof(cs));
 701         memset(&c1,0,sizeof(c1));
 702         cs.controls = &c1;
 703         cs.count = 1;
 704         c1.id = cptr->info->v4l_id;
 705         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 706                                 VIDIOC_G_EXT_CTRLS);
 707         if (ret) return ret;
 708         *vp = c1.value;
 709         return 0;
 710 }
 711
 712 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 713 {
 714         int ret;
 715         struct pvr2_hdw *hdw = cptr->hdw;
 716         struct v4l2_ext_controls cs;
 717         struct v4l2_ext_control c1;
 718         memset(&cs,0,sizeof(cs));
 719         memset(&c1,0,sizeof(c1));
 720         cs.controls = &c1;
 721         cs.count = 1;
 722         c1.id = cptr->info->v4l_id;
 723         c1.value = v;
 724         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 725                                 hdw->state_encoder_run, &cs,
 726                                 VIDIOC_S_EXT_CTRLS);
 727         if (ret == -EBUSY) {
 728                 /* Oops.  cx2341x is telling us it's not safe to change
 729                    this control while we're capturing.  Make a note of this
 730                    fact so that the pipeline will be stopped the next time
 731                    controls are committed.  Then go on ahead and store this
 732                    change anyway. */
 733                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 734                                         0, &cs,
 735                                         VIDIOC_S_EXT_CTRLS);
 736                 if (!ret) hdw->enc_unsafe_stale = !0;
 737         }
 738         if (ret) return ret;
 739         hdw->enc_stale = !0;
 740         return 0;
 741 }
 742
 743 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 744 {
 745         struct v4l2_queryctrl qctrl;
 746         struct pvr2_ctl_info *info;
 747         qctrl.id = cptr->info->v4l_id;
 748         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 749         /* Strip out the const so we can adjust a function pointer.  It's
 750            OK to do this here because we know this is a dynamically created
 751            control, so the underlying storage for the info pointer is (a)
 752            private to us, and (b) not in read-only storage.  Either we do
 753            this or we significantly complicate the underlying control
 754            implementation. */
 755         info = (struct pvr2_ctl_info *)(cptr->info);
 756         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 757                 if (info->set_value) {
 758                         info->set_value = NULL;
 759                 }
 760         } else {
 761                 if (!(info->set_value)) {
 762                         info->set_value = ctrl_cx2341x_set;
 763                 }
 764         }
 765         return qctrl.flags;
 766 }
 767
 768 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 769 {
 770         *vp = cptr->hdw->state_pipeline_req;
 771         return 0;
 772 }
 773
 774 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 775 {
 776         *vp = cptr->hdw->master_state;
 777         return 0;
 778 }
 779
 780 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 781 {
 782         int result = pvr2_hdw_is_hsm(cptr->hdw);
 783         *vp = PVR2_CVAL_HSM_FULL;
 784         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 785         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 786         return 0;
 787 }
 788
 789 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 790 {
 791         *vp = cptr->hdw->std_mask_avail;
 792         return 0;
 793 }
 794
 795 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 796 {
 797         struct pvr2_hdw *hdw = cptr->hdw;
 798         v4l2_std_id ns;
 799         ns = hdw->std_mask_avail;
 800         ns = (ns & ~m) | (v & m);
 801         if (ns == hdw->std_mask_avail) return 0;
 802         hdw->std_mask_avail = ns;
 803         pvr2_hdw_internal_set_std_avail(hdw);
 804         pvr2_hdw_internal_find_stdenum(hdw);
 805         return 0;
 806 }
 807
 808 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 809                                char *bufPtr,unsigned int bufSize,
 810                                unsigned int *len)
 811 {
 812         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 813         return 0;
 814 }
 815
 816 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 817                                const char *bufPtr,unsigned int bufSize,
 818                                int *mskp,int *valp)
 819 {
 820         int ret;
 821         v4l2_std_id id;
 822         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 823         if (ret < 0) return ret;
 824         if (mskp) *mskp = id;
 825         if (valp) *valp = id;
 826         return 0;
 827 }
 828
 829 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 830 {
 831         *vp = cptr->hdw->std_mask_cur;
 832         return 0;
 833 }
 834
 835 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 836 {
 837         struct pvr2_hdw *hdw = cptr->hdw;
 838         v4l2_std_id ns;
 839         ns = hdw->std_mask_cur;
 840         ns = (ns & ~m) | (v & m);
 841         if (ns == hdw->std_mask_cur) return 0;
 842         hdw->std_mask_cur = ns;
 843         hdw->std_dirty = !0;
 844         pvr2_hdw_internal_find_stdenum(hdw);
 845         return 0;
 846 }
 847
 848 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 849 {
 850         return cptr->hdw->std_dirty != 0;
 851 }
 852
 853 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 854 {
 855         cptr->hdw->std_dirty = 0;
 856 }
 857
 858 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 859 {
 860         struct pvr2_hdw *hdw = cptr->hdw;
 861         pvr2_i2c_core_status_poll(hdw);
 862         *vp = hdw->tuner_signal_info.signal;
 863         return 0;
 864 }
 865
 866 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 867 {
 868         int val = 0;
 869         unsigned int subchan;
 870         struct pvr2_hdw *hdw = cptr->hdw;
 871         pvr2_i2c_core_status_poll(hdw);
 872         subchan = hdw->tuner_signal_info.rxsubchans;
 873         if (subchan & V4L2_TUNER_SUB_MONO) {
 874                 val |= (1 << V4L2_TUNER_MODE_MONO);
 875         }
 876         if (subchan & V4L2_TUNER_SUB_STEREO) {
 877                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 878         }
 879         if (subchan & V4L2_TUNER_SUB_LANG1) {
 880                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 881         }
 882         if (subchan & V4L2_TUNER_SUB_LANG2) {
 883                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 884         }
 885         *vp = val;
 886         return 0;
 887 }
 888
 889
 890 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 891 {
 892         struct pvr2_hdw *hdw = cptr->hdw;
 893         if (v < 0) return -EINVAL;
 894         if (v > hdw->std_enum_cnt) return -EINVAL;
 895         hdw->std_enum_cur = v;
 896         if (!v) return 0;
 897         v--;
 898         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 899         hdw->std_mask_cur = hdw->std_defs[v].id;
 900         hdw->std_dirty = !0;
 901         return 0;
 902 }
 903
 904
 905 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 906 {
 907         *vp = cptr->hdw->std_enum_cur;
 908         return 0;
 909 }
 910
 911
 912 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 913 {
 914         return cptr->hdw->std_dirty != 0;
 915 }
 916
 917
 918 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 919 {
 920         cptr->hdw->std_dirty = 0;
 921 }
 922
 923
 924 #define DEFINT(vmin,vmax) \
 925         .type = pvr2_ctl_int, \
 926         .def.type_int.min_value = vmin, \
 927         .def.type_int.max_value = vmax
 928
 929 #define DEFENUM(tab) \
 930         .type = pvr2_ctl_enum, \
 931         .def.type_enum.count = ARRAY_SIZE(tab), \
 932         .def.type_enum.value_names = tab
 933
 934 #define DEFBOOL \
 935         .type = pvr2_ctl_bool
 936
 937 #define DEFMASK(msk,tab) \
 938         .type = pvr2_ctl_bitmask, \
 939         .def.type_bitmask.valid_bits = msk, \
 940         .def.type_bitmask.bit_names = tab
 941
 942 #define DEFREF(vname) \
 943         .set_value = ctrl_set_##vname, \
 944         .get_value = ctrl_get_##vname, \
 945         .is_dirty = ctrl_isdirty_##vname, \
 946         .clear_dirty = ctrl_cleardirty_##vname
 947
 948
 949 #define VCREATE_FUNCS(vname) \
 950 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 951 {*vp = cptr->hdw->vname##_val; return 0;} \
 952 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 953 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 954 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 955 {return cptr->hdw->vname##_dirty != 0;} \
 956 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 957 {cptr->hdw->vname##_dirty = 0;}
 958
 959 VCREATE_FUNCS(brightness)
 960 VCREATE_FUNCS(contrast)
 961 VCREATE_FUNCS(saturation)
 962 VCREATE_FUNCS(hue)
 963 VCREATE_FUNCS(volume)
 964 VCREATE_FUNCS(balance)
 965 VCREATE_FUNCS(bass)
 966 VCREATE_FUNCS(treble)
 967 VCREATE_FUNCS(mute)
 968 VCREATE_FUNCS(cropl)
 969 VCREATE_FUNCS(cropt)
 970 VCREATE_FUNCS(cropw)
 971 VCREATE_FUNCS(croph)
 972 VCREATE_FUNCS(audiomode)
 973 VCREATE_FUNCS(res_hor)
 974 VCREATE_FUNCS(res_ver)
 975 VCREATE_FUNCS(srate)
 976
 977 /* Table definition of all controls which can be manipulated */
 978 static const struct pvr2_ctl_info control_defs[] = {
 979         {
 980                 .v4l_id = V4L2_CID_BRIGHTNESS,
 981                 .desc = "Brightness",
 982                 .name = "brightness",
 983                 .default_value = 128,
 984                 DEFREF(brightness),
 985                 DEFINT(0,255),
 986         },{
 987                 .v4l_id = V4L2_CID_CONTRAST,
 988                 .desc = "Contrast",
 989                 .name = "contrast",
 990                 .default_value = 68,
 991                 DEFREF(contrast),
 992                 DEFINT(0,127),
 993         },{
 994                 .v4l_id = V4L2_CID_SATURATION,
 995                 .desc = "Saturation",
 996                 .name = "saturation",
 997                 .default_value = 64,
 998                 DEFREF(saturation),
 999                 DEFINT(0,127),
1000         },{
1001                 .v4l_id = V4L2_CID_HUE,
1002                 .desc = "Hue",
1003                 .name = "hue",
1004                 .default_value = 0,
1005                 DEFREF(hue),
1006                 DEFINT(-128,127),
1007         },{
1008                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1009                 .desc = "Volume",
1010                 .name = "volume",
1011                 .default_value = 62000,
1012                 DEFREF(volume),
1013                 DEFINT(0,65535),
1014         },{
1015                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1016                 .desc = "Balance",
1017                 .name = "balance",
1018                 .default_value = 0,
1019                 DEFREF(balance),
1020                 DEFINT(-32768,32767),
1021         },{
1022                 .v4l_id = V4L2_CID_AUDIO_BASS,
1023                 .desc = "Bass",
1024                 .name = "bass",
1025                 .default_value = 0,
1026                 DEFREF(bass),
1027                 DEFINT(-32768,32767),
1028         },{
1029                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1030                 .desc = "Treble",
1031                 .name = "treble",
1032                 .default_value = 0,
1033                 DEFREF(treble),
1034                 DEFINT(-32768,32767),
1035         },{
1036                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1037                 .desc = "Mute",
1038                 .name = "mute",
1039                 .default_value = 0,
1040                 DEFREF(mute),
1041                 DEFBOOL,
1042         }, {
1043                 .desc = "Capture crop left margin",
1044                 .name = "crop_left",
1045                 .internal_id = PVR2_CID_CROPL,
1046                 .default_value = 0,
1047                 DEFREF(cropl),
1048                 DEFINT(-129, 340),
1049                 .get_min_value = ctrl_cropl_min_get,
1050                 .get_max_value = ctrl_cropl_max_get,
1051                 .get_def_value = ctrl_get_cropcapdl,
1052         }, {
1053                 .desc = "Capture crop top margin",
1054                 .name = "crop_top",
1055                 .internal_id = PVR2_CID_CROPT,
1056                 .default_value = 0,
1057                 DEFREF(cropt),
1058                 DEFINT(-35, 544),
1059                 .get_min_value = ctrl_cropt_min_get,
1060                 .get_max_value = ctrl_cropt_max_get,
1061                 .get_def_value = ctrl_get_cropcapdt,
1062         }, {
1063                 .desc = "Capture crop width",
1064                 .name = "crop_width",
1065                 .internal_id = PVR2_CID_CROPW,
1066                 .default_value = 720,
1067                 DEFREF(cropw),
1068                 .get_max_value = ctrl_cropw_max_get,
1069                 .get_def_value = ctrl_get_cropcapdw,
1070         }, {
1071                 .desc = "Capture crop height",
1072                 .name = "crop_height",
1073                 .internal_id = PVR2_CID_CROPH,
1074                 .default_value = 480,
1075                 DEFREF(croph),
1076                 .get_max_value = ctrl_croph_max_get,
1077                 .get_def_value = ctrl_get_cropcapdh,
1078         }, {
1079                 .desc = "Capture capability pixel aspect numerator",
1080                 .name = "cropcap_pixel_numerator",
1081                 .internal_id = PVR2_CID_CROPCAPPAN,
1082                 .get_value = ctrl_get_cropcappan,
1083         }, {
1084                 .desc = "Capture capability pixel aspect denominator",
1085                 .name = "cropcap_pixel_denominator",
1086                 .internal_id = PVR2_CID_CROPCAPPAD,
1087                 .get_value = ctrl_get_cropcappad,
1088         }, {
1089                 .desc = "Capture capability bounds top",
1090                 .name = "cropcap_bounds_top",
1091                 .internal_id = PVR2_CID_CROPCAPBT,
1092                 .get_value = ctrl_get_cropcapbt,
1093         }, {
1094                 .desc = "Capture capability bounds left",
1095                 .name = "cropcap_bounds_left",
1096                 .internal_id = PVR2_CID_CROPCAPBL,
1097                 .get_value = ctrl_get_cropcapbl,
1098         }, {
1099                 .desc = "Capture capability bounds width",
1100                 .name = "cropcap_bounds_width",
1101                 .internal_id = PVR2_CID_CROPCAPBW,
1102                 .get_value = ctrl_get_cropcapbw,
1103         }, {
1104                 .desc = "Capture capability bounds height",
1105                 .name = "cropcap_bounds_height",
1106                 .internal_id = PVR2_CID_CROPCAPBH,
1107                 .get_value = ctrl_get_cropcapbh,
1108         },{
1109                 .desc = "Video Source",
1110                 .name = "input",
1111                 .internal_id = PVR2_CID_INPUT,
1112                 .default_value = PVR2_CVAL_INPUT_TV,
1113                 .check_value = ctrl_check_input,
1114                 DEFREF(input),
1115                 DEFENUM(control_values_input),
1116         },{
1117                 .desc = "Audio Mode",
1118                 .name = "audio_mode",
1119                 .internal_id = PVR2_CID_AUDIOMODE,
1120                 .default_value = V4L2_TUNER_MODE_STEREO,
1121                 DEFREF(audiomode),
1122                 DEFENUM(control_values_audiomode),
1123         },{
1124                 .desc = "Horizontal capture resolution",
1125                 .name = "resolution_hor",
1126                 .internal_id = PVR2_CID_HRES,
1127                 .default_value = 720,
1128                 DEFREF(res_hor),
1129                 DEFINT(19,720),
1130         },{
1131                 .desc = "Vertical capture resolution",
1132                 .name = "resolution_ver",
1133                 .internal_id = PVR2_CID_VRES,
1134                 .default_value = 480,
1135                 DEFREF(res_ver),
1136                 DEFINT(17,576),
1137                 /* Hook in check for video standard and adjust maximum
1138                    depending on the standard. */
1139                 .get_max_value = ctrl_vres_max_get,
1140                 .get_min_value = ctrl_vres_min_get,
1141         },{
1142                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1143                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1144                 .desc = "Audio Sampling Frequency",
1145                 .name = "srate",
1146                 DEFREF(srate),
1147                 DEFENUM(control_values_srate),
1148         },{
1149                 .desc = "Tuner Frequency (Hz)",
1150                 .name = "frequency",
1151                 .internal_id = PVR2_CID_FREQUENCY,
1152                 .default_value = 0,
1153                 .set_value = ctrl_freq_set,
1154                 .get_value = ctrl_freq_get,
1155                 .is_dirty = ctrl_freq_is_dirty,
1156                 .clear_dirty = ctrl_freq_clear_dirty,
1157                 DEFINT(0,0),
1158                 /* Hook in check for input value (tv/radio) and adjust
1159                    max/min values accordingly */
1160                 .get_max_value = ctrl_freq_max_get,
1161                 .get_min_value = ctrl_freq_min_get,
1162         },{
1163                 .desc = "Channel",
1164                 .name = "channel",
1165                 .set_value = ctrl_channel_set,
1166                 .get_value = ctrl_channel_get,
1167                 DEFINT(0,FREQTABLE_SIZE),
1168         },{
1169                 .desc = "Channel Program Frequency",
1170                 .name = "freq_table_value",
1171                 .set_value = ctrl_channelfreq_set,
1172                 .get_value = ctrl_channelfreq_get,
1173                 DEFINT(0,0),
1174                 /* Hook in check for input value (tv/radio) and adjust
1175                    max/min values accordingly */
1176                 .get_max_value = ctrl_freq_max_get,
1177                 .get_min_value = ctrl_freq_min_get,
1178         },{
1179                 .desc = "Channel Program ID",
1180                 .name = "freq_table_channel",
1181                 .set_value = ctrl_channelprog_set,
1182                 .get_value = ctrl_channelprog_get,
1183                 DEFINT(0,FREQTABLE_SIZE),
1184         },{
1185                 .desc = "Streaming Enabled",
1186                 .name = "streaming_enabled",
1187                 .get_value = ctrl_streamingenabled_get,
1188                 DEFBOOL,
1189         },{
1190                 .desc = "USB Speed",
1191                 .name = "usb_speed",
1192                 .get_value = ctrl_hsm_get,
1193                 DEFENUM(control_values_hsm),
1194         },{
1195                 .desc = "Master State",
1196                 .name = "master_state",
1197                 .get_value = ctrl_masterstate_get,
1198                 DEFENUM(pvr2_state_names),
1199         },{
1200                 .desc = "Signal Present",
1201                 .name = "signal_present",
1202                 .get_value = ctrl_signal_get,
1203                 DEFINT(0,65535),
1204         },{
1205                 .desc = "Audio Modes Present",
1206                 .name = "audio_modes_present",
1207                 .get_value = ctrl_audio_modes_present_get,
1208                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1209                    v4l.  Nothing outside of this module cares about this,
1210                    but I reuse it in order to also reuse the
1211                    control_values_audiomode string table. */
1212                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1213                          (1 << V4L2_TUNER_MODE_STEREO)|
1214                          (1 << V4L2_TUNER_MODE_LANG1)|
1215                          (1 << V4L2_TUNER_MODE_LANG2)),
1216                         control_values_audiomode),
1217         },{
1218                 .desc = "Video Standards Available Mask",
1219                 .name = "video_standard_mask_available",
1220                 .internal_id = PVR2_CID_STDAVAIL,
1221                 .skip_init = !0,
1222                 .get_value = ctrl_stdavail_get,
1223                 .set_value = ctrl_stdavail_set,
1224                 .val_to_sym = ctrl_std_val_to_sym,
1225                 .sym_to_val = ctrl_std_sym_to_val,
1226                 .type = pvr2_ctl_bitmask,
1227         },{
1228                 .desc = "Video Standards In Use Mask",
1229                 .name = "video_standard_mask_active",
1230                 .internal_id = PVR2_CID_STDCUR,
1231                 .skip_init = !0,
1232                 .get_value = ctrl_stdcur_get,
1233                 .set_value = ctrl_stdcur_set,
1234                 .is_dirty = ctrl_stdcur_is_dirty,
1235                 .clear_dirty = ctrl_stdcur_clear_dirty,
1236                 .val_to_sym = ctrl_std_val_to_sym,
1237                 .sym_to_val = ctrl_std_sym_to_val,
1238                 .type = pvr2_ctl_bitmask,
1239         },{
1240                 .desc = "Video Standard Name",
1241                 .name = "video_standard",
1242                 .internal_id = PVR2_CID_STDENUM,
1243                 .skip_init = !0,
1244                 .get_value = ctrl_stdenumcur_get,
1245                 .set_value = ctrl_stdenumcur_set,
1246                 .is_dirty = ctrl_stdenumcur_is_dirty,
1247                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1248                 .type = pvr2_ctl_enum,
1249         }
1250 };
1251
1252 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1253
1254
1255 const char *pvr2_config_get_name(enum pvr2_config cfg)
1256 {
1257         switch (cfg) {
1258         case pvr2_config_empty: return "empty";
1259         case pvr2_config_mpeg: return "mpeg";
1260         case pvr2_config_vbi: return "vbi";
1261         case pvr2_config_pcm: return "pcm";
1262         case pvr2_config_rawvideo: return "raw video";
1263         }
1264         return "<unknown>";
1265 }
1266
1267
1268 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1269 {
1270         return hdw->usb_dev;
1271 }
1272
1273
1274 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1275 {
1276         return hdw->serial_number;
1277 }
1278
1279
1280 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1281 {
1282         return hdw->bus_info;
1283 }
1284
1285
1286 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1287 {
1288         return hdw->identifier;
1289 }
1290
1291
1292 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1293 {
1294         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1295 }
1296
1297 /* Set the currently tuned frequency and account for all possible
1298    driver-core side effects of this action. */
1299 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1300 {
1301         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1302                 if (hdw->freqSelector) {
1303                         /* Swing over to radio frequency selection */
1304                         hdw->freqSelector = 0;
1305                         hdw->freqDirty = !0;
1306                 }
1307                 if (hdw->freqValRadio != val) {
1308                         hdw->freqValRadio = val;
1309                         hdw->freqSlotRadio = 0;
1310                         hdw->freqDirty = !0;
1311                 }
1312         } else {
1313                 if (!(hdw->freqSelector)) {
1314                         /* Swing over to television frequency selection */
1315                         hdw->freqSelector = 1;
1316                         hdw->freqDirty = !0;
1317                 }
1318                 if (hdw->freqValTelevision != val) {
1319                         hdw->freqValTelevision = val;
1320                         hdw->freqSlotTelevision = 0;
1321                         hdw->freqDirty = !0;
1322                 }
1323         }
1324 }
1325
1326 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1327 {
1328         return hdw->unit_number;
1329 }
1330
1331
1332 /* Attempt to locate one of the given set of files.  Messages are logged
1333    appropriate to what has been found.  The return value will be 0 or
1334    greater on success (it will be the index of the file name found) and
1335    fw_entry will be filled in.  Otherwise a negative error is returned on
1336    failure.  If the return value is -ENOENT then no viable firmware file
1337    could be located. */
1338 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1339                                 const struct firmware **fw_entry,
1340                                 const char *fwtypename,
1341                                 unsigned int fwcount,
1342                                 const char *fwnames[])
1343 {
1344         unsigned int idx;
1345         int ret = -EINVAL;
1346         for (idx = 0; idx < fwcount; idx++) {
1347                 ret = request_firmware(fw_entry,
1348                                        fwnames[idx],
1349                                        &hdw->usb_dev->dev);
1350                 if (!ret) {
1351                         trace_firmware("Located %s firmware: %s;"
1352                                        " uploading...",
1353                                        fwtypename,
1354                                        fwnames[idx]);
1355                         return idx;
1356                 }
1357                 if (ret == -ENOENT) continue;
1358                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1359                            "request_firmware fatal error with code=%d",ret);
1360                 return ret;
1361         }
1362         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1363                    "***WARNING***"
1364                    " Device %s firmware"
1365                    " seems to be missing.",
1366                    fwtypename);
1367         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1368                    "Did you install the pvrusb2 firmware files"
1369                    " in their proper location?");
1370         if (fwcount == 1) {
1371                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1372                            "request_firmware unable to locate %s file %s",
1373                            fwtypename,fwnames[0]);
1374         } else {
1375                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1376                            "request_firmware unable to locate"
1377                            " one of the following %s files:",
1378                            fwtypename);
1379                 for (idx = 0; idx < fwcount; idx++) {
1380                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1381                                    "request_firmware: Failed to find %s",
1382                                    fwnames[idx]);
1383                 }
1384         }
1385         return ret;
1386 }
1387
1388
1389 /*
1390  * pvr2_upload_firmware1().
1391  *
1392  * Send the 8051 firmware to the device.  After the upload, arrange for
1393  * device to re-enumerate.
1394  *
1395  * NOTE : the pointer to the firmware data given by request_firmware()
1396  * is not suitable for an usb transaction.
1397  *
1398  */
1399 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1400 {
1401         const struct firmware *fw_entry = NULL;
1402         void  *fw_ptr;
1403         unsigned int pipe;
1404         int ret;
1405         u16 address;
1406
1407         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1408                 hdw->fw1_state = FW1_STATE_OK;
1409                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1410                            "Connected device type defines"
1411                            " no firmware to upload; ignoring firmware");
1412                 return -ENOTTY;
1413         }
1414
1415         hdw->fw1_state = FW1_STATE_FAILED; // default result
1416
1417         trace_firmware("pvr2_upload_firmware1");
1418
1419         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1420                                    hdw->hdw_desc->fx2_firmware.cnt,
1421                                    hdw->hdw_desc->fx2_firmware.lst);
1422         if (ret < 0) {
1423                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1424                 return ret;
1425         }
1426
1427         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1428         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1429
1430         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1431
1432         if (fw_entry->size != 0x2000){
1433                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1434                 release_firmware(fw_entry);
1435                 return -ENOMEM;
1436         }
1437
1438         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1439         if (fw_ptr == NULL){
1440                 release_firmware(fw_entry);
1441                 return -ENOMEM;
1442         }
1443
1444         /* We have to hold the CPU during firmware upload. */
1445         pvr2_hdw_cpureset_assert(hdw,1);
1446
1447         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1448            chunk. */
1449
1450         ret = 0;
1451         for(address = 0; address < fw_entry->size; address += 0x800) {
1452                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1453                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1454                                        0, fw_ptr, 0x800, HZ);
1455         }
1456
1457         trace_firmware("Upload done, releasing device's CPU");
1458
1459         /* Now release the CPU.  It will disconnect and reconnect later. */
1460         pvr2_hdw_cpureset_assert(hdw,0);
1461
1462         kfree(fw_ptr);
1463         release_firmware(fw_entry);
1464
1465         trace_firmware("Upload done (%d bytes sent)",ret);
1466
1467         /* We should have written 8192 bytes */
1468         if (ret == 8192) {
1469                 hdw->fw1_state = FW1_STATE_RELOAD;
1470                 return 0;
1471         }
1472
1473         return -EIO;
1474 }
1475
1476
1477 /*
1478  * pvr2_upload_firmware2()
1479  *
1480  * This uploads encoder firmware on endpoint 2.
1481  *
1482  */
1483
1484 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1485 {
1486         const struct firmware *fw_entry = NULL;
1487         void  *fw_ptr;
1488         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1489         int actual_length;
1490         int ret = 0;
1491         int fwidx;
1492         static const char *fw_files[] = {
1493                 CX2341X_FIRM_ENC_FILENAME,
1494         };
1495
1496         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1497                 return 0;
1498         }
1499
1500         trace_firmware("pvr2_upload_firmware2");
1501
1502         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1503                                    ARRAY_SIZE(fw_files), fw_files);
1504         if (ret < 0) return ret;
1505         fwidx = ret;
1506         ret = 0;
1507         /* Since we're about to completely reinitialize the encoder,
1508            invalidate our cached copy of its configuration state.  Next
1509            time we configure the encoder, then we'll fully configure it. */
1510         hdw->enc_cur_valid = 0;
1511
1512         /* Encoder is about to be reset so note that as far as we're
1513            concerned now, the encoder has never been run. */
1514         del_timer_sync(&hdw->encoder_run_timer);
1515         if (hdw->state_encoder_runok) {
1516                 hdw->state_encoder_runok = 0;
1517                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1518         }
1519
1520         /* First prepare firmware loading */
1521         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1522         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1523         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1524         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1525         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1526         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1527         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1528         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1529         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1530         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1531         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1532         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1533         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1534         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1535         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1536         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1537         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1538         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1539
1540         if (ret) {
1541                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1542                            "firmware2 upload prep failed, ret=%d",ret);
1543                 release_firmware(fw_entry);
1544                 goto done;
1545         }
1546
1547         /* Now send firmware */
1548
1549         fw_len = fw_entry->size;
1550
1551         if (fw_len % sizeof(u32)) {
1552                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1553                            "size of %s firmware"
1554                            " must be a multiple of %zu bytes",
1555                            fw_files[fwidx],sizeof(u32));
1556                 release_firmware(fw_entry);
1557                 ret = -EINVAL;
1558                 goto done;
1559         }
1560
1561         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1562         if (fw_ptr == NULL){
1563                 release_firmware(fw_entry);
1564                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1565                            "failed to allocate memory for firmware2 upload");
1566                 ret = -ENOMEM;
1567                 goto done;
1568         }
1569
1570         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1571
1572         fw_done = 0;
1573         for (fw_done = 0; fw_done < fw_len;) {
1574                 bcnt = fw_len - fw_done;
1575                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1576                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1577                 /* Usbsnoop log shows that we must swap bytes... */
1578                 /* Some background info: The data being swapped here is a
1579                    firmware image destined for the mpeg encoder chip that
1580                    lives at the other end of a USB endpoint.  The encoder
1581                    chip always talks in 32 bit chunks and its storage is
1582                    organized into 32 bit words.  However from the file
1583                    system to the encoder chip everything is purely a byte
1584                    stream.  The firmware file's contents are always 32 bit
1585                    swapped from what the encoder expects.  Thus the need
1586                    always exists to swap the bytes regardless of the endian
1587                    type of the host processor and therefore swab32() makes
1588                    the most sense. */
1589                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1590                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1591
1592                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1593                                     &actual_length, HZ);
1594                 ret |= (actual_length != bcnt);
1595                 if (ret) break;
1596                 fw_done += bcnt;
1597         }
1598
1599         trace_firmware("upload of %s : %i / %i ",
1600                        fw_files[fwidx],fw_done,fw_len);
1601
1602         kfree(fw_ptr);
1603         release_firmware(fw_entry);
1604
1605         if (ret) {
1606                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1607                            "firmware2 upload transfer failure");
1608                 goto done;
1609         }
1610
1611         /* Finish upload */
1612
1613         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1614         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1615         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1616
1617         if (ret) {
1618                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1619                            "firmware2 upload post-proc failure");
1620         }
1621
1622  done:
1623         if (hdw->hdw_desc->signal_routing_scheme ==
1624             PVR2_ROUTING_SCHEME_GOTVIEW) {
1625                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1626                    hardware. */
1627                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1628         }
1629         return ret;
1630 }
1631
1632
1633 static const char *pvr2_get_state_name(unsigned int st)
1634 {
1635         if (st < ARRAY_SIZE(pvr2_state_names)) {
1636                 return pvr2_state_names[st];
1637         }
1638         return "???";
1639 }
1640
1641 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1642 {
1643         if (!hdw->decoder_ctrl) {
1644                 if (!hdw->flag_decoder_missed) {
1645                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1646                                    "WARNING: No decoder present");
1647                         hdw->flag_decoder_missed = !0;
1648                         trace_stbit("flag_decoder_missed",
1649                                     hdw->flag_decoder_missed);
1650                 }
1651                 return -EIO;
1652         }
1653         hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1654         return 0;
1655 }
1656
1657
1658 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1659 {
1660         if (hdw->decoder_ctrl == ptr) return;
1661         hdw->decoder_ctrl = ptr;
1662         if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1663                 hdw->flag_decoder_missed = 0;
1664                 trace_stbit("flag_decoder_missed",
1665                             hdw->flag_decoder_missed);
1666                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1667                            "Decoder has appeared");
1668                 pvr2_hdw_state_sched(hdw);
1669         }
1670 }
1671
1672
1673 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1674 {
1675         return hdw->master_state;
1676 }
1677
1678
1679 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1680 {
1681         if (!hdw->flag_tripped) return 0;
1682         hdw->flag_tripped = 0;
1683         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1684                    "Clearing driver error statuss");
1685         return !0;
1686 }
1687
1688
1689 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1690 {
1691         int fl;
1692         LOCK_TAKE(hdw->big_lock); do {
1693                 fl = pvr2_hdw_untrip_unlocked(hdw);
1694         } while (0); LOCK_GIVE(hdw->big_lock);
1695         if (fl) pvr2_hdw_state_sched(hdw);
1696         return 0;
1697 }
1698
1699
1700
1701
1702 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1703 {
1704         return hdw->state_pipeline_req != 0;
1705 }
1706
1707
1708 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1709 {
1710         int ret,st;
1711         LOCK_TAKE(hdw->big_lock); do {
1712                 pvr2_hdw_untrip_unlocked(hdw);
1713                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1714                         hdw->state_pipeline_req = enable_flag != 0;
1715                         pvr2_trace(PVR2_TRACE_START_STOP,
1716                                    "/*--TRACE_STREAM--*/ %s",
1717                                    enable_flag ? "enable" : "disable");
1718                 }
1719                 pvr2_hdw_state_sched(hdw);
1720         } while (0); LOCK_GIVE(hdw->big_lock);
1721         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1722         if (enable_flag) {
1723                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1724                         if (st != PVR2_STATE_READY) return -EIO;
1725                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1726                 }
1727         }
1728         return 0;
1729 }
1730
1731
1732 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1733 {
1734         int fl;
1735         LOCK_TAKE(hdw->big_lock);
1736         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1737                 hdw->desired_stream_type = config;
1738                 hdw->state_pipeline_config = 0;
1739                 trace_stbit("state_pipeline_config",
1740                             hdw->state_pipeline_config);
1741                 pvr2_hdw_state_sched(hdw);
1742         }
1743         LOCK_GIVE(hdw->big_lock);
1744         if (fl) return 0;
1745         return pvr2_hdw_wait(hdw,0);
1746 }
1747
1748
1749 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1750 {
1751         int unit_number = hdw->unit_number;
1752         int tp = -1;
1753         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1754                 tp = tuner[unit_number];
1755         }
1756         if (tp < 0) return -EINVAL;
1757         hdw->tuner_type = tp;
1758         hdw->tuner_updated = !0;
1759         return 0;
1760 }
1761
1762
1763 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1764 {
1765         int unit_number = hdw->unit_number;
1766         int tp = 0;
1767         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1768                 tp = video_std[unit_number];
1769                 if (tp) return tp;
1770         }
1771         return 0;
1772 }
1773
1774
1775 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1776 {
1777         int unit_number = hdw->unit_number;
1778         int tp = 0;
1779         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1780                 tp = tolerance[unit_number];
1781         }
1782         return tp;
1783 }
1784
1785
1786 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1787 {
1788         /* Try a harmless request to fetch the eeprom's address over
1789            endpoint 1.  See what happens.  Only the full FX2 image can
1790            respond to this.  If this probe fails then likely the FX2
1791            firmware needs be loaded. */
1792         int result;
1793         LOCK_TAKE(hdw->ctl_lock); do {
1794                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1795                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1796                                            hdw->cmd_buffer,1,
1797                                            hdw->cmd_buffer,1);
1798                 if (result < 0) break;
1799         } while(0); LOCK_GIVE(hdw->ctl_lock);
1800         if (result) {
1801                 pvr2_trace(PVR2_TRACE_INIT,
1802                            "Probe of device endpoint 1 result status %d",
1803                            result);
1804         } else {
1805                 pvr2_trace(PVR2_TRACE_INIT,
1806                            "Probe of device endpoint 1 succeeded");
1807         }
1808         return result == 0;
1809 }
1810
1811 struct pvr2_std_hack {
1812         v4l2_std_id pat;  /* Pattern to match */
1813         v4l2_std_id msk;  /* Which bits we care about */
1814         v4l2_std_id std;  /* What additional standards or default to set */
1815 };
1816
1817 /* This data structure labels specific combinations of standards from
1818    tveeprom that we'll try to recognize.  If we recognize one, then assume
1819    a specified default standard to use.  This is here because tveeprom only
1820    tells us about available standards not the intended default standard (if
1821    any) for the device in question.  We guess the default based on what has
1822    been reported as available.  Note that this is only for guessing a
1823    default - which can always be overridden explicitly - and if the user
1824    has otherwise named a default then that default will always be used in
1825    place of this table. */
1826 static const struct pvr2_std_hack std_eeprom_maps[] = {
1827         {       /* PAL(B/G) */
1828                 .pat = V4L2_STD_B|V4L2_STD_GH,
1829                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1830         },
1831         {       /* NTSC(M) */
1832                 .pat = V4L2_STD_MN,
1833                 .std = V4L2_STD_NTSC_M,
1834         },
1835         {       /* PAL(I) */
1836                 .pat = V4L2_STD_PAL_I,
1837                 .std = V4L2_STD_PAL_I,
1838         },
1839         {       /* SECAM(L/L') */
1840                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1841                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1842         },
1843         {       /* PAL(D/D1/K) */
1844                 .pat = V4L2_STD_DK,
1845                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1846         },
1847 };
1848
1849 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1850 {
1851         char buf[40];
1852         unsigned int bcnt;
1853         v4l2_std_id std1,std2,std3;
1854
1855         std1 = get_default_standard(hdw);
1856         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1857
1858         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1859         pvr2_trace(PVR2_TRACE_STD,
1860                    "Supported video standard(s) reported available"
1861                    " in hardware: %.*s",
1862                    bcnt,buf);
1863
1864         hdw->std_mask_avail = hdw->std_mask_eeprom;
1865
1866         std2 = (std1|std3) & ~hdw->std_mask_avail;
1867         if (std2) {
1868                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1869                 pvr2_trace(PVR2_TRACE_STD,
1870                            "Expanding supported video standards"
1871                            " to include: %.*s",
1872                            bcnt,buf);
1873                 hdw->std_mask_avail |= std2;
1874         }
1875
1876         pvr2_hdw_internal_set_std_avail(hdw);
1877
1878         if (std1) {
1879                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1880                 pvr2_trace(PVR2_TRACE_STD,
1881                            "Initial video standard forced to %.*s",
1882                            bcnt,buf);
1883                 hdw->std_mask_cur = std1;
1884                 hdw->std_dirty = !0;
1885                 pvr2_hdw_internal_find_stdenum(hdw);
1886                 return;
1887         }
1888         if (std3) {
1889                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1890                 pvr2_trace(PVR2_TRACE_STD,
1891                            "Initial video standard"
1892                            " (determined by device type): %.*s",bcnt,buf);
1893                 hdw->std_mask_cur = std3;
1894                 hdw->std_dirty = !0;
1895                 pvr2_hdw_internal_find_stdenum(hdw);
1896                 return;
1897         }
1898
1899         {
1900                 unsigned int idx;
1901                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1902                         if (std_eeprom_maps[idx].msk ?
1903                             ((std_eeprom_maps[idx].pat ^
1904                              hdw->std_mask_eeprom) &
1905                              std_eeprom_maps[idx].msk) :
1906                             (std_eeprom_maps[idx].pat !=
1907                              hdw->std_mask_eeprom)) continue;
1908                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1909                                                   std_eeprom_maps[idx].std);
1910                         pvr2_trace(PVR2_TRACE_STD,
1911                                    "Initial video standard guessed as %.*s",
1912                                    bcnt,buf);
1913                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1914                         hdw->std_dirty = !0;
1915                         pvr2_hdw_internal_find_stdenum(hdw);
1916                         return;
1917                 }
1918         }
1919
1920         if (hdw->std_enum_cnt > 1) {
1921                 // Autoselect the first listed standard
1922                 hdw->std_enum_cur = 1;
1923                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1924                 hdw->std_dirty = !0;
1925                 pvr2_trace(PVR2_TRACE_STD,
1926                            "Initial video standard auto-selected to %s",
1927                            hdw->std_defs[hdw->std_enum_cur-1].name);
1928                 return;
1929         }
1930
1931         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1932                    "Unable to select a viable initial video standard");
1933 }
1934
1935
1936 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1937 {
1938         int ret;
1939         unsigned int idx;
1940         struct pvr2_ctrl *cptr;
1941         int reloadFl = 0;
1942         if (hdw->hdw_desc->fx2_firmware.cnt) {
1943                 if (!reloadFl) {
1944                         reloadFl =
1945                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1946                                  == 0);
1947                         if (reloadFl) {
1948                                 pvr2_trace(PVR2_TRACE_INIT,
1949                                            "USB endpoint config looks strange"
1950                                            "; possibly firmware needs to be"
1951                                            " loaded");
1952                         }
1953                 }
1954                 if (!reloadFl) {
1955                         reloadFl = !pvr2_hdw_check_firmware(hdw);
1956                         if (reloadFl) {
1957                                 pvr2_trace(PVR2_TRACE_INIT,
1958                                            "Check for FX2 firmware failed"
1959                                            "; possibly firmware needs to be"
1960                                            " loaded");
1961                         }
1962                 }
1963                 if (reloadFl) {
1964                         if (pvr2_upload_firmware1(hdw) != 0) {
1965                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1966                                            "Failure uploading firmware1");
1967                         }
1968                         return;
1969                 }
1970         }
1971         hdw->fw1_state = FW1_STATE_OK;
1972
1973         if (!pvr2_hdw_dev_ok(hdw)) return;
1974
1975         for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) {
1976                 request_module(hdw->hdw_desc->client_modules.lst[idx]);
1977         }
1978
1979         if (!hdw->hdw_desc->flag_no_powerup) {
1980                 pvr2_hdw_cmd_powerup(hdw);
1981                 if (!pvr2_hdw_dev_ok(hdw)) return;
1982         }
1983
1984         /* Take the IR chip out of reset, if appropriate */
1985         if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
1986                 pvr2_issue_simple_cmd(hdw,
1987                                       FX2CMD_HCW_ZILOG_RESET |
1988                                       (1 << 8) |
1989                                       ((0) << 16));
1990         }
1991
1992         // This step MUST happen after the earlier powerup step.
1993         pvr2_i2c_core_init(hdw);
1994         if (!pvr2_hdw_dev_ok(hdw)) return;
1995
1996         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1997                 cptr = hdw->controls + idx;
1998                 if (cptr->info->skip_init) continue;
1999                 if (!cptr->info->set_value) continue;
2000                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2001         }
2002
2003         /* Set up special default values for the television and radio
2004            frequencies here.  It's not really important what these defaults
2005            are, but I set them to something usable in the Chicago area just
2006            to make driver testing a little easier. */
2007
2008         hdw->freqValTelevision = default_tv_freq;
2009         hdw->freqValRadio = default_radio_freq;
2010
2011         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2012         // thread-safe against the normal pvr2_send_request() mechanism.
2013         // (We should make it thread safe).
2014
2015         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2016                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2017                 if (!pvr2_hdw_dev_ok(hdw)) return;
2018                 if (ret < 0) {
2019                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2020                                    "Unable to determine location of eeprom,"
2021                                    " skipping");
2022                 } else {
2023                         hdw->eeprom_addr = ret;
2024                         pvr2_eeprom_analyze(hdw);
2025                         if (!pvr2_hdw_dev_ok(hdw)) return;
2026                 }
2027         } else {
2028                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2029                 hdw->tuner_updated = !0;
2030                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2031         }
2032
2033         if (hdw->serial_number) {
2034                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2035                                 "sn-%lu", hdw->serial_number);
2036         } else if (hdw->unit_number >= 0) {
2037                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2038                                 "unit-%c",
2039                                 hdw->unit_number + 'a');
2040         } else {
2041                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2042                                 "unit-??");
2043         }
2044         hdw->identifier[idx] = 0;
2045
2046         pvr2_hdw_setup_std(hdw);
2047
2048         if (!get_default_tuner_type(hdw)) {
2049                 pvr2_trace(PVR2_TRACE_INIT,
2050                            "pvr2_hdw_setup: Tuner type overridden to %d",
2051                            hdw->tuner_type);
2052         }
2053
2054         pvr2_i2c_core_check_stale(hdw);
2055         hdw->tuner_updated = 0;
2056
2057         if (!pvr2_hdw_dev_ok(hdw)) return;
2058
2059         if (hdw->hdw_desc->signal_routing_scheme ==
2060             PVR2_ROUTING_SCHEME_GOTVIEW) {
2061                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2062                    hardware. */
2063                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2064         }
2065
2066         pvr2_hdw_commit_setup(hdw);
2067
2068         hdw->vid_stream = pvr2_stream_create();
2069         if (!pvr2_hdw_dev_ok(hdw)) return;
2070         pvr2_trace(PVR2_TRACE_INIT,
2071                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2072         if (hdw->vid_stream) {
2073                 idx = get_default_error_tolerance(hdw);
2074                 if (idx) {
2075                         pvr2_trace(PVR2_TRACE_INIT,
2076                                    "pvr2_hdw_setup: video stream %p"
2077                                    " setting tolerance %u",
2078                                    hdw->vid_stream,idx);
2079                 }
2080                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2081                                   PVR2_VID_ENDPOINT,idx);
2082         }
2083
2084         if (!pvr2_hdw_dev_ok(hdw)) return;
2085
2086         hdw->flag_init_ok = !0;
2087
2088         pvr2_hdw_state_sched(hdw);
2089 }
2090
2091
2092 /* Set up the structure and attempt to put the device into a usable state.
2093    This can be a time-consuming operation, which is why it is not done
2094    internally as part of the create() step. */
2095 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2096 {
2097         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2098         do {
2099                 pvr2_hdw_setup_low(hdw);
2100                 pvr2_trace(PVR2_TRACE_INIT,
2101                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2102                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2103                 if (pvr2_hdw_dev_ok(hdw)) {
2104                         if (hdw->flag_init_ok) {
2105                                 pvr2_trace(
2106                                         PVR2_TRACE_INFO,
2107                                         "Device initialization"
2108                                         " completed successfully.");
2109                                 break;
2110                         }
2111                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2112                                 pvr2_trace(
2113                                         PVR2_TRACE_INFO,
2114                                         "Device microcontroller firmware"
2115                                         " (re)loaded; it should now reset"
2116                                         " and reconnect.");
2117                                 break;
2118                         }
2119                         pvr2_trace(
2120                                 PVR2_TRACE_ERROR_LEGS,
2121                                 "Device initialization was not successful.");
2122                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2123                                 pvr2_trace(
2124                                         PVR2_TRACE_ERROR_LEGS,
2125                                         "Giving up since device"
2126                                         " microcontroller firmware"
2127                                         " appears to be missing.");
2128                                 break;
2129                         }
2130                 }
2131                 if (procreload) {
2132                         pvr2_trace(
2133                                 PVR2_TRACE_ERROR_LEGS,
2134                                 "Attempting pvrusb2 recovery by reloading"
2135                                 " primary firmware.");
2136                         pvr2_trace(
2137                                 PVR2_TRACE_ERROR_LEGS,
2138                                 "If this works, device should disconnect"
2139                                 " and reconnect in a sane state.");
2140                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2141                         pvr2_upload_firmware1(hdw);
2142                 } else {
2143                         pvr2_trace(
2144                                 PVR2_TRACE_ERROR_LEGS,
2145                                 "***WARNING*** pvrusb2 device hardware"
2146                                 " appears to be jammed"
2147                                 " and I can't clear it.");
2148                         pvr2_trace(
2149                                 PVR2_TRACE_ERROR_LEGS,
2150                                 "You might need to power cycle"
2151                                 " the pvrusb2 device"
2152                                 " in order to recover.");
2153                 }
2154         } while (0);
2155         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2156 }
2157
2158
2159 /* Perform second stage initialization.  Set callback pointer first so that
2160    we can avoid a possible initialization race (if the kernel thread runs
2161    before the callback has been set). */
2162 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2163                         void (*callback_func)(void *),
2164                         void *callback_data)
2165 {
2166         LOCK_TAKE(hdw->big_lock); do {
2167                 if (hdw->flag_disconnected) {
2168                         /* Handle a race here: If we're already
2169                            disconnected by this point, then give up.  If we
2170                            get past this then we'll remain connected for
2171                            the duration of initialization since the entire
2172                            initialization sequence is now protected by the
2173                            big_lock. */
2174                         break;
2175                 }
2176                 hdw->state_data = callback_data;
2177                 hdw->state_func = callback_func;
2178                 pvr2_hdw_setup(hdw);
2179         } while (0); LOCK_GIVE(hdw->big_lock);
2180         return hdw->flag_init_ok;
2181 }
2182
2183
2184 /* Create, set up, and return a structure for interacting with the
2185    underlying hardware.  */
2186 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2187                                  const struct usb_device_id *devid)
2188 {
2189         unsigned int idx,cnt1,cnt2,m;
2190         struct pvr2_hdw *hdw = NULL;
2191         int valid_std_mask;
2192         struct pvr2_ctrl *cptr;
2193         const struct pvr2_device_desc *hdw_desc;
2194         __u8 ifnum;
2195         struct v4l2_queryctrl qctrl;
2196         struct pvr2_ctl_info *ciptr;
2197
2198         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2199
2200         if (hdw_desc == NULL) {
2201                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2202                            " No device description pointer,"
2203                            " unable to continue.");
2204                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2205                            " please contact Mike Isely <isely@pobox.com>"
2206                            " to get it included in the driver\n");
2207                 goto fail;
2208         }
2209
2210         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2211         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2212                    hdw,hdw_desc->description);
2213         if (!hdw) goto fail;
2214
2215         init_timer(&hdw->quiescent_timer);
2216         hdw->quiescent_timer.data = (unsigned long)hdw;
2217         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2218
2219         init_timer(&hdw->encoder_wait_timer);
2220         hdw->encoder_wait_timer.data = (unsigned long)hdw;
2221         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2222
2223         init_timer(&hdw->encoder_run_timer);
2224         hdw->encoder_run_timer.data = (unsigned long)hdw;
2225         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2226
2227         hdw->master_state = PVR2_STATE_DEAD;
2228
2229         init_waitqueue_head(&hdw->state_wait_data);
2230
2231         hdw->tuner_signal_stale = !0;
2232         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2233
2234         /* Calculate which inputs are OK */
2235         m = 0;
2236         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2237         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2238                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2239         }
2240         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2241         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2242         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2243         hdw->input_avail_mask = m;
2244         hdw->input_allowed_mask = hdw->input_avail_mask;
2245
2246         /* If not a hybrid device, pathway_state never changes.  So
2247            initialize it here to what it should forever be. */
2248         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2249                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2250         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2251                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2252         }
2253
2254         hdw->control_cnt = CTRLDEF_COUNT;
2255         hdw->control_cnt += MPEGDEF_COUNT;
2256         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2257                                 GFP_KERNEL);
2258         if (!hdw->controls) goto fail;
2259         hdw->hdw_desc = hdw_desc;
2260         for (idx = 0; idx < hdw->control_cnt; idx++) {
2261                 cptr = hdw->controls + idx;
2262                 cptr->hdw = hdw;
2263         }
2264         for (idx = 0; idx < 32; idx++) {
2265                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2266         }
2267         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2268                 cptr = hdw->controls + idx;
2269                 cptr->info = control_defs+idx;
2270         }
2271
2272         /* Ensure that default input choice is a valid one. */
2273         m = hdw->input_avail_mask;
2274         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2275                 if (!((1 << idx) & m)) continue;
2276                 hdw->input_val = idx;
2277                 break;
2278         }
2279
2280         /* Define and configure additional controls from cx2341x module. */
2281         hdw->mpeg_ctrl_info = kzalloc(
2282                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2283         if (!hdw->mpeg_ctrl_info) goto fail;
2284         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2285                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2286                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2287                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2288                 ciptr->name = mpeg_ids[idx].strid;
2289                 ciptr->v4l_id = mpeg_ids[idx].id;
2290                 ciptr->skip_init = !0;
2291                 ciptr->get_value = ctrl_cx2341x_get;
2292                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2293                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2294                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2295                 qctrl.id = ciptr->v4l_id;
2296                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2297                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2298                         ciptr->set_value = ctrl_cx2341x_set;
2299                 }
2300                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2301                         PVR2_CTLD_INFO_DESC_SIZE);
2302                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2303                 ciptr->default_value = qctrl.default_value;
2304                 switch (qctrl.type) {
2305                 default:
2306                 case V4L2_CTRL_TYPE_INTEGER:
2307                         ciptr->type = pvr2_ctl_int;
2308                         ciptr->def.type_int.min_value = qctrl.minimum;
2309                         ciptr->def.type_int.max_value = qctrl.maximum;
2310                         break;
2311                 case V4L2_CTRL_TYPE_BOOLEAN:
2312                         ciptr->type = pvr2_ctl_bool;
2313                         break;
2314                 case V4L2_CTRL_TYPE_MENU:
2315                         ciptr->type = pvr2_ctl_enum;
2316                         ciptr->def.type_enum.value_names =
2317                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2318                                                                 ciptr->v4l_id);
2319                         for (cnt1 = 0;
2320                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2321                              cnt1++) { }
2322                         ciptr->def.type_enum.count = cnt1;
2323                         break;
2324                 }
2325                 cptr->info = ciptr;
2326         }
2327
2328         // Initialize video standard enum dynamic control
2329         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2330         if (cptr) {
2331                 memcpy(&hdw->std_info_enum,cptr->info,
2332                        sizeof(hdw->std_info_enum));
2333                 cptr->info = &hdw->std_info_enum;
2334
2335         }
2336         // Initialize control data regarding video standard masks
2337         valid_std_mask = pvr2_std_get_usable();
2338         for (idx = 0; idx < 32; idx++) {
2339                 if (!(valid_std_mask & (1 << idx))) continue;
2340                 cnt1 = pvr2_std_id_to_str(
2341                         hdw->std_mask_names[idx],
2342                         sizeof(hdw->std_mask_names[idx])-1,
2343                         1 << idx);
2344                 hdw->std_mask_names[idx][cnt1] = 0;
2345         }
2346         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2347         if (cptr) {
2348                 memcpy(&hdw->std_info_avail,cptr->info,
2349                        sizeof(hdw->std_info_avail));
2350                 cptr->info = &hdw->std_info_avail;
2351                 hdw->std_info_avail.def.type_bitmask.bit_names =
2352                         hdw->std_mask_ptrs;
2353                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2354                         valid_std_mask;
2355         }
2356         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2357         if (cptr) {
2358                 memcpy(&hdw->std_info_cur,cptr->info,
2359                        sizeof(hdw->std_info_cur));
2360                 cptr->info = &hdw->std_info_cur;
2361                 hdw->std_info_cur.def.type_bitmask.bit_names =
2362                         hdw->std_mask_ptrs;
2363                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2364                         valid_std_mask;
2365         }
2366
2367         hdw->cropcap_stale = !0;
2368         hdw->eeprom_addr = -1;
2369         hdw->unit_number = -1;
2370         hdw->v4l_minor_number_video = -1;
2371         hdw->v4l_minor_number_vbi = -1;
2372         hdw->v4l_minor_number_radio = -1;
2373         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2374         if (!hdw->ctl_write_buffer) goto fail;
2375         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2376         if (!hdw->ctl_read_buffer) goto fail;
2377         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2378         if (!hdw->ctl_write_urb) goto fail;
2379         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2380         if (!hdw->ctl_read_urb) goto fail;
2381
2382         mutex_lock(&pvr2_unit_mtx); do {
2383                 for (idx = 0; idx < PVR_NUM; idx++) {
2384                         if (unit_pointers[idx]) continue;
2385                         hdw->unit_number = idx;
2386                         unit_pointers[idx] = hdw;
2387                         break;
2388                 }
2389         } while (0); mutex_unlock(&pvr2_unit_mtx);
2390
2391         cnt1 = 0;
2392         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2393         cnt1 += cnt2;
2394         if (hdw->unit_number >= 0) {
2395                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2396                                  ('a' + hdw->unit_number));
2397                 cnt1 += cnt2;
2398         }
2399         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2400         hdw->name[cnt1] = 0;
2401
2402         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2403         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2404         INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2405
2406         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2407                    hdw->unit_number,hdw->name);
2408
2409         hdw->tuner_type = -1;
2410         hdw->flag_ok = !0;
2411
2412         hdw->usb_intf = intf;
2413         hdw->usb_dev = interface_to_usbdev(intf);
2414
2415         scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
2416                   "usb %s address %d",
2417                   dev_name(&hdw->usb_dev->dev),
2418                   hdw->usb_dev->devnum);
2419
2420         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2421         usb_set_interface(hdw->usb_dev,ifnum,0);
2422
2423         mutex_init(&hdw->ctl_lock_mutex);
2424         mutex_init(&hdw->big_lock_mutex);
2425
2426         return hdw;
2427  fail:
2428         if (hdw) {
2429                 del_timer_sync(&hdw->quiescent_timer);
2430                 del_timer_sync(&hdw->encoder_run_timer);
2431                 del_timer_sync(&hdw->encoder_wait_timer);
2432                 if (hdw->workqueue) {
2433                         flush_workqueue(hdw->workqueue);
2434                         destroy_workqueue(hdw->workqueue);
2435                         hdw->workqueue = NULL;
2436                 }
2437                 usb_free_urb(hdw->ctl_read_urb);
2438                 usb_free_urb(hdw->ctl_write_urb);
2439                 kfree(hdw->ctl_read_buffer);
2440                 kfree(hdw->ctl_write_buffer);
2441                 kfree(hdw->controls);
2442                 kfree(hdw->mpeg_ctrl_info);
2443                 kfree(hdw->std_defs);
2444                 kfree(hdw->std_enum_names);
2445                 kfree(hdw);
2446         }
2447         return NULL;
2448 }
2449
2450
2451 /* Remove _all_ associations between this driver and the underlying USB
2452    layer. */
2453 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2454 {
2455         if (hdw->flag_disconnected) return;
2456         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2457         if (hdw->ctl_read_urb) {
2458                 usb_kill_urb(hdw->ctl_read_urb);
2459                 usb_free_urb(hdw->ctl_read_urb);
2460                 hdw->ctl_read_urb = NULL;
2461         }
2462         if (hdw->ctl_write_urb) {
2463                 usb_kill_urb(hdw->ctl_write_urb);
2464                 usb_free_urb(hdw->ctl_write_urb);
2465                 hdw->ctl_write_urb = NULL;
2466         }
2467         if (hdw->ctl_read_buffer) {
2468                 kfree(hdw->ctl_read_buffer);
2469                 hdw->ctl_read_buffer = NULL;
2470         }
2471         if (hdw->ctl_write_buffer) {
2472                 kfree(hdw->ctl_write_buffer);
2473                 hdw->ctl_write_buffer = NULL;
2474         }
2475         hdw->flag_disconnected = !0;
2476         hdw->usb_dev = NULL;
2477         hdw->usb_intf = NULL;
2478         pvr2_hdw_render_useless(hdw);
2479 }
2480
2481
2482 /* Destroy hardware interaction structure */
2483 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2484 {
2485         if (!hdw) return;
2486         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2487         if (hdw->workqueue) {
2488                 flush_workqueue(hdw->workqueue);
2489                 destroy_workqueue(hdw->workqueue);
2490                 hdw->workqueue = NULL;
2491         }
2492         del_timer_sync(&hdw->quiescent_timer);
2493         del_timer_sync(&hdw->encoder_run_timer);
2494         del_timer_sync(&hdw->encoder_wait_timer);
2495         if (hdw->fw_buffer) {
2496                 kfree(hdw->fw_buffer);
2497                 hdw->fw_buffer = NULL;
2498         }
2499         if (hdw->vid_stream) {
2500                 pvr2_stream_destroy(hdw->vid_stream);
2501                 hdw->vid_stream = NULL;
2502         }
2503         if (hdw->decoder_ctrl) {
2504                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2505         }
2506         pvr2_i2c_core_done(hdw);
2507         pvr2_hdw_remove_usb_stuff(hdw);
2508         mutex_lock(&pvr2_unit_mtx); do {
2509                 if ((hdw->unit_number >= 0) &&
2510                     (hdw->unit_number < PVR_NUM) &&
2511                     (unit_pointers[hdw->unit_number] == hdw)) {
2512                         unit_pointers[hdw->unit_number] = NULL;
2513                 }
2514         } while (0); mutex_unlock(&pvr2_unit_mtx);
2515         kfree(hdw->controls);
2516         kfree(hdw->mpeg_ctrl_info);
2517         kfree(hdw->std_defs);
2518         kfree(hdw->std_enum_names);
2519         kfree(hdw);
2520 }
2521
2522
2523 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2524 {
2525         return (hdw && hdw->flag_ok);
2526 }
2527
2528
2529 /* Called when hardware has been unplugged */
2530 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2531 {
2532         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2533         LOCK_TAKE(hdw->big_lock);
2534         LOCK_TAKE(hdw->ctl_lock);
2535         pvr2_hdw_remove_usb_stuff(hdw);
2536         LOCK_GIVE(hdw->ctl_lock);
2537         LOCK_GIVE(hdw->big_lock);
2538 }
2539
2540
2541 // Attempt to autoselect an appropriate value for std_enum_cur given
2542 // whatever is currently in std_mask_cur
2543 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2544 {
2545         unsigned int idx;
2546         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2547                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2548                         hdw->std_enum_cur = idx;
2549                         return;
2550                 }
2551         }
2552         hdw->std_enum_cur = 0;
2553 }
2554
2555
2556 // Calculate correct set of enumerated standards based on currently known
2557 // set of available standards bits.
2558 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2559 {
2560         struct v4l2_standard *newstd;
2561         unsigned int std_cnt;
2562         unsigned int idx;
2563
2564         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2565
2566         if (hdw->std_defs) {
2567                 kfree(hdw->std_defs);
2568                 hdw->std_defs = NULL;
2569         }
2570         hdw->std_enum_cnt = 0;
2571         if (hdw->std_enum_names) {
2572                 kfree(hdw->std_enum_names);
2573                 hdw->std_enum_names = NULL;
2574         }
2575
2576         if (!std_cnt) {
2577                 pvr2_trace(
2578                         PVR2_TRACE_ERROR_LEGS,
2579                         "WARNING: Failed to identify any viable standards");
2580         }
2581         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2582         hdw->std_enum_names[0] = "none";
2583         for (idx = 0; idx < std_cnt; idx++) {
2584                 hdw->std_enum_names[idx+1] =
2585                         newstd[idx].name;
2586         }
2587         // Set up the dynamic control for this standard
2588         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2589         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2590         hdw->std_defs = newstd;
2591         hdw->std_enum_cnt = std_cnt+1;
2592         hdw->std_enum_cur = 0;
2593         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2594 }
2595
2596
2597 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2598                                struct v4l2_standard *std,
2599                                unsigned int idx)
2600 {
2601         int ret = -EINVAL;
2602         if (!idx) return ret;
2603         LOCK_TAKE(hdw->big_lock); do {
2604                 if (idx >= hdw->std_enum_cnt) break;
2605                 idx--;
2606                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2607                 ret = 0;
2608         } while (0); LOCK_GIVE(hdw->big_lock);
2609         return ret;
2610 }
2611
2612
2613 /* Get the number of defined controls */
2614 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2615 {
2616         return hdw->control_cnt;
2617 }
2618
2619
2620 /* Retrieve a control handle given its index (0..count-1) */
2621 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2622                                              unsigned int idx)
2623 {
2624         if (idx >= hdw->control_cnt) return NULL;
2625         return hdw->controls + idx;
2626 }
2627
2628
2629 /* Retrieve a control handle given its index (0..count-1) */
2630 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2631                                           unsigned int ctl_id)
2632 {
2633         struct pvr2_ctrl *cptr;
2634         unsigned int idx;
2635         int i;
2636
2637         /* This could be made a lot more efficient, but for now... */
2638         for (idx = 0; idx < hdw->control_cnt; idx++) {
2639                 cptr = hdw->controls + idx;
2640                 i = cptr->info->internal_id;
2641                 if (i && (i == ctl_id)) return cptr;
2642         }
2643         return NULL;
2644 }
2645
2646
2647 /* Given a V4L ID, retrieve the control structure associated with it. */
2648 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2649 {
2650         struct pvr2_ctrl *cptr;
2651         unsigned int idx;
2652         int i;
2653
2654         /* This could be made a lot more efficient, but for now... */
2655         for (idx = 0; idx < hdw->control_cnt; idx++) {
2656                 cptr = hdw->controls + idx;
2657                 i = cptr->info->v4l_id;
2658                 if (i && (i == ctl_id)) return cptr;
2659         }
2660         return NULL;
2661 }
2662
2663
2664 /* Given a V4L ID for its immediate predecessor, retrieve the control
2665    structure associated with it. */
2666 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2667                                             unsigned int ctl_id)
2668 {
2669         struct pvr2_ctrl *cptr,*cp2;
2670         unsigned int idx;
2671         int i;
2672
2673         /* This could be made a lot more efficient, but for now... */
2674         cp2 = NULL;
2675         for (idx = 0; idx < hdw->control_cnt; idx++) {
2676                 cptr = hdw->controls + idx;
2677                 i = cptr->info->v4l_id;
2678                 if (!i) continue;
2679                 if (i <= ctl_id) continue;
2680                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2681                 cp2 = cptr;
2682         }
2683         return cp2;
2684         return NULL;
2685 }
2686
2687
2688 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2689 {
2690         switch (tp) {
2691         case pvr2_ctl_int: return "integer";
2692         case pvr2_ctl_enum: return "enum";
2693         case pvr2_ctl_bool: return "boolean";
2694         case pvr2_ctl_bitmask: return "bitmask";
2695         }
2696         return "";
2697 }
2698
2699
2700 /* Figure out if we need to commit control changes.  If so, mark internal
2701    state flags to indicate this fact and return true.  Otherwise do nothing
2702    else and return false. */
2703 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2704 {
2705         unsigned int idx;
2706         struct pvr2_ctrl *cptr;
2707         int value;
2708         int commit_flag = 0;
2709         char buf[100];
2710         unsigned int bcnt,ccnt;
2711
2712         for (idx = 0; idx < hdw->control_cnt; idx++) {
2713                 cptr = hdw->controls + idx;
2714                 if (!cptr->info->is_dirty) continue;
2715                 if (!cptr->info->is_dirty(cptr)) continue;
2716                 commit_flag = !0;
2717
2718                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2719                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2720                                  cptr->info->name);
2721                 value = 0;
2722                 cptr->info->get_value(cptr,&value);
2723                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2724                                                 buf+bcnt,
2725                                                 sizeof(buf)-bcnt,&ccnt);
2726                 bcnt += ccnt;
2727                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2728                                   get_ctrl_typename(cptr->info->type));
2729                 pvr2_trace(PVR2_TRACE_CTL,
2730                            "/*--TRACE_COMMIT--*/ %.*s",
2731                            bcnt,buf);
2732         }
2733
2734         if (!commit_flag) {
2735                 /* Nothing has changed */
2736                 return 0;
2737         }
2738
2739         hdw->state_pipeline_config = 0;
2740         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2741         pvr2_hdw_state_sched(hdw);
2742
2743         return !0;
2744 }
2745
2746
2747 /* Perform all operations needed to commit all control changes.  This must
2748    be performed in synchronization with the pipeline state and is thus
2749    expected to be called as part of the driver's worker thread.  Return
2750    true if commit successful, otherwise return false to indicate that
2751    commit isn't possible at this time. */
2752 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2753 {
2754         unsigned int idx;
2755         struct pvr2_ctrl *cptr;
2756         int disruptive_change;
2757
2758         /* Handle some required side effects when the video standard is
2759            changed.... */
2760         if (hdw->std_dirty) {
2761                 int nvres;
2762                 int gop_size;
2763                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2764                         nvres = 480;
2765                         gop_size = 15;
2766                 } else {
2767                         nvres = 576;
2768                         gop_size = 12;
2769                 }
2770                 /* Rewrite the vertical resolution to be appropriate to the
2771                    video standard that has been selected. */
2772                 if (nvres != hdw->res_ver_val) {
2773                         hdw->res_ver_val = nvres;
2774                         hdw->res_ver_dirty = !0;
2775                 }
2776                 /* Rewrite the GOP size to be appropriate to the video
2777                    standard that has been selected. */
2778                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
2779                         struct v4l2_ext_controls cs;
2780                         struct v4l2_ext_control c1;
2781                         memset(&cs, 0, sizeof(cs));
2782                         memset(&c1, 0, sizeof(c1));
2783                         cs.controls = &c1;
2784                         cs.count = 1;
2785                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
2786                         c1.value = gop_size;
2787                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
2788                                           VIDIOC_S_EXT_CTRLS);
2789                 }
2790         }
2791
2792         if (hdw->input_dirty && hdw->state_pathway_ok &&
2793             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
2794               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
2795              hdw->pathway_state)) {
2796                 /* Change of mode being asked for... */
2797                 hdw->state_pathway_ok = 0;
2798                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
2799         }
2800         if (!hdw->state_pathway_ok) {
2801                 /* Can't commit anything until pathway is ok. */
2802                 return 0;
2803         }
2804         /* The broadcast decoder can only scale down, so if
2805          * res_*_dirty && crop window < output format ==> enlarge crop.
2806          *
2807          * The mpeg encoder receives fields of res_hor_val dots and
2808          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
2809          */
2810         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
2811                 hdw->cropw_val = hdw->res_hor_val;
2812                 hdw->cropw_dirty = !0;
2813         } else if (hdw->cropw_dirty) {
2814                 hdw->res_hor_dirty = !0;           /* must rescale */
2815                 hdw->res_hor_val = min(720, hdw->cropw_val);
2816         }
2817         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
2818                 hdw->croph_val = hdw->res_ver_val;
2819                 hdw->croph_dirty = !0;
2820         } else if (hdw->croph_dirty) {
2821                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
2822                 hdw->res_ver_dirty = !0;
2823                 hdw->res_ver_val = min(nvres, hdw->croph_val);
2824         }
2825
2826         /* If any of the below has changed, then we can't do the update
2827            while the pipeline is running.  Pipeline must be paused first
2828            and decoder -> encoder connection be made quiescent before we
2829            can proceed. */
2830         disruptive_change =
2831                 (hdw->std_dirty ||
2832                  hdw->enc_unsafe_stale ||
2833                  hdw->srate_dirty ||
2834                  hdw->res_ver_dirty ||
2835                  hdw->res_hor_dirty ||
2836                  hdw->cropw_dirty ||
2837                  hdw->croph_dirty ||
2838                  hdw->input_dirty ||
2839                  (hdw->active_stream_type != hdw->desired_stream_type));
2840         if (disruptive_change && !hdw->state_pipeline_idle) {
2841                 /* Pipeline is not idle; we can't proceed.  Arrange to
2842                    cause pipeline to stop so that we can try this again
2843                    later.... */
2844                 hdw->state_pipeline_pause = !0;
2845                 return 0;
2846         }
2847
2848         if (hdw->srate_dirty) {
2849                 /* Write new sample rate into control structure since
2850                  * the master copy is stale.  We must track srate
2851                  * separate from the mpeg control structure because
2852                  * other logic also uses this value. */
2853                 struct v4l2_ext_controls cs;
2854                 struct v4l2_ext_control c1;
2855                 memset(&cs,0,sizeof(cs));
2856                 memset(&c1,0,sizeof(c1));
2857                 cs.controls = &c1;
2858                 cs.count = 1;
2859                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2860                 c1.value = hdw->srate_val;
2861                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
2862         }
2863
2864         /* Scan i2c core at this point - before we clear all the dirty
2865            bits.  Various parts of the i2c core will notice dirty bits as
2866            appropriate and arrange to broadcast or directly send updates to
2867            the client drivers in order to keep everything in sync */
2868         pvr2_i2c_core_check_stale(hdw);
2869
2870         for (idx = 0; idx < hdw->control_cnt; idx++) {
2871                 cptr = hdw->controls + idx;
2872                 if (!cptr->info->clear_dirty) continue;
2873                 cptr->info->clear_dirty(cptr);
2874         }
2875
2876         if (hdw->active_stream_type != hdw->desired_stream_type) {
2877                 /* Handle any side effects of stream config here */
2878                 hdw->active_stream_type = hdw->desired_stream_type;
2879         }
2880
2881         if (hdw->hdw_desc->signal_routing_scheme ==
2882             PVR2_ROUTING_SCHEME_GOTVIEW) {
2883                 u32 b;
2884                 /* Handle GOTVIEW audio switching */
2885                 pvr2_hdw_gpio_get_out(hdw,&b);
2886                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2887                         /* Set GPIO 11 */
2888                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
2889                 } else {
2890                         /* Clear GPIO 11 */
2891                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
2892                 }
2893         }
2894
2895         /* Now execute i2c core update */
2896         pvr2_i2c_core_sync(hdw);
2897
2898         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
2899             hdw->state_encoder_run) {
2900                 /* If encoder isn't running or it can't be touched, then
2901                    this will get worked out later when we start the
2902                    encoder. */
2903                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
2904         }
2905
2906         hdw->state_pipeline_config = !0;
2907         /* Hardware state may have changed in a way to cause the cropping
2908            capabilities to have changed.  So mark it stale, which will
2909            cause a later re-fetch. */
2910         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2911         return !0;
2912 }
2913
2914
2915 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2916 {
2917         int fl;
2918         LOCK_TAKE(hdw->big_lock);
2919         fl = pvr2_hdw_commit_setup(hdw);
2920         LOCK_GIVE(hdw->big_lock);
2921         if (!fl) return 0;
2922         return pvr2_hdw_wait(hdw,0);
2923 }
2924
2925
2926 static void pvr2_hdw_worker_i2c(struct work_struct *work)
2927 {
2928         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
2929         LOCK_TAKE(hdw->big_lock); do {
2930                 pvr2_i2c_core_sync(hdw);
2931         } while (0); LOCK_GIVE(hdw->big_lock);
2932 }
2933
2934
2935 static void pvr2_hdw_worker_poll(struct work_struct *work)
2936 {
2937         int fl = 0;
2938         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
2939         LOCK_TAKE(hdw->big_lock); do {
2940                 fl = pvr2_hdw_state_eval(hdw);
2941         } while (0); LOCK_GIVE(hdw->big_lock);
2942         if (fl && hdw->state_func) {
2943                 hdw->state_func(hdw->state_data);
2944         }
2945 }
2946
2947
2948 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
2949 {
2950         return wait_event_interruptible(
2951                 hdw->state_wait_data,
2952                 (hdw->state_stale == 0) &&
2953                 (!state || (hdw->master_state != state)));
2954 }
2955
2956
2957 /* Return name for this driver instance */
2958 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2959 {
2960         return hdw->name;
2961 }
2962
2963
2964 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
2965 {
2966         return hdw->hdw_desc->description;
2967 }
2968
2969
2970 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
2971 {
2972         return hdw->hdw_desc->shortname;
2973 }
2974
2975
2976 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2977 {
2978         int result;
2979         LOCK_TAKE(hdw->ctl_lock); do {
2980                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
2981                 result = pvr2_send_request(hdw,
2982                                            hdw->cmd_buffer,1,
2983                                            hdw->cmd_buffer,1);
2984                 if (result < 0) break;
2985                 result = (hdw->cmd_buffer[0] != 0);
2986         } while(0); LOCK_GIVE(hdw->ctl_lock);
2987         return result;
2988 }
2989
2990
2991 /* Execute poll of tuner status */
2992 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
2993 {
2994         LOCK_TAKE(hdw->big_lock); do {
2995                 pvr2_i2c_core_status_poll(hdw);
2996         } while (0); LOCK_GIVE(hdw->big_lock);
2997 }
2998
2999
3000 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3001 {
3002         if (!hdw->cropcap_stale) {
3003                 return 0;
3004         }
3005         pvr2_i2c_core_status_poll(hdw);
3006         if (hdw->cropcap_stale) {
3007                 return -EIO;
3008         }
3009         return 0;
3010 }
3011
3012
3013 /* Return information about cropping capabilities */
3014 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3015 {
3016         int stat = 0;
3017         LOCK_TAKE(hdw->big_lock);
3018         stat = pvr2_hdw_check_cropcap(hdw);
3019         if (!stat) {
3020                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3021         }
3022         LOCK_GIVE(hdw->big_lock);
3023         return stat;
3024 }
3025
3026
3027 /* Return information about the tuner */
3028 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3029 {
3030         LOCK_TAKE(hdw->big_lock); do {
3031                 if (hdw->tuner_signal_stale) {
3032                         pvr2_i2c_core_status_poll(hdw);
3033                 }
3034                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3035         } while (0); LOCK_GIVE(hdw->big_lock);
3036         return 0;
3037 }
3038
3039
3040 /* Get handle to video output stream */
3041 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3042 {
3043         return hp->vid_stream;
3044 }
3045
3046
3047 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3048 {
3049         int nr = pvr2_hdw_get_unit_number(hdw);
3050         LOCK_TAKE(hdw->big_lock); do {
3051                 hdw->log_requested = !0;
3052                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3053                 pvr2_i2c_core_check_stale(hdw);
3054                 hdw->log_requested = 0;
3055                 pvr2_i2c_core_sync(hdw);
3056                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3057                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3058                 pvr2_hdw_state_log_state(hdw);
3059                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3060         } while (0); LOCK_GIVE(hdw->big_lock);
3061 }
3062
3063
3064 /* Grab EEPROM contents, needed for direct method. */
3065 #define EEPROM_SIZE 8192
3066 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3067 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3068 {
3069         struct i2c_msg msg[2];
3070         u8 *eeprom;
3071         u8 iadd[2];
3072         u8 addr;
3073         u16 eepromSize;
3074         unsigned int offs;
3075         int ret;
3076         int mode16 = 0;
3077         unsigned pcnt,tcnt;
3078         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3079         if (!eeprom) {
3080                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3081                            "Failed to allocate memory"
3082                            " required to read eeprom");
3083                 return NULL;
3084         }
3085
3086         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3087                      hdw->eeprom_addr);
3088         addr = hdw->eeprom_addr;
3089         /* Seems that if the high bit is set, then the *real* eeprom
3090            address is shifted right now bit position (noticed this in
3091            newer PVR USB2 hardware) */
3092         if (addr & 0x80) addr >>= 1;
3093
3094         /* FX2 documentation states that a 16bit-addressed eeprom is
3095            expected if the I2C address is an odd number (yeah, this is
3096            strange but it's what they do) */
3097         mode16 = (addr & 1);
3098         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3099         trace_eeprom("Examining %d byte eeprom at location 0x%x"
3100                      " using %d bit addressing",eepromSize,addr,
3101                      mode16 ? 16 : 8);
3102
3103         msg[0].addr = addr;
3104         msg[0].flags = 0;
3105         msg[0].len = mode16 ? 2 : 1;
3106         msg[0].buf = iadd;
3107         msg[1].addr = addr;
3108         msg[1].flags = I2C_M_RD;
3109
3110         /* We have to do the actual eeprom data fetch ourselves, because
3111            (1) we're only fetching part of the eeprom, and (2) if we were
3112            getting the whole thing our I2C driver can't grab it in one
3113            pass - which is what tveeprom is otherwise going to attempt */
3114         memset(eeprom,0,EEPROM_SIZE);
3115         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3116                 pcnt = 16;
3117                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3118                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3119                 if (mode16) {
3120                         iadd[0] = offs >> 8;
3121                         iadd[1] = offs;
3122                 } else {
3123                         iadd[0] = offs;
3124                 }
3125                 msg[1].len = pcnt;
3126                 msg[1].buf = eeprom+tcnt;
3127                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3128                                         msg,ARRAY_SIZE(msg))) != 2) {
3129                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3130                                    "eeprom fetch set offs err=%d",ret);
3131                         kfree(eeprom);
3132                         return NULL;
3133                 }
3134         }
3135         return eeprom;
3136 }
3137
3138
3139 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3140                                 int prom_flag,
3141                                 int enable_flag)
3142 {
3143         int ret;
3144         u16 address;
3145         unsigned int pipe;
3146         LOCK_TAKE(hdw->big_lock); do {
3147                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3148
3149                 if (!enable_flag) {
3150                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3151                                    "Cleaning up after CPU firmware fetch");
3152                         kfree(hdw->fw_buffer);
3153                         hdw->fw_buffer = NULL;
3154                         hdw->fw_size = 0;
3155                         if (hdw->fw_cpu_flag) {
3156                                 /* Now release the CPU.  It will disconnect
3157                                    and reconnect later. */
3158                                 pvr2_hdw_cpureset_assert(hdw,0);
3159                         }
3160                         break;
3161                 }
3162
3163                 hdw->fw_cpu_flag = (prom_flag == 0);
3164                 if (hdw->fw_cpu_flag) {
3165                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3166                                    "Preparing to suck out CPU firmware");
3167                         hdw->fw_size = 0x2000;
3168                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3169                         if (!hdw->fw_buffer) {
3170                                 hdw->fw_size = 0;
3171                                 break;
3172                         }
3173
3174                         /* We have to hold the CPU during firmware upload. */
3175                         pvr2_hdw_cpureset_assert(hdw,1);
3176
3177                         /* download the firmware from address 0000-1fff in 2048
3178                            (=0x800) bytes chunk. */
3179
3180                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3181                                    "Grabbing CPU firmware");
3182                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3183                         for(address = 0; address < hdw->fw_size;
3184                             address += 0x800) {
3185                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3186                                                       0xa0,0xc0,
3187                                                       address,0,
3188                                                       hdw->fw_buffer+address,
3189                                                       0x800,HZ);
3190                                 if (ret < 0) break;
3191                         }
3192
3193                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3194                                    "Done grabbing CPU firmware");
3195                 } else {
3196                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3197                                    "Sucking down EEPROM contents");
3198                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3199                         if (!hdw->fw_buffer) {
3200                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3201                                            "EEPROM content suck failed.");
3202                                 break;
3203                         }
3204                         hdw->fw_size = EEPROM_SIZE;
3205                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3206                                    "Done sucking down EEPROM contents");
3207                 }
3208
3209         } while (0); LOCK_GIVE(hdw->big_lock);
3210 }
3211
3212
3213 /* Return true if we're in a mode for retrieval CPU firmware */
3214 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3215 {
3216         return hdw->fw_buffer != NULL;
3217 }
3218
3219
3220 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3221                        char *buf,unsigned int cnt)
3222 {
3223         int ret = -EINVAL;
3224         LOCK_TAKE(hdw->big_lock); do {
3225                 if (!buf) break;
3226                 if (!cnt) break;
3227
3228                 if (!hdw->fw_buffer) {
3229                         ret = -EIO;
3230                         break;
3231                 }
3232
3233                 if (offs >= hdw->fw_size) {
3234                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3235                                    "Read firmware data offs=%d EOF",
3236                                    offs);
3237                         ret = 0;
3238                         break;
3239                 }
3240
3241                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3242
3243                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3244
3245                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3246                            "Read firmware data offs=%d cnt=%d",
3247                            offs,cnt);
3248                 ret = cnt;
3249         } while (0); LOCK_GIVE(hdw->big_lock);
3250
3251         return ret;
3252 }
3253
3254
3255 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3256                                   enum pvr2_v4l_type index)
3257 {
3258         switch (index) {
3259         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3260         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3261         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3262         default: return -1;
3263         }
3264 }
3265
3266
3267 /* Store a v4l minor device number */
3268 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3269                                      enum pvr2_v4l_type index,int v)
3270 {
3271         switch (index) {
3272         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3273         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3274         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3275         default: break;
3276         }
3277 }
3278
3279
3280 static void pvr2_ctl_write_complete(struct urb *urb)
3281 {
3282         struct pvr2_hdw *hdw = urb->context;
3283         hdw->ctl_write_pend_flag = 0;
3284         if (hdw->ctl_read_pend_flag) return;
3285         complete(&hdw->ctl_done);
3286 }
3287
3288
3289 static void pvr2_ctl_read_complete(struct urb *urb)
3290 {
3291         struct pvr2_hdw *hdw = urb->context;
3292         hdw->ctl_read_pend_flag = 0;
3293         if (hdw->ctl_write_pend_flag) return;
3294         complete(&hdw->ctl_done);
3295 }
3296
3297
3298 static void pvr2_ctl_timeout(unsigned long data)
3299 {
3300         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3301         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3302                 hdw->ctl_timeout_flag = !0;
3303                 if (hdw->ctl_write_pend_flag)
3304                         usb_unlink_urb(hdw->ctl_write_urb);
3305                 if (hdw->ctl_read_pend_flag)
3306                         usb_unlink_urb(hdw->ctl_read_urb);
3307         }
3308 }
3309
3310
3311 /* Issue a command and get a response from the device.  This extended
3312    version includes a probe flag (which if set means that device errors
3313    should not be logged or treated as fatal) and a timeout in jiffies.
3314    This can be used to non-lethally probe the health of endpoint 1. */
3315 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3316                                 unsigned int timeout,int probe_fl,
3317                                 void *write_data,unsigned int write_len,
3318                                 void *read_data,unsigned int read_len)
3319 {
3320         unsigned int idx;
3321         int status = 0;
3322         struct timer_list timer;
3323         if (!hdw->ctl_lock_held) {
3324                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3325                            "Attempted to execute control transfer"
3326                            " without lock!!");
3327                 return -EDEADLK;
3328         }
3329         if (!hdw->flag_ok && !probe_fl) {
3330                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3331                            "Attempted to execute control transfer"
3332                            " when device not ok");
3333                 return -EIO;
3334         }
3335         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3336                 if (!probe_fl) {
3337                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3338                                    "Attempted to execute control transfer"
3339                                    " when USB is disconnected");
3340                 }
3341                 return -ENOTTY;
3342         }
3343
3344         /* Ensure that we have sane parameters */
3345         if (!write_data) write_len = 0;
3346         if (!read_data) read_len = 0;
3347         if (write_len > PVR2_CTL_BUFFSIZE) {
3348                 pvr2_trace(
3349                         PVR2_TRACE_ERROR_LEGS,
3350                         "Attempted to execute %d byte"
3351                         " control-write transfer (limit=%d)",
3352                         write_len,PVR2_CTL_BUFFSIZE);
3353                 return -EINVAL;
3354         }
3355         if (read_len > PVR2_CTL_BUFFSIZE) {
3356                 pvr2_trace(
3357                         PVR2_TRACE_ERROR_LEGS,
3358                         "Attempted to execute %d byte"
3359                         " control-read transfer (limit=%d)",
3360                         write_len,PVR2_CTL_BUFFSIZE);
3361                 return -EINVAL;
3362         }
3363         if ((!write_len) && (!read_len)) {
3364                 pvr2_trace(
3365                         PVR2_TRACE_ERROR_LEGS,
3366                         "Attempted to execute null control transfer?");
3367                 return -EINVAL;
3368         }
3369
3370
3371         hdw->cmd_debug_state = 1;
3372         if (write_len) {
3373                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3374         } else {
3375                 hdw->cmd_debug_code = 0;
3376         }
3377         hdw->cmd_debug_write_len = write_len;
3378         hdw->cmd_debug_read_len = read_len;
3379
3380         /* Initialize common stuff */
3381         init_completion(&hdw->ctl_done);
3382         hdw->ctl_timeout_flag = 0;
3383         hdw->ctl_write_pend_flag = 0;
3384         hdw->ctl_read_pend_flag = 0;
3385         init_timer(&timer);
3386         timer.expires = jiffies + timeout;
3387         timer.data = (unsigned long)hdw;
3388         timer.function = pvr2_ctl_timeout;
3389
3390         if (write_len) {
3391                 hdw->cmd_debug_state = 2;
3392                 /* Transfer write data to internal buffer */
3393                 for (idx = 0; idx < write_len; idx++) {
3394                         hdw->ctl_write_buffer[idx] =
3395                                 ((unsigned char *)write_data)[idx];
3396                 }
3397                 /* Initiate a write request */
3398                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3399                                   hdw->usb_dev,
3400                                   usb_sndbulkpipe(hdw->usb_dev,
3401                                                   PVR2_CTL_WRITE_ENDPOINT),
3402                                   hdw->ctl_write_buffer,
3403                                   write_len,
3404                                   pvr2_ctl_write_complete,
3405                                   hdw);
3406                 hdw->ctl_write_urb->actual_length = 0;
3407                 hdw->ctl_write_pend_flag = !0;
3408                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3409                 if (status < 0) {
3410                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3411                                    "Failed to submit write-control"
3412                                    " URB status=%d",status);
3413                         hdw->ctl_write_pend_flag = 0;
3414                         goto done;
3415                 }
3416         }
3417
3418         if (read_len) {
3419                 hdw->cmd_debug_state = 3;
3420                 memset(hdw->ctl_read_buffer,0x43,read_len);
3421                 /* Initiate a read request */
3422                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3423                                   hdw->usb_dev,
3424                                   usb_rcvbulkpipe(hdw->usb_dev,
3425                                                   PVR2_CTL_READ_ENDPOINT),
3426                                   hdw->ctl_read_buffer,
3427                                   read_len,
3428                                   pvr2_ctl_read_complete,
3429                                   hdw);
3430                 hdw->ctl_read_urb->actual_length = 0;
3431                 hdw->ctl_read_pend_flag = !0;
3432                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3433                 if (status < 0) {
3434                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3435                                    "Failed to submit read-control"
3436                                    " URB status=%d",status);
3437                         hdw->ctl_read_pend_flag = 0;
3438                         goto done;
3439                 }
3440         }
3441
3442         /* Start timer */
3443         add_timer(&timer);
3444
3445         /* Now wait for all I/O to complete */
3446         hdw->cmd_debug_state = 4;
3447         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3448                 wait_for_completion(&hdw->ctl_done);
3449         }
3450         hdw->cmd_debug_state = 5;
3451
3452         /* Stop timer */
3453         del_timer_sync(&timer);
3454
3455         hdw->cmd_debug_state = 6;
3456         status = 0;
3457
3458         if (hdw->ctl_timeout_flag) {
3459                 status = -ETIMEDOUT;
3460                 if (!probe_fl) {
3461                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3462                                    "Timed out control-write");
3463                 }
3464                 goto done;
3465         }
3466
3467         if (write_len) {
3468                 /* Validate results of write request */
3469                 if ((hdw->ctl_write_urb->status != 0) &&
3470                     (hdw->ctl_write_urb->status != -ENOENT) &&
3471                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3472                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3473                         /* USB subsystem is reporting some kind of failure
3474                            on the write */
3475                         status = hdw->ctl_write_urb->status;
3476                         if (!probe_fl) {
3477                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3478                                            "control-write URB failure,"
3479                                            " status=%d",
3480                                            status);
3481                         }
3482                         goto done;
3483                 }
3484                 if (hdw->ctl_write_urb->actual_length < write_len) {
3485                         /* Failed to write enough data */
3486                         status = -EIO;
3487                         if (!probe_fl) {
3488                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3489                                            "control-write URB short,"
3490                                            " expected=%d got=%d",
3491                                            write_len,
3492                                            hdw->ctl_write_urb->actual_length);
3493                         }
3494                         goto done;
3495                 }
3496         }
3497         if (read_len) {
3498                 /* Validate results of read request */
3499                 if ((hdw->ctl_read_urb->status != 0) &&
3500                     (hdw->ctl_read_urb->status != -ENOENT) &&
3501                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3502                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3503                         /* USB subsystem is reporting some kind of failure
3504                            on the read */
3505                         status = hdw->ctl_read_urb->status;
3506                         if (!probe_fl) {
3507                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3508                                            "control-read URB failure,"
3509                                            " status=%d",
3510                                            status);
3511                         }
3512                         goto done;
3513                 }
3514                 if (hdw->ctl_read_urb->actual_length < read_len) {
3515                         /* Failed to read enough data */
3516                         status = -EIO;
3517                         if (!probe_fl) {
3518                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3519                                            "control-read URB short,"
3520                                            " expected=%d got=%d",
3521                                            read_len,
3522                                            hdw->ctl_read_urb->actual_length);
3523                         }
3524                         goto done;
3525                 }
3526                 /* Transfer retrieved data out from internal buffer */
3527                 for (idx = 0; idx < read_len; idx++) {
3528                         ((unsigned char *)read_data)[idx] =
3529                                 hdw->ctl_read_buffer[idx];
3530                 }
3531         }
3532
3533  done:
3534
3535         hdw->cmd_debug_state = 0;
3536         if ((status < 0) && (!probe_fl)) {
3537                 pvr2_hdw_render_useless(hdw);
3538         }
3539         return status;
3540 }
3541
3542
3543 int pvr2_send_request(struct pvr2_hdw *hdw,
3544                       void *write_data,unsigned int write_len,
3545                       void *read_data,unsigned int read_len)
3546 {
3547         return pvr2_send_request_ex(hdw,HZ*4,0,
3548                                     write_data,write_len,
3549                                     read_data,read_len);
3550 }
3551
3552
3553 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3554 {
3555         int ret;
3556         unsigned int cnt = 1;
3557         unsigned int args = 0;
3558         LOCK_TAKE(hdw->ctl_lock);
3559         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3560         args = (cmdcode >> 8) & 0xffu;
3561         args = (args > 2) ? 2 : args;
3562         if (args) {
3563                 cnt += args;
3564                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3565                 if (args > 1) {
3566                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3567                 }
3568         }
3569         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3570                 unsigned int idx;
3571                 unsigned int ccnt,bcnt;
3572                 char tbuf[50];
3573                 cmdcode &= 0xffu;
3574                 bcnt = 0;
3575                 ccnt = scnprintf(tbuf+bcnt,
3576                                  sizeof(tbuf)-bcnt,
3577                                  "Sending FX2 command 0x%x",cmdcode);
3578                 bcnt += ccnt;
3579                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3580                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3581                                 ccnt = scnprintf(tbuf+bcnt,
3582                                                  sizeof(tbuf)-bcnt,
3583                                                  " \"%s\"",
3584                                                  pvr2_fx2cmd_desc[idx].desc);
3585                                 bcnt += ccnt;
3586                                 break;
3587                         }
3588                 }
3589                 if (args) {
3590                         ccnt = scnprintf(tbuf+bcnt,
3591                                          sizeof(tbuf)-bcnt,
3592                                          " (%u",hdw->cmd_buffer[1]);
3593                         bcnt += ccnt;
3594                         if (args > 1) {
3595                                 ccnt = scnprintf(tbuf+bcnt,
3596                                                  sizeof(tbuf)-bcnt,
3597                                                  ",%u",hdw->cmd_buffer[2]);
3598                                 bcnt += ccnt;
3599                         }
3600                         ccnt = scnprintf(tbuf+bcnt,
3601                                          sizeof(tbuf)-bcnt,
3602                                          ")");
3603                         bcnt += ccnt;
3604                 }
3605                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3606         }
3607         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3608         LOCK_GIVE(hdw->ctl_lock);
3609         return ret;
3610 }
3611
3612
3613 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3614 {
3615         int ret;
3616
3617         LOCK_TAKE(hdw->ctl_lock);
3618
3619         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3620         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3621         hdw->cmd_buffer[5] = 0;
3622         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3623         hdw->cmd_buffer[7] = reg & 0xff;
3624
3625
3626         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3627
3628         LOCK_GIVE(hdw->ctl_lock);
3629
3630         return ret;
3631 }
3632
3633
3634 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3635 {
3636         int ret = 0;
3637
3638         LOCK_TAKE(hdw->ctl_lock);
3639
3640         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3641         hdw->cmd_buffer[1] = 0;
3642         hdw->cmd_buffer[2] = 0;
3643         hdw->cmd_buffer[3] = 0;
3644         hdw->cmd_buffer[4] = 0;
3645         hdw->cmd_buffer[5] = 0;
3646         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3647         hdw->cmd_buffer[7] = reg & 0xff;
3648
3649         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3650         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3651
3652         LOCK_GIVE(hdw->ctl_lock);
3653
3654         return ret;
3655 }
3656
3657
3658 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3659 {
3660         if (!hdw->flag_ok) return;
3661         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3662                    "Device being rendered inoperable");
3663         if (hdw->vid_stream) {
3664                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3665         }
3666         hdw->flag_ok = 0;
3667         trace_stbit("flag_ok",hdw->flag_ok);
3668         pvr2_hdw_state_sched(hdw);
3669 }
3670
3671
3672 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3673 {
3674         int ret;
3675         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3676         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3677         if (ret == 0) {
3678                 ret = usb_reset_device(hdw->usb_dev);
3679                 usb_unlock_device(hdw->usb_dev);
3680         } else {
3681                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3682                            "Failed to lock USB device ret=%d",ret);
3683         }
3684         if (init_pause_msec) {
3685                 pvr2_trace(PVR2_TRACE_INFO,
3686                            "Waiting %u msec for hardware to settle",
3687                            init_pause_msec);
3688                 msleep(init_pause_msec);
3689         }
3690
3691 }
3692
3693
3694 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3695 {
3696         char da[1];
3697         unsigned int pipe;
3698         int ret;
3699
3700         if (!hdw->usb_dev) return;
3701
3702         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3703
3704         da[0] = val ? 0x01 : 0x00;
3705
3706         /* Write the CPUCS register on the 8051.  The lsb of the register
3707            is the reset bit; a 1 asserts reset while a 0 clears it. */
3708         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3709         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3710         if (ret < 0) {
3711                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3712                            "cpureset_assert(%d) error=%d",val,ret);
3713                 pvr2_hdw_render_useless(hdw);
3714         }
3715 }
3716
3717
3718 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3719 {
3720         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
3721 }
3722
3723
3724 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3725 {
3726         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
3727 }
3728
3729
3730 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
3731 {
3732         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
3733 }
3734
3735
3736 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3737 {
3738         if (!hdw->decoder_ctrl) {
3739                 pvr2_trace(PVR2_TRACE_INIT,
3740                            "Unable to reset decoder: nothing attached");
3741                 return -ENOTTY;
3742         }
3743
3744         if (!hdw->decoder_ctrl->force_reset) {
3745                 pvr2_trace(PVR2_TRACE_INIT,
3746                            "Unable to reset decoder: not implemented");
3747                 return -ENOTTY;
3748         }
3749
3750         pvr2_trace(PVR2_TRACE_INIT,
3751                    "Requesting decoder reset");
3752         hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3753         return 0;
3754 }
3755
3756
3757 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
3758 {
3759         hdw->flag_ok = !0;
3760         return pvr2_issue_simple_cmd(hdw,
3761                                      FX2CMD_HCW_DEMOD_RESETIN |
3762                                      (1 << 8) |
3763                                      ((onoff ? 1 : 0) << 16));
3764 }
3765
3766
3767 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
3768 {
3769         hdw->flag_ok = !0;
3770         return pvr2_issue_simple_cmd(hdw,(onoff ?
3771                                           FX2CMD_ONAIR_DTV_POWER_ON :
3772                                           FX2CMD_ONAIR_DTV_POWER_OFF));
3773 }
3774
3775
3776 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
3777                                                 int onoff)
3778 {
3779         return pvr2_issue_simple_cmd(hdw,(onoff ?
3780                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
3781                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
3782 }
3783
3784
3785 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
3786 {
3787         int cmode;
3788         /* Compare digital/analog desired setting with current setting.  If
3789            they don't match, fix it... */
3790         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
3791         if (cmode == hdw->pathway_state) {
3792                 /* They match; nothing to do */
3793                 return;
3794         }
3795
3796         switch (hdw->hdw_desc->digital_control_scheme) {
3797         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3798                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
3799                 if (cmode == PVR2_PATHWAY_ANALOG) {
3800                         /* If moving to analog mode, also force the decoder
3801                            to reset.  If no decoder is attached, then it's
3802                            ok to ignore this because if/when the decoder
3803                            attaches, it will reset itself at that time. */
3804                         pvr2_hdw_cmd_decoder_reset(hdw);
3805                 }
3806                 break;
3807         case PVR2_DIGITAL_SCHEME_ONAIR:
3808                 /* Supposedly we should always have the power on whether in
3809                    digital or analog mode.  But for now do what appears to
3810                    work... */
3811                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
3812                 break;
3813         default: break;
3814         }
3815
3816         pvr2_hdw_untrip_unlocked(hdw);
3817         hdw->pathway_state = cmode;
3818 }
3819
3820
3821 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
3822 {
3823         /* change some GPIO data
3824          *
3825          * note: bit d7 of dir appears to control the LED,
3826          * so we shut it off here.
3827          *
3828          */
3829         if (onoff) {
3830                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
3831         } else {
3832                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
3833         }
3834         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
3835 }
3836
3837
3838 typedef void (*led_method_func)(struct pvr2_hdw *,int);
3839
3840 static led_method_func led_methods[] = {
3841         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
3842 };
3843
3844
3845 /* Toggle LED */
3846 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
3847 {
3848         unsigned int scheme_id;
3849         led_method_func fp;
3850
3851         if ((!onoff) == (!hdw->led_on)) return;
3852
3853         hdw->led_on = onoff != 0;
3854
3855         scheme_id = hdw->hdw_desc->led_scheme;
3856         if (scheme_id < ARRAY_SIZE(led_methods)) {
3857                 fp = led_methods[scheme_id];
3858         } else {
3859                 fp = NULL;
3860         }
3861
3862         if (fp) (*fp)(hdw,onoff);
3863 }
3864
3865
3866 /* Stop / start video stream transport */
3867 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3868 {
3869         int ret;
3870
3871         /* If we're in analog mode, then just issue the usual analog
3872            command. */
3873         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3874                 return pvr2_issue_simple_cmd(hdw,
3875                                              (runFl ?
3876                                               FX2CMD_STREAMING_ON :
3877                                               FX2CMD_STREAMING_OFF));
3878                 /*Note: Not reached */
3879         }
3880
3881         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
3882                 /* Whoops, we don't know what mode we're in... */
3883                 return -EINVAL;
3884         }
3885
3886         /* To get here we have to be in digital mode.  The mechanism here
3887            is unfortunately different for different vendors.  So we switch
3888            on the device's digital scheme attribute in order to figure out
3889            what to do. */
3890         switch (hdw->hdw_desc->digital_control_scheme) {
3891         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3892                 return pvr2_issue_simple_cmd(hdw,
3893                                              (runFl ?
3894                                               FX2CMD_HCW_DTV_STREAMING_ON :
3895                                               FX2CMD_HCW_DTV_STREAMING_OFF));
3896         case PVR2_DIGITAL_SCHEME_ONAIR:
3897                 ret = pvr2_issue_simple_cmd(hdw,
3898                                             (runFl ?
3899                                              FX2CMD_STREAMING_ON :
3900                                              FX2CMD_STREAMING_OFF));
3901                 if (ret) return ret;
3902                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
3903         default:
3904                 return -EINVAL;
3905         }
3906 }
3907
3908
3909 /* Evaluate whether or not state_pathway_ok can change */
3910 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
3911 {
3912         if (hdw->state_pathway_ok) {
3913                 /* Nothing to do if pathway is already ok */
3914                 return 0;
3915         }
3916         if (!hdw->state_pipeline_idle) {
3917                 /* Not allowed to change anything if pipeline is not idle */
3918                 return 0;
3919         }
3920         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
3921         hdw->state_pathway_ok = !0;
3922         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3923         return !0;
3924 }
3925
3926
3927 /* Evaluate whether or not state_encoder_ok can change */
3928 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
3929 {
3930         if (hdw->state_encoder_ok) return 0;
3931         if (hdw->flag_tripped) return 0;
3932         if (hdw->state_encoder_run) return 0;
3933         if (hdw->state_encoder_config) return 0;
3934         if (hdw->state_decoder_run) return 0;
3935         if (hdw->state_usbstream_run) return 0;
3936         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
3937                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
3938         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
3939                 return 0;
3940         }
3941
3942         if (pvr2_upload_firmware2(hdw) < 0) {
3943                 hdw->flag_tripped = !0;
3944                 trace_stbit("flag_tripped",hdw->flag_tripped);
3945                 return !0;
3946         }
3947         hdw->state_encoder_ok = !0;
3948         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
3949         return !0;
3950 }
3951
3952
3953 /* Evaluate whether or not state_encoder_config can change */
3954 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
3955 {
3956         if (hdw->state_encoder_config) {
3957                 if (hdw->state_encoder_ok) {
3958                         if (hdw->state_pipeline_req &&
3959                             !hdw->state_pipeline_pause) return 0;
3960                 }
3961                 hdw->state_encoder_config = 0;
3962                 hdw->state_encoder_waitok = 0;
3963                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3964                 /* paranoia - solve race if timer just completed */
3965                 del_timer_sync(&hdw->encoder_wait_timer);
3966         } else {
3967                 if (!hdw->state_pathway_ok ||
3968                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3969                     !hdw->state_encoder_ok ||
3970                     !hdw->state_pipeline_idle ||
3971                     hdw->state_pipeline_pause ||
3972                     !hdw->state_pipeline_req ||
3973                     !hdw->state_pipeline_config) {
3974                         /* We must reset the enforced wait interval if
3975                            anything has happened that might have disturbed
3976                            the encoder.  This should be a rare case. */
3977                         if (timer_pending(&hdw->encoder_wait_timer)) {
3978                                 del_timer_sync(&hdw->encoder_wait_timer);
3979                         }
3980                         if (hdw->state_encoder_waitok) {
3981                                 /* Must clear the state - therefore we did
3982                                    something to a state bit and must also
3983                                    return true. */
3984                                 hdw->state_encoder_waitok = 0;
3985                                 trace_stbit("state_encoder_waitok",
3986                                             hdw->state_encoder_waitok);
3987                                 return !0;
3988                         }
3989                         return 0;
3990                 }
3991                 if (!hdw->state_encoder_waitok) {
3992                         if (!timer_pending(&hdw->encoder_wait_timer)) {
3993                                 /* waitok flag wasn't set and timer isn't
3994                                    running.  Check flag once more to avoid
3995                                    a race then start the timer.  This is
3996                                    the point when we measure out a minimal
3997                                    quiet interval before doing something to
3998                                    the encoder. */
3999                                 if (!hdw->state_encoder_waitok) {
4000                                         hdw->encoder_wait_timer.expires =
4001                                                 jiffies +
4002                                                 (HZ * TIME_MSEC_ENCODER_WAIT
4003                                                  / 1000);
4004                                         add_timer(&hdw->encoder_wait_timer);
4005                                 }
4006                         }
4007                         /* We can't continue until we know we have been
4008                            quiet for the interval measured by this
4009                            timer. */
4010                         return 0;
4011                 }
4012                 pvr2_encoder_configure(hdw);
4013                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4014         }
4015         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4016         return !0;
4017 }
4018
4019
4020 /* Return true if the encoder should not be running. */
4021 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4022 {
4023         if (!hdw->state_encoder_ok) {
4024                 /* Encoder isn't healthy at the moment, so stop it. */
4025                 return !0;
4026         }
4027         if (!hdw->state_pathway_ok) {
4028                 /* Mode is not understood at the moment (i.e. it wants to
4029                    change), so encoder must be stopped. */
4030                 return !0;
4031         }
4032
4033         switch (hdw->pathway_state) {
4034         case PVR2_PATHWAY_ANALOG:
4035                 if (!hdw->state_decoder_run) {
4036                         /* We're in analog mode and the decoder is not
4037                            running; thus the encoder should be stopped as
4038                            well. */
4039                         return !0;
4040                 }
4041                 break;
4042         case PVR2_PATHWAY_DIGITAL:
4043                 if (hdw->state_encoder_runok) {
4044                         /* This is a funny case.  We're in digital mode so
4045                            really the encoder should be stopped.  However
4046                            if it really is running, only kill it after
4047                            runok has been set.  This gives a chance for the
4048                            onair quirk to function (encoder must run
4049                            briefly first, at least once, before onair
4050                            digital streaming can work). */
4051                         return !0;
4052                 }
4053                 break;
4054         default:
4055                 /* Unknown mode; so encoder should be stopped. */
4056                 return !0;
4057         }
4058
4059         /* If we get here, we haven't found a reason to stop the
4060            encoder. */
4061         return 0;
4062 }
4063
4064
4065 /* Return true if the encoder should be running. */
4066 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4067 {
4068         if (!hdw->state_encoder_ok) {
4069                 /* Don't run the encoder if it isn't healthy... */
4070                 return 0;
4071         }
4072         if (!hdw->state_pathway_ok) {
4073                 /* Don't run the encoder if we don't (yet) know what mode
4074                    we need to be in... */
4075                 return 0;
4076         }
4077
4078         switch (hdw->pathway_state) {
4079         case PVR2_PATHWAY_ANALOG:
4080                 if (hdw->state_decoder_run) {
4081                         /* In analog mode, if the decoder is running, then
4082                            run the encoder. */
4083                         return !0;
4084                 }
4085                 break;
4086         case PVR2_PATHWAY_DIGITAL:
4087                 if ((hdw->hdw_desc->digital_control_scheme ==
4088                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4089                     !hdw->state_encoder_runok) {
4090                         /* This is a quirk.  OnAir hardware won't stream
4091                            digital until the encoder has been run at least
4092                            once, for a minimal period of time (empiricially
4093                            measured to be 1/4 second).  So if we're on
4094                            OnAir hardware and the encoder has never been
4095                            run at all, then start the encoder.  Normal
4096                            state machine logic in the driver will
4097                            automatically handle the remaining bits. */
4098                         return !0;
4099                 }
4100                 break;
4101         default:
4102                 /* For completeness (unknown mode; encoder won't run ever) */
4103                 break;
4104         }
4105         /* If we get here, then we haven't found any reason to run the
4106            encoder, so don't run it. */
4107         return 0;
4108 }
4109
4110
4111 /* Evaluate whether or not state_encoder_run can change */
4112 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4113 {
4114         if (hdw->state_encoder_run) {
4115                 if (!state_check_disable_encoder_run(hdw)) return 0;
4116                 if (hdw->state_encoder_ok) {
4117                         del_timer_sync(&hdw->encoder_run_timer);
4118                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4119                 }
4120                 hdw->state_encoder_run = 0;
4121         } else {
4122                 if (!state_check_enable_encoder_run(hdw)) return 0;
4123                 if (pvr2_encoder_start(hdw) < 0) return !0;
4124                 hdw->state_encoder_run = !0;
4125                 if (!hdw->state_encoder_runok) {
4126                         hdw->encoder_run_timer.expires =
4127                                 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4128                         add_timer(&hdw->encoder_run_timer);
4129                 }
4130         }
4131         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4132         return !0;
4133 }
4134
4135
4136 /* Timeout function for quiescent timer. */
4137 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4138 {
4139         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4140         hdw->state_decoder_quiescent = !0;
4141         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4142         hdw->state_stale = !0;
4143         queue_work(hdw->workqueue,&hdw->workpoll);
4144 }
4145
4146
4147 /* Timeout function for encoder wait timer. */
4148 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4149 {
4150         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4151         hdw->state_encoder_waitok = !0;
4152         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4153         hdw->state_stale = !0;
4154         queue_work(hdw->workqueue,&hdw->workpoll);
4155 }
4156
4157
4158 /* Timeout function for encoder run timer. */
4159 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4160 {
4161         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4162         if (!hdw->state_encoder_runok) {
4163                 hdw->state_encoder_runok = !0;
4164                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4165                 hdw->state_stale = !0;
4166                 queue_work(hdw->workqueue,&hdw->workpoll);
4167         }
4168 }
4169
4170
4171 /* Evaluate whether or not state_decoder_run can change */
4172 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4173 {
4174         if (hdw->state_decoder_run) {
4175                 if (hdw->state_encoder_ok) {
4176                         if (hdw->state_pipeline_req &&
4177                             !hdw->state_pipeline_pause &&
4178                             hdw->state_pathway_ok) return 0;
4179                 }
4180                 if (!hdw->flag_decoder_missed) {
4181                         pvr2_decoder_enable(hdw,0);
4182                 }
4183                 hdw->state_decoder_quiescent = 0;
4184                 hdw->state_decoder_run = 0;
4185                 /* paranoia - solve race if timer just completed */
4186                 del_timer_sync(&hdw->quiescent_timer);
4187         } else {
4188                 if (!hdw->state_decoder_quiescent) {
4189                         if (!timer_pending(&hdw->quiescent_timer)) {
4190                                 /* We don't do something about the
4191                                    quiescent timer until right here because
4192                                    we also want to catch cases where the
4193                                    decoder was already not running (like
4194                                    after initialization) as opposed to
4195                                    knowing that we had just stopped it.
4196                                    The second flag check is here to cover a
4197                                    race - the timer could have run and set
4198                                    this flag just after the previous check
4199                                    but before we did the pending check. */
4200                                 if (!hdw->state_decoder_quiescent) {
4201                                         hdw->quiescent_timer.expires =
4202                                                 jiffies +
4203                                                 (HZ * TIME_MSEC_DECODER_WAIT
4204                                                  / 1000);
4205                                         add_timer(&hdw->quiescent_timer);
4206                                 }
4207                         }
4208                         /* Don't allow decoder to start again until it has
4209                            been quiesced first.  This little detail should
4210                            hopefully further stabilize the encoder. */
4211                         return 0;
4212                 }
4213                 if (!hdw->state_pathway_ok ||
4214                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4215                     !hdw->state_pipeline_req ||
4216                     hdw->state_pipeline_pause ||
4217                     !hdw->state_pipeline_config ||
4218                     !hdw->state_encoder_config ||
4219                     !hdw->state_encoder_ok) return 0;
4220                 del_timer_sync(&hdw->quiescent_timer);
4221                 if (hdw->flag_decoder_missed) return 0;
4222                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4223                 hdw->state_decoder_quiescent = 0;
4224                 hdw->state_decoder_run = !0;
4225         }
4226         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4227         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4228         return !0;
4229 }
4230
4231
4232 /* Evaluate whether or not state_usbstream_run can change */
4233 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4234 {
4235         if (hdw->state_usbstream_run) {
4236                 int fl = !0;
4237                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4238                         fl = (hdw->state_encoder_ok &&
4239                               hdw->state_encoder_run);
4240                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4241                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4242                         fl = hdw->state_encoder_ok;
4243                 }
4244                 if (fl &&
4245                     hdw->state_pipeline_req &&
4246                     !hdw->state_pipeline_pause &&
4247                     hdw->state_pathway_ok) {
4248                         return 0;
4249                 }
4250                 pvr2_hdw_cmd_usbstream(hdw,0);
4251                 hdw->state_usbstream_run = 0;
4252         } else {
4253                 if (!hdw->state_pipeline_req ||
4254                     hdw->state_pipeline_pause ||
4255                     !hdw->state_pathway_ok) return 0;
4256                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4257                         if (!hdw->state_encoder_ok ||
4258                             !hdw->state_encoder_run) return 0;
4259                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4260                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4261                         if (!hdw->state_encoder_ok) return 0;
4262                         if (hdw->state_encoder_run) return 0;
4263                         if (hdw->hdw_desc->digital_control_scheme ==
4264                             PVR2_DIGITAL_SCHEME_ONAIR) {
4265                                 /* OnAir digital receivers won't stream
4266                                    unless the analog encoder has run first.
4267                                    Why?  I have no idea.  But don't even
4268                                    try until we know the analog side is
4269                                    known to have run. */
4270                                 if (!hdw->state_encoder_runok) return 0;
4271                         }
4272                 }
4273                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4274                 hdw->state_usbstream_run = !0;
4275         }
4276         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4277         return !0;
4278 }
4279
4280
4281 /* Attempt to configure pipeline, if needed */
4282 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4283 {
4284         if (hdw->state_pipeline_config ||
4285             hdw->state_pipeline_pause) return 0;
4286         pvr2_hdw_commit_execute(hdw);
4287         return !0;
4288 }
4289
4290
4291 /* Update pipeline idle and pipeline pause tracking states based on other
4292    inputs.  This must be called whenever the other relevant inputs have
4293    changed. */
4294 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4295 {
4296         unsigned int st;
4297         int updatedFl = 0;
4298         /* Update pipeline state */
4299         st = !(hdw->state_encoder_run ||
4300                hdw->state_decoder_run ||
4301                hdw->state_usbstream_run ||
4302                (!hdw->state_decoder_quiescent));
4303         if (!st != !hdw->state_pipeline_idle) {
4304                 hdw->state_pipeline_idle = st;
4305                 updatedFl = !0;
4306         }
4307         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4308                 hdw->state_pipeline_pause = 0;
4309                 updatedFl = !0;
4310         }
4311         return updatedFl;
4312 }
4313
4314
4315 typedef int (*state_eval_func)(struct pvr2_hdw *);
4316
4317 /* Set of functions to be run to evaluate various states in the driver. */
4318 static const state_eval_func eval_funcs[] = {
4319         state_eval_pathway_ok,
4320         state_eval_pipeline_config,
4321         state_eval_encoder_ok,
4322         state_eval_encoder_config,
4323         state_eval_decoder_run,
4324         state_eval_encoder_run,
4325         state_eval_usbstream_run,
4326 };
4327
4328
4329 /* Process various states and return true if we did anything interesting. */
4330 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4331 {
4332         unsigned int i;
4333         int state_updated = 0;
4334         int check_flag;
4335
4336         if (!hdw->state_stale) return 0;
4337         if ((hdw->fw1_state != FW1_STATE_OK) ||
4338             !hdw->flag_ok) {
4339                 hdw->state_stale = 0;
4340                 return !0;
4341         }
4342         /* This loop is the heart of the entire driver.  It keeps trying to
4343            evaluate various bits of driver state until nothing changes for
4344            one full iteration.  Each "bit of state" tracks some global
4345            aspect of the driver, e.g. whether decoder should run, if
4346            pipeline is configured, usb streaming is on, etc.  We separately
4347            evaluate each of those questions based on other driver state to
4348            arrive at the correct running configuration. */
4349         do {
4350                 check_flag = 0;
4351                 state_update_pipeline_state(hdw);
4352                 /* Iterate over each bit of state */
4353                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4354                         if ((*eval_funcs[i])(hdw)) {
4355                                 check_flag = !0;
4356                                 state_updated = !0;
4357                                 state_update_pipeline_state(hdw);
4358                         }
4359                 }
4360         } while (check_flag && hdw->flag_ok);
4361         hdw->state_stale = 0;
4362         trace_stbit("state_stale",hdw->state_stale);
4363         return state_updated;
4364 }
4365
4366
4367 static unsigned int print_input_mask(unsigned int msk,
4368                                      char *buf,unsigned int acnt)
4369 {
4370         unsigned int idx,ccnt;
4371         unsigned int tcnt = 0;
4372         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4373                 if (!((1 << idx) & msk)) continue;
4374                 ccnt = scnprintf(buf+tcnt,
4375                                  acnt-tcnt,
4376                                  "%s%s",
4377                                  (tcnt ? ", " : ""),
4378                                  control_values_input[idx]);
4379                 tcnt += ccnt;
4380         }
4381         return tcnt;
4382 }
4383
4384
4385 static const char *pvr2_pathway_state_name(int id)
4386 {
4387         switch (id) {
4388         case PVR2_PATHWAY_ANALOG: return "analog";
4389         case PVR2_PATHWAY_DIGITAL: return "digital";
4390         default: return "unknown";
4391         }
4392 }
4393
4394
4395 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4396                                              char *buf,unsigned int acnt)
4397 {
4398         switch (which) {
4399         case 0:
4400                 return scnprintf(
4401                         buf,acnt,
4402                         "driver:%s%s%s%s%s <mode=%s>",
4403                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4404                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4405                         (hdw->flag_disconnected ? " <disconnected>" :
4406                          " <connected>"),
4407                         (hdw->flag_tripped ? " <tripped>" : ""),
4408                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4409                         pvr2_pathway_state_name(hdw->pathway_state));
4410
4411         case 1:
4412                 return scnprintf(
4413                         buf,acnt,
4414                         "pipeline:%s%s%s%s",
4415                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4416                         (hdw->state_pipeline_config ?
4417                          " <configok>" : " <stale>"),
4418                         (hdw->state_pipeline_req ? " <req>" : ""),
4419                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4420         case 2:
4421                 return scnprintf(
4422                         buf,acnt,
4423                         "worker:%s%s%s%s%s%s%s",
4424                         (hdw->state_decoder_run ?
4425                          " <decode:run>" :
4426                          (hdw->state_decoder_quiescent ?
4427                           "" : " <decode:stop>")),
4428                         (hdw->state_decoder_quiescent ?
4429                          " <decode:quiescent>" : ""),
4430                         (hdw->state_encoder_ok ?
4431                          "" : " <encode:init>"),
4432                         (hdw->state_encoder_run ?
4433                          (hdw->state_encoder_runok ?
4434                           " <encode:run>" :
4435                           " <encode:firstrun>") :
4436                          (hdw->state_encoder_runok ?
4437                           " <encode:stop>" :
4438                           " <encode:virgin>")),
4439                         (hdw->state_encoder_config ?
4440                          " <encode:configok>" :
4441                          (hdw->state_encoder_waitok ?
4442                           "" : " <encode:waitok>")),
4443                         (hdw->state_usbstream_run ?
4444                          " <usb:run>" : " <usb:stop>"),
4445                         (hdw->state_pathway_ok ?
4446                          " <pathway:ok>" : ""));
4447         case 3:
4448                 return scnprintf(
4449                         buf,acnt,
4450                         "state: %s",
4451                         pvr2_get_state_name(hdw->master_state));
4452         case 4: {
4453                 unsigned int tcnt = 0;
4454                 unsigned int ccnt;
4455
4456                 ccnt = scnprintf(buf,
4457                                  acnt,
4458                                  "Hardware supported inputs: ");
4459                 tcnt += ccnt;
4460                 tcnt += print_input_mask(hdw->input_avail_mask,
4461                                          buf+tcnt,
4462                                          acnt-tcnt);
4463                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4464                         ccnt = scnprintf(buf+tcnt,
4465                                          acnt-tcnt,
4466                                          "; allowed inputs: ");
4467                         tcnt += ccnt;
4468                         tcnt += print_input_mask(hdw->input_allowed_mask,
4469                                                  buf+tcnt,
4470                                                  acnt-tcnt);
4471                 }
4472                 return tcnt;
4473         }
4474         case 5: {
4475                 struct pvr2_stream_stats stats;
4476                 if (!hdw->vid_stream) break;
4477                 pvr2_stream_get_stats(hdw->vid_stream,
4478                                       &stats,
4479                                       0);
4480                 return scnprintf(
4481                         buf,acnt,
4482                         "Bytes streamed=%u"
4483                         " URBs: queued=%u idle=%u ready=%u"
4484                         " processed=%u failed=%u",
4485                         stats.bytes_processed,
4486                         stats.buffers_in_queue,
4487                         stats.buffers_in_idle,
4488                         stats.buffers_in_ready,
4489                         stats.buffers_processed,
4490                         stats.buffers_failed);
4491         }
4492         default: break;
4493         }
4494         return 0;
4495 }
4496
4497
4498 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4499                                    char *buf,unsigned int acnt)
4500 {
4501         unsigned int bcnt,ccnt,idx;
4502         bcnt = 0;
4503         LOCK_TAKE(hdw->big_lock);
4504         for (idx = 0; ; idx++) {
4505                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4506                 if (!ccnt) break;
4507                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4508                 if (!acnt) break;
4509                 buf[0] = '\n'; ccnt = 1;
4510                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4511         }
4512         LOCK_GIVE(hdw->big_lock);
4513         return bcnt;
4514 }
4515
4516
4517 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4518 {
4519         char buf[128];
4520         unsigned int idx,ccnt;
4521
4522         for (idx = 0; ; idx++) {
4523                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4524                 if (!ccnt) break;
4525                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4526         }
4527 }
4528
4529
4530 /* Evaluate and update the driver's current state, taking various actions
4531    as appropriate for the update. */
4532 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4533 {
4534         unsigned int st;
4535         int state_updated = 0;
4536         int callback_flag = 0;
4537         int analog_mode;
4538
4539         pvr2_trace(PVR2_TRACE_STBITS,
4540                    "Drive state check START");
4541         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4542                 pvr2_hdw_state_log_state(hdw);
4543         }
4544
4545         /* Process all state and get back over disposition */
4546         state_updated = pvr2_hdw_state_update(hdw);
4547
4548         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4549
4550         /* Update master state based upon all other states. */
4551         if (!hdw->flag_ok) {
4552                 st = PVR2_STATE_DEAD;
4553         } else if (hdw->fw1_state != FW1_STATE_OK) {
4554                 st = PVR2_STATE_COLD;
4555         } else if ((analog_mode ||
4556                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4557                    !hdw->state_encoder_ok) {
4558                 st = PVR2_STATE_WARM;
4559         } else if (hdw->flag_tripped ||
4560                    (analog_mode && hdw->flag_decoder_missed)) {
4561                 st = PVR2_STATE_ERROR;
4562         } else if (hdw->state_usbstream_run &&
4563                    (!analog_mode ||
4564                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4565                 st = PVR2_STATE_RUN;
4566         } else {
4567                 st = PVR2_STATE_READY;
4568         }
4569         if (hdw->master_state != st) {
4570                 pvr2_trace(PVR2_TRACE_STATE,
4571                            "Device state change from %s to %s",
4572                            pvr2_get_state_name(hdw->master_state),
4573                            pvr2_get_state_name(st));
4574                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4575                 hdw->master_state = st;
4576                 state_updated = !0;
4577                 callback_flag = !0;
4578         }
4579         if (state_updated) {
4580                 /* Trigger anyone waiting on any state changes here. */
4581                 wake_up(&hdw->state_wait_data);
4582         }
4583
4584         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4585                 pvr2_hdw_state_log_state(hdw);
4586         }
4587         pvr2_trace(PVR2_TRACE_STBITS,
4588                    "Drive state check DONE callback=%d",callback_flag);
4589
4590         return callback_flag;
4591 }
4592
4593
4594 /* Cause kernel thread to check / update driver state */
4595 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4596 {
4597         if (hdw->state_stale) return;
4598         hdw->state_stale = !0;
4599         trace_stbit("state_stale",hdw->state_stale);
4600         queue_work(hdw->workqueue,&hdw->workpoll);
4601 }
4602
4603
4604 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4605 {
4606         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4607 }
4608
4609
4610 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4611 {
4612         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4613 }
4614
4615
4616 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4617 {
4618         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4619 }
4620
4621
4622 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4623 {
4624         u32 cval,nval;
4625         int ret;
4626         if (~msk) {
4627                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4628                 if (ret) return ret;
4629                 nval = (cval & ~msk) | (val & msk);
4630                 pvr2_trace(PVR2_TRACE_GPIO,
4631                            "GPIO direction changing 0x%x:0x%x"
4632                            " from 0x%x to 0x%x",
4633                            msk,val,cval,nval);
4634         } else {
4635                 nval = val;
4636                 pvr2_trace(PVR2_TRACE_GPIO,
4637                            "GPIO direction changing to 0x%x",nval);
4638         }
4639         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4640 }
4641
4642
4643 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4644 {
4645         u32 cval,nval;
4646         int ret;
4647         if (~msk) {
4648                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4649                 if (ret) return ret;
4650                 nval = (cval & ~msk) | (val & msk);
4651                 pvr2_trace(PVR2_TRACE_GPIO,
4652                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4653                            msk,val,cval,nval);
4654         } else {
4655                 nval = val;
4656                 pvr2_trace(PVR2_TRACE_GPIO,
4657                            "GPIO output changing to 0x%x",nval);
4658         }
4659         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4660 }
4661
4662
4663 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
4664 {
4665         return hdw->input_avail_mask;
4666 }
4667
4668
4669 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
4670 {
4671         return hdw->input_allowed_mask;
4672 }
4673
4674
4675 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
4676 {
4677         if (hdw->input_val != v) {
4678                 hdw->input_val = v;
4679                 hdw->input_dirty = !0;
4680         }
4681
4682         /* Handle side effects - if we switch to a mode that needs the RF
4683            tuner, then select the right frequency choice as well and mark
4684            it dirty. */
4685         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
4686                 hdw->freqSelector = 0;
4687                 hdw->freqDirty = !0;
4688         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
4689                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
4690                 hdw->freqSelector = 1;
4691                 hdw->freqDirty = !0;
4692         }
4693         return 0;
4694 }
4695
4696
4697 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
4698                                unsigned int change_mask,
4699                                unsigned int change_val)
4700 {
4701         int ret = 0;
4702         unsigned int nv,m,idx;
4703         LOCK_TAKE(hdw->big_lock);
4704         do {
4705                 nv = hdw->input_allowed_mask & ~change_mask;
4706                 nv |= (change_val & change_mask);
4707                 nv &= hdw->input_avail_mask;
4708                 if (!nv) {
4709                         /* No legal modes left; return error instead. */
4710                         ret = -EPERM;
4711                         break;
4712                 }
4713                 hdw->input_allowed_mask = nv;
4714                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
4715                         /* Current mode is still in the allowed mask, so
4716                            we're done. */
4717                         break;
4718                 }
4719                 /* Select and switch to a mode that is still in the allowed
4720                    mask */
4721                 if (!hdw->input_allowed_mask) {
4722                         /* Nothing legal; give up */
4723                         break;
4724                 }
4725                 m = hdw->input_allowed_mask;
4726                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
4727                         if (!((1 << idx) & m)) continue;
4728                         pvr2_hdw_set_input(hdw,idx);
4729                         break;
4730                 }
4731         } while (0);
4732         LOCK_GIVE(hdw->big_lock);
4733         return ret;
4734 }
4735
4736
4737 /* Find I2C address of eeprom */
4738 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
4739 {
4740         int result;
4741         LOCK_TAKE(hdw->ctl_lock); do {
4742                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
4743                 result = pvr2_send_request(hdw,
4744                                            hdw->cmd_buffer,1,
4745                                            hdw->cmd_buffer,1);
4746                 if (result < 0) break;
4747                 result = hdw->cmd_buffer[0];
4748         } while(0); LOCK_GIVE(hdw->ctl_lock);
4749         return result;
4750 }
4751
4752
4753 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
4754                              struct v4l2_dbg_match *match, u64 reg_id,
4755                              int setFl, u64 *val_ptr)
4756 {
4757 #ifdef CONFIG_VIDEO_ADV_DEBUG
4758         struct pvr2_i2c_client *cp;
4759         struct v4l2_dbg_register req;
4760         int stat = 0;
4761         int okFl = 0;
4762
4763         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
4764
4765         req.match = *match;
4766         req.reg = reg_id;
4767         if (setFl) req.val = *val_ptr;
4768         mutex_lock(&hdw->i2c_list_lock); do {
4769                 list_for_each_entry(cp, &hdw->i2c_clients, list) {
4770                         if (!v4l2_chip_match_i2c_client(
4771                                     cp->client,
4772                                     &req.match)) {
4773                                 continue;
4774                         }
4775                         stat = pvr2_i2c_client_cmd(
4776                                 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
4777                                     VIDIOC_DBG_G_REGISTER),&req);
4778                         if (!setFl) *val_ptr = req.val;
4779                         okFl = !0;
4780                         break;
4781                 }
4782         } while (0); mutex_unlock(&hdw->i2c_list_lock);
4783         if (okFl) {
4784                 return stat;
4785         }
4786         return -EINVAL;
4787 #else
4788         return -ENOSYS;
4789 #endif
4790 }
4791
4792
4793 /*
4794   Stuff for Emacs to see, in order to encourage consistent editing style:
4795   *** Local Variables: ***
4796   *** mode: c ***
4797   *** fill-column: 75 ***
4798   *** tab-width: 8 ***
4799   *** c-basic-offset: 8 ***
4800   *** End: ***
4801   */