Pileus Git - ~andy/linux/blob - drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/firmware.h>
  25 #include <linux/videodev2.h>
  26 #include <media/v4l2-common.h>
  27 #include "pvrusb2.h"
  28 #include "pvrusb2-std.h"
  29 #include "pvrusb2-util.h"
  30 #include "pvrusb2-hdw.h"
  31 #include "pvrusb2-i2c-core.h"
  32 #include "pvrusb2-i2c-track.h"
  33 #include "pvrusb2-tuner.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38 #include "pvrusb2-fx2-cmd.h"
  39
  40 #define TV_MIN_FREQ     55250000L
  41 #define TV_MAX_FREQ    850000000L
  42
  43 /* This defines a minimum interval that the decoder must remain quiet
  44    before we are allowed to start it running. */
  45 #define TIME_MSEC_DECODER_WAIT 50
  46
  47 /* This defines a minimum interval that the encoder must remain quiet
  48    before we are allowed to configure it.  I had this originally set to
  49    50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
  50    things work better when it's set to 100msec. */
  51 #define TIME_MSEC_ENCODER_WAIT 100
  52
  53 /* This defines the minimum interval that the encoder must successfully run
  54    before we consider that the encoder has run at least once since its
  55    firmware has been loaded.  This measurement is in important for cases
  56    where we can't do something until we know that the encoder has been run
  57    at least once. */
  58 #define TIME_MSEC_ENCODER_OK 250
  59
  60 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  61 static DEFINE_MUTEX(pvr2_unit_mtx);
  62
  63 static int ctlchg;
  64 static int procreload;
  65 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  66 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  67 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  68 static int init_pause_msec;
  69
  70 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  71 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  72 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  73 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  74 module_param(procreload, int, S_IRUGO|S_IWUSR);
  75 MODULE_PARM_DESC(procreload,
  76                  "Attempt init failure recovery with firmware reload");
  77 module_param_array(tuner,    int, NULL, 0444);
  78 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  79 module_param_array(video_std,    int, NULL, 0444);
  80 MODULE_PARM_DESC(video_std,"specify initial video standard");
  81 module_param_array(tolerance,    int, NULL, 0444);
  82 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  83
  84 /* US Broadcast channel 7 (175.25 MHz) */
  85 static int default_tv_freq    = 175250000L;
  86 /* 104.3 MHz, a usable FM station for my area */
  87 static int default_radio_freq = 104300000L;
  88
  89 module_param_named(tv_freq, default_tv_freq, int, 0444);
  90 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  91 module_param_named(radio_freq, default_radio_freq, int, 0444);
  92 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  93
  94 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  95 #define PVR2_CTL_READ_ENDPOINT   0x81
  96
  97 #define PVR2_GPIO_IN 0x9008
  98 #define PVR2_GPIO_OUT 0x900c
  99 #define PVR2_GPIO_DIR 0x9020
 100
 101 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 102
 103 #define PVR2_FIRMWARE_ENDPOINT   0x02
 104
 105 /* size of a firmware chunk */
 106 #define FIRMWARE_CHUNK_SIZE 0x2000
 107
 108 static const char *module_names[] = {
 109         [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 110         [PVR2_CLIENT_ID_CX25840] = "cx25840",
 111         [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 112         [PVR2_CLIENT_ID_TUNER] = "tuner",
 113         [PVR2_CLIENT_ID_CS53132A] = "cs53132a",
 114 };
 115
 116
 117 static const unsigned char *module_i2c_addresses[] = {
 118         [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 119 };
 120
 121
 122 /* Define the list of additional controls we'll dynamically construct based
 123    on query of the cx2341x module. */
 124 struct pvr2_mpeg_ids {
 125         const char *strid;
 126         int id;
 127 };
 128 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 129         {
 130                 .strid = "audio_layer",
 131                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 132         },{
 133                 .strid = "audio_bitrate",
 134                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 135         },{
 136                 /* Already using audio_mode elsewhere :-( */
 137                 .strid = "mpeg_audio_mode",
 138                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 139         },{
 140                 .strid = "mpeg_audio_mode_extension",
 141                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 142         },{
 143                 .strid = "audio_emphasis",
 144                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 145         },{
 146                 .strid = "audio_crc",
 147                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 148         },{
 149                 .strid = "video_aspect",
 150                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 151         },{
 152                 .strid = "video_b_frames",
 153                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 154         },{
 155                 .strid = "video_gop_size",
 156                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 157         },{
 158                 .strid = "video_gop_closure",
 159                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 160         },{
 161                 .strid = "video_bitrate_mode",
 162                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 163         },{
 164                 .strid = "video_bitrate",
 165                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 166         },{
 167                 .strid = "video_bitrate_peak",
 168                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 169         },{
 170                 .strid = "video_temporal_decimation",
 171                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 172         },{
 173                 .strid = "stream_type",
 174                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 175         },{
 176                 .strid = "video_spatial_filter_mode",
 177                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 178         },{
 179                 .strid = "video_spatial_filter",
 180                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 181         },{
 182                 .strid = "video_luma_spatial_filter_type",
 183                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 184         },{
 185                 .strid = "video_chroma_spatial_filter_type",
 186                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 187         },{
 188                 .strid = "video_temporal_filter_mode",
 189                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 190         },{
 191                 .strid = "video_temporal_filter",
 192                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 193         },{
 194                 .strid = "video_median_filter_type",
 195                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 196         },{
 197                 .strid = "video_luma_median_filter_top",
 198                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 199         },{
 200                 .strid = "video_luma_median_filter_bottom",
 201                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 202         },{
 203                 .strid = "video_chroma_median_filter_top",
 204                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 205         },{
 206                 .strid = "video_chroma_median_filter_bottom",
 207                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 208         }
 209 };
 210 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 211
 212
 213 static const char *control_values_srate[] = {
 214         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 215         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 216         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 217 };
 218
 219
 220
 221 static const char *control_values_input[] = {
 222         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 223         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 224         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 225         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 226         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 227 };
 228
 229
 230 static const char *control_values_audiomode[] = {
 231         [V4L2_TUNER_MODE_MONO]   = "Mono",
 232         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 233         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 234         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 235         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 236 };
 237
 238
 239 static const char *control_values_hsm[] = {
 240         [PVR2_CVAL_HSM_FAIL] = "Fail",
 241         [PVR2_CVAL_HSM_HIGH] = "High",
 242         [PVR2_CVAL_HSM_FULL] = "Full",
 243 };
 244
 245
 246 static const char *pvr2_state_names[] = {
 247         [PVR2_STATE_NONE] =    "none",
 248         [PVR2_STATE_DEAD] =    "dead",
 249         [PVR2_STATE_COLD] =    "cold",
 250         [PVR2_STATE_WARM] =    "warm",
 251         [PVR2_STATE_ERROR] =   "error",
 252         [PVR2_STATE_READY] =   "ready",
 253         [PVR2_STATE_RUN] =     "run",
 254 };
 255
 256
 257 struct pvr2_fx2cmd_descdef {
 258         unsigned char id;
 259         unsigned char *desc;
 260 };
 261
 262 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 263         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 264         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 265         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 266         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 267         {FX2CMD_REG_WRITE, "write encoder register"},
 268         {FX2CMD_REG_READ, "read encoder register"},
 269         {FX2CMD_MEMSEL, "encoder memsel"},
 270         {FX2CMD_I2C_WRITE, "i2c write"},
 271         {FX2CMD_I2C_READ, "i2c read"},
 272         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 273         {FX2CMD_STREAMING_ON, "stream on"},
 274         {FX2CMD_STREAMING_OFF, "stream off"},
 275         {FX2CMD_FWPOST1, "fwpost1"},
 276         {FX2CMD_POWER_OFF, "power off"},
 277         {FX2CMD_POWER_ON, "power on"},
 278         {FX2CMD_DEEP_RESET, "deep reset"},
 279         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 280         {FX2CMD_GET_IR_CODE, "get IR code"},
 281         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 282         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 283         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 284         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 285         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 286         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 287         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 288 };
 289
 290
 291 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 292 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 293 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 294 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 295 static void pvr2_hdw_worker_i2c(struct work_struct *work);
 296 static void pvr2_hdw_worker_poll(struct work_struct *work);
 297 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 298 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 299 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 300 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 301 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 302 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 303 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 304 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 305 static void pvr2_hdw_quiescent_timeout(unsigned long);
 306 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 307 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 308 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 309 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 310                                 unsigned int timeout,int probe_fl,
 311                                 void *write_data,unsigned int write_len,
 312                                 void *read_data,unsigned int read_len);
 313 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 314
 315
 316 static void trace_stbit(const char *name,int val)
 317 {
 318         pvr2_trace(PVR2_TRACE_STBITS,
 319                    "State bit %s <-- %s",
 320                    name,(val ? "true" : "false"));
 321 }
 322
 323 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 324 {
 325         struct pvr2_hdw *hdw = cptr->hdw;
 326         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 327                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 328         } else {
 329                 *vp = 0;
 330         }
 331         return 0;
 332 }
 333
 334 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 335 {
 336         struct pvr2_hdw *hdw = cptr->hdw;
 337         unsigned int slotId = hdw->freqProgSlot;
 338         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 339                 hdw->freqTable[slotId-1] = v;
 340                 /* Handle side effects correctly - if we're tuned to this
 341                    slot, then forgot the slot id relation since the stored
 342                    frequency has been changed. */
 343                 if (hdw->freqSelector) {
 344                         if (hdw->freqSlotRadio == slotId) {
 345                                 hdw->freqSlotRadio = 0;
 346                         }
 347                 } else {
 348                         if (hdw->freqSlotTelevision == slotId) {
 349                                 hdw->freqSlotTelevision = 0;
 350                         }
 351                 }
 352         }
 353         return 0;
 354 }
 355
 356 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 357 {
 358         *vp = cptr->hdw->freqProgSlot;
 359         return 0;
 360 }
 361
 362 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 363 {
 364         struct pvr2_hdw *hdw = cptr->hdw;
 365         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 366                 hdw->freqProgSlot = v;
 367         }
 368         return 0;
 369 }
 370
 371 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 372 {
 373         struct pvr2_hdw *hdw = cptr->hdw;
 374         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 375         return 0;
 376 }
 377
 378 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 379 {
 380         unsigned freq = 0;
 381         struct pvr2_hdw *hdw = cptr->hdw;
 382         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 383         if (slotId > 0) {
 384                 freq = hdw->freqTable[slotId-1];
 385                 if (!freq) return 0;
 386                 pvr2_hdw_set_cur_freq(hdw,freq);
 387         }
 388         if (hdw->freqSelector) {
 389                 hdw->freqSlotRadio = slotId;
 390         } else {
 391                 hdw->freqSlotTelevision = slotId;
 392         }
 393         return 0;
 394 }
 395
 396 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 397 {
 398         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 399         return 0;
 400 }
 401
 402 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 403 {
 404         return cptr->hdw->freqDirty != 0;
 405 }
 406
 407 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 408 {
 409         cptr->hdw->freqDirty = 0;
 410 }
 411
 412 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 413 {
 414         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 415         return 0;
 416 }
 417
 418 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 419 {
 420         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 421         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 422         if (stat != 0) {
 423                 return stat;
 424         }
 425         *left = cap->bounds.left;
 426         return 0;
 427 }
 428
 429 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 430 {
 431         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 432         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 433         if (stat != 0) {
 434                 return stat;
 435         }
 436         *left = cap->bounds.left;
 437         if (cap->bounds.width > cptr->hdw->cropw_val) {
 438                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 439         }
 440         return 0;
 441 }
 442
 443 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 444 {
 445         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 446         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 447         if (stat != 0) {
 448                 return stat;
 449         }
 450         *top = cap->bounds.top;
 451         return 0;
 452 }
 453
 454 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 455 {
 456         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 457         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 458         if (stat != 0) {
 459                 return stat;
 460         }
 461         *top = cap->bounds.top;
 462         if (cap->bounds.height > cptr->hdw->croph_val) {
 463                 *top += cap->bounds.height - cptr->hdw->croph_val;
 464         }
 465         return 0;
 466 }
 467
 468 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *val)
 469 {
 470         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 471         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 472         if (stat != 0) {
 473                 return stat;
 474         }
 475         *val = 0;
 476         if (cap->bounds.width > cptr->hdw->cropl_val) {
 477                 *val = cap->bounds.width - cptr->hdw->cropl_val;
 478         }
 479         return 0;
 480 }
 481
 482 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *val)
 483 {
 484         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 485         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 486         if (stat != 0) {
 487                 return stat;
 488         }
 489         *val = 0;
 490         if (cap->bounds.height > cptr->hdw->cropt_val) {
 491                 *val = cap->bounds.height - cptr->hdw->cropt_val;
 492         }
 493         return 0;
 494 }
 495
 496 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 497 {
 498         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 499         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 500         if (stat != 0) {
 501                 return stat;
 502         }
 503         *val = cap->bounds.left;
 504         return 0;
 505 }
 506
 507 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 508 {
 509         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 510         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 511         if (stat != 0) {
 512                 return stat;
 513         }
 514         *val = cap->bounds.top;
 515         return 0;
 516 }
 517
 518 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 519 {
 520         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 521         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 522         if (stat != 0) {
 523                 return stat;
 524         }
 525         *val = cap->bounds.width;
 526         return 0;
 527 }
 528
 529 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 530 {
 531         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 532         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 533         if (stat != 0) {
 534                 return stat;
 535         }
 536         *val = cap->bounds.height;
 537         return 0;
 538 }
 539
 540 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 541 {
 542         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 543         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 544         if (stat != 0) {
 545                 return stat;
 546         }
 547         *val = cap->defrect.left;
 548         return 0;
 549 }
 550
 551 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 552 {
 553         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 554         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 555         if (stat != 0) {
 556                 return stat;
 557         }
 558         *val = cap->defrect.top;
 559         return 0;
 560 }
 561
 562 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 563 {
 564         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 565         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 566         if (stat != 0) {
 567                 return stat;
 568         }
 569         *val = cap->defrect.width;
 570         return 0;
 571 }
 572
 573 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 574 {
 575         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 576         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 577         if (stat != 0) {
 578                 return stat;
 579         }
 580         *val = cap->defrect.height;
 581         return 0;
 582 }
 583
 584 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 585 {
 586         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 587         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 588         if (stat != 0) {
 589                 return stat;
 590         }
 591         *val = cap->pixelaspect.numerator;
 592         return 0;
 593 }
 594
 595 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 596 {
 597         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 598         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 599         if (stat != 0) {
 600                 return stat;
 601         }
 602         *val = cap->pixelaspect.denominator;
 603         return 0;
 604 }
 605
 606 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 607 {
 608         /* Actual maximum depends on the video standard in effect. */
 609         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 610                 *vp = 480;
 611         } else {
 612                 *vp = 576;
 613         }
 614         return 0;
 615 }
 616
 617 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 618 {
 619         /* Actual minimum depends on device digitizer type. */
 620         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 621                 *vp = 75;
 622         } else {
 623                 *vp = 17;
 624         }
 625         return 0;
 626 }
 627
 628 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 629 {
 630         *vp = cptr->hdw->input_val;
 631         return 0;
 632 }
 633
 634 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 635 {
 636         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 637 }
 638
 639 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 640 {
 641         return pvr2_hdw_set_input(cptr->hdw,v);
 642 }
 643
 644 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 645 {
 646         return cptr->hdw->input_dirty != 0;
 647 }
 648
 649 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 650 {
 651         cptr->hdw->input_dirty = 0;
 652 }
 653
 654
 655 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 656 {
 657         unsigned long fv;
 658         struct pvr2_hdw *hdw = cptr->hdw;
 659         if (hdw->tuner_signal_stale) {
 660                 pvr2_hdw_status_poll(hdw);
 661         }
 662         fv = hdw->tuner_signal_info.rangehigh;
 663         if (!fv) {
 664                 /* Safety fallback */
 665                 *vp = TV_MAX_FREQ;
 666                 return 0;
 667         }
 668         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 669                 fv = (fv * 125) / 2;
 670         } else {
 671                 fv = fv * 62500;
 672         }
 673         *vp = fv;
 674         return 0;
 675 }
 676
 677 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 678 {
 679         unsigned long fv;
 680         struct pvr2_hdw *hdw = cptr->hdw;
 681         if (hdw->tuner_signal_stale) {
 682                 pvr2_hdw_status_poll(hdw);
 683         }
 684         fv = hdw->tuner_signal_info.rangelow;
 685         if (!fv) {
 686                 /* Safety fallback */
 687                 *vp = TV_MIN_FREQ;
 688                 return 0;
 689         }
 690         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 691                 fv = (fv * 125) / 2;
 692         } else {
 693                 fv = fv * 62500;
 694         }
 695         *vp = fv;
 696         return 0;
 697 }
 698
 699 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 700 {
 701         return cptr->hdw->enc_stale != 0;
 702 }
 703
 704 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 705 {
 706         cptr->hdw->enc_stale = 0;
 707         cptr->hdw->enc_unsafe_stale = 0;
 708 }
 709
 710 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 711 {
 712         int ret;
 713         struct v4l2_ext_controls cs;
 714         struct v4l2_ext_control c1;
 715         memset(&cs,0,sizeof(cs));
 716         memset(&c1,0,sizeof(c1));
 717         cs.controls = &c1;
 718         cs.count = 1;
 719         c1.id = cptr->info->v4l_id;
 720         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 721                                 VIDIOC_G_EXT_CTRLS);
 722         if (ret) return ret;
 723         *vp = c1.value;
 724         return 0;
 725 }
 726
 727 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 728 {
 729         int ret;
 730         struct pvr2_hdw *hdw = cptr->hdw;
 731         struct v4l2_ext_controls cs;
 732         struct v4l2_ext_control c1;
 733         memset(&cs,0,sizeof(cs));
 734         memset(&c1,0,sizeof(c1));
 735         cs.controls = &c1;
 736         cs.count = 1;
 737         c1.id = cptr->info->v4l_id;
 738         c1.value = v;
 739         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 740                                 hdw->state_encoder_run, &cs,
 741                                 VIDIOC_S_EXT_CTRLS);
 742         if (ret == -EBUSY) {
 743                 /* Oops.  cx2341x is telling us it's not safe to change
 744                    this control while we're capturing.  Make a note of this
 745                    fact so that the pipeline will be stopped the next time
 746                    controls are committed.  Then go on ahead and store this
 747                    change anyway. */
 748                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 749                                         0, &cs,
 750                                         VIDIOC_S_EXT_CTRLS);
 751                 if (!ret) hdw->enc_unsafe_stale = !0;
 752         }
 753         if (ret) return ret;
 754         hdw->enc_stale = !0;
 755         return 0;
 756 }
 757
 758 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 759 {
 760         struct v4l2_queryctrl qctrl;
 761         struct pvr2_ctl_info *info;
 762         qctrl.id = cptr->info->v4l_id;
 763         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 764         /* Strip out the const so we can adjust a function pointer.  It's
 765            OK to do this here because we know this is a dynamically created
 766            control, so the underlying storage for the info pointer is (a)
 767            private to us, and (b) not in read-only storage.  Either we do
 768            this or we significantly complicate the underlying control
 769            implementation. */
 770         info = (struct pvr2_ctl_info *)(cptr->info);
 771         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 772                 if (info->set_value) {
 773                         info->set_value = NULL;
 774                 }
 775         } else {
 776                 if (!(info->set_value)) {
 777                         info->set_value = ctrl_cx2341x_set;
 778                 }
 779         }
 780         return qctrl.flags;
 781 }
 782
 783 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 784 {
 785         *vp = cptr->hdw->state_pipeline_req;
 786         return 0;
 787 }
 788
 789 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 790 {
 791         *vp = cptr->hdw->master_state;
 792         return 0;
 793 }
 794
 795 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 796 {
 797         int result = pvr2_hdw_is_hsm(cptr->hdw);
 798         *vp = PVR2_CVAL_HSM_FULL;
 799         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 800         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 801         return 0;
 802 }
 803
 804 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 805 {
 806         *vp = cptr->hdw->std_mask_avail;
 807         return 0;
 808 }
 809
 810 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 811 {
 812         struct pvr2_hdw *hdw = cptr->hdw;
 813         v4l2_std_id ns;
 814         ns = hdw->std_mask_avail;
 815         ns = (ns & ~m) | (v & m);
 816         if (ns == hdw->std_mask_avail) return 0;
 817         hdw->std_mask_avail = ns;
 818         pvr2_hdw_internal_set_std_avail(hdw);
 819         pvr2_hdw_internal_find_stdenum(hdw);
 820         return 0;
 821 }
 822
 823 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 824                                char *bufPtr,unsigned int bufSize,
 825                                unsigned int *len)
 826 {
 827         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 828         return 0;
 829 }
 830
 831 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 832                                const char *bufPtr,unsigned int bufSize,
 833                                int *mskp,int *valp)
 834 {
 835         int ret;
 836         v4l2_std_id id;
 837         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 838         if (ret < 0) return ret;
 839         if (mskp) *mskp = id;
 840         if (valp) *valp = id;
 841         return 0;
 842 }
 843
 844 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 845 {
 846         *vp = cptr->hdw->std_mask_cur;
 847         return 0;
 848 }
 849
 850 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 851 {
 852         struct pvr2_hdw *hdw = cptr->hdw;
 853         v4l2_std_id ns;
 854         ns = hdw->std_mask_cur;
 855         ns = (ns & ~m) | (v & m);
 856         if (ns == hdw->std_mask_cur) return 0;
 857         hdw->std_mask_cur = ns;
 858         hdw->std_dirty = !0;
 859         pvr2_hdw_internal_find_stdenum(hdw);
 860         return 0;
 861 }
 862
 863 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 864 {
 865         return cptr->hdw->std_dirty != 0;
 866 }
 867
 868 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 869 {
 870         cptr->hdw->std_dirty = 0;
 871 }
 872
 873 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 874 {
 875         struct pvr2_hdw *hdw = cptr->hdw;
 876         pvr2_hdw_status_poll(hdw);
 877         *vp = hdw->tuner_signal_info.signal;
 878         return 0;
 879 }
 880
 881 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 882 {
 883         int val = 0;
 884         unsigned int subchan;
 885         struct pvr2_hdw *hdw = cptr->hdw;
 886         pvr2_hdw_status_poll(hdw);
 887         subchan = hdw->tuner_signal_info.rxsubchans;
 888         if (subchan & V4L2_TUNER_SUB_MONO) {
 889                 val |= (1 << V4L2_TUNER_MODE_MONO);
 890         }
 891         if (subchan & V4L2_TUNER_SUB_STEREO) {
 892                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 893         }
 894         if (subchan & V4L2_TUNER_SUB_LANG1) {
 895                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 896         }
 897         if (subchan & V4L2_TUNER_SUB_LANG2) {
 898                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 899         }
 900         *vp = val;
 901         return 0;
 902 }
 903
 904
 905 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 906 {
 907         struct pvr2_hdw *hdw = cptr->hdw;
 908         if (v < 0) return -EINVAL;
 909         if (v > hdw->std_enum_cnt) return -EINVAL;
 910         hdw->std_enum_cur = v;
 911         if (!v) return 0;
 912         v--;
 913         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 914         hdw->std_mask_cur = hdw->std_defs[v].id;
 915         hdw->std_dirty = !0;
 916         return 0;
 917 }
 918
 919
 920 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 921 {
 922         *vp = cptr->hdw->std_enum_cur;
 923         return 0;
 924 }
 925
 926
 927 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 928 {
 929         return cptr->hdw->std_dirty != 0;
 930 }
 931
 932
 933 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 934 {
 935         cptr->hdw->std_dirty = 0;
 936 }
 937
 938
 939 #define DEFINT(vmin,vmax) \
 940         .type = pvr2_ctl_int, \
 941         .def.type_int.min_value = vmin, \
 942         .def.type_int.max_value = vmax
 943
 944 #define DEFENUM(tab) \
 945         .type = pvr2_ctl_enum, \
 946         .def.type_enum.count = ARRAY_SIZE(tab), \
 947         .def.type_enum.value_names = tab
 948
 949 #define DEFBOOL \
 950         .type = pvr2_ctl_bool
 951
 952 #define DEFMASK(msk,tab) \
 953         .type = pvr2_ctl_bitmask, \
 954         .def.type_bitmask.valid_bits = msk, \
 955         .def.type_bitmask.bit_names = tab
 956
 957 #define DEFREF(vname) \
 958         .set_value = ctrl_set_##vname, \
 959         .get_value = ctrl_get_##vname, \
 960         .is_dirty = ctrl_isdirty_##vname, \
 961         .clear_dirty = ctrl_cleardirty_##vname
 962
 963
 964 #define VCREATE_FUNCS(vname) \
 965 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 966 {*vp = cptr->hdw->vname##_val; return 0;} \
 967 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 968 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 969 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 970 {return cptr->hdw->vname##_dirty != 0;} \
 971 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 972 {cptr->hdw->vname##_dirty = 0;}
 973
 974 VCREATE_FUNCS(brightness)
 975 VCREATE_FUNCS(contrast)
 976 VCREATE_FUNCS(saturation)
 977 VCREATE_FUNCS(hue)
 978 VCREATE_FUNCS(volume)
 979 VCREATE_FUNCS(balance)
 980 VCREATE_FUNCS(bass)
 981 VCREATE_FUNCS(treble)
 982 VCREATE_FUNCS(mute)
 983 VCREATE_FUNCS(cropl)
 984 VCREATE_FUNCS(cropt)
 985 VCREATE_FUNCS(cropw)
 986 VCREATE_FUNCS(croph)
 987 VCREATE_FUNCS(audiomode)
 988 VCREATE_FUNCS(res_hor)
 989 VCREATE_FUNCS(res_ver)
 990 VCREATE_FUNCS(srate)
 991
 992 /* Table definition of all controls which can be manipulated */
 993 static const struct pvr2_ctl_info control_defs[] = {
 994         {
 995                 .v4l_id = V4L2_CID_BRIGHTNESS,
 996                 .desc = "Brightness",
 997                 .name = "brightness",
 998                 .default_value = 128,
 999                 DEFREF(brightness),
1000                 DEFINT(0,255),
1001         },{
1002                 .v4l_id = V4L2_CID_CONTRAST,
1003                 .desc = "Contrast",
1004                 .name = "contrast",
1005                 .default_value = 68,
1006                 DEFREF(contrast),
1007                 DEFINT(0,127),
1008         },{
1009                 .v4l_id = V4L2_CID_SATURATION,
1010                 .desc = "Saturation",
1011                 .name = "saturation",
1012                 .default_value = 64,
1013                 DEFREF(saturation),
1014                 DEFINT(0,127),
1015         },{
1016                 .v4l_id = V4L2_CID_HUE,
1017                 .desc = "Hue",
1018                 .name = "hue",
1019                 .default_value = 0,
1020                 DEFREF(hue),
1021                 DEFINT(-128,127),
1022         },{
1023                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1024                 .desc = "Volume",
1025                 .name = "volume",
1026                 .default_value = 62000,
1027                 DEFREF(volume),
1028                 DEFINT(0,65535),
1029         },{
1030                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1031                 .desc = "Balance",
1032                 .name = "balance",
1033                 .default_value = 0,
1034                 DEFREF(balance),
1035                 DEFINT(-32768,32767),
1036         },{
1037                 .v4l_id = V4L2_CID_AUDIO_BASS,
1038                 .desc = "Bass",
1039                 .name = "bass",
1040                 .default_value = 0,
1041                 DEFREF(bass),
1042                 DEFINT(-32768,32767),
1043         },{
1044                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1045                 .desc = "Treble",
1046                 .name = "treble",
1047                 .default_value = 0,
1048                 DEFREF(treble),
1049                 DEFINT(-32768,32767),
1050         },{
1051                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1052                 .desc = "Mute",
1053                 .name = "mute",
1054                 .default_value = 0,
1055                 DEFREF(mute),
1056                 DEFBOOL,
1057         }, {
1058                 .desc = "Capture crop left margin",
1059                 .name = "crop_left",
1060                 .internal_id = PVR2_CID_CROPL,
1061                 .default_value = 0,
1062                 DEFREF(cropl),
1063                 DEFINT(-129, 340),
1064                 .get_min_value = ctrl_cropl_min_get,
1065                 .get_max_value = ctrl_cropl_max_get,
1066                 .get_def_value = ctrl_get_cropcapdl,
1067         }, {
1068                 .desc = "Capture crop top margin",
1069                 .name = "crop_top",
1070                 .internal_id = PVR2_CID_CROPT,
1071                 .default_value = 0,
1072                 DEFREF(cropt),
1073                 DEFINT(-35, 544),
1074                 .get_min_value = ctrl_cropt_min_get,
1075                 .get_max_value = ctrl_cropt_max_get,
1076                 .get_def_value = ctrl_get_cropcapdt,
1077         }, {
1078                 .desc = "Capture crop width",
1079                 .name = "crop_width",
1080                 .internal_id = PVR2_CID_CROPW,
1081                 .default_value = 720,
1082                 DEFREF(cropw),
1083                 .get_max_value = ctrl_cropw_max_get,
1084                 .get_def_value = ctrl_get_cropcapdw,
1085         }, {
1086                 .desc = "Capture crop height",
1087                 .name = "crop_height",
1088                 .internal_id = PVR2_CID_CROPH,
1089                 .default_value = 480,
1090                 DEFREF(croph),
1091                 .get_max_value = ctrl_croph_max_get,
1092                 .get_def_value = ctrl_get_cropcapdh,
1093         }, {
1094                 .desc = "Capture capability pixel aspect numerator",
1095                 .name = "cropcap_pixel_numerator",
1096                 .internal_id = PVR2_CID_CROPCAPPAN,
1097                 .get_value = ctrl_get_cropcappan,
1098         }, {
1099                 .desc = "Capture capability pixel aspect denominator",
1100                 .name = "cropcap_pixel_denominator",
1101                 .internal_id = PVR2_CID_CROPCAPPAD,
1102                 .get_value = ctrl_get_cropcappad,
1103         }, {
1104                 .desc = "Capture capability bounds top",
1105                 .name = "cropcap_bounds_top",
1106                 .internal_id = PVR2_CID_CROPCAPBT,
1107                 .get_value = ctrl_get_cropcapbt,
1108         }, {
1109                 .desc = "Capture capability bounds left",
1110                 .name = "cropcap_bounds_left",
1111                 .internal_id = PVR2_CID_CROPCAPBL,
1112                 .get_value = ctrl_get_cropcapbl,
1113         }, {
1114                 .desc = "Capture capability bounds width",
1115                 .name = "cropcap_bounds_width",
1116                 .internal_id = PVR2_CID_CROPCAPBW,
1117                 .get_value = ctrl_get_cropcapbw,
1118         }, {
1119                 .desc = "Capture capability bounds height",
1120                 .name = "cropcap_bounds_height",
1121                 .internal_id = PVR2_CID_CROPCAPBH,
1122                 .get_value = ctrl_get_cropcapbh,
1123         },{
1124                 .desc = "Video Source",
1125                 .name = "input",
1126                 .internal_id = PVR2_CID_INPUT,
1127                 .default_value = PVR2_CVAL_INPUT_TV,
1128                 .check_value = ctrl_check_input,
1129                 DEFREF(input),
1130                 DEFENUM(control_values_input),
1131         },{
1132                 .desc = "Audio Mode",
1133                 .name = "audio_mode",
1134                 .internal_id = PVR2_CID_AUDIOMODE,
1135                 .default_value = V4L2_TUNER_MODE_STEREO,
1136                 DEFREF(audiomode),
1137                 DEFENUM(control_values_audiomode),
1138         },{
1139                 .desc = "Horizontal capture resolution",
1140                 .name = "resolution_hor",
1141                 .internal_id = PVR2_CID_HRES,
1142                 .default_value = 720,
1143                 DEFREF(res_hor),
1144                 DEFINT(19,720),
1145         },{
1146                 .desc = "Vertical capture resolution",
1147                 .name = "resolution_ver",
1148                 .internal_id = PVR2_CID_VRES,
1149                 .default_value = 480,
1150                 DEFREF(res_ver),
1151                 DEFINT(17,576),
1152                 /* Hook in check for video standard and adjust maximum
1153                    depending on the standard. */
1154                 .get_max_value = ctrl_vres_max_get,
1155                 .get_min_value = ctrl_vres_min_get,
1156         },{
1157                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1158                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1159                 .desc = "Audio Sampling Frequency",
1160                 .name = "srate",
1161                 DEFREF(srate),
1162                 DEFENUM(control_values_srate),
1163         },{
1164                 .desc = "Tuner Frequency (Hz)",
1165                 .name = "frequency",
1166                 .internal_id = PVR2_CID_FREQUENCY,
1167                 .default_value = 0,
1168                 .set_value = ctrl_freq_set,
1169                 .get_value = ctrl_freq_get,
1170                 .is_dirty = ctrl_freq_is_dirty,
1171                 .clear_dirty = ctrl_freq_clear_dirty,
1172                 DEFINT(0,0),
1173                 /* Hook in check for input value (tv/radio) and adjust
1174                    max/min values accordingly */
1175                 .get_max_value = ctrl_freq_max_get,
1176                 .get_min_value = ctrl_freq_min_get,
1177         },{
1178                 .desc = "Channel",
1179                 .name = "channel",
1180                 .set_value = ctrl_channel_set,
1181                 .get_value = ctrl_channel_get,
1182                 DEFINT(0,FREQTABLE_SIZE),
1183         },{
1184                 .desc = "Channel Program Frequency",
1185                 .name = "freq_table_value",
1186                 .set_value = ctrl_channelfreq_set,
1187                 .get_value = ctrl_channelfreq_get,
1188                 DEFINT(0,0),
1189                 /* Hook in check for input value (tv/radio) and adjust
1190                    max/min values accordingly */
1191                 .get_max_value = ctrl_freq_max_get,
1192                 .get_min_value = ctrl_freq_min_get,
1193         },{
1194                 .desc = "Channel Program ID",
1195                 .name = "freq_table_channel",
1196                 .set_value = ctrl_channelprog_set,
1197                 .get_value = ctrl_channelprog_get,
1198                 DEFINT(0,FREQTABLE_SIZE),
1199         },{
1200                 .desc = "Streaming Enabled",
1201                 .name = "streaming_enabled",
1202                 .get_value = ctrl_streamingenabled_get,
1203                 DEFBOOL,
1204         },{
1205                 .desc = "USB Speed",
1206                 .name = "usb_speed",
1207                 .get_value = ctrl_hsm_get,
1208                 DEFENUM(control_values_hsm),
1209         },{
1210                 .desc = "Master State",
1211                 .name = "master_state",
1212                 .get_value = ctrl_masterstate_get,
1213                 DEFENUM(pvr2_state_names),
1214         },{
1215                 .desc = "Signal Present",
1216                 .name = "signal_present",
1217                 .get_value = ctrl_signal_get,
1218                 DEFINT(0,65535),
1219         },{
1220                 .desc = "Audio Modes Present",
1221                 .name = "audio_modes_present",
1222                 .get_value = ctrl_audio_modes_present_get,
1223                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1224                    v4l.  Nothing outside of this module cares about this,
1225                    but I reuse it in order to also reuse the
1226                    control_values_audiomode string table. */
1227                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1228                          (1 << V4L2_TUNER_MODE_STEREO)|
1229                          (1 << V4L2_TUNER_MODE_LANG1)|
1230                          (1 << V4L2_TUNER_MODE_LANG2)),
1231                         control_values_audiomode),
1232         },{
1233                 .desc = "Video Standards Available Mask",
1234                 .name = "video_standard_mask_available",
1235                 .internal_id = PVR2_CID_STDAVAIL,
1236                 .skip_init = !0,
1237                 .get_value = ctrl_stdavail_get,
1238                 .set_value = ctrl_stdavail_set,
1239                 .val_to_sym = ctrl_std_val_to_sym,
1240                 .sym_to_val = ctrl_std_sym_to_val,
1241                 .type = pvr2_ctl_bitmask,
1242         },{
1243                 .desc = "Video Standards In Use Mask",
1244                 .name = "video_standard_mask_active",
1245                 .internal_id = PVR2_CID_STDCUR,
1246                 .skip_init = !0,
1247                 .get_value = ctrl_stdcur_get,
1248                 .set_value = ctrl_stdcur_set,
1249                 .is_dirty = ctrl_stdcur_is_dirty,
1250                 .clear_dirty = ctrl_stdcur_clear_dirty,
1251                 .val_to_sym = ctrl_std_val_to_sym,
1252                 .sym_to_val = ctrl_std_sym_to_val,
1253                 .type = pvr2_ctl_bitmask,
1254         },{
1255                 .desc = "Video Standard Name",
1256                 .name = "video_standard",
1257                 .internal_id = PVR2_CID_STDENUM,
1258                 .skip_init = !0,
1259                 .get_value = ctrl_stdenumcur_get,
1260                 .set_value = ctrl_stdenumcur_set,
1261                 .is_dirty = ctrl_stdenumcur_is_dirty,
1262                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1263                 .type = pvr2_ctl_enum,
1264         }
1265 };
1266
1267 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1268
1269
1270 const char *pvr2_config_get_name(enum pvr2_config cfg)
1271 {
1272         switch (cfg) {
1273         case pvr2_config_empty: return "empty";
1274         case pvr2_config_mpeg: return "mpeg";
1275         case pvr2_config_vbi: return "vbi";
1276         case pvr2_config_pcm: return "pcm";
1277         case pvr2_config_rawvideo: return "raw video";
1278         }
1279         return "<unknown>";
1280 }
1281
1282
1283 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1284 {
1285         return hdw->usb_dev;
1286 }
1287
1288
1289 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1290 {
1291         return hdw->serial_number;
1292 }
1293
1294
1295 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1296 {
1297         return hdw->bus_info;
1298 }
1299
1300
1301 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1302 {
1303         return hdw->identifier;
1304 }
1305
1306
1307 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1308 {
1309         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1310 }
1311
1312 /* Set the currently tuned frequency and account for all possible
1313    driver-core side effects of this action. */
1314 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1315 {
1316         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1317                 if (hdw->freqSelector) {
1318                         /* Swing over to radio frequency selection */
1319                         hdw->freqSelector = 0;
1320                         hdw->freqDirty = !0;
1321                 }
1322                 if (hdw->freqValRadio != val) {
1323                         hdw->freqValRadio = val;
1324                         hdw->freqSlotRadio = 0;
1325                         hdw->freqDirty = !0;
1326                 }
1327         } else {
1328                 if (!(hdw->freqSelector)) {
1329                         /* Swing over to television frequency selection */
1330                         hdw->freqSelector = 1;
1331                         hdw->freqDirty = !0;
1332                 }
1333                 if (hdw->freqValTelevision != val) {
1334                         hdw->freqValTelevision = val;
1335                         hdw->freqSlotTelevision = 0;
1336                         hdw->freqDirty = !0;
1337                 }
1338         }
1339 }
1340
1341 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1342 {
1343         return hdw->unit_number;
1344 }
1345
1346
1347 /* Attempt to locate one of the given set of files.  Messages are logged
1348    appropriate to what has been found.  The return value will be 0 or
1349    greater on success (it will be the index of the file name found) and
1350    fw_entry will be filled in.  Otherwise a negative error is returned on
1351    failure.  If the return value is -ENOENT then no viable firmware file
1352    could be located. */
1353 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1354                                 const struct firmware **fw_entry,
1355                                 const char *fwtypename,
1356                                 unsigned int fwcount,
1357                                 const char *fwnames[])
1358 {
1359         unsigned int idx;
1360         int ret = -EINVAL;
1361         for (idx = 0; idx < fwcount; idx++) {
1362                 ret = request_firmware(fw_entry,
1363                                        fwnames[idx],
1364                                        &hdw->usb_dev->dev);
1365                 if (!ret) {
1366                         trace_firmware("Located %s firmware: %s;"
1367                                        " uploading...",
1368                                        fwtypename,
1369                                        fwnames[idx]);
1370                         return idx;
1371                 }
1372                 if (ret == -ENOENT) continue;
1373                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1374                            "request_firmware fatal error with code=%d",ret);
1375                 return ret;
1376         }
1377         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1378                    "***WARNING***"
1379                    " Device %s firmware"
1380                    " seems to be missing.",
1381                    fwtypename);
1382         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1383                    "Did you install the pvrusb2 firmware files"
1384                    " in their proper location?");
1385         if (fwcount == 1) {
1386                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1387                            "request_firmware unable to locate %s file %s",
1388                            fwtypename,fwnames[0]);
1389         } else {
1390                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1391                            "request_firmware unable to locate"
1392                            " one of the following %s files:",
1393                            fwtypename);
1394                 for (idx = 0; idx < fwcount; idx++) {
1395                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1396                                    "request_firmware: Failed to find %s",
1397                                    fwnames[idx]);
1398                 }
1399         }
1400         return ret;
1401 }
1402
1403
1404 /*
1405  * pvr2_upload_firmware1().
1406  *
1407  * Send the 8051 firmware to the device.  After the upload, arrange for
1408  * device to re-enumerate.
1409  *
1410  * NOTE : the pointer to the firmware data given by request_firmware()
1411  * is not suitable for an usb transaction.
1412  *
1413  */
1414 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1415 {
1416         const struct firmware *fw_entry = NULL;
1417         void  *fw_ptr;
1418         unsigned int pipe;
1419         int ret;
1420         u16 address;
1421
1422         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1423                 hdw->fw1_state = FW1_STATE_OK;
1424                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1425                            "Connected device type defines"
1426                            " no firmware to upload; ignoring firmware");
1427                 return -ENOTTY;
1428         }
1429
1430         hdw->fw1_state = FW1_STATE_FAILED; // default result
1431
1432         trace_firmware("pvr2_upload_firmware1");
1433
1434         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1435                                    hdw->hdw_desc->fx2_firmware.cnt,
1436                                    hdw->hdw_desc->fx2_firmware.lst);
1437         if (ret < 0) {
1438                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1439                 return ret;
1440         }
1441
1442         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1443         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1444
1445         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1446
1447         if (fw_entry->size != 0x2000){
1448                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1449                 release_firmware(fw_entry);
1450                 return -ENOMEM;
1451         }
1452
1453         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1454         if (fw_ptr == NULL){
1455                 release_firmware(fw_entry);
1456                 return -ENOMEM;
1457         }
1458
1459         /* We have to hold the CPU during firmware upload. */
1460         pvr2_hdw_cpureset_assert(hdw,1);
1461
1462         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1463            chunk. */
1464
1465         ret = 0;
1466         for(address = 0; address < fw_entry->size; address += 0x800) {
1467                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1468                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1469                                        0, fw_ptr, 0x800, HZ);
1470         }
1471
1472         trace_firmware("Upload done, releasing device's CPU");
1473
1474         /* Now release the CPU.  It will disconnect and reconnect later. */
1475         pvr2_hdw_cpureset_assert(hdw,0);
1476
1477         kfree(fw_ptr);
1478         release_firmware(fw_entry);
1479
1480         trace_firmware("Upload done (%d bytes sent)",ret);
1481
1482         /* We should have written 8192 bytes */
1483         if (ret == 8192) {
1484                 hdw->fw1_state = FW1_STATE_RELOAD;
1485                 return 0;
1486         }
1487
1488         return -EIO;
1489 }
1490
1491
1492 /*
1493  * pvr2_upload_firmware2()
1494  *
1495  * This uploads encoder firmware on endpoint 2.
1496  *
1497  */
1498
1499 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1500 {
1501         const struct firmware *fw_entry = NULL;
1502         void  *fw_ptr;
1503         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1504         int actual_length;
1505         int ret = 0;
1506         int fwidx;
1507         static const char *fw_files[] = {
1508                 CX2341X_FIRM_ENC_FILENAME,
1509         };
1510
1511         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1512                 return 0;
1513         }
1514
1515         trace_firmware("pvr2_upload_firmware2");
1516
1517         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1518                                    ARRAY_SIZE(fw_files), fw_files);
1519         if (ret < 0) return ret;
1520         fwidx = ret;
1521         ret = 0;
1522         /* Since we're about to completely reinitialize the encoder,
1523            invalidate our cached copy of its configuration state.  Next
1524            time we configure the encoder, then we'll fully configure it. */
1525         hdw->enc_cur_valid = 0;
1526
1527         /* Encoder is about to be reset so note that as far as we're
1528            concerned now, the encoder has never been run. */
1529         del_timer_sync(&hdw->encoder_run_timer);
1530         if (hdw->state_encoder_runok) {
1531                 hdw->state_encoder_runok = 0;
1532                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1533         }
1534
1535         /* First prepare firmware loading */
1536         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1537         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1538         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1539         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1540         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1541         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1542         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1543         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1544         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1545         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1546         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1547         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1548         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1549         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1550         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1551         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1552         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1553         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1554
1555         if (ret) {
1556                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1557                            "firmware2 upload prep failed, ret=%d",ret);
1558                 release_firmware(fw_entry);
1559                 goto done;
1560         }
1561
1562         /* Now send firmware */
1563
1564         fw_len = fw_entry->size;
1565
1566         if (fw_len % sizeof(u32)) {
1567                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1568                            "size of %s firmware"
1569                            " must be a multiple of %zu bytes",
1570                            fw_files[fwidx],sizeof(u32));
1571                 release_firmware(fw_entry);
1572                 ret = -EINVAL;
1573                 goto done;
1574         }
1575
1576         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1577         if (fw_ptr == NULL){
1578                 release_firmware(fw_entry);
1579                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1580                            "failed to allocate memory for firmware2 upload");
1581                 ret = -ENOMEM;
1582                 goto done;
1583         }
1584
1585         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1586
1587         fw_done = 0;
1588         for (fw_done = 0; fw_done < fw_len;) {
1589                 bcnt = fw_len - fw_done;
1590                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1591                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1592                 /* Usbsnoop log shows that we must swap bytes... */
1593                 /* Some background info: The data being swapped here is a
1594                    firmware image destined for the mpeg encoder chip that
1595                    lives at the other end of a USB endpoint.  The encoder
1596                    chip always talks in 32 bit chunks and its storage is
1597                    organized into 32 bit words.  However from the file
1598                    system to the encoder chip everything is purely a byte
1599                    stream.  The firmware file's contents are always 32 bit
1600                    swapped from what the encoder expects.  Thus the need
1601                    always exists to swap the bytes regardless of the endian
1602                    type of the host processor and therefore swab32() makes
1603                    the most sense. */
1604                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1605                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1606
1607                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1608                                     &actual_length, HZ);
1609                 ret |= (actual_length != bcnt);
1610                 if (ret) break;
1611                 fw_done += bcnt;
1612         }
1613
1614         trace_firmware("upload of %s : %i / %i ",
1615                        fw_files[fwidx],fw_done,fw_len);
1616
1617         kfree(fw_ptr);
1618         release_firmware(fw_entry);
1619
1620         if (ret) {
1621                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1622                            "firmware2 upload transfer failure");
1623                 goto done;
1624         }
1625
1626         /* Finish upload */
1627
1628         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1629         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1630         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1631
1632         if (ret) {
1633                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1634                            "firmware2 upload post-proc failure");
1635         }
1636
1637  done:
1638         if (hdw->hdw_desc->signal_routing_scheme ==
1639             PVR2_ROUTING_SCHEME_GOTVIEW) {
1640                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1641                    hardware. */
1642                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1643         }
1644         return ret;
1645 }
1646
1647
1648 static const char *pvr2_get_state_name(unsigned int st)
1649 {
1650         if (st < ARRAY_SIZE(pvr2_state_names)) {
1651                 return pvr2_state_names[st];
1652         }
1653         return "???";
1654 }
1655
1656 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1657 {
1658         if (!hdw->decoder_ctrl) {
1659                 if (!hdw->flag_decoder_missed) {
1660                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1661                                    "WARNING: No decoder present");
1662                         hdw->flag_decoder_missed = !0;
1663                         trace_stbit("flag_decoder_missed",
1664                                     hdw->flag_decoder_missed);
1665                 }
1666                 return -EIO;
1667         }
1668         hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1669         return 0;
1670 }
1671
1672
1673 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1674 {
1675         if (hdw->decoder_ctrl == ptr) return;
1676         hdw->decoder_ctrl = ptr;
1677         if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1678                 hdw->flag_decoder_missed = 0;
1679                 trace_stbit("flag_decoder_missed",
1680                             hdw->flag_decoder_missed);
1681                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1682                            "Decoder has appeared");
1683                 pvr2_hdw_state_sched(hdw);
1684         }
1685 }
1686
1687
1688 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1689 {
1690         return hdw->master_state;
1691 }
1692
1693
1694 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1695 {
1696         if (!hdw->flag_tripped) return 0;
1697         hdw->flag_tripped = 0;
1698         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1699                    "Clearing driver error statuss");
1700         return !0;
1701 }
1702
1703
1704 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1705 {
1706         int fl;
1707         LOCK_TAKE(hdw->big_lock); do {
1708                 fl = pvr2_hdw_untrip_unlocked(hdw);
1709         } while (0); LOCK_GIVE(hdw->big_lock);
1710         if (fl) pvr2_hdw_state_sched(hdw);
1711         return 0;
1712 }
1713
1714
1715
1716
1717 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1718 {
1719         return hdw->state_pipeline_req != 0;
1720 }
1721
1722
1723 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1724 {
1725         int ret,st;
1726         LOCK_TAKE(hdw->big_lock); do {
1727                 pvr2_hdw_untrip_unlocked(hdw);
1728                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1729                         hdw->state_pipeline_req = enable_flag != 0;
1730                         pvr2_trace(PVR2_TRACE_START_STOP,
1731                                    "/*--TRACE_STREAM--*/ %s",
1732                                    enable_flag ? "enable" : "disable");
1733                 }
1734                 pvr2_hdw_state_sched(hdw);
1735         } while (0); LOCK_GIVE(hdw->big_lock);
1736         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1737         if (enable_flag) {
1738                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1739                         if (st != PVR2_STATE_READY) return -EIO;
1740                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1741                 }
1742         }
1743         return 0;
1744 }
1745
1746
1747 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1748 {
1749         int fl;
1750         LOCK_TAKE(hdw->big_lock);
1751         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1752                 hdw->desired_stream_type = config;
1753                 hdw->state_pipeline_config = 0;
1754                 trace_stbit("state_pipeline_config",
1755                             hdw->state_pipeline_config);
1756                 pvr2_hdw_state_sched(hdw);
1757         }
1758         LOCK_GIVE(hdw->big_lock);
1759         if (fl) return 0;
1760         return pvr2_hdw_wait(hdw,0);
1761 }
1762
1763
1764 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1765 {
1766         int unit_number = hdw->unit_number;
1767         int tp = -1;
1768         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1769                 tp = tuner[unit_number];
1770         }
1771         if (tp < 0) return -EINVAL;
1772         hdw->tuner_type = tp;
1773         hdw->tuner_updated = !0;
1774         return 0;
1775 }
1776
1777
1778 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1779 {
1780         int unit_number = hdw->unit_number;
1781         int tp = 0;
1782         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1783                 tp = video_std[unit_number];
1784                 if (tp) return tp;
1785         }
1786         return 0;
1787 }
1788
1789
1790 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1791 {
1792         int unit_number = hdw->unit_number;
1793         int tp = 0;
1794         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1795                 tp = tolerance[unit_number];
1796         }
1797         return tp;
1798 }
1799
1800
1801 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1802 {
1803         /* Try a harmless request to fetch the eeprom's address over
1804            endpoint 1.  See what happens.  Only the full FX2 image can
1805            respond to this.  If this probe fails then likely the FX2
1806            firmware needs be loaded. */
1807         int result;
1808         LOCK_TAKE(hdw->ctl_lock); do {
1809                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1810                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1811                                            hdw->cmd_buffer,1,
1812                                            hdw->cmd_buffer,1);
1813                 if (result < 0) break;
1814         } while(0); LOCK_GIVE(hdw->ctl_lock);
1815         if (result) {
1816                 pvr2_trace(PVR2_TRACE_INIT,
1817                            "Probe of device endpoint 1 result status %d",
1818                            result);
1819         } else {
1820                 pvr2_trace(PVR2_TRACE_INIT,
1821                            "Probe of device endpoint 1 succeeded");
1822         }
1823         return result == 0;
1824 }
1825
1826 struct pvr2_std_hack {
1827         v4l2_std_id pat;  /* Pattern to match */
1828         v4l2_std_id msk;  /* Which bits we care about */
1829         v4l2_std_id std;  /* What additional standards or default to set */
1830 };
1831
1832 /* This data structure labels specific combinations of standards from
1833    tveeprom that we'll try to recognize.  If we recognize one, then assume
1834    a specified default standard to use.  This is here because tveeprom only
1835    tells us about available standards not the intended default standard (if
1836    any) for the device in question.  We guess the default based on what has
1837    been reported as available.  Note that this is only for guessing a
1838    default - which can always be overridden explicitly - and if the user
1839    has otherwise named a default then that default will always be used in
1840    place of this table. */
1841 static const struct pvr2_std_hack std_eeprom_maps[] = {
1842         {       /* PAL(B/G) */
1843                 .pat = V4L2_STD_B|V4L2_STD_GH,
1844                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1845         },
1846         {       /* NTSC(M) */
1847                 .pat = V4L2_STD_MN,
1848                 .std = V4L2_STD_NTSC_M,
1849         },
1850         {       /* PAL(I) */
1851                 .pat = V4L2_STD_PAL_I,
1852                 .std = V4L2_STD_PAL_I,
1853         },
1854         {       /* SECAM(L/L') */
1855                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1856                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1857         },
1858         {       /* PAL(D/D1/K) */
1859                 .pat = V4L2_STD_DK,
1860                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1861         },
1862 };
1863
1864 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1865 {
1866         char buf[40];
1867         unsigned int bcnt;
1868         v4l2_std_id std1,std2,std3;
1869
1870         std1 = get_default_standard(hdw);
1871         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1872
1873         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1874         pvr2_trace(PVR2_TRACE_STD,
1875                    "Supported video standard(s) reported available"
1876                    " in hardware: %.*s",
1877                    bcnt,buf);
1878
1879         hdw->std_mask_avail = hdw->std_mask_eeprom;
1880
1881         std2 = (std1|std3) & ~hdw->std_mask_avail;
1882         if (std2) {
1883                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1884                 pvr2_trace(PVR2_TRACE_STD,
1885                            "Expanding supported video standards"
1886                            " to include: %.*s",
1887                            bcnt,buf);
1888                 hdw->std_mask_avail |= std2;
1889         }
1890
1891         pvr2_hdw_internal_set_std_avail(hdw);
1892
1893         if (std1) {
1894                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1895                 pvr2_trace(PVR2_TRACE_STD,
1896                            "Initial video standard forced to %.*s",
1897                            bcnt,buf);
1898                 hdw->std_mask_cur = std1;
1899                 hdw->std_dirty = !0;
1900                 pvr2_hdw_internal_find_stdenum(hdw);
1901                 return;
1902         }
1903         if (std3) {
1904                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1905                 pvr2_trace(PVR2_TRACE_STD,
1906                            "Initial video standard"
1907                            " (determined by device type): %.*s",bcnt,buf);
1908                 hdw->std_mask_cur = std3;
1909                 hdw->std_dirty = !0;
1910                 pvr2_hdw_internal_find_stdenum(hdw);
1911                 return;
1912         }
1913
1914         {
1915                 unsigned int idx;
1916                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1917                         if (std_eeprom_maps[idx].msk ?
1918                             ((std_eeprom_maps[idx].pat ^
1919                              hdw->std_mask_eeprom) &
1920                              std_eeprom_maps[idx].msk) :
1921                             (std_eeprom_maps[idx].pat !=
1922                              hdw->std_mask_eeprom)) continue;
1923                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1924                                                   std_eeprom_maps[idx].std);
1925                         pvr2_trace(PVR2_TRACE_STD,
1926                                    "Initial video standard guessed as %.*s",
1927                                    bcnt,buf);
1928                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1929                         hdw->std_dirty = !0;
1930                         pvr2_hdw_internal_find_stdenum(hdw);
1931                         return;
1932                 }
1933         }
1934
1935         if (hdw->std_enum_cnt > 1) {
1936                 // Autoselect the first listed standard
1937                 hdw->std_enum_cur = 1;
1938                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1939                 hdw->std_dirty = !0;
1940                 pvr2_trace(PVR2_TRACE_STD,
1941                            "Initial video standard auto-selected to %s",
1942                            hdw->std_defs[hdw->std_enum_cur-1].name);
1943                 return;
1944         }
1945
1946         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1947                    "Unable to select a viable initial video standard");
1948 }
1949
1950
1951 static unsigned int pvr2_copy_i2c_addr_list(
1952         unsigned short *dst, const unsigned char *src,
1953         unsigned int dst_max)
1954 {
1955         unsigned int cnt;
1956         if (!src) return 0;
1957         while (src[cnt] && (cnt + 1) < dst_max) {
1958                 dst[cnt] = src[cnt];
1959                 cnt++;
1960         }
1961         dst[cnt] = I2C_CLIENT_END;
1962         return cnt;
1963 }
1964
1965
1966 static void pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1967                                  const struct pvr2_device_client_desc *cd)
1968 {
1969         const char *fname;
1970         unsigned char mid;
1971         struct v4l2_subdev *sd;
1972         unsigned int i2ccnt;
1973         const unsigned char *p;
1974         /* Arbitrary count - max # i2c addresses we will probe */
1975         unsigned short i2caddr[25];
1976
1977         mid = cd->module_id;
1978         fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
1979         if (!fname) {
1980                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1981                            "Module ID %u for device %s is unknown"
1982                            " (this is probably a bad thing...)",
1983                            mid,
1984                            hdw->hdw_desc->description);
1985                 return;
1986         }
1987
1988         i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
1989                                          ARRAY_SIZE(i2caddr));
1990         if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
1991                          module_i2c_addresses[mid] : NULL) != NULL)) {
1992                 /* Second chance: Try default i2c address list */
1993                 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
1994                                                  ARRAY_SIZE(i2caddr));
1995         }
1996
1997         if (!i2ccnt) {
1998                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1999                            "Module ID %u for device %s:"
2000                            " No i2c addresses"
2001                            " (this is probably a bad thing...)",
2002                            mid, hdw->hdw_desc->description);
2003                 return;
2004         }
2005
2006         /* Note how the 2nd and 3rd arguments are the same for both
2007          * v4l2_i2c_new_subdev() and v4l2_i2c_new_probed_subdev().  Why?
2008          * Well the 2nd argument is the module name to load, while the 3rd
2009          * argument is documented in the framework as being the "chipid" -
2010          * and every other place where I can find examples of this, the
2011          * "chipid" appears to just be the module name again.  So here we
2012          * just do the same thing. */
2013         if (i2ccnt == 1) {
2014                 sd = v4l2_i2c_new_subdev(&hdw->i2c_adap,
2015                                          fname, fname,
2016                                          i2caddr[0]);
2017         } else {
2018                 sd = v4l2_i2c_new_probed_subdev(&hdw->i2c_adap,
2019                                                 fname, fname,
2020                                                 i2caddr);
2021         }
2022
2023         if (!sd) {
2024                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2025                            "Module ID %u for device %s failed to load"
2026                            " (this is probably a bad thing...)",
2027                            mid, hdw->hdw_desc->description);
2028                 return;
2029         }
2030
2031         /* Tag this sub-device instance with the module ID we know about.
2032            In other places we'll use that tag to determine if the instance
2033            requires special handling. */
2034         sd->grp_id = mid;
2035
2036         /* If we have both old and new i2c layers enabled, make sure that
2037            old layer isn't also tracking this module.  This is a debugging
2038            aid, in normal situations there's no reason for both mechanisms
2039            to be enabled. */
2040         pvr2_i2c_untrack_subdev(hdw, sd);
2041         pvr2_trace(PVR2_TRACE_INIT, "Attached sub-driver %s", fname);
2042
2043
2044         /* client-specific setup... */
2045         switch (mid) {
2046         case PVR2_CLIENT_ID_CX25840:
2047                 hdw->decoder_client_id = mid;
2048                 {
2049                         /*
2050                           Mike Isely <isely@pobox.com> 19-Nov-2006 - This
2051                           bit of nuttiness for cx25840 causes that module
2052                           to correctly set up its video scaling.  This is
2053                           really a problem in the cx25840 module itself,
2054                           but we work around it here.  The problem has not
2055                           been seen in ivtv because there VBI is supported
2056                           and set up.  We don't do VBI here (at least not
2057                           yet) and thus we never attempted to even set it
2058                           up.
2059                         */
2060                         struct v4l2_format fmt;
2061                         memset(&fmt, 0, sizeof(fmt));
2062                         fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2063                         v4l2_device_call_all(&hdw->v4l2_dev, mid,
2064                                              video, s_fmt, &fmt);
2065                 }
2066                 break;
2067         case PVR2_CLIENT_ID_SAA7115:
2068                 hdw->decoder_client_id = mid;
2069                 break;
2070         default: break;
2071         }
2072 }
2073
2074
2075 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2076 {
2077         unsigned int idx;
2078         const struct pvr2_string_table *cm;
2079         const struct pvr2_device_client_table *ct;
2080
2081         cm = &hdw->hdw_desc->client_modules;
2082         for (idx = 0; idx < cm->cnt; idx++) {
2083                 request_module(cm->lst[idx]);
2084         }
2085
2086         ct = &hdw->hdw_desc->client_table;
2087         for (idx = 0; idx < ct->cnt; idx++) {
2088                 pvr2_hdw_load_subdev(hdw,&ct->lst[idx]);
2089         }
2090 }
2091
2092
2093 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2094 {
2095         int ret;
2096         unsigned int idx;
2097         struct pvr2_ctrl *cptr;
2098         int reloadFl = 0;
2099         if (hdw->hdw_desc->fx2_firmware.cnt) {
2100                 if (!reloadFl) {
2101                         reloadFl =
2102                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2103                                  == 0);
2104                         if (reloadFl) {
2105                                 pvr2_trace(PVR2_TRACE_INIT,
2106                                            "USB endpoint config looks strange"
2107                                            "; possibly firmware needs to be"
2108                                            " loaded");
2109                         }
2110                 }
2111                 if (!reloadFl) {
2112                         reloadFl = !pvr2_hdw_check_firmware(hdw);
2113                         if (reloadFl) {
2114                                 pvr2_trace(PVR2_TRACE_INIT,
2115                                            "Check for FX2 firmware failed"
2116                                            "; possibly firmware needs to be"
2117                                            " loaded");
2118                         }
2119                 }
2120                 if (reloadFl) {
2121                         if (pvr2_upload_firmware1(hdw) != 0) {
2122                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2123                                            "Failure uploading firmware1");
2124                         }
2125                         return;
2126                 }
2127         }
2128         hdw->fw1_state = FW1_STATE_OK;
2129
2130         if (!pvr2_hdw_dev_ok(hdw)) return;
2131
2132         if (!hdw->hdw_desc->flag_no_powerup) {
2133                 pvr2_hdw_cmd_powerup(hdw);
2134                 if (!pvr2_hdw_dev_ok(hdw)) return;
2135         }
2136
2137         /* Take the IR chip out of reset, if appropriate */
2138         if (hdw->hdw_desc->ir_scheme == PVR2_IR_SCHEME_ZILOG) {
2139                 pvr2_issue_simple_cmd(hdw,
2140                                       FX2CMD_HCW_ZILOG_RESET |
2141                                       (1 << 8) |
2142                                       ((0) << 16));
2143         }
2144
2145         // This step MUST happen after the earlier powerup step.
2146         pvr2_i2c_track_init(hdw);
2147         pvr2_i2c_core_init(hdw);
2148         if (!pvr2_hdw_dev_ok(hdw)) return;
2149
2150         pvr2_hdw_load_modules(hdw);
2151
2152         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2153                 cptr = hdw->controls + idx;
2154                 if (cptr->info->skip_init) continue;
2155                 if (!cptr->info->set_value) continue;
2156                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2157         }
2158
2159         /* Set up special default values for the television and radio
2160            frequencies here.  It's not really important what these defaults
2161            are, but I set them to something usable in the Chicago area just
2162            to make driver testing a little easier. */
2163
2164         hdw->freqValTelevision = default_tv_freq;
2165         hdw->freqValRadio = default_radio_freq;
2166
2167         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2168         // thread-safe against the normal pvr2_send_request() mechanism.
2169         // (We should make it thread safe).
2170
2171         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2172                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2173                 if (!pvr2_hdw_dev_ok(hdw)) return;
2174                 if (ret < 0) {
2175                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2176                                    "Unable to determine location of eeprom,"
2177                                    " skipping");
2178                 } else {
2179                         hdw->eeprom_addr = ret;
2180                         pvr2_eeprom_analyze(hdw);
2181                         if (!pvr2_hdw_dev_ok(hdw)) return;
2182                 }
2183         } else {
2184                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2185                 hdw->tuner_updated = !0;
2186                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2187         }
2188
2189         if (hdw->serial_number) {
2190                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2191                                 "sn-%lu", hdw->serial_number);
2192         } else if (hdw->unit_number >= 0) {
2193                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2194                                 "unit-%c",
2195                                 hdw->unit_number + 'a');
2196         } else {
2197                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2198                                 "unit-??");
2199         }
2200         hdw->identifier[idx] = 0;
2201
2202         pvr2_hdw_setup_std(hdw);
2203
2204         if (!get_default_tuner_type(hdw)) {
2205                 pvr2_trace(PVR2_TRACE_INIT,
2206                            "pvr2_hdw_setup: Tuner type overridden to %d",
2207                            hdw->tuner_type);
2208         }
2209
2210         pvr2_i2c_core_check_stale(hdw);
2211         hdw->tuner_updated = 0;
2212
2213         if (!pvr2_hdw_dev_ok(hdw)) return;
2214
2215         if (hdw->hdw_desc->signal_routing_scheme ==
2216             PVR2_ROUTING_SCHEME_GOTVIEW) {
2217                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2218                    hardware. */
2219                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2220         }
2221
2222         pvr2_hdw_commit_setup(hdw);
2223
2224         hdw->vid_stream = pvr2_stream_create();
2225         if (!pvr2_hdw_dev_ok(hdw)) return;
2226         pvr2_trace(PVR2_TRACE_INIT,
2227                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2228         if (hdw->vid_stream) {
2229                 idx = get_default_error_tolerance(hdw);
2230                 if (idx) {
2231                         pvr2_trace(PVR2_TRACE_INIT,
2232                                    "pvr2_hdw_setup: video stream %p"
2233                                    " setting tolerance %u",
2234                                    hdw->vid_stream,idx);
2235                 }
2236                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2237                                   PVR2_VID_ENDPOINT,idx);
2238         }
2239
2240         if (!pvr2_hdw_dev_ok(hdw)) return;
2241
2242         hdw->flag_init_ok = !0;
2243
2244         pvr2_hdw_state_sched(hdw);
2245 }
2246
2247
2248 /* Set up the structure and attempt to put the device into a usable state.
2249    This can be a time-consuming operation, which is why it is not done
2250    internally as part of the create() step. */
2251 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2252 {
2253         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2254         do {
2255                 pvr2_hdw_setup_low(hdw);
2256                 pvr2_trace(PVR2_TRACE_INIT,
2257                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2258                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2259                 if (pvr2_hdw_dev_ok(hdw)) {
2260                         if (hdw->flag_init_ok) {
2261                                 pvr2_trace(
2262                                         PVR2_TRACE_INFO,
2263                                         "Device initialization"
2264                                         " completed successfully.");
2265                                 break;
2266                         }
2267                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2268                                 pvr2_trace(
2269                                         PVR2_TRACE_INFO,
2270                                         "Device microcontroller firmware"
2271                                         " (re)loaded; it should now reset"
2272                                         " and reconnect.");
2273                                 break;
2274                         }
2275                         pvr2_trace(
2276                                 PVR2_TRACE_ERROR_LEGS,
2277                                 "Device initialization was not successful.");
2278                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2279                                 pvr2_trace(
2280                                         PVR2_TRACE_ERROR_LEGS,
2281                                         "Giving up since device"
2282                                         " microcontroller firmware"
2283                                         " appears to be missing.");
2284                                 break;
2285                         }
2286                 }
2287                 if (procreload) {
2288                         pvr2_trace(
2289                                 PVR2_TRACE_ERROR_LEGS,
2290                                 "Attempting pvrusb2 recovery by reloading"
2291                                 " primary firmware.");
2292                         pvr2_trace(
2293                                 PVR2_TRACE_ERROR_LEGS,
2294                                 "If this works, device should disconnect"
2295                                 " and reconnect in a sane state.");
2296                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2297                         pvr2_upload_firmware1(hdw);
2298                 } else {
2299                         pvr2_trace(
2300                                 PVR2_TRACE_ERROR_LEGS,
2301                                 "***WARNING*** pvrusb2 device hardware"
2302                                 " appears to be jammed"
2303                                 " and I can't clear it.");
2304                         pvr2_trace(
2305                                 PVR2_TRACE_ERROR_LEGS,
2306                                 "You might need to power cycle"
2307                                 " the pvrusb2 device"
2308                                 " in order to recover.");
2309                 }
2310         } while (0);
2311         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2312 }
2313
2314
2315 /* Perform second stage initialization.  Set callback pointer first so that
2316    we can avoid a possible initialization race (if the kernel thread runs
2317    before the callback has been set). */
2318 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2319                         void (*callback_func)(void *),
2320                         void *callback_data)
2321 {
2322         LOCK_TAKE(hdw->big_lock); do {
2323                 if (hdw->flag_disconnected) {
2324                         /* Handle a race here: If we're already
2325                            disconnected by this point, then give up.  If we
2326                            get past this then we'll remain connected for
2327                            the duration of initialization since the entire
2328                            initialization sequence is now protected by the
2329                            big_lock. */
2330                         break;
2331                 }
2332                 hdw->state_data = callback_data;
2333                 hdw->state_func = callback_func;
2334                 pvr2_hdw_setup(hdw);
2335         } while (0); LOCK_GIVE(hdw->big_lock);
2336         return hdw->flag_init_ok;
2337 }
2338
2339
2340 /* Create, set up, and return a structure for interacting with the
2341    underlying hardware.  */
2342 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2343                                  const struct usb_device_id *devid)
2344 {
2345         unsigned int idx,cnt1,cnt2,m;
2346         struct pvr2_hdw *hdw = NULL;
2347         int valid_std_mask;
2348         struct pvr2_ctrl *cptr;
2349         struct usb_device *usb_dev;
2350         const struct pvr2_device_desc *hdw_desc;
2351         __u8 ifnum;
2352         struct v4l2_queryctrl qctrl;
2353         struct pvr2_ctl_info *ciptr;
2354
2355         usb_dev = interface_to_usbdev(intf);
2356
2357         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2358
2359         if (hdw_desc == NULL) {
2360                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2361                            " No device description pointer,"
2362                            " unable to continue.");
2363                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2364                            " please contact Mike Isely <isely@pobox.com>"
2365                            " to get it included in the driver\n");
2366                 goto fail;
2367         }
2368
2369         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2370         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2371                    hdw,hdw_desc->description);
2372         if (!hdw) goto fail;
2373
2374         init_timer(&hdw->quiescent_timer);
2375         hdw->quiescent_timer.data = (unsigned long)hdw;
2376         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2377
2378         init_timer(&hdw->encoder_wait_timer);
2379         hdw->encoder_wait_timer.data = (unsigned long)hdw;
2380         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2381
2382         init_timer(&hdw->encoder_run_timer);
2383         hdw->encoder_run_timer.data = (unsigned long)hdw;
2384         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2385
2386         hdw->master_state = PVR2_STATE_DEAD;
2387
2388         init_waitqueue_head(&hdw->state_wait_data);
2389
2390         hdw->tuner_signal_stale = !0;
2391         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2392
2393         /* Calculate which inputs are OK */
2394         m = 0;
2395         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2396         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2397                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2398         }
2399         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2400         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2401         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2402         hdw->input_avail_mask = m;
2403         hdw->input_allowed_mask = hdw->input_avail_mask;
2404
2405         /* If not a hybrid device, pathway_state never changes.  So
2406            initialize it here to what it should forever be. */
2407         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2408                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2409         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2410                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2411         }
2412
2413         hdw->control_cnt = CTRLDEF_COUNT;
2414         hdw->control_cnt += MPEGDEF_COUNT;
2415         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2416                                 GFP_KERNEL);
2417         if (!hdw->controls) goto fail;
2418         hdw->hdw_desc = hdw_desc;
2419         for (idx = 0; idx < hdw->control_cnt; idx++) {
2420                 cptr = hdw->controls + idx;
2421                 cptr->hdw = hdw;
2422         }
2423         for (idx = 0; idx < 32; idx++) {
2424                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2425         }
2426         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2427                 cptr = hdw->controls + idx;
2428                 cptr->info = control_defs+idx;
2429         }
2430
2431         /* Ensure that default input choice is a valid one. */
2432         m = hdw->input_avail_mask;
2433         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2434                 if (!((1 << idx) & m)) continue;
2435                 hdw->input_val = idx;
2436                 break;
2437         }
2438
2439         /* Define and configure additional controls from cx2341x module. */
2440         hdw->mpeg_ctrl_info = kzalloc(
2441                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
2442         if (!hdw->mpeg_ctrl_info) goto fail;
2443         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2444                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2445                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2446                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2447                 ciptr->name = mpeg_ids[idx].strid;
2448                 ciptr->v4l_id = mpeg_ids[idx].id;
2449                 ciptr->skip_init = !0;
2450                 ciptr->get_value = ctrl_cx2341x_get;
2451                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2452                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2453                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2454                 qctrl.id = ciptr->v4l_id;
2455                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2456                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2457                         ciptr->set_value = ctrl_cx2341x_set;
2458                 }
2459                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2460                         PVR2_CTLD_INFO_DESC_SIZE);
2461                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2462                 ciptr->default_value = qctrl.default_value;
2463                 switch (qctrl.type) {
2464                 default:
2465                 case V4L2_CTRL_TYPE_INTEGER:
2466                         ciptr->type = pvr2_ctl_int;
2467                         ciptr->def.type_int.min_value = qctrl.minimum;
2468                         ciptr->def.type_int.max_value = qctrl.maximum;
2469                         break;
2470                 case V4L2_CTRL_TYPE_BOOLEAN:
2471                         ciptr->type = pvr2_ctl_bool;
2472                         break;
2473                 case V4L2_CTRL_TYPE_MENU:
2474                         ciptr->type = pvr2_ctl_enum;
2475                         ciptr->def.type_enum.value_names =
2476                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2477                                                                 ciptr->v4l_id);
2478                         for (cnt1 = 0;
2479                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2480                              cnt1++) { }
2481                         ciptr->def.type_enum.count = cnt1;
2482                         break;
2483                 }
2484                 cptr->info = ciptr;
2485         }
2486
2487         // Initialize video standard enum dynamic control
2488         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2489         if (cptr) {
2490                 memcpy(&hdw->std_info_enum,cptr->info,
2491                        sizeof(hdw->std_info_enum));
2492                 cptr->info = &hdw->std_info_enum;
2493
2494         }
2495         // Initialize control data regarding video standard masks
2496         valid_std_mask = pvr2_std_get_usable();
2497         for (idx = 0; idx < 32; idx++) {
2498                 if (!(valid_std_mask & (1 << idx))) continue;
2499                 cnt1 = pvr2_std_id_to_str(
2500                         hdw->std_mask_names[idx],
2501                         sizeof(hdw->std_mask_names[idx])-1,
2502                         1 << idx);
2503                 hdw->std_mask_names[idx][cnt1] = 0;
2504         }
2505         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2506         if (cptr) {
2507                 memcpy(&hdw->std_info_avail,cptr->info,
2508                        sizeof(hdw->std_info_avail));
2509                 cptr->info = &hdw->std_info_avail;
2510                 hdw->std_info_avail.def.type_bitmask.bit_names =
2511                         hdw->std_mask_ptrs;
2512                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2513                         valid_std_mask;
2514         }
2515         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2516         if (cptr) {
2517                 memcpy(&hdw->std_info_cur,cptr->info,
2518                        sizeof(hdw->std_info_cur));
2519                 cptr->info = &hdw->std_info_cur;
2520                 hdw->std_info_cur.def.type_bitmask.bit_names =
2521                         hdw->std_mask_ptrs;
2522                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2523                         valid_std_mask;
2524         }
2525
2526         hdw->cropcap_stale = !0;
2527         hdw->eeprom_addr = -1;
2528         hdw->unit_number = -1;
2529         hdw->v4l_minor_number_video = -1;
2530         hdw->v4l_minor_number_vbi = -1;
2531         hdw->v4l_minor_number_radio = -1;
2532         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2533         if (!hdw->ctl_write_buffer) goto fail;
2534         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2535         if (!hdw->ctl_read_buffer) goto fail;
2536         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2537         if (!hdw->ctl_write_urb) goto fail;
2538         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2539         if (!hdw->ctl_read_urb) goto fail;
2540
2541         if (v4l2_device_register(&usb_dev->dev, &hdw->v4l2_dev) != 0) {
2542                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2543                            "Error registering with v4l core, giving up");
2544                 goto fail;
2545         }
2546         mutex_lock(&pvr2_unit_mtx); do {
2547                 for (idx = 0; idx < PVR_NUM; idx++) {
2548                         if (unit_pointers[idx]) continue;
2549                         hdw->unit_number = idx;
2550                         unit_pointers[idx] = hdw;
2551                         break;
2552                 }
2553         } while (0); mutex_unlock(&pvr2_unit_mtx);
2554
2555         cnt1 = 0;
2556         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2557         cnt1 += cnt2;
2558         if (hdw->unit_number >= 0) {
2559                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2560                                  ('a' + hdw->unit_number));
2561                 cnt1 += cnt2;
2562         }
2563         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2564         hdw->name[cnt1] = 0;
2565
2566         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2567         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2568         INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2569
2570         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2571                    hdw->unit_number,hdw->name);
2572
2573         hdw->tuner_type = -1;
2574         hdw->flag_ok = !0;
2575
2576         hdw->usb_intf = intf;
2577         hdw->usb_dev = usb_dev;
2578
2579         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2580
2581         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2582         usb_set_interface(hdw->usb_dev,ifnum,0);
2583
2584         mutex_init(&hdw->ctl_lock_mutex);
2585         mutex_init(&hdw->big_lock_mutex);
2586
2587         return hdw;
2588  fail:
2589         if (hdw) {
2590                 del_timer_sync(&hdw->quiescent_timer);
2591                 del_timer_sync(&hdw->encoder_run_timer);
2592                 del_timer_sync(&hdw->encoder_wait_timer);
2593                 if (hdw->workqueue) {
2594                         flush_workqueue(hdw->workqueue);
2595                         destroy_workqueue(hdw->workqueue);
2596                         hdw->workqueue = NULL;
2597                 }
2598                 usb_free_urb(hdw->ctl_read_urb);
2599                 usb_free_urb(hdw->ctl_write_urb);
2600                 kfree(hdw->ctl_read_buffer);
2601                 kfree(hdw->ctl_write_buffer);
2602                 kfree(hdw->controls);
2603                 kfree(hdw->mpeg_ctrl_info);
2604                 kfree(hdw->std_defs);
2605                 kfree(hdw->std_enum_names);
2606                 kfree(hdw);
2607         }
2608         return NULL;
2609 }
2610
2611
2612 /* Remove _all_ associations between this driver and the underlying USB
2613    layer. */
2614 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2615 {
2616         if (hdw->flag_disconnected) return;
2617         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2618         if (hdw->ctl_read_urb) {
2619                 usb_kill_urb(hdw->ctl_read_urb);
2620                 usb_free_urb(hdw->ctl_read_urb);
2621                 hdw->ctl_read_urb = NULL;
2622         }
2623         if (hdw->ctl_write_urb) {
2624                 usb_kill_urb(hdw->ctl_write_urb);
2625                 usb_free_urb(hdw->ctl_write_urb);
2626                 hdw->ctl_write_urb = NULL;
2627         }
2628         if (hdw->ctl_read_buffer) {
2629                 kfree(hdw->ctl_read_buffer);
2630                 hdw->ctl_read_buffer = NULL;
2631         }
2632         if (hdw->ctl_write_buffer) {
2633                 kfree(hdw->ctl_write_buffer);
2634                 hdw->ctl_write_buffer = NULL;
2635         }
2636         hdw->flag_disconnected = !0;
2637         /* If we don't do this, then there will be a dangling struct device
2638            reference to our disappearing device persisting inside the V4L
2639            core... */
2640         if (hdw->v4l2_dev.dev) {
2641                 dev_set_drvdata(hdw->v4l2_dev.dev, NULL);
2642                 hdw->v4l2_dev.dev = NULL;
2643         }
2644         hdw->usb_dev = NULL;
2645         hdw->usb_intf = NULL;
2646         pvr2_hdw_render_useless(hdw);
2647 }
2648
2649
2650 /* Destroy hardware interaction structure */
2651 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2652 {
2653         if (!hdw) return;
2654         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2655         if (hdw->workqueue) {
2656                 flush_workqueue(hdw->workqueue);
2657                 destroy_workqueue(hdw->workqueue);
2658                 hdw->workqueue = NULL;
2659         }
2660         del_timer_sync(&hdw->quiescent_timer);
2661         del_timer_sync(&hdw->encoder_run_timer);
2662         del_timer_sync(&hdw->encoder_wait_timer);
2663         if (hdw->fw_buffer) {
2664                 kfree(hdw->fw_buffer);
2665                 hdw->fw_buffer = NULL;
2666         }
2667         if (hdw->vid_stream) {
2668                 pvr2_stream_destroy(hdw->vid_stream);
2669                 hdw->vid_stream = NULL;
2670         }
2671         if (hdw->decoder_ctrl) {
2672                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2673         }
2674         pvr2_i2c_core_done(hdw);
2675         pvr2_i2c_track_done(hdw);
2676         v4l2_device_unregister(&hdw->v4l2_dev);
2677         pvr2_hdw_remove_usb_stuff(hdw);
2678         mutex_lock(&pvr2_unit_mtx); do {
2679                 if ((hdw->unit_number >= 0) &&
2680                     (hdw->unit_number < PVR_NUM) &&
2681                     (unit_pointers[hdw->unit_number] == hdw)) {
2682                         unit_pointers[hdw->unit_number] = NULL;
2683                 }
2684         } while (0); mutex_unlock(&pvr2_unit_mtx);
2685         kfree(hdw->controls);
2686         kfree(hdw->mpeg_ctrl_info);
2687         kfree(hdw->std_defs);
2688         kfree(hdw->std_enum_names);
2689         kfree(hdw);
2690 }
2691
2692
2693 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2694 {
2695         return (hdw && hdw->flag_ok);
2696 }
2697
2698
2699 /* Called when hardware has been unplugged */
2700 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2701 {
2702         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2703         LOCK_TAKE(hdw->big_lock);
2704         LOCK_TAKE(hdw->ctl_lock);
2705         pvr2_hdw_remove_usb_stuff(hdw);
2706         LOCK_GIVE(hdw->ctl_lock);
2707         LOCK_GIVE(hdw->big_lock);
2708 }
2709
2710
2711 // Attempt to autoselect an appropriate value for std_enum_cur given
2712 // whatever is currently in std_mask_cur
2713 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2714 {
2715         unsigned int idx;
2716         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2717                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2718                         hdw->std_enum_cur = idx;
2719                         return;
2720                 }
2721         }
2722         hdw->std_enum_cur = 0;
2723 }
2724
2725
2726 // Calculate correct set of enumerated standards based on currently known
2727 // set of available standards bits.
2728 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2729 {
2730         struct v4l2_standard *newstd;
2731         unsigned int std_cnt;
2732         unsigned int idx;
2733
2734         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2735
2736         if (hdw->std_defs) {
2737                 kfree(hdw->std_defs);
2738                 hdw->std_defs = NULL;
2739         }
2740         hdw->std_enum_cnt = 0;
2741         if (hdw->std_enum_names) {
2742                 kfree(hdw->std_enum_names);
2743                 hdw->std_enum_names = NULL;
2744         }
2745
2746         if (!std_cnt) {
2747                 pvr2_trace(
2748                         PVR2_TRACE_ERROR_LEGS,
2749                         "WARNING: Failed to identify any viable standards");
2750         }
2751         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2752         hdw->std_enum_names[0] = "none";
2753         for (idx = 0; idx < std_cnt; idx++) {
2754                 hdw->std_enum_names[idx+1] =
2755                         newstd[idx].name;
2756         }
2757         // Set up the dynamic control for this standard
2758         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2759         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2760         hdw->std_defs = newstd;
2761         hdw->std_enum_cnt = std_cnt+1;
2762         hdw->std_enum_cur = 0;
2763         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2764 }
2765
2766
2767 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2768                                struct v4l2_standard *std,
2769                                unsigned int idx)
2770 {
2771         int ret = -EINVAL;
2772         if (!idx) return ret;
2773         LOCK_TAKE(hdw->big_lock); do {
2774                 if (idx >= hdw->std_enum_cnt) break;
2775                 idx--;
2776                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2777                 ret = 0;
2778         } while (0); LOCK_GIVE(hdw->big_lock);
2779         return ret;
2780 }
2781
2782
2783 /* Get the number of defined controls */
2784 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2785 {
2786         return hdw->control_cnt;
2787 }
2788
2789
2790 /* Retrieve a control handle given its index (0..count-1) */
2791 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2792                                              unsigned int idx)
2793 {
2794         if (idx >= hdw->control_cnt) return NULL;
2795         return hdw->controls + idx;
2796 }
2797
2798
2799 /* Retrieve a control handle given its index (0..count-1) */
2800 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2801                                           unsigned int ctl_id)
2802 {
2803         struct pvr2_ctrl *cptr;
2804         unsigned int idx;
2805         int i;
2806
2807         /* This could be made a lot more efficient, but for now... */
2808         for (idx = 0; idx < hdw->control_cnt; idx++) {
2809                 cptr = hdw->controls + idx;
2810                 i = cptr->info->internal_id;
2811                 if (i && (i == ctl_id)) return cptr;
2812         }
2813         return NULL;
2814 }
2815
2816
2817 /* Given a V4L ID, retrieve the control structure associated with it. */
2818 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2819 {
2820         struct pvr2_ctrl *cptr;
2821         unsigned int idx;
2822         int i;
2823
2824         /* This could be made a lot more efficient, but for now... */
2825         for (idx = 0; idx < hdw->control_cnt; idx++) {
2826                 cptr = hdw->controls + idx;
2827                 i = cptr->info->v4l_id;
2828                 if (i && (i == ctl_id)) return cptr;
2829         }
2830         return NULL;
2831 }
2832
2833
2834 /* Given a V4L ID for its immediate predecessor, retrieve the control
2835    structure associated with it. */
2836 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2837                                             unsigned int ctl_id)
2838 {
2839         struct pvr2_ctrl *cptr,*cp2;
2840         unsigned int idx;
2841         int i;
2842
2843         /* This could be made a lot more efficient, but for now... */
2844         cp2 = NULL;
2845         for (idx = 0; idx < hdw->control_cnt; idx++) {
2846                 cptr = hdw->controls + idx;
2847                 i = cptr->info->v4l_id;
2848                 if (!i) continue;
2849                 if (i <= ctl_id) continue;
2850                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2851                 cp2 = cptr;
2852         }
2853         return cp2;
2854         return NULL;
2855 }
2856
2857
2858 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2859 {
2860         switch (tp) {
2861         case pvr2_ctl_int: return "integer";
2862         case pvr2_ctl_enum: return "enum";
2863         case pvr2_ctl_bool: return "boolean";
2864         case pvr2_ctl_bitmask: return "bitmask";
2865         }
2866         return "";
2867 }
2868
2869
2870 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2871                                     const char *name, int val)
2872 {
2873         struct v4l2_control ctrl;
2874         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2875         memset(&ctrl, 0, sizeof(ctrl));
2876         ctrl.id = id;
2877         ctrl.value = val;
2878         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2879 }
2880
2881 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2882         if ((hdw)->lab##_dirty) { \
2883                 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2884         }
2885
2886 /* Execute whatever commands are required to update the state of all the
2887    sub-devices so that they match our current control values. */
2888 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2889 {
2890         if (hdw->input_dirty || hdw->std_dirty) {
2891                 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_standard");
2892                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2893                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2894                                              tuner, s_radio);
2895                 } else {
2896                         v4l2_std_id vs;
2897                         vs = hdw->std_mask_cur;
2898                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
2899                                              tuner, s_std, vs);
2900                 }
2901                 hdw->tuner_signal_stale = !0;
2902                 hdw->cropcap_stale = !0;
2903         }
2904
2905         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2906         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2907         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2908         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2909         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2910         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2911         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2912         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2913         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2914
2915         if (hdw->input_dirty || hdw->audiomode_dirty) {
2916                 struct v4l2_tuner vt;
2917                 memset(&vt, 0, sizeof(vt));
2918                 vt.audmode = hdw->audiomode_val;
2919                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2920         }
2921
2922         if (hdw->freqDirty) {
2923                 unsigned long fv;
2924                 struct v4l2_frequency freq;
2925                 fv = pvr2_hdw_get_cur_freq(hdw);
2926                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2927                 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2928                 memset(&freq, 0, sizeof(freq));
2929                 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2930                         /* ((fv * 1000) / 62500) */
2931                         freq.frequency = (fv * 2) / 125;
2932                 } else {
2933                         freq.frequency = fv / 62500;
2934                 }
2935                 /* tuner-core currently doesn't seem to care about this, but
2936                    let's set it anyway for completeness. */
2937                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2938                         freq.type = V4L2_TUNER_RADIO;
2939                 } else {
2940                         freq.type = V4L2_TUNER_ANALOG_TV;
2941                 }
2942                 freq.tuner = 0;
2943                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2944                                      s_frequency, &freq);
2945         }
2946
2947         if (hdw->res_hor_dirty || hdw->res_ver_dirty) {
2948                 struct v4l2_format fmt;
2949                 memset(&fmt, 0, sizeof(fmt));
2950                 fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2951                 fmt.fmt.pix.width = hdw->res_hor_val;
2952                 fmt.fmt.pix.height = hdw->res_ver_val;
2953                 pvr2_trace(PVR2_TRACE_CHIPS,"subdev v4l2 set_size(%dx%d)",
2954                            fmt.fmt.pix.width, fmt.fmt.pix.height);
2955                 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_fmt, &fmt);
2956         }
2957
2958         /* Unable to set crop parameters; there is apparently no equivalent
2959            for VIDIOC_S_CROP */
2960
2961         /* ????? Cover special cases for specific sub-devices. */
2962
2963         if (hdw->tuner_signal_stale && hdw->cropcap_stale) {
2964                 pvr2_hdw_status_poll(hdw);
2965         }
2966 }
2967
2968
2969 /* Figure out if we need to commit control changes.  If so, mark internal
2970    state flags to indicate this fact and return true.  Otherwise do nothing
2971    else and return false. */
2972 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2973 {
2974         unsigned int idx;
2975         struct pvr2_ctrl *cptr;
2976         int value;
2977         int commit_flag = 0;
2978         char buf[100];
2979         unsigned int bcnt,ccnt;
2980
2981         for (idx = 0; idx < hdw->control_cnt; idx++) {
2982                 cptr = hdw->controls + idx;
2983                 if (!cptr->info->is_dirty) continue;
2984                 if (!cptr->info->is_dirty(cptr)) continue;
2985                 commit_flag = !0;
2986
2987                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2988                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2989                                  cptr->info->name);
2990                 value = 0;
2991                 cptr->info->get_value(cptr,&value);
2992                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2993                                                 buf+bcnt,
2994                                                 sizeof(buf)-bcnt,&ccnt);
2995                 bcnt += ccnt;
2996                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2997                                   get_ctrl_typename(cptr->info->type));
2998                 pvr2_trace(PVR2_TRACE_CTL,
2999                            "/*--TRACE_COMMIT--*/ %.*s",
3000                            bcnt,buf);
3001         }
3002
3003         if (!commit_flag) {
3004                 /* Nothing has changed */
3005                 return 0;
3006         }
3007
3008         hdw->state_pipeline_config = 0;
3009         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3010         pvr2_hdw_state_sched(hdw);
3011
3012         return !0;
3013 }
3014
3015
3016 /* Perform all operations needed to commit all control changes.  This must
3017    be performed in synchronization with the pipeline state and is thus
3018    expected to be called as part of the driver's worker thread.  Return
3019    true if commit successful, otherwise return false to indicate that
3020    commit isn't possible at this time. */
3021 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3022 {
3023         unsigned int idx;
3024         struct pvr2_ctrl *cptr;
3025         int disruptive_change;
3026
3027         /* Handle some required side effects when the video standard is
3028            changed.... */
3029         if (hdw->std_dirty) {
3030                 int nvres;
3031                 int gop_size;
3032                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3033                         nvres = 480;
3034                         gop_size = 15;
3035                 } else {
3036                         nvres = 576;
3037                         gop_size = 12;
3038                 }
3039                 /* Rewrite the vertical resolution to be appropriate to the
3040                    video standard that has been selected. */
3041                 if (nvres != hdw->res_ver_val) {
3042                         hdw->res_ver_val = nvres;
3043                         hdw->res_ver_dirty = !0;
3044                 }
3045                 /* Rewrite the GOP size to be appropriate to the video
3046                    standard that has been selected. */
3047                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3048                         struct v4l2_ext_controls cs;
3049                         struct v4l2_ext_control c1;
3050                         memset(&cs, 0, sizeof(cs));
3051                         memset(&c1, 0, sizeof(c1));
3052                         cs.controls = &c1;
3053                         cs.count = 1;
3054                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3055                         c1.value = gop_size;
3056                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3057                                           VIDIOC_S_EXT_CTRLS);
3058                 }
3059         }
3060
3061         if (hdw->input_dirty && hdw->state_pathway_ok &&
3062             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3063               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3064              hdw->pathway_state)) {
3065                 /* Change of mode being asked for... */
3066                 hdw->state_pathway_ok = 0;
3067                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3068         }
3069         if (!hdw->state_pathway_ok) {
3070                 /* Can't commit anything until pathway is ok. */
3071                 return 0;
3072         }
3073         /* The broadcast decoder can only scale down, so if
3074          * res_*_dirty && crop window < output format ==> enlarge crop.
3075          *
3076          * The mpeg encoder receives fields of res_hor_val dots and
3077          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3078          */
3079         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3080                 hdw->cropw_val = hdw->res_hor_val;
3081                 hdw->cropw_dirty = !0;
3082         } else if (hdw->cropw_dirty) {
3083                 hdw->res_hor_dirty = !0;           /* must rescale */
3084                 hdw->res_hor_val = min(720, hdw->cropw_val);
3085         }
3086         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3087                 hdw->croph_val = hdw->res_ver_val;
3088                 hdw->croph_dirty = !0;
3089         } else if (hdw->croph_dirty) {
3090                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3091                 hdw->res_ver_dirty = !0;
3092                 hdw->res_ver_val = min(nvres, hdw->croph_val);
3093         }
3094
3095         /* If any of the below has changed, then we can't do the update
3096            while the pipeline is running.  Pipeline must be paused first
3097            and decoder -> encoder connection be made quiescent before we
3098            can proceed. */
3099         disruptive_change =
3100                 (hdw->std_dirty ||
3101                  hdw->enc_unsafe_stale ||
3102                  hdw->srate_dirty ||
3103                  hdw->res_ver_dirty ||
3104                  hdw->res_hor_dirty ||
3105                  hdw->cropw_dirty ||
3106                  hdw->croph_dirty ||
3107                  hdw->input_dirty ||
3108                  (hdw->active_stream_type != hdw->desired_stream_type));
3109         if (disruptive_change && !hdw->state_pipeline_idle) {
3110                 /* Pipeline is not idle; we can't proceed.  Arrange to
3111                    cause pipeline to stop so that we can try this again
3112                    later.... */
3113                 hdw->state_pipeline_pause = !0;
3114                 return 0;
3115         }
3116
3117         if (hdw->srate_dirty) {
3118                 /* Write new sample rate into control structure since
3119                  * the master copy is stale.  We must track srate
3120                  * separate from the mpeg control structure because
3121                  * other logic also uses this value. */
3122                 struct v4l2_ext_controls cs;
3123                 struct v4l2_ext_control c1;
3124                 memset(&cs,0,sizeof(cs));
3125                 memset(&c1,0,sizeof(c1));
3126                 cs.controls = &c1;
3127                 cs.count = 1;
3128                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3129                 c1.value = hdw->srate_val;
3130                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3131         }
3132
3133         /* Scan i2c core at this point - before we clear all the dirty
3134            bits.  Various parts of the i2c core will notice dirty bits as
3135            appropriate and arrange to broadcast or directly send updates to
3136            the client drivers in order to keep everything in sync */
3137         pvr2_i2c_core_check_stale(hdw);
3138
3139         if (hdw->active_stream_type != hdw->desired_stream_type) {
3140                 /* Handle any side effects of stream config here */
3141                 hdw->active_stream_type = hdw->desired_stream_type;
3142         }
3143
3144         if (hdw->hdw_desc->signal_routing_scheme ==
3145             PVR2_ROUTING_SCHEME_GOTVIEW) {
3146                 u32 b;
3147                 /* Handle GOTVIEW audio switching */
3148                 pvr2_hdw_gpio_get_out(hdw,&b);
3149                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3150                         /* Set GPIO 11 */
3151                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3152                 } else {
3153                         /* Clear GPIO 11 */
3154                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3155                 }
3156         }
3157
3158         for (idx = 0; idx < hdw->control_cnt; idx++) {
3159                 cptr = hdw->controls + idx;
3160                 if (!cptr->info->clear_dirty) continue;
3161                 cptr->info->clear_dirty(cptr);
3162         }
3163
3164         /* Check and update state for all sub-devices. */
3165         pvr2_subdev_update(hdw);
3166
3167         /* Now execute i2c core update */
3168         pvr2_i2c_core_sync(hdw);
3169
3170         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3171             hdw->state_encoder_run) {
3172                 /* If encoder isn't running or it can't be touched, then
3173                    this will get worked out later when we start the
3174                    encoder. */
3175                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3176         }
3177
3178         hdw->state_pipeline_config = !0;
3179         /* Hardware state may have changed in a way to cause the cropping
3180            capabilities to have changed.  So mark it stale, which will
3181            cause a later re-fetch. */
3182         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3183         return !0;
3184 }
3185
3186
3187 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3188 {
3189         int fl;
3190         LOCK_TAKE(hdw->big_lock);
3191         fl = pvr2_hdw_commit_setup(hdw);
3192         LOCK_GIVE(hdw->big_lock);
3193         if (!fl) return 0;
3194         return pvr2_hdw_wait(hdw,0);
3195 }
3196
3197
3198 static void pvr2_hdw_worker_i2c(struct work_struct *work)
3199 {
3200         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
3201         LOCK_TAKE(hdw->big_lock); do {
3202                 pvr2_i2c_core_sync(hdw);
3203         } while (0); LOCK_GIVE(hdw->big_lock);
3204 }
3205
3206
3207 static void pvr2_hdw_worker_poll(struct work_struct *work)
3208 {
3209         int fl = 0;
3210         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3211         LOCK_TAKE(hdw->big_lock); do {
3212                 fl = pvr2_hdw_state_eval(hdw);
3213         } while (0); LOCK_GIVE(hdw->big_lock);
3214         if (fl && hdw->state_func) {
3215                 hdw->state_func(hdw->state_data);
3216         }
3217 }
3218
3219
3220 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3221 {
3222         return wait_event_interruptible(
3223                 hdw->state_wait_data,
3224                 (hdw->state_stale == 0) &&
3225                 (!state || (hdw->master_state != state)));
3226 }
3227
3228
3229 /* Return name for this driver instance */
3230 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3231 {
3232         return hdw->name;
3233 }
3234
3235
3236 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3237 {
3238         return hdw->hdw_desc->description;
3239 }
3240
3241
3242 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3243 {
3244         return hdw->hdw_desc->shortname;
3245 }
3246
3247
3248 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3249 {
3250         int result;
3251         LOCK_TAKE(hdw->ctl_lock); do {
3252                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3253                 result = pvr2_send_request(hdw,
3254                                            hdw->cmd_buffer,1,
3255                                            hdw->cmd_buffer,1);
3256                 if (result < 0) break;
3257                 result = (hdw->cmd_buffer[0] != 0);
3258         } while(0); LOCK_GIVE(hdw->ctl_lock);
3259         return result;
3260 }
3261
3262
3263 /* Execute poll of tuner status */
3264 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3265 {
3266         LOCK_TAKE(hdw->big_lock); do {
3267                 pvr2_hdw_status_poll(hdw);
3268         } while (0); LOCK_GIVE(hdw->big_lock);
3269 }
3270
3271
3272 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3273 {
3274         if (!hdw->cropcap_stale) {
3275                 return 0;
3276         }
3277         pvr2_hdw_status_poll(hdw);
3278         if (hdw->cropcap_stale) {
3279                 return -EIO;
3280         }
3281         return 0;
3282 }
3283
3284
3285 /* Return information about cropping capabilities */
3286 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3287 {
3288         int stat = 0;
3289         LOCK_TAKE(hdw->big_lock);
3290         stat = pvr2_hdw_check_cropcap(hdw);
3291         if (!stat) {
3292                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3293         }
3294         LOCK_GIVE(hdw->big_lock);
3295         return stat;
3296 }
3297
3298
3299 /* Return information about the tuner */
3300 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3301 {
3302         LOCK_TAKE(hdw->big_lock); do {
3303                 if (hdw->tuner_signal_stale) {
3304                         pvr2_hdw_status_poll(hdw);
3305                 }
3306                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3307         } while (0); LOCK_GIVE(hdw->big_lock);
3308         return 0;
3309 }
3310
3311
3312 /* Get handle to video output stream */
3313 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3314 {
3315         return hp->vid_stream;
3316 }
3317
3318
3319 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3320 {
3321         int nr = pvr2_hdw_get_unit_number(hdw);
3322         LOCK_TAKE(hdw->big_lock); do {
3323                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3324                 hdw->log_requested = !0;
3325                 pvr2_i2c_core_check_stale(hdw);
3326                 pvr2_i2c_core_sync(hdw);
3327                 hdw->log_requested = 0;
3328                 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3329                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3330                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3331                 pvr2_hdw_state_log_state(hdw);
3332                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3333         } while (0); LOCK_GIVE(hdw->big_lock);
3334 }
3335
3336
3337 /* Grab EEPROM contents, needed for direct method. */
3338 #define EEPROM_SIZE 8192
3339 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3340 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3341 {
3342         struct i2c_msg msg[2];
3343         u8 *eeprom;
3344         u8 iadd[2];
3345         u8 addr;
3346         u16 eepromSize;
3347         unsigned int offs;
3348         int ret;
3349         int mode16 = 0;
3350         unsigned pcnt,tcnt;
3351         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3352         if (!eeprom) {
3353                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3354                            "Failed to allocate memory"
3355                            " required to read eeprom");
3356                 return NULL;
3357         }
3358
3359         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3360                      hdw->eeprom_addr);
3361         addr = hdw->eeprom_addr;
3362         /* Seems that if the high bit is set, then the *real* eeprom
3363            address is shifted right now bit position (noticed this in
3364            newer PVR USB2 hardware) */
3365         if (addr & 0x80) addr >>= 1;
3366
3367         /* FX2 documentation states that a 16bit-addressed eeprom is
3368            expected if the I2C address is an odd number (yeah, this is
3369            strange but it's what they do) */
3370         mode16 = (addr & 1);
3371         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3372         trace_eeprom("Examining %d byte eeprom at location 0x%x"
3373                      " using %d bit addressing",eepromSize,addr,
3374                      mode16 ? 16 : 8);
3375
3376         msg[0].addr = addr;
3377         msg[0].flags = 0;
3378         msg[0].len = mode16 ? 2 : 1;
3379         msg[0].buf = iadd;
3380         msg[1].addr = addr;
3381         msg[1].flags = I2C_M_RD;
3382
3383         /* We have to do the actual eeprom data fetch ourselves, because
3384            (1) we're only fetching part of the eeprom, and (2) if we were
3385            getting the whole thing our I2C driver can't grab it in one
3386            pass - which is what tveeprom is otherwise going to attempt */
3387         memset(eeprom,0,EEPROM_SIZE);
3388         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3389                 pcnt = 16;
3390                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3391                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3392                 if (mode16) {
3393                         iadd[0] = offs >> 8;
3394                         iadd[1] = offs;
3395                 } else {
3396                         iadd[0] = offs;
3397                 }
3398                 msg[1].len = pcnt;
3399                 msg[1].buf = eeprom+tcnt;
3400                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3401                                         msg,ARRAY_SIZE(msg))) != 2) {
3402                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3403                                    "eeprom fetch set offs err=%d",ret);
3404                         kfree(eeprom);
3405                         return NULL;
3406                 }
3407         }
3408         return eeprom;
3409 }
3410
3411
3412 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3413                                 int prom_flag,
3414                                 int enable_flag)
3415 {
3416         int ret;
3417         u16 address;
3418         unsigned int pipe;
3419         LOCK_TAKE(hdw->big_lock); do {
3420                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3421
3422                 if (!enable_flag) {
3423                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3424                                    "Cleaning up after CPU firmware fetch");
3425                         kfree(hdw->fw_buffer);
3426                         hdw->fw_buffer = NULL;
3427                         hdw->fw_size = 0;
3428                         if (hdw->fw_cpu_flag) {
3429                                 /* Now release the CPU.  It will disconnect
3430                                    and reconnect later. */
3431                                 pvr2_hdw_cpureset_assert(hdw,0);
3432                         }
3433                         break;
3434                 }
3435
3436                 hdw->fw_cpu_flag = (prom_flag == 0);
3437                 if (hdw->fw_cpu_flag) {
3438                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3439                                    "Preparing to suck out CPU firmware");
3440                         hdw->fw_size = 0x2000;
3441                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3442                         if (!hdw->fw_buffer) {
3443                                 hdw->fw_size = 0;
3444                                 break;
3445                         }
3446
3447                         /* We have to hold the CPU during firmware upload. */
3448                         pvr2_hdw_cpureset_assert(hdw,1);
3449
3450                         /* download the firmware from address 0000-1fff in 2048
3451                            (=0x800) bytes chunk. */
3452
3453                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3454                                    "Grabbing CPU firmware");
3455                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3456                         for(address = 0; address < hdw->fw_size;
3457                             address += 0x800) {
3458                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3459                                                       0xa0,0xc0,
3460                                                       address,0,
3461                                                       hdw->fw_buffer+address,
3462                                                       0x800,HZ);
3463                                 if (ret < 0) break;
3464                         }
3465
3466                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3467                                    "Done grabbing CPU firmware");
3468                 } else {
3469                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3470                                    "Sucking down EEPROM contents");
3471                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3472                         if (!hdw->fw_buffer) {
3473                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3474                                            "EEPROM content suck failed.");
3475                                 break;
3476                         }
3477                         hdw->fw_size = EEPROM_SIZE;
3478                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3479                                    "Done sucking down EEPROM contents");
3480                 }
3481
3482         } while (0); LOCK_GIVE(hdw->big_lock);
3483 }
3484
3485
3486 /* Return true if we're in a mode for retrieval CPU firmware */
3487 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3488 {
3489         return hdw->fw_buffer != NULL;
3490 }
3491
3492
3493 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3494                        char *buf,unsigned int cnt)
3495 {
3496         int ret = -EINVAL;
3497         LOCK_TAKE(hdw->big_lock); do {
3498                 if (!buf) break;
3499                 if (!cnt) break;
3500
3501                 if (!hdw->fw_buffer) {
3502                         ret = -EIO;
3503                         break;
3504                 }
3505
3506                 if (offs >= hdw->fw_size) {
3507                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3508                                    "Read firmware data offs=%d EOF",
3509                                    offs);
3510                         ret = 0;
3511                         break;
3512                 }
3513
3514                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3515
3516                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3517
3518                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3519                            "Read firmware data offs=%d cnt=%d",
3520                            offs,cnt);
3521                 ret = cnt;
3522         } while (0); LOCK_GIVE(hdw->big_lock);
3523
3524         return ret;
3525 }
3526
3527
3528 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3529                                   enum pvr2_v4l_type index)
3530 {
3531         switch (index) {
3532         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3533         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3534         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3535         default: return -1;
3536         }
3537 }
3538
3539
3540 /* Store a v4l minor device number */
3541 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3542                                      enum pvr2_v4l_type index,int v)
3543 {
3544         switch (index) {
3545         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3546         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3547         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3548         default: break;
3549         }
3550 }
3551
3552
3553 static void pvr2_ctl_write_complete(struct urb *urb)
3554 {
3555         struct pvr2_hdw *hdw = urb->context;
3556         hdw->ctl_write_pend_flag = 0;
3557         if (hdw->ctl_read_pend_flag) return;
3558         complete(&hdw->ctl_done);
3559 }
3560
3561
3562 static void pvr2_ctl_read_complete(struct urb *urb)
3563 {
3564         struct pvr2_hdw *hdw = urb->context;
3565         hdw->ctl_read_pend_flag = 0;
3566         if (hdw->ctl_write_pend_flag) return;
3567         complete(&hdw->ctl_done);
3568 }
3569
3570
3571 static void pvr2_ctl_timeout(unsigned long data)
3572 {
3573         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3574         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3575                 hdw->ctl_timeout_flag = !0;
3576                 if (hdw->ctl_write_pend_flag)
3577                         usb_unlink_urb(hdw->ctl_write_urb);
3578                 if (hdw->ctl_read_pend_flag)
3579                         usb_unlink_urb(hdw->ctl_read_urb);
3580         }
3581 }
3582
3583
3584 /* Issue a command and get a response from the device.  This extended
3585    version includes a probe flag (which if set means that device errors
3586    should not be logged or treated as fatal) and a timeout in jiffies.
3587    This can be used to non-lethally probe the health of endpoint 1. */
3588 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3589                                 unsigned int timeout,int probe_fl,
3590                                 void *write_data,unsigned int write_len,
3591                                 void *read_data,unsigned int read_len)
3592 {
3593         unsigned int idx;
3594         int status = 0;
3595         struct timer_list timer;
3596         if (!hdw->ctl_lock_held) {
3597                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3598                            "Attempted to execute control transfer"
3599                            " without lock!!");
3600                 return -EDEADLK;
3601         }
3602         if (!hdw->flag_ok && !probe_fl) {
3603                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3604                            "Attempted to execute control transfer"
3605                            " when device not ok");
3606                 return -EIO;
3607         }
3608         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3609                 if (!probe_fl) {
3610                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3611                                    "Attempted to execute control transfer"
3612                                    " when USB is disconnected");
3613                 }
3614                 return -ENOTTY;
3615         }
3616
3617         /* Ensure that we have sane parameters */
3618         if (!write_data) write_len = 0;
3619         if (!read_data) read_len = 0;
3620         if (write_len > PVR2_CTL_BUFFSIZE) {
3621                 pvr2_trace(
3622                         PVR2_TRACE_ERROR_LEGS,
3623                         "Attempted to execute %d byte"
3624                         " control-write transfer (limit=%d)",
3625                         write_len,PVR2_CTL_BUFFSIZE);
3626                 return -EINVAL;
3627         }
3628         if (read_len > PVR2_CTL_BUFFSIZE) {
3629                 pvr2_trace(
3630                         PVR2_TRACE_ERROR_LEGS,
3631                         "Attempted to execute %d byte"
3632                         " control-read transfer (limit=%d)",
3633                         write_len,PVR2_CTL_BUFFSIZE);
3634                 return -EINVAL;
3635         }
3636         if ((!write_len) && (!read_len)) {
3637                 pvr2_trace(
3638                         PVR2_TRACE_ERROR_LEGS,
3639                         "Attempted to execute null control transfer?");
3640                 return -EINVAL;
3641         }
3642
3643
3644         hdw->cmd_debug_state = 1;
3645         if (write_len) {
3646                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3647         } else {
3648                 hdw->cmd_debug_code = 0;
3649         }
3650         hdw->cmd_debug_write_len = write_len;
3651         hdw->cmd_debug_read_len = read_len;
3652
3653         /* Initialize common stuff */
3654         init_completion(&hdw->ctl_done);
3655         hdw->ctl_timeout_flag = 0;
3656         hdw->ctl_write_pend_flag = 0;
3657         hdw->ctl_read_pend_flag = 0;
3658         init_timer(&timer);
3659         timer.expires = jiffies + timeout;
3660         timer.data = (unsigned long)hdw;
3661         timer.function = pvr2_ctl_timeout;
3662
3663         if (write_len) {
3664                 hdw->cmd_debug_state = 2;
3665                 /* Transfer write data to internal buffer */
3666                 for (idx = 0; idx < write_len; idx++) {
3667                         hdw->ctl_write_buffer[idx] =
3668                                 ((unsigned char *)write_data)[idx];
3669                 }
3670                 /* Initiate a write request */
3671                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3672                                   hdw->usb_dev,
3673                                   usb_sndbulkpipe(hdw->usb_dev,
3674                                                   PVR2_CTL_WRITE_ENDPOINT),
3675                                   hdw->ctl_write_buffer,
3676                                   write_len,
3677                                   pvr2_ctl_write_complete,
3678                                   hdw);
3679                 hdw->ctl_write_urb->actual_length = 0;
3680                 hdw->ctl_write_pend_flag = !0;
3681                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3682                 if (status < 0) {
3683                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3684                                    "Failed to submit write-control"
3685                                    " URB status=%d",status);
3686                         hdw->ctl_write_pend_flag = 0;
3687                         goto done;
3688                 }
3689         }
3690
3691         if (read_len) {
3692                 hdw->cmd_debug_state = 3;
3693                 memset(hdw->ctl_read_buffer,0x43,read_len);
3694                 /* Initiate a read request */
3695                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3696                                   hdw->usb_dev,
3697                                   usb_rcvbulkpipe(hdw->usb_dev,
3698                                                   PVR2_CTL_READ_ENDPOINT),
3699                                   hdw->ctl_read_buffer,
3700                                   read_len,
3701                                   pvr2_ctl_read_complete,
3702                                   hdw);
3703                 hdw->ctl_read_urb->actual_length = 0;
3704                 hdw->ctl_read_pend_flag = !0;
3705                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3706                 if (status < 0) {
3707                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3708                                    "Failed to submit read-control"
3709                                    " URB status=%d",status);
3710                         hdw->ctl_read_pend_flag = 0;
3711                         goto done;
3712                 }
3713         }
3714
3715         /* Start timer */
3716         add_timer(&timer);
3717
3718         /* Now wait for all I/O to complete */
3719         hdw->cmd_debug_state = 4;
3720         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3721                 wait_for_completion(&hdw->ctl_done);
3722         }
3723         hdw->cmd_debug_state = 5;
3724
3725         /* Stop timer */
3726         del_timer_sync(&timer);
3727
3728         hdw->cmd_debug_state = 6;
3729         status = 0;
3730
3731         if (hdw->ctl_timeout_flag) {
3732                 status = -ETIMEDOUT;
3733                 if (!probe_fl) {
3734                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3735                                    "Timed out control-write");
3736                 }
3737                 goto done;
3738         }
3739
3740         if (write_len) {
3741                 /* Validate results of write request */
3742                 if ((hdw->ctl_write_urb->status != 0) &&
3743                     (hdw->ctl_write_urb->status != -ENOENT) &&
3744                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3745                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3746                         /* USB subsystem is reporting some kind of failure
3747                            on the write */
3748                         status = hdw->ctl_write_urb->status;
3749                         if (!probe_fl) {
3750                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3751                                            "control-write URB failure,"
3752                                            " status=%d",
3753                                            status);
3754                         }
3755                         goto done;
3756                 }
3757                 if (hdw->ctl_write_urb->actual_length < write_len) {
3758                         /* Failed to write enough data */
3759                         status = -EIO;
3760                         if (!probe_fl) {
3761                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3762                                            "control-write URB short,"
3763                                            " expected=%d got=%d",
3764                                            write_len,
3765                                            hdw->ctl_write_urb->actual_length);
3766                         }
3767                         goto done;
3768                 }
3769         }
3770         if (read_len) {
3771                 /* Validate results of read request */
3772                 if ((hdw->ctl_read_urb->status != 0) &&
3773                     (hdw->ctl_read_urb->status != -ENOENT) &&
3774                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3775                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3776                         /* USB subsystem is reporting some kind of failure
3777                            on the read */
3778                         status = hdw->ctl_read_urb->status;
3779                         if (!probe_fl) {
3780                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3781                                            "control-read URB failure,"
3782                                            " status=%d",
3783                                            status);
3784                         }
3785                         goto done;
3786                 }
3787                 if (hdw->ctl_read_urb->actual_length < read_len) {
3788                         /* Failed to read enough data */
3789                         status = -EIO;
3790                         if (!probe_fl) {
3791                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3792                                            "control-read URB short,"
3793                                            " expected=%d got=%d",
3794                                            read_len,
3795                                            hdw->ctl_read_urb->actual_length);
3796                         }
3797                         goto done;
3798                 }
3799                 /* Transfer retrieved data out from internal buffer */
3800                 for (idx = 0; idx < read_len; idx++) {
3801                         ((unsigned char *)read_data)[idx] =
3802                                 hdw->ctl_read_buffer[idx];
3803                 }
3804         }
3805
3806  done:
3807
3808         hdw->cmd_debug_state = 0;
3809         if ((status < 0) && (!probe_fl)) {
3810                 pvr2_hdw_render_useless(hdw);
3811         }
3812         return status;
3813 }
3814
3815
3816 int pvr2_send_request(struct pvr2_hdw *hdw,
3817                       void *write_data,unsigned int write_len,
3818                       void *read_data,unsigned int read_len)
3819 {
3820         return pvr2_send_request_ex(hdw,HZ*4,0,
3821                                     write_data,write_len,
3822                                     read_data,read_len);
3823 }
3824
3825
3826 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3827 {
3828         int ret;
3829         unsigned int cnt = 1;
3830         unsigned int args = 0;
3831         LOCK_TAKE(hdw->ctl_lock);
3832         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3833         args = (cmdcode >> 8) & 0xffu;
3834         args = (args > 2) ? 2 : args;
3835         if (args) {
3836                 cnt += args;
3837                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3838                 if (args > 1) {
3839                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3840                 }
3841         }
3842         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3843                 unsigned int idx;
3844                 unsigned int ccnt,bcnt;
3845                 char tbuf[50];
3846                 cmdcode &= 0xffu;
3847                 bcnt = 0;
3848                 ccnt = scnprintf(tbuf+bcnt,
3849                                  sizeof(tbuf)-bcnt,
3850                                  "Sending FX2 command 0x%x",cmdcode);
3851                 bcnt += ccnt;
3852                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3853                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3854                                 ccnt = scnprintf(tbuf+bcnt,
3855                                                  sizeof(tbuf)-bcnt,
3856                                                  " \"%s\"",
3857                                                  pvr2_fx2cmd_desc[idx].desc);
3858                                 bcnt += ccnt;
3859                                 break;
3860                         }
3861                 }
3862                 if (args) {
3863                         ccnt = scnprintf(tbuf+bcnt,
3864                                          sizeof(tbuf)-bcnt,
3865                                          " (%u",hdw->cmd_buffer[1]);
3866                         bcnt += ccnt;
3867                         if (args > 1) {
3868                                 ccnt = scnprintf(tbuf+bcnt,
3869                                                  sizeof(tbuf)-bcnt,
3870                                                  ",%u",hdw->cmd_buffer[2]);
3871                                 bcnt += ccnt;
3872                         }
3873                         ccnt = scnprintf(tbuf+bcnt,
3874                                          sizeof(tbuf)-bcnt,
3875                                          ")");
3876                         bcnt += ccnt;
3877                 }
3878                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3879         }
3880         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3881         LOCK_GIVE(hdw->ctl_lock);
3882         return ret;
3883 }
3884
3885
3886 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3887 {
3888         int ret;
3889
3890         LOCK_TAKE(hdw->ctl_lock);
3891
3892         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3893         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3894         hdw->cmd_buffer[5] = 0;
3895         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3896         hdw->cmd_buffer[7] = reg & 0xff;
3897
3898
3899         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3900
3901         LOCK_GIVE(hdw->ctl_lock);
3902
3903         return ret;
3904 }
3905
3906
3907 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3908 {
3909         int ret = 0;
3910
3911         LOCK_TAKE(hdw->ctl_lock);
3912
3913         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3914         hdw->cmd_buffer[1] = 0;
3915         hdw->cmd_buffer[2] = 0;
3916         hdw->cmd_buffer[3] = 0;
3917         hdw->cmd_buffer[4] = 0;
3918         hdw->cmd_buffer[5] = 0;
3919         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3920         hdw->cmd_buffer[7] = reg & 0xff;
3921
3922         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3923         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3924
3925         LOCK_GIVE(hdw->ctl_lock);
3926
3927         return ret;
3928 }
3929
3930
3931 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3932 {
3933         if (!hdw->flag_ok) return;
3934         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3935                    "Device being rendered inoperable");
3936         if (hdw->vid_stream) {
3937                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3938         }
3939         hdw->flag_ok = 0;
3940         trace_stbit("flag_ok",hdw->flag_ok);
3941         pvr2_hdw_state_sched(hdw);
3942 }
3943
3944
3945 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3946 {
3947         int ret;
3948         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3949         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3950         if (ret == 0) {
3951                 ret = usb_reset_device(hdw->usb_dev);
3952                 usb_unlock_device(hdw->usb_dev);
3953         } else {
3954                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3955                            "Failed to lock USB device ret=%d",ret);
3956         }
3957         if (init_pause_msec) {
3958                 pvr2_trace(PVR2_TRACE_INFO,
3959                            "Waiting %u msec for hardware to settle",
3960                            init_pause_msec);
3961                 msleep(init_pause_msec);
3962         }
3963
3964 }
3965
3966
3967 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3968 {
3969         char da[1];
3970         unsigned int pipe;
3971         int ret;
3972
3973         if (!hdw->usb_dev) return;
3974
3975         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3976
3977         da[0] = val ? 0x01 : 0x00;
3978
3979         /* Write the CPUCS register on the 8051.  The lsb of the register
3980            is the reset bit; a 1 asserts reset while a 0 clears it. */
3981         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3982         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3983         if (ret < 0) {
3984                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3985                            "cpureset_assert(%d) error=%d",val,ret);
3986                 pvr2_hdw_render_useless(hdw);
3987         }
3988 }
3989
3990
3991 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3992 {
3993         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
3994 }
3995
3996
3997 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3998 {
3999         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4000 }
4001
4002
4003 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4004 {
4005         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
4006 }
4007
4008
4009 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4010 {
4011         if (!hdw->decoder_ctrl) {
4012                 pvr2_trace(PVR2_TRACE_INIT,
4013                            "Unable to reset decoder: nothing attached");
4014                 return -ENOTTY;
4015         }
4016
4017         if (!hdw->decoder_ctrl->force_reset) {
4018                 pvr2_trace(PVR2_TRACE_INIT,
4019                            "Unable to reset decoder: not implemented");
4020                 return -ENOTTY;
4021         }
4022
4023         pvr2_trace(PVR2_TRACE_INIT,
4024                    "Requesting decoder reset");
4025         hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
4026         return 0;
4027 }
4028
4029
4030 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4031 {
4032         hdw->flag_ok = !0;
4033         return pvr2_issue_simple_cmd(hdw,
4034                                      FX2CMD_HCW_DEMOD_RESETIN |
4035                                      (1 << 8) |
4036                                      ((onoff ? 1 : 0) << 16));
4037 }
4038
4039
4040 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4041 {
4042         hdw->flag_ok = !0;
4043         return pvr2_issue_simple_cmd(hdw,(onoff ?
4044                                           FX2CMD_ONAIR_DTV_POWER_ON :
4045                                           FX2CMD_ONAIR_DTV_POWER_OFF));
4046 }
4047
4048
4049 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4050                                                 int onoff)
4051 {
4052         return pvr2_issue_simple_cmd(hdw,(onoff ?
4053                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
4054                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
4055 }
4056
4057
4058 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4059 {
4060         int cmode;
4061         /* Compare digital/analog desired setting with current setting.  If
4062            they don't match, fix it... */
4063         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4064         if (cmode == hdw->pathway_state) {
4065                 /* They match; nothing to do */
4066                 return;
4067         }
4068
4069         switch (hdw->hdw_desc->digital_control_scheme) {
4070         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4071                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4072                 if (cmode == PVR2_PATHWAY_ANALOG) {
4073                         /* If moving to analog mode, also force the decoder
4074                            to reset.  If no decoder is attached, then it's
4075                            ok to ignore this because if/when the decoder
4076                            attaches, it will reset itself at that time. */
4077                         pvr2_hdw_cmd_decoder_reset(hdw);
4078                 }
4079                 break;
4080         case PVR2_DIGITAL_SCHEME_ONAIR:
4081                 /* Supposedly we should always have the power on whether in
4082                    digital or analog mode.  But for now do what appears to
4083                    work... */
4084                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4085                 break;
4086         default: break;
4087         }
4088
4089         pvr2_hdw_untrip_unlocked(hdw);
4090         hdw->pathway_state = cmode;
4091 }
4092
4093
4094 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4095 {
4096         /* change some GPIO data
4097          *
4098          * note: bit d7 of dir appears to control the LED,
4099          * so we shut it off here.
4100          *
4101          */
4102         if (onoff) {
4103                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4104         } else {
4105                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4106         }
4107         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4108 }
4109
4110
4111 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4112
4113 static led_method_func led_methods[] = {
4114         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4115 };
4116
4117
4118 /* Toggle LED */
4119 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4120 {
4121         unsigned int scheme_id;
4122         led_method_func fp;
4123
4124         if ((!onoff) == (!hdw->led_on)) return;
4125
4126         hdw->led_on = onoff != 0;
4127
4128         scheme_id = hdw->hdw_desc->led_scheme;
4129         if (scheme_id < ARRAY_SIZE(led_methods)) {
4130                 fp = led_methods[scheme_id];
4131         } else {
4132                 fp = NULL;
4133         }
4134
4135         if (fp) (*fp)(hdw,onoff);
4136 }
4137
4138
4139 /* Stop / start video stream transport */
4140 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4141 {
4142         int ret;
4143
4144         /* If we're in analog mode, then just issue the usual analog
4145            command. */
4146         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4147                 return pvr2_issue_simple_cmd(hdw,
4148                                              (runFl ?
4149                                               FX2CMD_STREAMING_ON :
4150                                               FX2CMD_STREAMING_OFF));
4151                 /*Note: Not reached */
4152         }
4153
4154         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4155                 /* Whoops, we don't know what mode we're in... */
4156                 return -EINVAL;
4157         }
4158
4159         /* To get here we have to be in digital mode.  The mechanism here
4160            is unfortunately different for different vendors.  So we switch
4161            on the device's digital scheme attribute in order to figure out
4162            what to do. */
4163         switch (hdw->hdw_desc->digital_control_scheme) {
4164         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4165                 return pvr2_issue_simple_cmd(hdw,
4166                                              (runFl ?
4167                                               FX2CMD_HCW_DTV_STREAMING_ON :
4168                                               FX2CMD_HCW_DTV_STREAMING_OFF));
4169         case PVR2_DIGITAL_SCHEME_ONAIR:
4170                 ret = pvr2_issue_simple_cmd(hdw,
4171                                             (runFl ?
4172                                              FX2CMD_STREAMING_ON :
4173                                              FX2CMD_STREAMING_OFF));
4174                 if (ret) return ret;
4175                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4176         default:
4177                 return -EINVAL;
4178         }
4179 }
4180
4181
4182 /* Evaluate whether or not state_pathway_ok can change */
4183 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4184 {
4185         if (hdw->state_pathway_ok) {
4186                 /* Nothing to do if pathway is already ok */
4187                 return 0;
4188         }
4189         if (!hdw->state_pipeline_idle) {
4190                 /* Not allowed to change anything if pipeline is not idle */
4191                 return 0;
4192         }
4193         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4194         hdw->state_pathway_ok = !0;
4195         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4196         return !0;
4197 }
4198
4199
4200 /* Evaluate whether or not state_encoder_ok can change */
4201 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4202 {
4203         if (hdw->state_encoder_ok) return 0;
4204         if (hdw->flag_tripped) return 0;
4205         if (hdw->state_encoder_run) return 0;
4206         if (hdw->state_encoder_config) return 0;
4207         if (hdw->state_decoder_run) return 0;
4208         if (hdw->state_usbstream_run) return 0;
4209         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4210                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4211         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4212                 return 0;
4213         }
4214
4215         if (pvr2_upload_firmware2(hdw) < 0) {
4216                 hdw->flag_tripped = !0;
4217                 trace_stbit("flag_tripped",hdw->flag_tripped);
4218                 return !0;
4219         }
4220         hdw->state_encoder_ok = !0;
4221         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4222         return !0;
4223 }
4224
4225
4226 /* Evaluate whether or not state_encoder_config can change */
4227 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4228 {
4229         if (hdw->state_encoder_config) {
4230                 if (hdw->state_encoder_ok) {
4231                         if (hdw->state_pipeline_req &&
4232                             !hdw->state_pipeline_pause) return 0;
4233                 }
4234                 hdw->state_encoder_config = 0;
4235                 hdw->state_encoder_waitok = 0;
4236                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4237                 /* paranoia - solve race if timer just completed */
4238                 del_timer_sync(&hdw->encoder_wait_timer);
4239         } else {
4240                 if (!hdw->state_pathway_ok ||
4241                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4242                     !hdw->state_encoder_ok ||
4243                     !hdw->state_pipeline_idle ||
4244                     hdw->state_pipeline_pause ||
4245                     !hdw->state_pipeline_req ||
4246                     !hdw->state_pipeline_config) {
4247                         /* We must reset the enforced wait interval if
4248                            anything has happened that might have disturbed
4249                            the encoder.  This should be a rare case. */
4250                         if (timer_pending(&hdw->encoder_wait_timer)) {
4251                                 del_timer_sync(&hdw->encoder_wait_timer);
4252                         }
4253                         if (hdw->state_encoder_waitok) {
4254                                 /* Must clear the state - therefore we did
4255                                    something to a state bit and must also
4256                                    return true. */
4257                                 hdw->state_encoder_waitok = 0;
4258                                 trace_stbit("state_encoder_waitok",
4259                                             hdw->state_encoder_waitok);
4260                                 return !0;
4261                         }
4262                         return 0;
4263                 }
4264                 if (!hdw->state_encoder_waitok) {
4265                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4266                                 /* waitok flag wasn't set and timer isn't
4267                                    running.  Check flag once more to avoid
4268                                    a race then start the timer.  This is
4269                                    the point when we measure out a minimal
4270                                    quiet interval before doing something to
4271                                    the encoder. */
4272                                 if (!hdw->state_encoder_waitok) {
4273                                         hdw->encoder_wait_timer.expires =
4274                                                 jiffies +
4275                                                 (HZ * TIME_MSEC_ENCODER_WAIT
4276                                                  / 1000);
4277                                         add_timer(&hdw->encoder_wait_timer);
4278                                 }
4279                         }
4280                         /* We can't continue until we know we have been
4281                            quiet for the interval measured by this
4282                            timer. */
4283                         return 0;
4284                 }
4285                 pvr2_encoder_configure(hdw);
4286                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4287         }
4288         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4289         return !0;
4290 }
4291
4292
4293 /* Return true if the encoder should not be running. */
4294 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4295 {
4296         if (!hdw->state_encoder_ok) {
4297                 /* Encoder isn't healthy at the moment, so stop it. */
4298                 return !0;
4299         }
4300         if (!hdw->state_pathway_ok) {
4301                 /* Mode is not understood at the moment (i.e. it wants to
4302                    change), so encoder must be stopped. */
4303                 return !0;
4304         }
4305
4306         switch (hdw->pathway_state) {
4307         case PVR2_PATHWAY_ANALOG:
4308                 if (!hdw->state_decoder_run) {
4309                         /* We're in analog mode and the decoder is not
4310                            running; thus the encoder should be stopped as
4311                            well. */
4312                         return !0;
4313                 }
4314                 break;
4315         case PVR2_PATHWAY_DIGITAL:
4316                 if (hdw->state_encoder_runok) {
4317                         /* This is a funny case.  We're in digital mode so
4318                            really the encoder should be stopped.  However
4319                            if it really is running, only kill it after
4320                            runok has been set.  This gives a chance for the
4321                            onair quirk to function (encoder must run
4322                            briefly first, at least once, before onair
4323                            digital streaming can work). */
4324                         return !0;
4325                 }
4326                 break;
4327         default:
4328                 /* Unknown mode; so encoder should be stopped. */
4329                 return !0;
4330         }
4331
4332         /* If we get here, we haven't found a reason to stop the
4333            encoder. */
4334         return 0;
4335 }
4336
4337
4338 /* Return true if the encoder should be running. */
4339 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4340 {
4341         if (!hdw->state_encoder_ok) {
4342                 /* Don't run the encoder if it isn't healthy... */
4343                 return 0;
4344         }
4345         if (!hdw->state_pathway_ok) {
4346                 /* Don't run the encoder if we don't (yet) know what mode
4347                    we need to be in... */
4348                 return 0;
4349         }
4350
4351         switch (hdw->pathway_state) {
4352         case PVR2_PATHWAY_ANALOG:
4353                 if (hdw->state_decoder_run) {
4354                         /* In analog mode, if the decoder is running, then
4355                            run the encoder. */
4356                         return !0;
4357                 }
4358                 break;
4359         case PVR2_PATHWAY_DIGITAL:
4360                 if ((hdw->hdw_desc->digital_control_scheme ==
4361                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4362                     !hdw->state_encoder_runok) {
4363                         /* This is a quirk.  OnAir hardware won't stream
4364                            digital until the encoder has been run at least
4365                            once, for a minimal period of time (empiricially
4366                            measured to be 1/4 second).  So if we're on
4367                            OnAir hardware and the encoder has never been
4368                            run at all, then start the encoder.  Normal
4369                            state machine logic in the driver will
4370                            automatically handle the remaining bits. */
4371                         return !0;
4372                 }
4373                 break;
4374         default:
4375                 /* For completeness (unknown mode; encoder won't run ever) */
4376                 break;
4377         }
4378         /* If we get here, then we haven't found any reason to run the
4379            encoder, so don't run it. */
4380         return 0;
4381 }
4382
4383
4384 /* Evaluate whether or not state_encoder_run can change */
4385 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4386 {
4387         if (hdw->state_encoder_run) {
4388                 if (!state_check_disable_encoder_run(hdw)) return 0;
4389                 if (hdw->state_encoder_ok) {
4390                         del_timer_sync(&hdw->encoder_run_timer);
4391                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4392                 }
4393                 hdw->state_encoder_run = 0;
4394         } else {
4395                 if (!state_check_enable_encoder_run(hdw)) return 0;
4396                 if (pvr2_encoder_start(hdw) < 0) return !0;
4397                 hdw->state_encoder_run = !0;
4398                 if (!hdw->state_encoder_runok) {
4399                         hdw->encoder_run_timer.expires =
4400                                 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4401                         add_timer(&hdw->encoder_run_timer);
4402                 }
4403         }
4404         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4405         return !0;
4406 }
4407
4408
4409 /* Timeout function for quiescent timer. */
4410 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4411 {
4412         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4413         hdw->state_decoder_quiescent = !0;
4414         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4415         hdw->state_stale = !0;
4416         queue_work(hdw->workqueue,&hdw->workpoll);
4417 }
4418
4419
4420 /* Timeout function for encoder wait timer. */
4421 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4422 {
4423         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4424         hdw->state_encoder_waitok = !0;
4425         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4426         hdw->state_stale = !0;
4427         queue_work(hdw->workqueue,&hdw->workpoll);
4428 }
4429
4430
4431 /* Timeout function for encoder run timer. */
4432 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4433 {
4434         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4435         if (!hdw->state_encoder_runok) {
4436                 hdw->state_encoder_runok = !0;
4437                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4438                 hdw->state_stale = !0;
4439                 queue_work(hdw->workqueue,&hdw->workpoll);
4440         }
4441 }
4442
4443
4444 /* Evaluate whether or not state_decoder_run can change */
4445 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4446 {
4447         if (hdw->state_decoder_run) {
4448                 if (hdw->state_encoder_ok) {
4449                         if (hdw->state_pipeline_req &&
4450                             !hdw->state_pipeline_pause &&
4451                             hdw->state_pathway_ok) return 0;
4452                 }
4453                 if (!hdw->flag_decoder_missed) {
4454                         pvr2_decoder_enable(hdw,0);
4455                 }
4456                 hdw->state_decoder_quiescent = 0;
4457                 hdw->state_decoder_run = 0;
4458                 /* paranoia - solve race if timer just completed */
4459                 del_timer_sync(&hdw->quiescent_timer);
4460         } else {
4461                 if (!hdw->state_decoder_quiescent) {
4462                         if (!timer_pending(&hdw->quiescent_timer)) {
4463                                 /* We don't do something about the
4464                                    quiescent timer until right here because
4465                                    we also want to catch cases where the
4466                                    decoder was already not running (like
4467                                    after initialization) as opposed to
4468                                    knowing that we had just stopped it.
4469                                    The second flag check is here to cover a
4470                                    race - the timer could have run and set
4471                                    this flag just after the previous check
4472                                    but before we did the pending check. */
4473                                 if (!hdw->state_decoder_quiescent) {
4474                                         hdw->quiescent_timer.expires =
4475                                                 jiffies +
4476                                                 (HZ * TIME_MSEC_DECODER_WAIT
4477                                                  / 1000);
4478                                         add_timer(&hdw->quiescent_timer);
4479                                 }
4480                         }
4481                         /* Don't allow decoder to start again until it has
4482                            been quiesced first.  This little detail should
4483                            hopefully further stabilize the encoder. */
4484                         return 0;
4485                 }
4486                 if (!hdw->state_pathway_ok ||
4487                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4488                     !hdw->state_pipeline_req ||
4489                     hdw->state_pipeline_pause ||
4490                     !hdw->state_pipeline_config ||
4491                     !hdw->state_encoder_config ||
4492                     !hdw->state_encoder_ok) return 0;
4493                 del_timer_sync(&hdw->quiescent_timer);
4494                 if (hdw->flag_decoder_missed) return 0;
4495                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4496                 hdw->state_decoder_quiescent = 0;
4497                 hdw->state_decoder_run = !0;
4498         }
4499         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4500         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4501         return !0;
4502 }
4503
4504
4505 /* Evaluate whether or not state_usbstream_run can change */
4506 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4507 {
4508         if (hdw->state_usbstream_run) {
4509                 int fl = !0;
4510                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4511                         fl = (hdw->state_encoder_ok &&
4512                               hdw->state_encoder_run);
4513                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4514                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4515                         fl = hdw->state_encoder_ok;
4516                 }
4517                 if (fl &&
4518                     hdw->state_pipeline_req &&
4519                     !hdw->state_pipeline_pause &&
4520                     hdw->state_pathway_ok) {
4521                         return 0;
4522                 }
4523                 pvr2_hdw_cmd_usbstream(hdw,0);
4524                 hdw->state_usbstream_run = 0;
4525         } else {
4526                 if (!hdw->state_pipeline_req ||
4527                     hdw->state_pipeline_pause ||
4528                     !hdw->state_pathway_ok) return 0;
4529                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4530                         if (!hdw->state_encoder_ok ||
4531                             !hdw->state_encoder_run) return 0;
4532                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4533                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4534                         if (!hdw->state_encoder_ok) return 0;
4535                         if (hdw->state_encoder_run) return 0;
4536                         if (hdw->hdw_desc->digital_control_scheme ==
4537                             PVR2_DIGITAL_SCHEME_ONAIR) {
4538                                 /* OnAir digital receivers won't stream
4539                                    unless the analog encoder has run first.
4540                                    Why?  I have no idea.  But don't even
4541                                    try until we know the analog side is
4542                                    known to have run. */
4543                                 if (!hdw->state_encoder_runok) return 0;
4544                         }
4545                 }
4546                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4547                 hdw->state_usbstream_run = !0;
4548         }
4549         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4550         return !0;
4551 }
4552
4553
4554 /* Attempt to configure pipeline, if needed */
4555 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4556 {
4557         if (hdw->state_pipeline_config ||
4558             hdw->state_pipeline_pause) return 0;
4559         pvr2_hdw_commit_execute(hdw);
4560         return !0;
4561 }
4562
4563
4564 /* Update pipeline idle and pipeline pause tracking states based on other
4565    inputs.  This must be called whenever the other relevant inputs have
4566    changed. */
4567 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4568 {
4569         unsigned int st;
4570         int updatedFl = 0;
4571         /* Update pipeline state */
4572         st = !(hdw->state_encoder_run ||
4573                hdw->state_decoder_run ||
4574                hdw->state_usbstream_run ||
4575                (!hdw->state_decoder_quiescent));
4576         if (!st != !hdw->state_pipeline_idle) {
4577                 hdw->state_pipeline_idle = st;
4578                 updatedFl = !0;
4579         }
4580         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4581                 hdw->state_pipeline_pause = 0;
4582                 updatedFl = !0;
4583         }
4584         return updatedFl;
4585 }
4586
4587
4588 typedef int (*state_eval_func)(struct pvr2_hdw *);
4589
4590 /* Set of functions to be run to evaluate various states in the driver. */
4591 static const state_eval_func eval_funcs[] = {
4592         state_eval_pathway_ok,
4593         state_eval_pipeline_config,
4594         state_eval_encoder_ok,
4595         state_eval_encoder_config,
4596         state_eval_decoder_run,
4597         state_eval_encoder_run,
4598         state_eval_usbstream_run,
4599 };
4600
4601
4602 /* Process various states and return true if we did anything interesting. */
4603 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4604 {
4605         unsigned int i;
4606         int state_updated = 0;
4607         int check_flag;
4608
4609         if (!hdw->state_stale) return 0;
4610         if ((hdw->fw1_state != FW1_STATE_OK) ||
4611             !hdw->flag_ok) {
4612                 hdw->state_stale = 0;
4613                 return !0;
4614         }
4615         /* This loop is the heart of the entire driver.  It keeps trying to
4616            evaluate various bits of driver state until nothing changes for
4617            one full iteration.  Each "bit of state" tracks some global
4618            aspect of the driver, e.g. whether decoder should run, if
4619            pipeline is configured, usb streaming is on, etc.  We separately
4620            evaluate each of those questions based on other driver state to
4621            arrive at the correct running configuration. */
4622         do {
4623                 check_flag = 0;
4624                 state_update_pipeline_state(hdw);
4625                 /* Iterate over each bit of state */
4626                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4627                         if ((*eval_funcs[i])(hdw)) {
4628                                 check_flag = !0;
4629                                 state_updated = !0;
4630                                 state_update_pipeline_state(hdw);
4631                         }
4632                 }
4633         } while (check_flag && hdw->flag_ok);
4634         hdw->state_stale = 0;
4635         trace_stbit("state_stale",hdw->state_stale);
4636         return state_updated;
4637 }
4638
4639
4640 static unsigned int print_input_mask(unsigned int msk,
4641                                      char *buf,unsigned int acnt)
4642 {
4643         unsigned int idx,ccnt;
4644         unsigned int tcnt = 0;
4645         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4646                 if (!((1 << idx) & msk)) continue;
4647                 ccnt = scnprintf(buf+tcnt,
4648                                  acnt-tcnt,
4649                                  "%s%s",
4650                                  (tcnt ? ", " : ""),
4651                                  control_values_input[idx]);
4652                 tcnt += ccnt;
4653         }
4654         return tcnt;
4655 }
4656
4657
4658 static const char *pvr2_pathway_state_name(int id)
4659 {
4660         switch (id) {
4661         case PVR2_PATHWAY_ANALOG: return "analog";
4662         case PVR2_PATHWAY_DIGITAL: return "digital";
4663         default: return "unknown";
4664         }
4665 }
4666
4667
4668 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4669                                              char *buf,unsigned int acnt)
4670 {
4671         switch (which) {
4672         case 0:
4673                 return scnprintf(
4674                         buf,acnt,
4675                         "driver:%s%s%s%s%s <mode=%s>",
4676                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4677                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4678                         (hdw->flag_disconnected ? " <disconnected>" :
4679                          " <connected>"),
4680                         (hdw->flag_tripped ? " <tripped>" : ""),
4681                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4682                         pvr2_pathway_state_name(hdw->pathway_state));
4683
4684         case 1:
4685                 return scnprintf(
4686                         buf,acnt,
4687                         "pipeline:%s%s%s%s",
4688                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4689                         (hdw->state_pipeline_config ?
4690                          " <configok>" : " <stale>"),
4691                         (hdw->state_pipeline_req ? " <req>" : ""),
4692                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4693         case 2:
4694                 return scnprintf(
4695                         buf,acnt,
4696                         "worker:%s%s%s%s%s%s%s",
4697                         (hdw->state_decoder_run ?
4698                          " <decode:run>" :
4699                          (hdw->state_decoder_quiescent ?
4700                           "" : " <decode:stop>")),
4701                         (hdw->state_decoder_quiescent ?
4702                          " <decode:quiescent>" : ""),
4703                         (hdw->state_encoder_ok ?
4704                          "" : " <encode:init>"),
4705                         (hdw->state_encoder_run ?
4706                          (hdw->state_encoder_runok ?
4707                           " <encode:run>" :
4708                           " <encode:firstrun>") :
4709                          (hdw->state_encoder_runok ?
4710                           " <encode:stop>" :
4711                           " <encode:virgin>")),
4712                         (hdw->state_encoder_config ?
4713                          " <encode:configok>" :
4714                          (hdw->state_encoder_waitok ?
4715                           "" : " <encode:waitok>")),
4716                         (hdw->state_usbstream_run ?
4717                          " <usb:run>" : " <usb:stop>"),
4718                         (hdw->state_pathway_ok ?
4719                          " <pathway:ok>" : ""));
4720         case 3:
4721                 return scnprintf(
4722                         buf,acnt,
4723                         "state: %s",
4724                         pvr2_get_state_name(hdw->master_state));
4725         case 4: {
4726                 unsigned int tcnt = 0;
4727                 unsigned int ccnt;
4728
4729                 ccnt = scnprintf(buf,
4730                                  acnt,
4731                                  "Hardware supported inputs: ");
4732                 tcnt += ccnt;
4733                 tcnt += print_input_mask(hdw->input_avail_mask,
4734                                          buf+tcnt,
4735                                          acnt-tcnt);
4736                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4737                         ccnt = scnprintf(buf+tcnt,
4738                                          acnt-tcnt,
4739                                          "; allowed inputs: ");
4740                         tcnt += ccnt;
4741                         tcnt += print_input_mask(hdw->input_allowed_mask,
4742                                                  buf+tcnt,
4743                                                  acnt-tcnt);
4744                 }
4745                 return tcnt;
4746         }
4747         case 5: {
4748                 struct pvr2_stream_stats stats;
4749                 if (!hdw->vid_stream) break;
4750                 pvr2_stream_get_stats(hdw->vid_stream,
4751                                       &stats,
4752                                       0);
4753                 return scnprintf(
4754                         buf,acnt,
4755                         "Bytes streamed=%u"
4756                         " URBs: queued=%u idle=%u ready=%u"
4757                         " processed=%u failed=%u",
4758                         stats.bytes_processed,
4759                         stats.buffers_in_queue,
4760                         stats.buffers_in_idle,
4761                         stats.buffers_in_ready,
4762                         stats.buffers_processed,
4763                         stats.buffers_failed);
4764         }
4765         default: break;
4766         }
4767         return 0;
4768 }
4769
4770
4771 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4772                                    char *buf,unsigned int acnt)
4773 {
4774         unsigned int bcnt,ccnt,idx;
4775         bcnt = 0;
4776         LOCK_TAKE(hdw->big_lock);
4777         for (idx = 0; ; idx++) {
4778                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4779                 if (!ccnt) break;
4780                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4781                 if (!acnt) break;
4782                 buf[0] = '\n'; ccnt = 1;
4783                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4784         }
4785         LOCK_GIVE(hdw->big_lock);
4786         return bcnt;
4787 }
4788
4789
4790 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4791 {
4792         char buf[128];
4793         unsigned int idx,ccnt;
4794
4795         for (idx = 0; ; idx++) {
4796                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4797                 if (!ccnt) break;
4798                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4799         }
4800 }
4801
4802
4803 /* Evaluate and update the driver's current state, taking various actions
4804    as appropriate for the update. */
4805 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4806 {
4807         unsigned int st;
4808         int state_updated = 0;
4809         int callback_flag = 0;
4810         int analog_mode;
4811
4812         pvr2_trace(PVR2_TRACE_STBITS,
4813                    "Drive state check START");
4814         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4815                 pvr2_hdw_state_log_state(hdw);
4816         }
4817
4818         /* Process all state and get back over disposition */
4819         state_updated = pvr2_hdw_state_update(hdw);
4820
4821         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4822
4823         /* Update master state based upon all other states. */
4824         if (!hdw->flag_ok) {
4825                 st = PVR2_STATE_DEAD;
4826         } else if (hdw->fw1_state != FW1_STATE_OK) {
4827                 st = PVR2_STATE_COLD;
4828         } else if ((analog_mode ||
4829                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4830                    !hdw->state_encoder_ok) {
4831                 st = PVR2_STATE_WARM;
4832         } else if (hdw->flag_tripped ||
4833                    (analog_mode && hdw->flag_decoder_missed)) {
4834                 st = PVR2_STATE_ERROR;
4835         } else if (hdw->state_usbstream_run &&
4836                    (!analog_mode ||
4837                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4838                 st = PVR2_STATE_RUN;
4839         } else {
4840                 st = PVR2_STATE_READY;
4841         }
4842         if (hdw->master_state != st) {
4843                 pvr2_trace(PVR2_TRACE_STATE,
4844                            "Device state change from %s to %s",
4845                            pvr2_get_state_name(hdw->master_state),
4846                            pvr2_get_state_name(st));
4847                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4848                 hdw->master_state = st;
4849                 state_updated = !0;
4850                 callback_flag = !0;
4851         }
4852         if (state_updated) {
4853                 /* Trigger anyone waiting on any state changes here. */
4854                 wake_up(&hdw->state_wait_data);
4855         }
4856
4857         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4858                 pvr2_hdw_state_log_state(hdw);
4859         }
4860         pvr2_trace(PVR2_TRACE_STBITS,
4861                    "Drive state check DONE callback=%d",callback_flag);
4862
4863         return callback_flag;
4864 }
4865
4866
4867 /* Cause kernel thread to check / update driver state */
4868 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4869 {
4870         if (hdw->state_stale) return;
4871         hdw->state_stale = !0;
4872         trace_stbit("state_stale",hdw->state_stale);
4873         queue_work(hdw->workqueue,&hdw->workpoll);
4874 }
4875
4876
4877 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4878 {
4879         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4880 }
4881
4882
4883 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4884 {
4885         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4886 }
4887
4888
4889 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4890 {
4891         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4892 }
4893
4894
4895 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4896 {
4897         u32 cval,nval;
4898         int ret;
4899         if (~msk) {
4900                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4901                 if (ret) return ret;
4902                 nval = (cval & ~msk) | (val & msk);
4903                 pvr2_trace(PVR2_TRACE_GPIO,
4904                            "GPIO direction changing 0x%x:0x%x"
4905                            " from 0x%x to 0x%x",
4906                            msk,val,cval,nval);
4907         } else {
4908                 nval = val;
4909                 pvr2_trace(PVR2_TRACE_GPIO,
4910                            "GPIO direction changing to 0x%x",nval);
4911         }
4912         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4913 }
4914
4915
4916 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4917 {
4918         u32 cval,nval;
4919         int ret;
4920         if (~msk) {
4921                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4922                 if (ret) return ret;
4923                 nval = (cval & ~msk) | (val & msk);
4924                 pvr2_trace(PVR2_TRACE_GPIO,
4925                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4926                            msk,val,cval,nval);
4927         } else {
4928                 nval = val;
4929                 pvr2_trace(PVR2_TRACE_GPIO,
4930                            "GPIO output changing to 0x%x",nval);
4931         }
4932         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4933 }
4934
4935
4936 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
4937 {
4938         struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
4939         memset(vtp, 0, sizeof(*vtp));
4940         hdw->tuner_signal_stale = 0;
4941         pvr2_i2c_core_status_poll(hdw);
4942         /* Note: There apparently is no replacement for VIDIOC_CROPCAP
4943            using v4l2-subdev - therefore we can't support that AT ALL right
4944            now.  (Of course, no sub-drivers seem to implement it either.
4945            But now it's a a chicken and egg problem...) */
4946         v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner,
4947                              &hdw->tuner_signal_info);
4948         pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
4949                    " type=%u strength=%u audio=0x%x cap=0x%x"
4950                    " low=%u hi=%u",
4951                    vtp->type,
4952                    vtp->signal, vtp->rxsubchans, vtp->capability,
4953                    vtp->rangelow, vtp->rangehigh);
4954
4955         /* We have to do this to avoid getting into constant polling if
4956            there's nobody to answer a poll of cropcap info. */
4957         hdw->cropcap_stale = 0;
4958 }
4959
4960
4961 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
4962 {
4963         return hdw->input_avail_mask;
4964 }
4965
4966
4967 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
4968 {
4969         return hdw->input_allowed_mask;
4970 }
4971
4972
4973 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
4974 {
4975         if (hdw->input_val != v) {
4976                 hdw->input_val = v;
4977                 hdw->input_dirty = !0;
4978         }
4979
4980         /* Handle side effects - if we switch to a mode that needs the RF
4981            tuner, then select the right frequency choice as well and mark
4982            it dirty. */
4983         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
4984                 hdw->freqSelector = 0;
4985                 hdw->freqDirty = !0;
4986         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
4987                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
4988                 hdw->freqSelector = 1;
4989                 hdw->freqDirty = !0;
4990         }
4991         return 0;
4992 }
4993
4994
4995 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
4996                                unsigned int change_mask,
4997                                unsigned int change_val)
4998 {
4999         int ret = 0;
5000         unsigned int nv,m,idx;
5001         LOCK_TAKE(hdw->big_lock);
5002         do {
5003                 nv = hdw->input_allowed_mask & ~change_mask;
5004                 nv |= (change_val & change_mask);
5005                 nv &= hdw->input_avail_mask;
5006                 if (!nv) {
5007                         /* No legal modes left; return error instead. */
5008                         ret = -EPERM;
5009                         break;
5010                 }
5011                 hdw->input_allowed_mask = nv;
5012                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5013                         /* Current mode is still in the allowed mask, so
5014                            we're done. */
5015                         break;
5016                 }
5017                 /* Select and switch to a mode that is still in the allowed
5018                    mask */
5019                 if (!hdw->input_allowed_mask) {
5020                         /* Nothing legal; give up */
5021                         break;
5022                 }
5023                 m = hdw->input_allowed_mask;
5024                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5025                         if (!((1 << idx) & m)) continue;
5026                         pvr2_hdw_set_input(hdw,idx);
5027                         break;
5028                 }
5029         } while (0);
5030         LOCK_GIVE(hdw->big_lock);
5031         return ret;
5032 }
5033
5034
5035 /* Find I2C address of eeprom */
5036 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5037 {
5038         int result;
5039         LOCK_TAKE(hdw->ctl_lock); do {
5040                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5041                 result = pvr2_send_request(hdw,
5042                                            hdw->cmd_buffer,1,
5043                                            hdw->cmd_buffer,1);
5044                 if (result < 0) break;
5045                 result = hdw->cmd_buffer[0];
5046         } while(0); LOCK_GIVE(hdw->ctl_lock);
5047         return result;
5048 }
5049
5050
5051 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
5052                              struct v4l2_dbg_match *match, u64 reg_id,
5053                              int setFl, u64 *val_ptr)
5054 {
5055 #ifdef CONFIG_VIDEO_ADV_DEBUG
5056         struct pvr2_i2c_client *cp;
5057         struct v4l2_dbg_register req;
5058         int stat = 0;
5059         int okFl = 0;
5060
5061         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5062
5063         req.match = *match;
5064         req.reg = reg_id;
5065         if (setFl) req.val = *val_ptr;
5066         /* It would be nice to know if a sub-device answered the request */
5067         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5068         if (!setFl) *val_ptr = req.val;
5069         if (!okFl) mutex_lock(&hdw->i2c_list_lock); do {
5070                 list_for_each_entry(cp, &hdw->i2c_clients, list) {
5071                         if (!v4l2_chip_match_i2c_client(
5072                                     cp->client,
5073                                     &req.match)) {
5074                                 continue;
5075                         }
5076                         stat = pvr2_i2c_client_cmd(
5077                                 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
5078                                     VIDIOC_DBG_G_REGISTER),&req);
5079                         if (!setFl) *val_ptr = req.val;
5080                         okFl = !0;
5081                         break;
5082                 }
5083         } while (0); mutex_unlock(&hdw->i2c_list_lock);
5084         if (okFl) {
5085                 return stat;
5086         }
5087         return -EINVAL;
5088 #else
5089         return -ENOSYS;
5090 #endif
5091 }
5092
5093
5094 /*
5095   Stuff for Emacs to see, in order to encourage consistent editing style:
5096   *** Local Variables: ***
5097   *** mode: c ***
5098   *** fill-column: 75 ***
5099   *** tab-width: 8 ***
5100   *** c-basic-offset: 8 ***
5101   *** End: ***
5102   */