Pileus Git - ~andy/linux/blob - drivers/media/video/pvrusb2/pvrusb2-encoder.c

   1 /*
   2  *
   3  *  $Id$
   4  *
   5  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   6  *  Copyright (C) 2004 Aurelien Alleaume <slts@free.fr>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; either version 2 of the License
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  *
  21  */
  22
  23 #include <linux/device.h>   // for linux/firmware.h
  24 #include <linux/firmware.h>
  25 #include "pvrusb2-util.h"
  26 #include "pvrusb2-encoder.h"
  27 #include "pvrusb2-hdw-internal.h"
  28 #include "pvrusb2-debug.h"
  29 #include "pvrusb2-fx2-cmd.h"
  30
  31
  32
  33 /* Firmware mailbox flags - definitions found from ivtv */
  34 #define IVTV_MBOX_FIRMWARE_DONE 0x00000004
  35 #define IVTV_MBOX_DRIVER_DONE 0x00000002
  36 #define IVTV_MBOX_DRIVER_BUSY 0x00000001
  37
  38 #define MBOX_BASE 0x44
  39
  40
  41 static int pvr2_encoder_write_words(struct pvr2_hdw *hdw,
  42                                     unsigned int offs,
  43                                     const u32 *data, unsigned int dlen)
  44 {
  45         unsigned int idx,addr;
  46         unsigned int bAddr;
  47         int ret;
  48         unsigned int chunkCnt;
  49
  50         /*
  51
  52         Format: First byte must be 0x01.  Remaining 32 bit words are
  53         spread out into chunks of 7 bytes each, with the first 4 bytes
  54         being the data word (little endian), and the next 3 bytes
  55         being the address where that data word is to be written (big
  56         endian).  Repeat request for additional words, with offset
  57         adjusted accordingly.
  58
  59         */
  60         while (dlen) {
  61                 chunkCnt = 8;
  62                 if (chunkCnt > dlen) chunkCnt = dlen;
  63                 memset(hdw->cmd_buffer,0,sizeof(hdw->cmd_buffer));
  64                 bAddr = 0;
  65                 hdw->cmd_buffer[bAddr++] = FX2CMD_MEM_WRITE_DWORD;
  66                 for (idx = 0; idx < chunkCnt; idx++) {
  67                         addr = idx + offs;
  68                         hdw->cmd_buffer[bAddr+6] = (addr & 0xffu);
  69                         hdw->cmd_buffer[bAddr+5] = ((addr>>8) & 0xffu);
  70                         hdw->cmd_buffer[bAddr+4] = ((addr>>16) & 0xffu);
  71                         PVR2_DECOMPOSE_LE(hdw->cmd_buffer, bAddr,data[idx]);
  72                         bAddr += 7;
  73                 }
  74                 ret = pvr2_send_request(hdw,
  75                                         hdw->cmd_buffer,1+(chunkCnt*7),
  76                                         NULL,0);
  77                 if (ret) return ret;
  78                 data += chunkCnt;
  79                 dlen -= chunkCnt;
  80                 offs += chunkCnt;
  81         }
  82
  83         return 0;
  84 }
  85
  86
  87 static int pvr2_encoder_read_words(struct pvr2_hdw *hdw,
  88                                    unsigned int offs,
  89                                    u32 *data, unsigned int dlen)
  90 {
  91         unsigned int idx;
  92         int ret;
  93         unsigned int chunkCnt;
  94
  95         /*
  96
  97         Format: First byte must be 0x02 (status check) or 0x28 (read
  98         back block of 32 bit words).  Next 6 bytes must be zero,
  99         followed by a single byte of MBOX_BASE+offset for portion to
 100         be read.  Returned data is packed set of 32 bits words that
 101         were read.
 102
 103         */
 104
 105         while (dlen) {
 106                 chunkCnt = 16;
 107                 if (chunkCnt > dlen) chunkCnt = dlen;
 108                 if (chunkCnt < 16) chunkCnt = 1;
 109                 hdw->cmd_buffer[0] =
 110                         ((chunkCnt == 1) ?
 111                          FX2CMD_MEM_READ_DWORD : FX2CMD_MEM_READ_64BYTES);
 112                 hdw->cmd_buffer[1] = 0;
 113                 hdw->cmd_buffer[2] = 0;
 114                 hdw->cmd_buffer[3] = 0;
 115                 hdw->cmd_buffer[4] = 0;
 116                 hdw->cmd_buffer[5] = ((offs>>16) & 0xffu);
 117                 hdw->cmd_buffer[6] = ((offs>>8) & 0xffu);
 118                 hdw->cmd_buffer[7] = (offs & 0xffu);
 119                 ret = pvr2_send_request(hdw,
 120                                         hdw->cmd_buffer,8,
 121                                         hdw->cmd_buffer,
 122                                         (chunkCnt == 1 ? 4 : 16 * 4));
 123                 if (ret) return ret;
 124
 125                 for (idx = 0; idx < chunkCnt; idx++) {
 126                         data[idx] = PVR2_COMPOSE_LE(hdw->cmd_buffer,idx*4);
 127                 }
 128                 data += chunkCnt;
 129                 dlen -= chunkCnt;
 130                 offs += chunkCnt;
 131         }
 132
 133         return 0;
 134 }
 135
 136
 137 /* This prototype is set up to be compatible with the
 138    cx2341x_mbox_func prototype in cx2341x.h, which should be in
 139    kernels 2.6.18 or later.  We do this so that we can enable
 140    cx2341x.ko to write to our encoder (by handing it a pointer to this
 141    function).  For earlier kernels this doesn't really matter. */
 142 static int pvr2_encoder_cmd(void *ctxt,
 143                             int cmd,
 144                             int arg_cnt_send,
 145                             int arg_cnt_recv,
 146                             u32 *argp)
 147 {
 148         unsigned int poll_count;
 149         unsigned int try_count = 0;
 150         int retry_flag;
 151         int ret = 0;
 152         unsigned int idx;
 153         /* These sizes look to be limited by the FX2 firmware implementation */
 154         u32 wrData[16];
 155         u32 rdData[16];
 156         struct pvr2_hdw *hdw = (struct pvr2_hdw *)ctxt;
 157
 158
 159         /*
 160
 161         The encoder seems to speak entirely using blocks 32 bit words.
 162         In ivtv driver terms, this is a mailbox at MBOX_BASE which we
 163         populate with data and watch what the hardware does with it.
 164         The first word is a set of flags used to control the
 165         transaction, the second word is the command to execute, the
 166         third byte is zero (ivtv driver suggests that this is some
 167         kind of return value), and the fourth byte is a specified
 168         timeout (windows driver always uses 0x00060000 except for one
 169         case when it is zero).  All successive words are the argument
 170         words for the command.
 171
 172         First, write out the entire set of words, with the first word
 173         being zero.
 174
 175         Next, write out just the first word again, but set it to
 176         IVTV_MBOX_DRIVER_DONE | IVTV_DRIVER_BUSY this time (which
 177         probably means "go").
 178
 179         Next, read back the return count words.  Check the first word,
 180         which should have IVTV_MBOX_FIRMWARE_DONE set.  If however
 181         that bit is not set, then the command isn't done so repeat the
 182         read until it is set.
 183
 184         Finally, write out just the first word again, but set it to
 185         0x0 this time (which probably means "idle").
 186
 187         */
 188
 189         if (arg_cnt_send > (ARRAY_SIZE(wrData) - 4)) {
 190                 pvr2_trace(
 191                         PVR2_TRACE_ERROR_LEGS,
 192                         "Failed to write cx23416 command"
 193                         " - too many input arguments"
 194                         " (was given %u limit %lu)",
 195                         arg_cnt_send, (long unsigned) ARRAY_SIZE(wrData) - 4);
 196                 return -EINVAL;
 197         }
 198
 199         if (arg_cnt_recv > (ARRAY_SIZE(rdData) - 4)) {
 200                 pvr2_trace(
 201                         PVR2_TRACE_ERROR_LEGS,
 202                         "Failed to write cx23416 command"
 203                         " - too many return arguments"
 204                         " (was given %u limit %lu)",
 205                         arg_cnt_recv, (long unsigned) ARRAY_SIZE(rdData) - 4);
 206                 return -EINVAL;
 207         }
 208
 209
 210         LOCK_TAKE(hdw->ctl_lock); do {
 211
 212                 retry_flag = 0;
 213                 try_count++;
 214                 ret = 0;
 215                 wrData[0] = 0;
 216                 wrData[1] = cmd;
 217                 wrData[2] = 0;
 218                 wrData[3] = 0x00060000;
 219                 for (idx = 0; idx < arg_cnt_send; idx++) {
 220                         wrData[idx+4] = argp[idx];
 221                 }
 222                 for (; idx < ARRAY_SIZE(wrData) - 4; idx++) {
 223                         wrData[idx+4] = 0;
 224                 }
 225
 226                 ret = pvr2_encoder_write_words(hdw,MBOX_BASE,wrData,idx);
 227                 if (ret) break;
 228                 wrData[0] = IVTV_MBOX_DRIVER_DONE|IVTV_MBOX_DRIVER_BUSY;
 229                 ret = pvr2_encoder_write_words(hdw,MBOX_BASE,wrData,1);
 230                 if (ret) break;
 231                 poll_count = 0;
 232                 while (1) {
 233                         poll_count++;
 234                         ret = pvr2_encoder_read_words(hdw,MBOX_BASE,rdData,
 235                                                       arg_cnt_recv+4);
 236                         if (ret) {
 237                                 break;
 238                         }
 239                         if (rdData[0] & IVTV_MBOX_FIRMWARE_DONE) {
 240                                 break;
 241                         }
 242                         if (rdData[0] && (poll_count < 1000)) continue;
 243                         if (!rdData[0]) {
 244                                 retry_flag = !0;
 245                                 pvr2_trace(
 246                                         PVR2_TRACE_ERROR_LEGS,
 247                                         "Encoder timed out waiting for us"
 248                                         "; arranging to retry");
 249                         } else {
 250                                 pvr2_trace(
 251                                         PVR2_TRACE_ERROR_LEGS,
 252                                         "***WARNING*** device's encoder"
 253                                         " appears to be stuck"
 254                                         " (status=0%08x)",rdData[0]);
 255                         }
 256                         pvr2_trace(
 257                                 PVR2_TRACE_ERROR_LEGS,
 258                                 "Encoder command: 0x%02x",cmd);
 259                         for (idx = 4; idx < arg_cnt_send; idx++) {
 260                                 pvr2_trace(
 261                                         PVR2_TRACE_ERROR_LEGS,
 262                                         "Encoder arg%d: 0x%08x",
 263                                         idx-3,wrData[idx]);
 264                         }
 265                         ret = -EBUSY;
 266                         break;
 267                 }
 268                 if (retry_flag) {
 269                         if (try_count < 20) continue;
 270                         pvr2_trace(
 271                                 PVR2_TRACE_ERROR_LEGS,
 272                                 "Too many retries...");
 273                         ret = -EBUSY;
 274                 }
 275                 if (ret) {
 276                         pvr2_trace(
 277                                 PVR2_TRACE_ERROR_LEGS,
 278                                 "Giving up on command."
 279                                 "  It is likely that"
 280                                 " this is a bad idea...");
 281                         break;
 282                 }
 283                 wrData[0] = 0x7;
 284                 for (idx = 0; idx < arg_cnt_recv; idx++) {
 285                         argp[idx] = rdData[idx+4];
 286                 }
 287
 288                 wrData[0] = 0x0;
 289                 ret = pvr2_encoder_write_words(hdw,MBOX_BASE,wrData,1);
 290                 if (ret) break;
 291
 292         } while(0); LOCK_GIVE(hdw->ctl_lock);
 293
 294         return ret;
 295 }
 296
 297
 298 static int pvr2_encoder_vcmd(struct pvr2_hdw *hdw, int cmd,
 299                              int args, ...)
 300 {
 301         va_list vl;
 302         unsigned int idx;
 303         u32 data[12];
 304
 305         if (args > ARRAY_SIZE(data)) {
 306                 pvr2_trace(
 307                         PVR2_TRACE_ERROR_LEGS,
 308                         "Failed to write cx23416 command"
 309                         " - too many arguments"
 310                         " (was given %u limit %lu)",
 311                         args, (long unsigned) ARRAY_SIZE(data));
 312                 return -EINVAL;
 313         }
 314
 315         va_start(vl, args);
 316         for (idx = 0; idx < args; idx++) {
 317                 data[idx] = va_arg(vl, u32);
 318         }
 319         va_end(vl);
 320
 321         return pvr2_encoder_cmd(hdw,cmd,args,0,data);
 322 }
 323
 324 int pvr2_encoder_configure(struct pvr2_hdw *hdw)
 325 {
 326         int ret;
 327         pvr2_trace(PVR2_TRACE_ENCODER,"pvr2_encoder_configure"
 328                    " (cx2341x module)");
 329         hdw->enc_ctl_state.port = CX2341X_PORT_STREAMING;
 330         hdw->enc_ctl_state.width = hdw->res_hor_val;
 331         hdw->enc_ctl_state.height = hdw->res_ver_val;
 332         hdw->enc_ctl_state.is_50hz = ((hdw->std_mask_cur &
 333                                        (V4L2_STD_NTSC|V4L2_STD_PAL_M)) ?
 334                                       0 : 1);
 335
 336         ret = 0;
 337
 338         if (!ret) ret = pvr2_encoder_vcmd(
 339                 hdw,CX2341X_ENC_SET_NUM_VSYNC_LINES, 2,
 340                 0xf0, 0xf0);
 341
 342         /* setup firmware to notify us about some events (don't know why...) */
 343         if (!ret) ret = pvr2_encoder_vcmd(
 344                 hdw,CX2341X_ENC_SET_EVENT_NOTIFICATION, 4,
 345                 0, 0, 0x10000000, 0xffffffff);
 346
 347         if (!ret) ret = pvr2_encoder_vcmd(
 348                 hdw,CX2341X_ENC_SET_VBI_LINE, 5,
 349                 0xffffffff,0,0,0,0);
 350
 351         if (ret) {
 352                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 353                            "Failed to configure cx23416");
 354                 return ret;
 355         }
 356
 357         ret = cx2341x_update(hdw,pvr2_encoder_cmd,
 358                              (hdw->enc_cur_valid ? &hdw->enc_cur_state : NULL),
 359                              &hdw->enc_ctl_state);
 360         if (ret) {
 361                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 362                            "Error from cx2341x module code=%d",ret);
 363                 return ret;
 364         }
 365
 366         ret = 0;
 367
 368         if (!ret) ret = pvr2_encoder_vcmd(
 369                 hdw, CX2341X_ENC_INITIALIZE_INPUT, 0);
 370
 371         if (ret) {
 372                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
 373                            "Failed to initialize cx23416 video input");
 374                 return ret;
 375         }
 376
 377         hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_CFG);
 378         memcpy(&hdw->enc_cur_state,&hdw->enc_ctl_state,
 379                sizeof(struct cx2341x_mpeg_params));
 380         hdw->enc_cur_valid = !0;
 381         return 0;
 382 }
 383
 384
 385 int pvr2_encoder_start(struct pvr2_hdw *hdw)
 386 {
 387         int status;
 388
 389         /* unmask some interrupts */
 390         pvr2_write_register(hdw, 0x0048, 0xbfffffff);
 391
 392         /* change some GPIO data */
 393         pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000481);
 394         pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000000);
 395
 396         pvr2_encoder_vcmd(hdw,CX2341X_ENC_MUTE_VIDEO,1,
 397                           hdw->input_val == PVR2_CVAL_INPUT_RADIO ? 1 : 0);
 398
 399         switch (hdw->config) {
 400         case pvr2_config_vbi:
 401                 status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
 402                                            0x01,0x14);
 403                 break;
 404         case pvr2_config_mpeg:
 405                 status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
 406                                            0,0x13);
 407                 break;
 408         default: /* Unhandled cases for now */
 409                 status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
 410                                            0,0x13);
 411                 break;
 412         }
 413         if (!status) {
 414                 hdw->subsys_enabled_mask |= (1<<PVR2_SUBSYS_B_ENC_RUN);
 415         }
 416         return status;
 417 }
 418
 419 int pvr2_encoder_stop(struct pvr2_hdw *hdw)
 420 {
 421         int status;
 422
 423         /* mask all interrupts */
 424         pvr2_write_register(hdw, 0x0048, 0xffffffff);
 425
 426         switch (hdw->config) {
 427         case pvr2_config_vbi:
 428                 status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
 429                                            0x01,0x01,0x14);
 430                 break;
 431         case pvr2_config_mpeg:
 432                 status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
 433                                            0x01,0,0x13);
 434                 break;
 435         default: /* Unhandled cases for now */
 436                 status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
 437                                            0x01,0,0x13);
 438                 break;
 439         }
 440
 441         /* change some GPIO data */
 442         /* Note: Bit d7 of dir appears to control the LED.  So we shut it
 443            off here. */
 444         pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000401);
 445         pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000000);
 446
 447         if (!status) {
 448                 hdw->subsys_enabled_mask &= ~(1<<PVR2_SUBSYS_B_ENC_RUN);
 449         }
 450         return status;
 451 }
 452
 453
 454 /*
 455   Stuff for Emacs to see, in order to encourage consistent editing style:
 456   *** Local Variables: ***
 457   *** mode: c ***
 458   *** fill-column: 70 ***
 459   *** tab-width: 8 ***
 460   *** c-basic-offset: 8 ***
 461   *** End: ***
 462   */