Pileus Git - ~andy/linux/blob - drivers/media/platform/davinci/vpbe_osd.c

   1 /*
   2  * Copyright (C) 2007-2010 Texas Instruments Inc
   3  * Copyright (C) 2007 MontaVista Software, Inc.
   4  *
   5  * Andy Lowe (alowe@mvista.com), MontaVista Software
   6  * - Initial version
   7  * Murali Karicheri (mkaricheri@gmail.com), Texas Instruments Ltd.
   8  * - ported to sub device interface
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation version 2.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22  *
  23  */
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/slab.h>
  30
  31 #include <mach/cputype.h>
  32 #include <mach/hardware.h>
  33
  34 #include <media/davinci/vpss.h>
  35 #include <media/v4l2-device.h>
  36 #include <media/davinci/vpbe_types.h>
  37 #include <media/davinci/vpbe_osd.h>
  38
  39 #include <linux/io.h>
  40 #include "vpbe_osd_regs.h"
  41
  42 #define MODULE_NAME     "davinci-vpbe-osd"
  43
  44 static struct platform_device_id vpbe_osd_devtype[] = {
  45         {
  46                 .name = DM644X_VPBE_OSD_SUBDEV_NAME,
  47                 .driver_data = VPBE_VERSION_1,
  48         }, {
  49                 .name = DM365_VPBE_OSD_SUBDEV_NAME,
  50                 .driver_data = VPBE_VERSION_2,
  51         }, {
  52                 .name = DM355_VPBE_OSD_SUBDEV_NAME,
  53                 .driver_data = VPBE_VERSION_3,
  54         },
  55 };
  56
  57 MODULE_DEVICE_TABLE(platform, vpbe_osd_devtype);
  58
  59 /* register access routines */
  60 static inline u32 osd_read(struct osd_state *sd, u32 offset)
  61 {
  62         struct osd_state *osd = sd;
  63
  64         return readl(osd->osd_base + offset);
  65 }
  66
  67 static inline u32 osd_write(struct osd_state *sd, u32 val, u32 offset)
  68 {
  69         struct osd_state *osd = sd;
  70
  71         writel(val, osd->osd_base + offset);
  72
  73         return val;
  74 }
  75
  76 static inline u32 osd_set(struct osd_state *sd, u32 mask, u32 offset)
  77 {
  78         struct osd_state *osd = sd;
  79
  80         void __iomem *addr = osd->osd_base + offset;
  81         u32 val = readl(addr) | mask;
  82
  83         writel(val, addr);
  84
  85         return val;
  86 }
  87
  88 static inline u32 osd_clear(struct osd_state *sd, u32 mask, u32 offset)
  89 {
  90         struct osd_state *osd = sd;
  91
  92         void __iomem *addr = osd->osd_base + offset;
  93         u32 val = readl(addr) & ~mask;
  94
  95         writel(val, addr);
  96
  97         return val;
  98 }
  99
 100 static inline u32 osd_modify(struct osd_state *sd, u32 mask, u32 val,
 101                                  u32 offset)
 102 {
 103         struct osd_state *osd = sd;
 104
 105         void __iomem *addr = osd->osd_base + offset;
 106         u32 new_val = (readl(addr) & ~mask) | (val & mask);
 107
 108         writel(new_val, addr);
 109
 110         return new_val;
 111 }
 112
 113 /* define some macros for layer and pixfmt classification */
 114 #define is_osd_win(layer) (((layer) == WIN_OSD0) || ((layer) == WIN_OSD1))
 115 #define is_vid_win(layer) (((layer) == WIN_VID0) || ((layer) == WIN_VID1))
 116 #define is_rgb_pixfmt(pixfmt) \
 117         (((pixfmt) == PIXFMT_RGB565) || ((pixfmt) == PIXFMT_RGB888))
 118 #define is_yc_pixfmt(pixfmt) \
 119         (((pixfmt) == PIXFMT_YCbCrI) || ((pixfmt) == PIXFMT_YCrCbI) || \
 120         ((pixfmt) == PIXFMT_NV12))
 121 #define MAX_WIN_SIZE OSD_VIDWIN0XP_V0X
 122 #define MAX_LINE_LENGTH (OSD_VIDWIN0OFST_V0LO << 5)
 123
 124 /**
 125  * _osd_dm6446_vid0_pingpong() - field inversion fix for DM6446
 126  * @sd - ptr to struct osd_state
 127  * @field_inversion - inversion flag
 128  * @fb_base_phys - frame buffer address
 129  * @lconfig - ptr to layer config
 130  *
 131  * This routine implements a workaround for the field signal inversion silicon
 132  * erratum described in Advisory 1.3.8 for the DM6446.  The fb_base_phys and
 133  * lconfig parameters apply to the vid0 window.  This routine should be called
 134  * whenever the vid0 layer configuration or start address is modified, or when
 135  * the OSD field inversion setting is modified.
 136  * Returns: 1 if the ping-pong buffers need to be toggled in the vsync isr, or
 137  *          0 otherwise
 138  */
 139 static int _osd_dm6446_vid0_pingpong(struct osd_state *sd,
 140                                      int field_inversion,
 141                                      unsigned long fb_base_phys,
 142                                      const struct osd_layer_config *lconfig)
 143 {
 144         struct osd_platform_data *pdata;
 145
 146         pdata = (struct osd_platform_data *)sd->dev->platform_data;
 147         if (pdata != NULL && pdata->field_inv_wa_enable) {
 148
 149                 if (!field_inversion || !lconfig->interlaced) {
 150                         osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN0ADR);
 151                         osd_write(sd, fb_base_phys & ~0x1F, OSD_PPVWIN0ADR);
 152                         osd_modify(sd, OSD_MISCCTL_PPSW | OSD_MISCCTL_PPRV, 0,
 153                                    OSD_MISCCTL);
 154                         return 0;
 155                 } else {
 156                         unsigned miscctl = OSD_MISCCTL_PPRV;
 157
 158                         osd_write(sd,
 159                                 (fb_base_phys & ~0x1F) - lconfig->line_length,
 160                                 OSD_VIDWIN0ADR);
 161                         osd_write(sd,
 162                                 (fb_base_phys & ~0x1F) + lconfig->line_length,
 163                                 OSD_PPVWIN0ADR);
 164                         osd_modify(sd,
 165                                 OSD_MISCCTL_PPSW | OSD_MISCCTL_PPRV, miscctl,
 166                                 OSD_MISCCTL);
 167
 168                         return 1;
 169                 }
 170         }
 171
 172         return 0;
 173 }
 174
 175 static void _osd_set_field_inversion(struct osd_state *sd, int enable)
 176 {
 177         unsigned fsinv = 0;
 178
 179         if (enable)
 180                 fsinv = OSD_MODE_FSINV;
 181
 182         osd_modify(sd, OSD_MODE_FSINV, fsinv, OSD_MODE);
 183 }
 184
 185 static void _osd_set_blink_attribute(struct osd_state *sd, int enable,
 186                                      enum osd_blink_interval blink)
 187 {
 188         u32 osdatrmd = 0;
 189
 190         if (enable) {
 191                 osdatrmd |= OSD_OSDATRMD_BLNK;
 192                 osdatrmd |= blink << OSD_OSDATRMD_BLNKINT_SHIFT;
 193         }
 194         /* caller must ensure that OSD1 is configured in attribute mode */
 195         osd_modify(sd, OSD_OSDATRMD_BLNKINT | OSD_OSDATRMD_BLNK, osdatrmd,
 196                   OSD_OSDATRMD);
 197 }
 198
 199 static void _osd_set_rom_clut(struct osd_state *sd,
 200                               enum osd_rom_clut rom_clut)
 201 {
 202         if (rom_clut == ROM_CLUT0)
 203                 osd_clear(sd, OSD_MISCCTL_RSEL, OSD_MISCCTL);
 204         else
 205                 osd_set(sd, OSD_MISCCTL_RSEL, OSD_MISCCTL);
 206 }
 207
 208 static void _osd_set_palette_map(struct osd_state *sd,
 209                                  enum osd_win_layer osdwin,
 210                                  unsigned char pixel_value,
 211                                  unsigned char clut_index,
 212                                  enum osd_pix_format pixfmt)
 213 {
 214         static const int map_2bpp[] = { 0, 5, 10, 15 };
 215         static const int map_1bpp[] = { 0, 15 };
 216         int bmp_offset;
 217         int bmp_shift;
 218         int bmp_mask;
 219         int bmp_reg;
 220
 221         switch (pixfmt) {
 222         case PIXFMT_1BPP:
 223                 bmp_reg = map_1bpp[pixel_value & 0x1];
 224                 break;
 225         case PIXFMT_2BPP:
 226                 bmp_reg = map_2bpp[pixel_value & 0x3];
 227                 break;
 228         case PIXFMT_4BPP:
 229                 bmp_reg = pixel_value & 0xf;
 230                 break;
 231         default:
 232                 return;
 233         }
 234
 235         switch (osdwin) {
 236         case OSDWIN_OSD0:
 237                 bmp_offset = OSD_W0BMP01 + (bmp_reg >> 1) * sizeof(u32);
 238                 break;
 239         case OSDWIN_OSD1:
 240                 bmp_offset = OSD_W1BMP01 + (bmp_reg >> 1) * sizeof(u32);
 241                 break;
 242         default:
 243                 return;
 244         }
 245
 246         if (bmp_reg & 1) {
 247                 bmp_shift = 8;
 248                 bmp_mask = 0xff << 8;
 249         } else {
 250                 bmp_shift = 0;
 251                 bmp_mask = 0xff;
 252         }
 253
 254         osd_modify(sd, bmp_mask, clut_index << bmp_shift, bmp_offset);
 255 }
 256
 257 static void _osd_set_rec601_attenuation(struct osd_state *sd,
 258                                         enum osd_win_layer osdwin, int enable)
 259 {
 260         switch (osdwin) {
 261         case OSDWIN_OSD0:
 262                 osd_modify(sd, OSD_OSDWIN0MD_ATN0E,
 263                           enable ? OSD_OSDWIN0MD_ATN0E : 0,
 264                           OSD_OSDWIN0MD);
 265                 if (sd->vpbe_type == VPBE_VERSION_1)
 266                         osd_modify(sd, OSD_OSDWIN0MD_ATN0E,
 267                                   enable ? OSD_OSDWIN0MD_ATN0E : 0,
 268                                   OSD_OSDWIN0MD);
 269                 else if ((sd->vpbe_type == VPBE_VERSION_3) ||
 270                            (sd->vpbe_type == VPBE_VERSION_2))
 271                         osd_modify(sd, OSD_EXTMODE_ATNOSD0EN,
 272                                   enable ? OSD_EXTMODE_ATNOSD0EN : 0,
 273                                   OSD_EXTMODE);
 274                 break;
 275         case OSDWIN_OSD1:
 276                 osd_modify(sd, OSD_OSDWIN1MD_ATN1E,
 277                           enable ? OSD_OSDWIN1MD_ATN1E : 0,
 278                           OSD_OSDWIN1MD);
 279                 if (sd->vpbe_type == VPBE_VERSION_1)
 280                         osd_modify(sd, OSD_OSDWIN1MD_ATN1E,
 281                                   enable ? OSD_OSDWIN1MD_ATN1E : 0,
 282                                   OSD_OSDWIN1MD);
 283                 else if ((sd->vpbe_type == VPBE_VERSION_3) ||
 284                            (sd->vpbe_type == VPBE_VERSION_2))
 285                         osd_modify(sd, OSD_EXTMODE_ATNOSD1EN,
 286                                   enable ? OSD_EXTMODE_ATNOSD1EN : 0,
 287                                   OSD_EXTMODE);
 288                 break;
 289         }
 290 }
 291
 292 static void _osd_set_blending_factor(struct osd_state *sd,
 293                                      enum osd_win_layer osdwin,
 294                                      enum osd_blending_factor blend)
 295 {
 296         switch (osdwin) {
 297         case OSDWIN_OSD0:
 298                 osd_modify(sd, OSD_OSDWIN0MD_BLND0,
 299                           blend << OSD_OSDWIN0MD_BLND0_SHIFT, OSD_OSDWIN0MD);
 300                 break;
 301         case OSDWIN_OSD1:
 302                 osd_modify(sd, OSD_OSDWIN1MD_BLND1,
 303                           blend << OSD_OSDWIN1MD_BLND1_SHIFT, OSD_OSDWIN1MD);
 304                 break;
 305         }
 306 }
 307
 308 static void _osd_enable_rgb888_pixblend(struct osd_state *sd,
 309                                         enum osd_win_layer osdwin)
 310 {
 311
 312         osd_modify(sd, OSD_MISCCTL_BLDSEL, 0, OSD_MISCCTL);
 313         switch (osdwin) {
 314         case OSDWIN_OSD0:
 315                 osd_modify(sd, OSD_EXTMODE_OSD0BLDCHR,
 316                           OSD_EXTMODE_OSD0BLDCHR, OSD_EXTMODE);
 317                 break;
 318         case OSDWIN_OSD1:
 319                 osd_modify(sd, OSD_EXTMODE_OSD1BLDCHR,
 320                           OSD_EXTMODE_OSD1BLDCHR, OSD_EXTMODE);
 321                 break;
 322         }
 323 }
 324
 325 static void _osd_enable_color_key(struct osd_state *sd,
 326                                   enum osd_win_layer osdwin,
 327                                   unsigned colorkey,
 328                                   enum osd_pix_format pixfmt)
 329 {
 330         switch (pixfmt) {
 331         case PIXFMT_1BPP:
 332         case PIXFMT_2BPP:
 333         case PIXFMT_4BPP:
 334         case PIXFMT_8BPP:
 335                 if (sd->vpbe_type == VPBE_VERSION_3) {
 336                         switch (osdwin) {
 337                         case OSDWIN_OSD0:
 338                                 osd_modify(sd, OSD_TRANSPBMPIDX_BMP0,
 339                                           colorkey <<
 340                                           OSD_TRANSPBMPIDX_BMP0_SHIFT,
 341                                           OSD_TRANSPBMPIDX);
 342                                 break;
 343                         case OSDWIN_OSD1:
 344                                 osd_modify(sd, OSD_TRANSPBMPIDX_BMP1,
 345                                           colorkey <<
 346                                           OSD_TRANSPBMPIDX_BMP1_SHIFT,
 347                                           OSD_TRANSPBMPIDX);
 348                                 break;
 349                         }
 350                 }
 351                 break;
 352         case PIXFMT_RGB565:
 353                 if (sd->vpbe_type == VPBE_VERSION_1)
 354                         osd_write(sd, colorkey & OSD_TRANSPVAL_RGBTRANS,
 355                                   OSD_TRANSPVAL);
 356                 else if (sd->vpbe_type == VPBE_VERSION_3)
 357                         osd_write(sd, colorkey & OSD_TRANSPVALL_RGBL,
 358                                   OSD_TRANSPVALL);
 359                 break;
 360         case PIXFMT_YCbCrI:
 361         case PIXFMT_YCrCbI:
 362                 if (sd->vpbe_type == VPBE_VERSION_3)
 363                         osd_modify(sd, OSD_TRANSPVALU_Y, colorkey,
 364                                    OSD_TRANSPVALU);
 365                 break;
 366         case PIXFMT_RGB888:
 367                 if (sd->vpbe_type == VPBE_VERSION_3) {
 368                         osd_write(sd, colorkey & OSD_TRANSPVALL_RGBL,
 369                                   OSD_TRANSPVALL);
 370                         osd_modify(sd, OSD_TRANSPVALU_RGBU, colorkey >> 16,
 371                                   OSD_TRANSPVALU);
 372                 }
 373                 break;
 374         default:
 375                 break;
 376         }
 377
 378         switch (osdwin) {
 379         case OSDWIN_OSD0:
 380                 osd_set(sd, OSD_OSDWIN0MD_TE0, OSD_OSDWIN0MD);
 381                 break;
 382         case OSDWIN_OSD1:
 383                 osd_set(sd, OSD_OSDWIN1MD_TE1, OSD_OSDWIN1MD);
 384                 break;
 385         }
 386 }
 387
 388 static void _osd_disable_color_key(struct osd_state *sd,
 389                                    enum osd_win_layer osdwin)
 390 {
 391         switch (osdwin) {
 392         case OSDWIN_OSD0:
 393                 osd_clear(sd, OSD_OSDWIN0MD_TE0, OSD_OSDWIN0MD);
 394                 break;
 395         case OSDWIN_OSD1:
 396                 osd_clear(sd, OSD_OSDWIN1MD_TE1, OSD_OSDWIN1MD);
 397                 break;
 398         }
 399 }
 400
 401 static void _osd_set_osd_clut(struct osd_state *sd,
 402                               enum osd_win_layer osdwin,
 403                               enum osd_clut clut)
 404 {
 405         u32 winmd = 0;
 406
 407         switch (osdwin) {
 408         case OSDWIN_OSD0:
 409                 if (clut == RAM_CLUT)
 410                         winmd |= OSD_OSDWIN0MD_CLUTS0;
 411                 osd_modify(sd, OSD_OSDWIN0MD_CLUTS0, winmd, OSD_OSDWIN0MD);
 412                 break;
 413         case OSDWIN_OSD1:
 414                 if (clut == RAM_CLUT)
 415                         winmd |= OSD_OSDWIN1MD_CLUTS1;
 416                 osd_modify(sd, OSD_OSDWIN1MD_CLUTS1, winmd, OSD_OSDWIN1MD);
 417                 break;
 418         }
 419 }
 420
 421 static void _osd_set_zoom(struct osd_state *sd, enum osd_layer layer,
 422                           enum osd_zoom_factor h_zoom,
 423                           enum osd_zoom_factor v_zoom)
 424 {
 425         u32 winmd = 0;
 426
 427         switch (layer) {
 428         case WIN_OSD0:
 429                 winmd |= (h_zoom << OSD_OSDWIN0MD_OHZ0_SHIFT);
 430                 winmd |= (v_zoom << OSD_OSDWIN0MD_OVZ0_SHIFT);
 431                 osd_modify(sd, OSD_OSDWIN0MD_OHZ0 | OSD_OSDWIN0MD_OVZ0, winmd,
 432                           OSD_OSDWIN0MD);
 433                 break;
 434         case WIN_VID0:
 435                 winmd |= (h_zoom << OSD_VIDWINMD_VHZ0_SHIFT);
 436                 winmd |= (v_zoom << OSD_VIDWINMD_VVZ0_SHIFT);
 437                 osd_modify(sd, OSD_VIDWINMD_VHZ0 | OSD_VIDWINMD_VVZ0, winmd,
 438                           OSD_VIDWINMD);
 439                 break;
 440         case WIN_OSD1:
 441                 winmd |= (h_zoom << OSD_OSDWIN1MD_OHZ1_SHIFT);
 442                 winmd |= (v_zoom << OSD_OSDWIN1MD_OVZ1_SHIFT);
 443                 osd_modify(sd, OSD_OSDWIN1MD_OHZ1 | OSD_OSDWIN1MD_OVZ1, winmd,
 444                           OSD_OSDWIN1MD);
 445                 break;
 446         case WIN_VID1:
 447                 winmd |= (h_zoom << OSD_VIDWINMD_VHZ1_SHIFT);
 448                 winmd |= (v_zoom << OSD_VIDWINMD_VVZ1_SHIFT);
 449                 osd_modify(sd, OSD_VIDWINMD_VHZ1 | OSD_VIDWINMD_VVZ1, winmd,
 450                           OSD_VIDWINMD);
 451                 break;
 452         }
 453 }
 454
 455 static void _osd_disable_layer(struct osd_state *sd, enum osd_layer layer)
 456 {
 457         switch (layer) {
 458         case WIN_OSD0:
 459                 osd_clear(sd, OSD_OSDWIN0MD_OACT0, OSD_OSDWIN0MD);
 460                 break;
 461         case WIN_VID0:
 462                 osd_clear(sd, OSD_VIDWINMD_ACT0, OSD_VIDWINMD);
 463                 break;
 464         case WIN_OSD1:
 465                 /* disable attribute mode as well as disabling the window */
 466                 osd_clear(sd, OSD_OSDWIN1MD_OASW | OSD_OSDWIN1MD_OACT1,
 467                           OSD_OSDWIN1MD);
 468                 break;
 469         case WIN_VID1:
 470                 osd_clear(sd, OSD_VIDWINMD_ACT1, OSD_VIDWINMD);
 471                 break;
 472         }
 473 }
 474
 475 static void osd_disable_layer(struct osd_state *sd, enum osd_layer layer)
 476 {
 477         struct osd_state *osd = sd;
 478         struct osd_window_state *win = &osd->win[layer];
 479         unsigned long flags;
 480
 481         spin_lock_irqsave(&osd->lock, flags);
 482
 483         if (!win->is_enabled) {
 484                 spin_unlock_irqrestore(&osd->lock, flags);
 485                 return;
 486         }
 487         win->is_enabled = 0;
 488
 489         _osd_disable_layer(sd, layer);
 490
 491         spin_unlock_irqrestore(&osd->lock, flags);
 492 }
 493
 494 static void _osd_enable_attribute_mode(struct osd_state *sd)
 495 {
 496         /* enable attribute mode for OSD1 */
 497         osd_set(sd, OSD_OSDWIN1MD_OASW, OSD_OSDWIN1MD);
 498 }
 499
 500 static void _osd_enable_layer(struct osd_state *sd, enum osd_layer layer)
 501 {
 502         switch (layer) {
 503         case WIN_OSD0:
 504                 osd_set(sd, OSD_OSDWIN0MD_OACT0, OSD_OSDWIN0MD);
 505                 break;
 506         case WIN_VID0:
 507                 osd_set(sd, OSD_VIDWINMD_ACT0, OSD_VIDWINMD);
 508                 break;
 509         case WIN_OSD1:
 510                 /* enable OSD1 and disable attribute mode */
 511                 osd_modify(sd, OSD_OSDWIN1MD_OASW | OSD_OSDWIN1MD_OACT1,
 512                           OSD_OSDWIN1MD_OACT1, OSD_OSDWIN1MD);
 513                 break;
 514         case WIN_VID1:
 515                 osd_set(sd, OSD_VIDWINMD_ACT1, OSD_VIDWINMD);
 516                 break;
 517         }
 518 }
 519
 520 static int osd_enable_layer(struct osd_state *sd, enum osd_layer layer,
 521                             int otherwin)
 522 {
 523         struct osd_state *osd = sd;
 524         struct osd_window_state *win = &osd->win[layer];
 525         struct osd_layer_config *cfg = &win->lconfig;
 526         unsigned long flags;
 527
 528         spin_lock_irqsave(&osd->lock, flags);
 529
 530         /*
 531          * use otherwin flag to know this is the other vid window
 532          * in YUV420 mode, if is, skip this check
 533          */
 534         if (!otherwin && (!win->is_allocated ||
 535                         !win->fb_base_phys ||
 536                         !cfg->line_length ||
 537                         !cfg->xsize ||
 538                         !cfg->ysize)) {
 539                 spin_unlock_irqrestore(&osd->lock, flags);
 540                 return -1;
 541         }
 542
 543         if (win->is_enabled) {
 544                 spin_unlock_irqrestore(&osd->lock, flags);
 545                 return 0;
 546         }
 547         win->is_enabled = 1;
 548
 549         if (cfg->pixfmt != PIXFMT_OSD_ATTR)
 550                 _osd_enable_layer(sd, layer);
 551         else {
 552                 _osd_enable_attribute_mode(sd);
 553                 _osd_set_blink_attribute(sd, osd->is_blinking, osd->blink);
 554         }
 555
 556         spin_unlock_irqrestore(&osd->lock, flags);
 557
 558         return 0;
 559 }
 560
 561 #define OSD_SRC_ADDR_HIGH4      0x7800000
 562 #define OSD_SRC_ADDR_HIGH7      0x7F0000
 563 #define OSD_SRCADD_OFSET_SFT    23
 564 #define OSD_SRCADD_ADD_SFT      16
 565 #define OSD_WINADL_MASK         0xFFFF
 566 #define OSD_WINOFST_MASK        0x1000
 567 #define VPBE_REG_BASE           0x80000000
 568
 569 static void _osd_start_layer(struct osd_state *sd, enum osd_layer layer,
 570                              unsigned long fb_base_phys,
 571                              unsigned long cbcr_ofst)
 572 {
 573
 574         if (sd->vpbe_type == VPBE_VERSION_1) {
 575                 switch (layer) {
 576                 case WIN_OSD0:
 577                         osd_write(sd, fb_base_phys & ~0x1F, OSD_OSDWIN0ADR);
 578                         break;
 579                 case WIN_VID0:
 580                         osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN0ADR);
 581                         break;
 582                 case WIN_OSD1:
 583                         osd_write(sd, fb_base_phys & ~0x1F, OSD_OSDWIN1ADR);
 584                         break;
 585                 case WIN_VID1:
 586                         osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN1ADR);
 587                         break;
 588               }
 589         } else if (sd->vpbe_type == VPBE_VERSION_3) {
 590                 unsigned long fb_offset_32 =
 591                     (fb_base_phys - VPBE_REG_BASE) >> 5;
 592
 593                 switch (layer) {
 594                 case WIN_OSD0:
 595                         osd_modify(sd, OSD_OSDWINADH_O0AH,
 596                                   fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
 597                                                    OSD_OSDWINADH_O0AH_SHIFT),
 598                                   OSD_OSDWINADH);
 599                         osd_write(sd, fb_offset_32 & OSD_OSDWIN0ADL_O0AL,
 600                                   OSD_OSDWIN0ADL);
 601                         break;
 602                 case WIN_VID0:
 603                         osd_modify(sd, OSD_VIDWINADH_V0AH,
 604                                   fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
 605                                                    OSD_VIDWINADH_V0AH_SHIFT),
 606                                   OSD_VIDWINADH);
 607                         osd_write(sd, fb_offset_32 & OSD_VIDWIN0ADL_V0AL,
 608                                   OSD_VIDWIN0ADL);
 609                         break;
 610                 case WIN_OSD1:
 611                         osd_modify(sd, OSD_OSDWINADH_O1AH,
 612                                   fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
 613                                                    OSD_OSDWINADH_O1AH_SHIFT),
 614                                   OSD_OSDWINADH);
 615                         osd_write(sd, fb_offset_32 & OSD_OSDWIN1ADL_O1AL,
 616                                   OSD_OSDWIN1ADL);
 617                         break;
 618                 case WIN_VID1:
 619                         osd_modify(sd, OSD_VIDWINADH_V1AH,
 620                                   fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
 621                                                    OSD_VIDWINADH_V1AH_SHIFT),
 622                                   OSD_VIDWINADH);
 623                         osd_write(sd, fb_offset_32 & OSD_VIDWIN1ADL_V1AL,
 624                                   OSD_VIDWIN1ADL);
 625                         break;
 626                 }
 627         } else if (sd->vpbe_type == VPBE_VERSION_2) {
 628                 struct osd_window_state *win = &sd->win[layer];
 629                 unsigned long fb_offset_32, cbcr_offset_32;
 630
 631                 fb_offset_32 = fb_base_phys - VPBE_REG_BASE;
 632                 if (cbcr_ofst)
 633                         cbcr_offset_32 = cbcr_ofst;
 634                 else
 635                         cbcr_offset_32 = win->lconfig.line_length *
 636                                          win->lconfig.ysize;
 637                 cbcr_offset_32 += fb_offset_32;
 638                 fb_offset_32 = fb_offset_32 >> 5;
 639                 cbcr_offset_32 = cbcr_offset_32 >> 5;
 640                 /*
 641                  * DM365: start address is 27-bit long address b26 - b23 are
 642                  * in offset register b12 - b9, and * bit 26 has to be '1'
 643                  */
 644                 if (win->lconfig.pixfmt == PIXFMT_NV12) {
 645                         switch (layer) {
 646                         case WIN_VID0:
 647                         case WIN_VID1:
 648                                 /* Y is in VID0 */
 649                                 osd_modify(sd, OSD_VIDWIN0OFST_V0AH,
 650                                          ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
 651                                          (OSD_SRCADD_OFSET_SFT -
 652                                          OSD_WINOFST_AH_SHIFT)) |
 653                                          OSD_WINOFST_MASK, OSD_VIDWIN0OFST);
 654                                 osd_modify(sd, OSD_VIDWINADH_V0AH,
 655                                           (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
 656                                           (OSD_SRCADD_ADD_SFT -
 657                                           OSD_VIDWINADH_V0AH_SHIFT),
 658                                            OSD_VIDWINADH);
 659                                 osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
 660                                           OSD_VIDWIN0ADL);
 661                                 /* CbCr is in VID1 */
 662                                 osd_modify(sd, OSD_VIDWIN1OFST_V1AH,
 663                                          ((cbcr_offset_32 &
 664                                          OSD_SRC_ADDR_HIGH4) >>
 665                                          (OSD_SRCADD_OFSET_SFT -
 666                                          OSD_WINOFST_AH_SHIFT)) |
 667                                          OSD_WINOFST_MASK, OSD_VIDWIN1OFST);
 668                                 osd_modify(sd, OSD_VIDWINADH_V1AH,
 669                                           (cbcr_offset_32 &
 670                                           OSD_SRC_ADDR_HIGH7) >>
 671                                           (OSD_SRCADD_ADD_SFT -
 672                                           OSD_VIDWINADH_V1AH_SHIFT),
 673                                           OSD_VIDWINADH);
 674                                 osd_write(sd, cbcr_offset_32 & OSD_WINADL_MASK,
 675                                           OSD_VIDWIN1ADL);
 676                                 break;
 677                         default:
 678                                 break;
 679                         }
 680                 }
 681
 682                 switch (layer) {
 683                 case WIN_OSD0:
 684                         osd_modify(sd, OSD_OSDWIN0OFST_O0AH,
 685                                  ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
 686                                  (OSD_SRCADD_OFSET_SFT -
 687                                  OSD_WINOFST_AH_SHIFT)) | OSD_WINOFST_MASK,
 688                                   OSD_OSDWIN0OFST);
 689                         osd_modify(sd, OSD_OSDWINADH_O0AH,
 690                                  (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
 691                                  (OSD_SRCADD_ADD_SFT -
 692                                  OSD_OSDWINADH_O0AH_SHIFT), OSD_OSDWINADH);
 693                         osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
 694                                         OSD_OSDWIN0ADL);
 695                         break;
 696                 case WIN_VID0:
 697                         if (win->lconfig.pixfmt != PIXFMT_NV12) {
 698                                 osd_modify(sd, OSD_VIDWIN0OFST_V0AH,
 699                                          ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
 700                                          (OSD_SRCADD_OFSET_SFT -
 701                                          OSD_WINOFST_AH_SHIFT)) |
 702                                          OSD_WINOFST_MASK, OSD_VIDWIN0OFST);
 703                                 osd_modify(sd, OSD_VIDWINADH_V0AH,
 704                                           (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
 705                                           (OSD_SRCADD_ADD_SFT -
 706                                           OSD_VIDWINADH_V0AH_SHIFT),
 707                                           OSD_VIDWINADH);
 708                                 osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
 709                                           OSD_VIDWIN0ADL);
 710                         }
 711                         break;
 712                 case WIN_OSD1:
 713                         osd_modify(sd, OSD_OSDWIN1OFST_O1AH,
 714                                  ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
 715                                  (OSD_SRCADD_OFSET_SFT -
 716                                  OSD_WINOFST_AH_SHIFT)) | OSD_WINOFST_MASK,
 717                                   OSD_OSDWIN1OFST);
 718                         osd_modify(sd, OSD_OSDWINADH_O1AH,
 719                                   (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
 720                                   (OSD_SRCADD_ADD_SFT -
 721                                   OSD_OSDWINADH_O1AH_SHIFT),
 722                                   OSD_OSDWINADH);
 723                         osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
 724                                         OSD_OSDWIN1ADL);
 725                         break;
 726                 case WIN_VID1:
 727                         if (win->lconfig.pixfmt != PIXFMT_NV12) {
 728                                 osd_modify(sd, OSD_VIDWIN1OFST_V1AH,
 729                                          ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
 730                                          (OSD_SRCADD_OFSET_SFT -
 731                                          OSD_WINOFST_AH_SHIFT)) |
 732                                          OSD_WINOFST_MASK, OSD_VIDWIN1OFST);
 733                                 osd_modify(sd, OSD_VIDWINADH_V1AH,
 734                                           (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
 735                                           (OSD_SRCADD_ADD_SFT -
 736                                           OSD_VIDWINADH_V1AH_SHIFT),
 737                                           OSD_VIDWINADH);
 738                                 osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
 739                                           OSD_VIDWIN1ADL);
 740                         }
 741                         break;
 742                 }
 743         }
 744 }
 745
 746 static void osd_start_layer(struct osd_state *sd, enum osd_layer layer,
 747                             unsigned long fb_base_phys,
 748                             unsigned long cbcr_ofst)
 749 {
 750         struct osd_state *osd = sd;
 751         struct osd_window_state *win = &osd->win[layer];
 752         struct osd_layer_config *cfg = &win->lconfig;
 753         unsigned long flags;
 754
 755         spin_lock_irqsave(&osd->lock, flags);
 756
 757         win->fb_base_phys = fb_base_phys & ~0x1F;
 758         _osd_start_layer(sd, layer, fb_base_phys, cbcr_ofst);
 759
 760         if (layer == WIN_VID0) {
 761                 osd->pingpong =
 762                     _osd_dm6446_vid0_pingpong(sd, osd->field_inversion,
 763                                                        win->fb_base_phys,
 764                                                        cfg);
 765         }
 766
 767         spin_unlock_irqrestore(&osd->lock, flags);
 768 }
 769
 770 static void osd_get_layer_config(struct osd_state *sd, enum osd_layer layer,
 771                                  struct osd_layer_config *lconfig)
 772 {
 773         struct osd_state *osd = sd;
 774         struct osd_window_state *win = &osd->win[layer];
 775         unsigned long flags;
 776
 777         spin_lock_irqsave(&osd->lock, flags);
 778
 779         *lconfig = win->lconfig;
 780
 781         spin_unlock_irqrestore(&osd->lock, flags);
 782 }
 783
 784 /**
 785  * try_layer_config() - Try a specific configuration for the layer
 786  * @sd  - ptr to struct osd_state
 787  * @layer - layer to configure
 788  * @lconfig - layer configuration to try
 789  *
 790  * If the requested lconfig is completely rejected and the value of lconfig on
 791  * exit is the current lconfig, then try_layer_config() returns 1.  Otherwise,
 792  * try_layer_config() returns 0.  A return value of 0 does not necessarily mean
 793  * that the value of lconfig on exit is identical to the value of lconfig on
 794  * entry, but merely that it represents a change from the current lconfig.
 795  */
 796 static int try_layer_config(struct osd_state *sd, enum osd_layer layer,
 797                             struct osd_layer_config *lconfig)
 798 {
 799         struct osd_state *osd = sd;
 800         struct osd_window_state *win = &osd->win[layer];
 801         int bad_config = 0;
 802
 803         /* verify that the pixel format is compatible with the layer */
 804         switch (lconfig->pixfmt) {
 805         case PIXFMT_1BPP:
 806         case PIXFMT_2BPP:
 807         case PIXFMT_4BPP:
 808         case PIXFMT_8BPP:
 809         case PIXFMT_RGB565:
 810                 if (osd->vpbe_type == VPBE_VERSION_1)
 811                         bad_config = !is_vid_win(layer);
 812                 break;
 813         case PIXFMT_YCbCrI:
 814         case PIXFMT_YCrCbI:
 815                 bad_config = !is_vid_win(layer);
 816                 break;
 817         case PIXFMT_RGB888:
 818                 if (osd->vpbe_type == VPBE_VERSION_1)
 819                         bad_config = !is_vid_win(layer);
 820                 else if ((osd->vpbe_type == VPBE_VERSION_3) ||
 821                          (osd->vpbe_type == VPBE_VERSION_2))
 822                         bad_config = !is_osd_win(layer);
 823                 break;
 824         case PIXFMT_NV12:
 825                 if (osd->vpbe_type != VPBE_VERSION_2)
 826                         bad_config = 1;
 827                 else
 828                         bad_config = is_osd_win(layer);
 829                 break;
 830         case PIXFMT_OSD_ATTR:
 831                 bad_config = (layer != WIN_OSD1);
 832                 break;
 833         default:
 834                 bad_config = 1;
 835                 break;
 836         }
 837         if (bad_config) {
 838                 /*
 839                  * The requested pixel format is incompatible with the layer,
 840                  * so keep the current layer configuration.
 841                  */
 842                 *lconfig = win->lconfig;
 843                 return bad_config;
 844         }
 845
 846         /* DM6446: */
 847         /* only one OSD window at a time can use RGB pixel formats */
 848           if ((osd->vpbe_type == VPBE_VERSION_1) &&
 849                   is_osd_win(layer) && is_rgb_pixfmt(lconfig->pixfmt)) {
 850                 enum osd_pix_format pixfmt;
 851                 if (layer == WIN_OSD0)
 852                         pixfmt = osd->win[WIN_OSD1].lconfig.pixfmt;
 853                 else
 854                         pixfmt = osd->win[WIN_OSD0].lconfig.pixfmt;
 855
 856                 if (is_rgb_pixfmt(pixfmt)) {
 857                         /*
 858                          * The other OSD window is already configured for an
 859                          * RGB, so keep the current layer configuration.
 860                          */
 861                         *lconfig = win->lconfig;
 862                         return 1;
 863                 }
 864         }
 865
 866         /* DM6446: only one video window at a time can use RGB888 */
 867         if ((osd->vpbe_type == VPBE_VERSION_1) && is_vid_win(layer) &&
 868                 lconfig->pixfmt == PIXFMT_RGB888) {
 869                 enum osd_pix_format pixfmt;
 870
 871                 if (layer == WIN_VID0)
 872                         pixfmt = osd->win[WIN_VID1].lconfig.pixfmt;
 873                 else
 874                         pixfmt = osd->win[WIN_VID0].lconfig.pixfmt;
 875
 876                 if (pixfmt == PIXFMT_RGB888) {
 877                         /*
 878                          * The other video window is already configured for
 879                          * RGB888, so keep the current layer configuration.
 880                          */
 881                         *lconfig = win->lconfig;
 882                         return 1;
 883                 }
 884         }
 885
 886         /* window dimensions must be non-zero */
 887         if (!lconfig->line_length || !lconfig->xsize || !lconfig->ysize) {
 888                 *lconfig = win->lconfig;
 889                 return 1;
 890         }
 891
 892         /* round line_length up to a multiple of 32 */
 893         lconfig->line_length = ((lconfig->line_length + 31) / 32) * 32;
 894         lconfig->line_length =
 895             min(lconfig->line_length, (unsigned)MAX_LINE_LENGTH);
 896         lconfig->xsize = min(lconfig->xsize, (unsigned)MAX_WIN_SIZE);
 897         lconfig->ysize = min(lconfig->ysize, (unsigned)MAX_WIN_SIZE);
 898         lconfig->xpos = min(lconfig->xpos, (unsigned)MAX_WIN_SIZE);
 899         lconfig->ypos = min(lconfig->ypos, (unsigned)MAX_WIN_SIZE);
 900         lconfig->interlaced = (lconfig->interlaced != 0);
 901         if (lconfig->interlaced) {
 902                 /* ysize and ypos must be even for interlaced displays */
 903                 lconfig->ysize &= ~1;
 904                 lconfig->ypos &= ~1;
 905         }
 906
 907         return 0;
 908 }
 909
 910 static void _osd_disable_vid_rgb888(struct osd_state *sd)
 911 {
 912         /*
 913          * The DM6446 supports RGB888 pixel format in a single video window.
 914          * This routine disables RGB888 pixel format for both video windows.
 915          * The caller must ensure that neither video window is currently
 916          * configured for RGB888 pixel format.
 917          */
 918         if (sd->vpbe_type == VPBE_VERSION_1)
 919                 osd_clear(sd, OSD_MISCCTL_RGBEN, OSD_MISCCTL);
 920 }
 921
 922 static void _osd_enable_vid_rgb888(struct osd_state *sd,
 923                                    enum osd_layer layer)
 924 {
 925         /*
 926          * The DM6446 supports RGB888 pixel format in a single video window.
 927          * This routine enables RGB888 pixel format for the specified video
 928          * window.  The caller must ensure that the other video window is not
 929          * currently configured for RGB888 pixel format, as this routine will
 930          * disable RGB888 pixel format for the other window.
 931          */
 932         if (sd->vpbe_type == VPBE_VERSION_1) {
 933                 if (layer == WIN_VID0)
 934                         osd_modify(sd, OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN,
 935                                   OSD_MISCCTL_RGBEN, OSD_MISCCTL);
 936                 else if (layer == WIN_VID1)
 937                         osd_modify(sd, OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN,
 938                                   OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN,
 939                                   OSD_MISCCTL);
 940         }
 941 }
 942
 943 static void _osd_set_cbcr_order(struct osd_state *sd,
 944                                 enum osd_pix_format pixfmt)
 945 {
 946         /*
 947          * The caller must ensure that all windows using YC pixfmt use the same
 948          * Cb/Cr order.
 949          */
 950         if (pixfmt == PIXFMT_YCbCrI)
 951                 osd_clear(sd, OSD_MODE_CS, OSD_MODE);
 952         else if (pixfmt == PIXFMT_YCrCbI)
 953                 osd_set(sd, OSD_MODE_CS, OSD_MODE);
 954 }
 955
 956 static void _osd_set_layer_config(struct osd_state *sd, enum osd_layer layer,
 957                                   const struct osd_layer_config *lconfig)
 958 {
 959         u32 winmd = 0, winmd_mask = 0, bmw = 0;
 960
 961         _osd_set_cbcr_order(sd, lconfig->pixfmt);
 962
 963         switch (layer) {
 964         case WIN_OSD0:
 965                 if (sd->vpbe_type == VPBE_VERSION_1) {
 966                         winmd_mask |= OSD_OSDWIN0MD_RGB0E;
 967                         if (lconfig->pixfmt == PIXFMT_RGB565)
 968                                 winmd |= OSD_OSDWIN0MD_RGB0E;
 969                 } else if ((sd->vpbe_type == VPBE_VERSION_3) ||
 970                   (sd->vpbe_type == VPBE_VERSION_2)) {
 971                         winmd_mask |= OSD_OSDWIN0MD_BMP0MD;
 972                         switch (lconfig->pixfmt) {
 973                         case PIXFMT_RGB565:
 974                                         winmd |= (1 <<
 975                                         OSD_OSDWIN0MD_BMP0MD_SHIFT);
 976                                         break;
 977                         case PIXFMT_RGB888:
 978                                 winmd |= (2 << OSD_OSDWIN0MD_BMP0MD_SHIFT);
 979                                 _osd_enable_rgb888_pixblend(sd, OSDWIN_OSD0);
 980                                 break;
 981                         case PIXFMT_YCbCrI:
 982                         case PIXFMT_YCrCbI:
 983                                 winmd |= (3 << OSD_OSDWIN0MD_BMP0MD_SHIFT);
 984                                 break;
 985                         default:
 986                                 break;
 987                         }
 988                 }
 989
 990                 winmd_mask |= OSD_OSDWIN0MD_BMW0 | OSD_OSDWIN0MD_OFF0;
 991
 992                 switch (lconfig->pixfmt) {
 993                 case PIXFMT_1BPP:
 994                         bmw = 0;
 995                         break;
 996                 case PIXFMT_2BPP:
 997                         bmw = 1;
 998                         break;
 999                 case PIXFMT_4BPP:
1000                         bmw = 2;
1001                         break;
1002                 case PIXFMT_8BPP:
1003                         bmw = 3;
1004                         break;
1005                 default:
1006                         break;
1007                 }
1008                 winmd |= (bmw << OSD_OSDWIN0MD_BMW0_SHIFT);
1009
1010                 if (lconfig->interlaced)
1011                         winmd |= OSD_OSDWIN0MD_OFF0;
1012
1013                 osd_modify(sd, winmd_mask, winmd, OSD_OSDWIN0MD);
1014                 osd_write(sd, lconfig->line_length >> 5, OSD_OSDWIN0OFST);
1015                 osd_write(sd, lconfig->xpos, OSD_OSDWIN0XP);
1016                 osd_write(sd, lconfig->xsize, OSD_OSDWIN0XL);
1017                 if (lconfig->interlaced) {
1018                         osd_write(sd, lconfig->ypos >> 1, OSD_OSDWIN0YP);
1019                         osd_write(sd, lconfig->ysize >> 1, OSD_OSDWIN0YL);
1020                 } else {
1021                         osd_write(sd, lconfig->ypos, OSD_OSDWIN0YP);
1022                         osd_write(sd, lconfig->ysize, OSD_OSDWIN0YL);
1023                 }
1024                 break;
1025         case WIN_VID0:
1026                 winmd_mask |= OSD_VIDWINMD_VFF0;
1027                 if (lconfig->interlaced)
1028                         winmd |= OSD_VIDWINMD_VFF0;
1029
1030                 osd_modify(sd, winmd_mask, winmd, OSD_VIDWINMD);
1031                 osd_write(sd, lconfig->line_length >> 5, OSD_VIDWIN0OFST);
1032                 osd_write(sd, lconfig->xpos, OSD_VIDWIN0XP);
1033                 osd_write(sd, lconfig->xsize, OSD_VIDWIN0XL);
1034                 /*
1035                  * For YUV420P format the register contents are
1036                  * duplicated in both VID registers
1037                  */
1038                 if ((sd->vpbe_type == VPBE_VERSION_2) &&
1039                                 (lconfig->pixfmt == PIXFMT_NV12)) {
1040                         /* other window also */
1041                         if (lconfig->interlaced) {
1042                                 winmd_mask |= OSD_VIDWINMD_VFF1;
1043                                 winmd |= OSD_VIDWINMD_VFF1;
1044                                 osd_modify(sd, winmd_mask, winmd,
1045                                           OSD_VIDWINMD);
1046                         }
1047
1048                         osd_modify(sd, OSD_MISCCTL_S420D,
1049                                     OSD_MISCCTL_S420D, OSD_MISCCTL);
1050                         osd_write(sd, lconfig->line_length >> 5,
1051                                   OSD_VIDWIN1OFST);
1052                         osd_write(sd, lconfig->xpos, OSD_VIDWIN1XP);
1053                         osd_write(sd, lconfig->xsize, OSD_VIDWIN1XL);
1054                         /*
1055                           * if NV21 pixfmt and line length not 32B
1056                           * aligned (e.g. NTSC), Need to set window
1057                           * X pixel size to be 32B aligned as well
1058                           */
1059                         if (lconfig->xsize % 32) {
1060                                 osd_write(sd,
1061                                           ((lconfig->xsize + 31) & ~31),
1062                                           OSD_VIDWIN1XL);
1063                                 osd_write(sd,
1064                                           ((lconfig->xsize + 31) & ~31),
1065                                           OSD_VIDWIN0XL);
1066                         }
1067                 } else if ((sd->vpbe_type == VPBE_VERSION_2) &&
1068                                 (lconfig->pixfmt != PIXFMT_NV12)) {
1069                         osd_modify(sd, OSD_MISCCTL_S420D, ~OSD_MISCCTL_S420D,
1070                                                 OSD_MISCCTL);
1071                 }
1072
1073                 if (lconfig->interlaced) {
1074                         osd_write(sd, lconfig->ypos >> 1, OSD_VIDWIN0YP);
1075                         osd_write(sd, lconfig->ysize >> 1, OSD_VIDWIN0YL);
1076                         if ((sd->vpbe_type == VPBE_VERSION_2) &&
1077                                 lconfig->pixfmt == PIXFMT_NV12) {
1078                                 osd_write(sd, lconfig->ypos >> 1,
1079                                           OSD_VIDWIN1YP);
1080                                 osd_write(sd, lconfig->ysize >> 1,
1081                                           OSD_VIDWIN1YL);
1082                         }
1083                 } else {
1084                         osd_write(sd, lconfig->ypos, OSD_VIDWIN0YP);
1085                         osd_write(sd, lconfig->ysize, OSD_VIDWIN0YL);
1086                         if ((sd->vpbe_type == VPBE_VERSION_2) &&
1087                                 lconfig->pixfmt == PIXFMT_NV12) {
1088                                 osd_write(sd, lconfig->ypos, OSD_VIDWIN1YP);
1089                                 osd_write(sd, lconfig->ysize, OSD_VIDWIN1YL);
1090                         }
1091                 }
1092                 break;
1093         case WIN_OSD1:
1094                 /*
1095                  * The caller must ensure that OSD1 is disabled prior to
1096                  * switching from a normal mode to attribute mode or from
1097                  * attribute mode to a normal mode.
1098                  */
1099                 if (lconfig->pixfmt == PIXFMT_OSD_ATTR) {
1100                         if (sd->vpbe_type == VPBE_VERSION_1) {
1101                                 winmd_mask |= OSD_OSDWIN1MD_ATN1E |
1102                                 OSD_OSDWIN1MD_RGB1E | OSD_OSDWIN1MD_CLUTS1 |
1103                                 OSD_OSDWIN1MD_BLND1 | OSD_OSDWIN1MD_TE1;
1104                         } else {
1105                                 winmd_mask |= OSD_OSDWIN1MD_BMP1MD |
1106                                 OSD_OSDWIN1MD_CLUTS1 | OSD_OSDWIN1MD_BLND1 |
1107                                 OSD_OSDWIN1MD_TE1;
1108                         }
1109                 } else {
1110                         if (sd->vpbe_type == VPBE_VERSION_1) {
1111                                 winmd_mask |= OSD_OSDWIN1MD_RGB1E;
1112                                 if (lconfig->pixfmt == PIXFMT_RGB565)
1113                                         winmd |= OSD_OSDWIN1MD_RGB1E;
1114                         } else if ((sd->vpbe_type == VPBE_VERSION_3)
1115                                    || (sd->vpbe_type == VPBE_VERSION_2)) {
1116                                 winmd_mask |= OSD_OSDWIN1MD_BMP1MD;
1117                                 switch (lconfig->pixfmt) {
1118                                 case PIXFMT_RGB565:
1119                                         winmd |=
1120                                             (1 << OSD_OSDWIN1MD_BMP1MD_SHIFT);
1121                                         break;
1122                                 case PIXFMT_RGB888:
1123                                         winmd |=
1124                                             (2 << OSD_OSDWIN1MD_BMP1MD_SHIFT);
1125                                         _osd_enable_rgb888_pixblend(sd,
1126                                                         OSDWIN_OSD1);
1127                                         break;
1128                                 case PIXFMT_YCbCrI:
1129                                 case PIXFMT_YCrCbI:
1130                                         winmd |=
1131                                             (3 << OSD_OSDWIN1MD_BMP1MD_SHIFT);
1132                                         break;
1133                                 default:
1134                                         break;
1135                                 }
1136                         }
1137
1138                         winmd_mask |= OSD_OSDWIN1MD_BMW1;
1139                         switch (lconfig->pixfmt) {
1140                         case PIXFMT_1BPP:
1141                                 bmw = 0;
1142                                 break;
1143                         case PIXFMT_2BPP:
1144                                 bmw = 1;
1145                                 break;
1146                         case PIXFMT_4BPP:
1147                                 bmw = 2;
1148                                 break;
1149                         case PIXFMT_8BPP:
1150                                 bmw = 3;
1151                                 break;
1152                         default:
1153                                 break;
1154                         }
1155                         winmd |= (bmw << OSD_OSDWIN1MD_BMW1_SHIFT);
1156                 }
1157
1158                 winmd_mask |= OSD_OSDWIN1MD_OFF1;
1159                 if (lconfig->interlaced)
1160                         winmd |= OSD_OSDWIN1MD_OFF1;
1161
1162                 osd_modify(sd, winmd_mask, winmd, OSD_OSDWIN1MD);
1163                 osd_write(sd, lconfig->line_length >> 5, OSD_OSDWIN1OFST);
1164                 osd_write(sd, lconfig->xpos, OSD_OSDWIN1XP);
1165                 osd_write(sd, lconfig->xsize, OSD_OSDWIN1XL);
1166                 if (lconfig->interlaced) {
1167                         osd_write(sd, lconfig->ypos >> 1, OSD_OSDWIN1YP);
1168                         osd_write(sd, lconfig->ysize >> 1, OSD_OSDWIN1YL);
1169                 } else {
1170                         osd_write(sd, lconfig->ypos, OSD_OSDWIN1YP);
1171                         osd_write(sd, lconfig->ysize, OSD_OSDWIN1YL);
1172                 }
1173                 break;
1174         case WIN_VID1:
1175                 winmd_mask |= OSD_VIDWINMD_VFF1;
1176                 if (lconfig->interlaced)
1177                         winmd |= OSD_VIDWINMD_VFF1;
1178
1179                 osd_modify(sd, winmd_mask, winmd, OSD_VIDWINMD);
1180                 osd_write(sd, lconfig->line_length >> 5, OSD_VIDWIN1OFST);
1181                 osd_write(sd, lconfig->xpos, OSD_VIDWIN1XP);
1182                 osd_write(sd, lconfig->xsize, OSD_VIDWIN1XL);
1183                 /*
1184                  * For YUV420P format the register contents are
1185                  * duplicated in both VID registers
1186                  */
1187                 if (sd->vpbe_type == VPBE_VERSION_2) {
1188                         if (lconfig->pixfmt == PIXFMT_NV12) {
1189                                 /* other window also */
1190                                 if (lconfig->interlaced) {
1191                                         winmd_mask |= OSD_VIDWINMD_VFF0;
1192                                         winmd |= OSD_VIDWINMD_VFF0;
1193                                         osd_modify(sd, winmd_mask, winmd,
1194                                                   OSD_VIDWINMD);
1195                                 }
1196                                 osd_modify(sd, OSD_MISCCTL_S420D,
1197                                            OSD_MISCCTL_S420D, OSD_MISCCTL);
1198                                 osd_write(sd, lconfig->line_length >> 5,
1199                                           OSD_VIDWIN0OFST);
1200                                 osd_write(sd, lconfig->xpos, OSD_VIDWIN0XP);
1201                                 osd_write(sd, lconfig->xsize, OSD_VIDWIN0XL);
1202                         } else {
1203                                 osd_modify(sd, OSD_MISCCTL_S420D,
1204                                            ~OSD_MISCCTL_S420D, OSD_MISCCTL);
1205                         }
1206                 }
1207
1208                 if (lconfig->interlaced) {
1209                         osd_write(sd, lconfig->ypos >> 1, OSD_VIDWIN1YP);
1210                         osd_write(sd, lconfig->ysize >> 1, OSD_VIDWIN1YL);
1211                         if ((sd->vpbe_type == VPBE_VERSION_2) &&
1212                                 lconfig->pixfmt == PIXFMT_NV12) {
1213                                 osd_write(sd, lconfig->ypos >> 1,
1214                                           OSD_VIDWIN0YP);
1215                                 osd_write(sd, lconfig->ysize >> 1,
1216                                           OSD_VIDWIN0YL);
1217                         }
1218                 } else {
1219                         osd_write(sd, lconfig->ypos, OSD_VIDWIN1YP);
1220                         osd_write(sd, lconfig->ysize, OSD_VIDWIN1YL);
1221                         if ((sd->vpbe_type == VPBE_VERSION_2) &&
1222                                 lconfig->pixfmt == PIXFMT_NV12) {
1223                                 osd_write(sd, lconfig->ypos, OSD_VIDWIN0YP);
1224                                 osd_write(sd, lconfig->ysize, OSD_VIDWIN0YL);
1225                         }
1226                 }
1227                 break;
1228         }
1229 }
1230
1231 static int osd_set_layer_config(struct osd_state *sd, enum osd_layer layer,
1232                                 struct osd_layer_config *lconfig)
1233 {
1234         struct osd_state *osd = sd;
1235         struct osd_window_state *win = &osd->win[layer];
1236         struct osd_layer_config *cfg = &win->lconfig;
1237         unsigned long flags;
1238         int reject_config;
1239
1240         spin_lock_irqsave(&osd->lock, flags);
1241
1242         reject_config = try_layer_config(sd, layer, lconfig);
1243         if (reject_config) {
1244                 spin_unlock_irqrestore(&osd->lock, flags);
1245                 return reject_config;
1246         }
1247
1248         /* update the current Cb/Cr order */
1249         if (is_yc_pixfmt(lconfig->pixfmt))
1250                 osd->yc_pixfmt = lconfig->pixfmt;
1251
1252         /*
1253          * If we are switching OSD1 from normal mode to attribute mode or from
1254          * attribute mode to normal mode, then we must disable the window.
1255          */
1256         if (layer == WIN_OSD1) {
1257                 if (((lconfig->pixfmt == PIXFMT_OSD_ATTR) &&
1258                   (cfg->pixfmt != PIXFMT_OSD_ATTR)) ||
1259                   ((lconfig->pixfmt != PIXFMT_OSD_ATTR) &&
1260                   (cfg->pixfmt == PIXFMT_OSD_ATTR))) {
1261                         win->is_enabled = 0;
1262                         _osd_disable_layer(sd, layer);
1263                 }
1264         }
1265
1266         _osd_set_layer_config(sd, layer, lconfig);
1267
1268         if (layer == WIN_OSD1) {
1269                 struct osd_osdwin_state *osdwin_state =
1270                     &osd->osdwin[OSDWIN_OSD1];
1271
1272                 if ((lconfig->pixfmt != PIXFMT_OSD_ATTR) &&
1273                   (cfg->pixfmt == PIXFMT_OSD_ATTR)) {
1274                         /*
1275                          * We just switched OSD1 from attribute mode to normal
1276                          * mode, so we must initialize the CLUT select, the
1277                          * blend factor, transparency colorkey enable, and
1278                          * attenuation enable (DM6446 only) bits in the
1279                          * OSDWIN1MD register.
1280                          */
1281                         _osd_set_osd_clut(sd, OSDWIN_OSD1,
1282                                                    osdwin_state->clut);
1283                         _osd_set_blending_factor(sd, OSDWIN_OSD1,
1284                                                           osdwin_state->blend);
1285                         if (osdwin_state->colorkey_blending) {
1286                                 _osd_enable_color_key(sd, OSDWIN_OSD1,
1287                                                                osdwin_state->
1288                                                                colorkey,
1289                                                                lconfig->pixfmt);
1290                         } else
1291                                 _osd_disable_color_key(sd, OSDWIN_OSD1);
1292                         _osd_set_rec601_attenuation(sd, OSDWIN_OSD1,
1293                                                     osdwin_state->
1294                                                     rec601_attenuation);
1295                 } else if ((lconfig->pixfmt == PIXFMT_OSD_ATTR) &&
1296                   (cfg->pixfmt != PIXFMT_OSD_ATTR)) {
1297                         /*
1298                          * We just switched OSD1 from normal mode to attribute
1299                          * mode, so we must initialize the blink enable and
1300                          * blink interval bits in the OSDATRMD register.
1301                          */
1302                         _osd_set_blink_attribute(sd, osd->is_blinking,
1303                                                           osd->blink);
1304                 }
1305         }
1306
1307         /*
1308          * If we just switched to a 1-, 2-, or 4-bits-per-pixel bitmap format
1309          * then configure a default palette map.
1310          */
1311         if ((lconfig->pixfmt != cfg->pixfmt) &&
1312           ((lconfig->pixfmt == PIXFMT_1BPP) ||
1313           (lconfig->pixfmt == PIXFMT_2BPP) ||
1314           (lconfig->pixfmt == PIXFMT_4BPP))) {
1315                 enum osd_win_layer osdwin =
1316                     ((layer == WIN_OSD0) ? OSDWIN_OSD0 : OSDWIN_OSD1);
1317                 struct osd_osdwin_state *osdwin_state =
1318                     &osd->osdwin[osdwin];
1319                 unsigned char clut_index;
1320                 unsigned char clut_entries = 0;
1321
1322                 switch (lconfig->pixfmt) {
1323                 case PIXFMT_1BPP:
1324                         clut_entries = 2;
1325                         break;
1326                 case PIXFMT_2BPP:
1327                         clut_entries = 4;
1328                         break;
1329                 case PIXFMT_4BPP:
1330                         clut_entries = 16;
1331                         break;
1332                 default:
1333                         break;
1334                 }
1335                 /*
1336                  * The default palette map maps the pixel value to the clut
1337                  * index, i.e. pixel value 0 maps to clut entry 0, pixel value
1338                  * 1 maps to clut entry 1, etc.
1339                  */
1340                 for (clut_index = 0; clut_index < 16; clut_index++) {
1341                         osdwin_state->palette_map[clut_index] = clut_index;
1342                         if (clut_index < clut_entries) {
1343                                 _osd_set_palette_map(sd, osdwin, clut_index,
1344                                                      clut_index,
1345                                                      lconfig->pixfmt);
1346                         }
1347                 }
1348         }
1349
1350         *cfg = *lconfig;
1351         /* DM6446: configure the RGB888 enable and window selection */
1352         if (osd->win[WIN_VID0].lconfig.pixfmt == PIXFMT_RGB888)
1353                 _osd_enable_vid_rgb888(sd, WIN_VID0);
1354         else if (osd->win[WIN_VID1].lconfig.pixfmt == PIXFMT_RGB888)
1355                 _osd_enable_vid_rgb888(sd, WIN_VID1);
1356         else
1357                 _osd_disable_vid_rgb888(sd);
1358
1359         if (layer == WIN_VID0) {
1360                 osd->pingpong =
1361                     _osd_dm6446_vid0_pingpong(sd, osd->field_inversion,
1362                                                        win->fb_base_phys,
1363                                                        cfg);
1364         }
1365
1366         spin_unlock_irqrestore(&osd->lock, flags);
1367
1368         return 0;
1369 }
1370
1371 static void osd_init_layer(struct osd_state *sd, enum osd_layer layer)
1372 {
1373         struct osd_state *osd = sd;
1374         struct osd_window_state *win = &osd->win[layer];
1375         enum osd_win_layer osdwin;
1376         struct osd_osdwin_state *osdwin_state;
1377         struct osd_layer_config *cfg = &win->lconfig;
1378         unsigned long flags;
1379
1380         spin_lock_irqsave(&osd->lock, flags);
1381
1382         win->is_enabled = 0;
1383         _osd_disable_layer(sd, layer);
1384
1385         win->h_zoom = ZOOM_X1;
1386         win->v_zoom = ZOOM_X1;
1387         _osd_set_zoom(sd, layer, win->h_zoom, win->v_zoom);
1388
1389         win->fb_base_phys = 0;
1390         _osd_start_layer(sd, layer, win->fb_base_phys, 0);
1391
1392         cfg->line_length = 0;
1393         cfg->xsize = 0;
1394         cfg->ysize = 0;
1395         cfg->xpos = 0;
1396         cfg->ypos = 0;
1397         cfg->interlaced = 0;
1398         switch (layer) {
1399         case WIN_OSD0:
1400         case WIN_OSD1:
1401                 osdwin = (layer == WIN_OSD0) ? OSDWIN_OSD0 : OSDWIN_OSD1;
1402                 osdwin_state = &osd->osdwin[osdwin];
1403                 /*
1404                  * Other code relies on the fact that OSD windows default to a
1405                  * bitmap pixel format when they are deallocated, so don't
1406                  * change this default pixel format.
1407                  */
1408                 cfg->pixfmt = PIXFMT_8BPP;
1409                 _osd_set_layer_config(sd, layer, cfg);
1410                 osdwin_state->clut = RAM_CLUT;
1411                 _osd_set_osd_clut(sd, osdwin, osdwin_state->clut);
1412                 osdwin_state->colorkey_blending = 0;
1413                 _osd_disable_color_key(sd, osdwin);
1414                 osdwin_state->blend = OSD_8_VID_0;
1415                 _osd_set_blending_factor(sd, osdwin, osdwin_state->blend);
1416                 osdwin_state->rec601_attenuation = 0;
1417                 _osd_set_rec601_attenuation(sd, osdwin,
1418                                                      osdwin_state->
1419                                                      rec601_attenuation);
1420                 if (osdwin == OSDWIN_OSD1) {
1421                         osd->is_blinking = 0;
1422                         osd->blink = BLINK_X1;
1423                 }
1424                 break;
1425         case WIN_VID0:
1426         case WIN_VID1:
1427                 cfg->pixfmt = osd->yc_pixfmt;
1428                 _osd_set_layer_config(sd, layer, cfg);
1429                 break;
1430         }
1431
1432         spin_unlock_irqrestore(&osd->lock, flags);
1433 }
1434
1435 static void osd_release_layer(struct osd_state *sd, enum osd_layer layer)
1436 {
1437         struct osd_state *osd = sd;
1438         struct osd_window_state *win = &osd->win[layer];
1439         unsigned long flags;
1440
1441         spin_lock_irqsave(&osd->lock, flags);
1442
1443         if (!win->is_allocated) {
1444                 spin_unlock_irqrestore(&osd->lock, flags);
1445                 return;
1446         }
1447
1448         spin_unlock_irqrestore(&osd->lock, flags);
1449         osd_init_layer(sd, layer);
1450         spin_lock_irqsave(&osd->lock, flags);
1451
1452         win->is_allocated = 0;
1453
1454         spin_unlock_irqrestore(&osd->lock, flags);
1455 }
1456
1457 static int osd_request_layer(struct osd_state *sd, enum osd_layer layer)
1458 {
1459         struct osd_state *osd = sd;
1460         struct osd_window_state *win = &osd->win[layer];
1461         unsigned long flags;
1462
1463         spin_lock_irqsave(&osd->lock, flags);
1464
1465         if (win->is_allocated) {
1466                 spin_unlock_irqrestore(&osd->lock, flags);
1467                 return -1;
1468         }
1469         win->is_allocated = 1;
1470
1471         spin_unlock_irqrestore(&osd->lock, flags);
1472
1473         return 0;
1474 }
1475
1476 static void _osd_init(struct osd_state *sd)
1477 {
1478         osd_write(sd, 0, OSD_MODE);
1479         osd_write(sd, 0, OSD_VIDWINMD);
1480         osd_write(sd, 0, OSD_OSDWIN0MD);
1481         osd_write(sd, 0, OSD_OSDWIN1MD);
1482         osd_write(sd, 0, OSD_RECTCUR);
1483         osd_write(sd, 0, OSD_MISCCTL);
1484         if (sd->vpbe_type == VPBE_VERSION_3) {
1485                 osd_write(sd, 0, OSD_VBNDRY);
1486                 osd_write(sd, 0, OSD_EXTMODE);
1487                 osd_write(sd, OSD_MISCCTL_DMANG, OSD_MISCCTL);
1488         }
1489 }
1490
1491 static void osd_set_left_margin(struct osd_state *sd, u32 val)
1492 {
1493         osd_write(sd, val, OSD_BASEPX);
1494 }
1495
1496 static void osd_set_top_margin(struct osd_state *sd, u32 val)
1497 {
1498         osd_write(sd, val, OSD_BASEPY);
1499 }
1500
1501 static int osd_initialize(struct osd_state *osd)
1502 {
1503         if (osd == NULL)
1504                 return -ENODEV;
1505         _osd_init(osd);
1506
1507         /* set default Cb/Cr order */
1508         osd->yc_pixfmt = PIXFMT_YCbCrI;
1509
1510         if (osd->vpbe_type == VPBE_VERSION_3) {
1511                 /*
1512                  * ROM CLUT1 on the DM355 is similar (identical?) to ROM CLUT0
1513                  * on the DM6446, so make ROM_CLUT1 the default on the DM355.
1514                  */
1515                 osd->rom_clut = ROM_CLUT1;
1516         }
1517
1518         _osd_set_field_inversion(osd, osd->field_inversion);
1519         _osd_set_rom_clut(osd, osd->rom_clut);
1520
1521         osd_init_layer(osd, WIN_OSD0);
1522         osd_init_layer(osd, WIN_VID0);
1523         osd_init_layer(osd, WIN_OSD1);
1524         osd_init_layer(osd, WIN_VID1);
1525
1526         return 0;
1527 }
1528
1529 static const struct vpbe_osd_ops osd_ops = {
1530         .initialize = osd_initialize,
1531         .request_layer = osd_request_layer,
1532         .release_layer = osd_release_layer,
1533         .enable_layer = osd_enable_layer,
1534         .disable_layer = osd_disable_layer,
1535         .set_layer_config = osd_set_layer_config,
1536         .get_layer_config = osd_get_layer_config,
1537         .start_layer = osd_start_layer,
1538         .set_left_margin = osd_set_left_margin,
1539         .set_top_margin = osd_set_top_margin,
1540 };
1541
1542 static int osd_probe(struct platform_device *pdev)
1543 {
1544         const struct platform_device_id *pdev_id;
1545         struct osd_state *osd;
1546         struct resource *res;
1547         int ret = 0;
1548
1549         osd = kzalloc(sizeof(struct osd_state), GFP_KERNEL);
1550         if (osd == NULL)
1551                 return -ENOMEM;
1552
1553         pdev_id = platform_get_device_id(pdev);
1554         if (!pdev_id) {
1555                 ret = -EINVAL;
1556                 goto free_mem;
1557         }
1558
1559         osd->dev = &pdev->dev;
1560         osd->vpbe_type = pdev_id->driver_data;
1561
1562         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1563         if (!res) {
1564                 dev_err(osd->dev, "Unable to get OSD register address map\n");
1565                 ret = -ENODEV;
1566                 goto free_mem;
1567         }
1568         osd->osd_base_phys = res->start;
1569         osd->osd_size = resource_size(res);
1570         if (!request_mem_region(osd->osd_base_phys, osd->osd_size,
1571                                 MODULE_NAME)) {
1572                 dev_err(osd->dev, "Unable to reserve OSD MMIO region\n");
1573                 ret = -ENODEV;
1574                 goto free_mem;
1575         }
1576         osd->osd_base = ioremap_nocache(res->start, osd->osd_size);
1577         if (!osd->osd_base) {
1578                 dev_err(osd->dev, "Unable to map the OSD region\n");
1579                 ret = -ENODEV;
1580                 goto release_mem_region;
1581         }
1582         spin_lock_init(&osd->lock);
1583         osd->ops = osd_ops;
1584         platform_set_drvdata(pdev, osd);
1585         dev_notice(osd->dev, "OSD sub device probe success\n");
1586         return ret;
1587
1588 release_mem_region:
1589         release_mem_region(osd->osd_base_phys, osd->osd_size);
1590 free_mem:
1591         kfree(osd);
1592         return ret;
1593 }
1594
1595 static int osd_remove(struct platform_device *pdev)
1596 {
1597         struct osd_state *osd = platform_get_drvdata(pdev);
1598
1599         iounmap((void *)osd->osd_base);
1600         release_mem_region(osd->osd_base_phys, osd->osd_size);
1601         kfree(osd);
1602         return 0;
1603 }
1604
1605 static struct platform_driver osd_driver = {
1606         .probe          = osd_probe,
1607         .remove         = osd_remove,
1608         .driver         = {
1609                 .name   = MODULE_NAME,
1610                 .owner  = THIS_MODULE,
1611         },
1612         .id_table       = vpbe_osd_devtype
1613 };
1614
1615 module_platform_driver(osd_driver);
1616
1617 MODULE_LICENSE("GPL");
1618 MODULE_DESCRIPTION("DaVinci OSD Manager Driver");
1619 MODULE_AUTHOR("Texas Instruments");