2 * Copyright (C) 2006-2009 Texas Instruments Inc
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 * CCDC hardware module for DM6446
19 * ------------------------------
21 * This module is for configuring CCD controller of DM6446 VPFE to capture
22 * Raw yuv or Bayer RGB data from a decoder. CCDC has several modules
23 * such as Defect Pixel Correction, Color Space Conversion etc to
24 * pre-process the Raw Bayer RGB data, before writing it to SDRAM. This
25 * module also allows application to configure individual
26 * module parameters through VPFE_CMD_S_CCDC_RAW_PARAMS IOCTL.
27 * To do so, application includes dm644x_ccdc.h and vpfe_capture.h header
28 * files. The setparams() API is called by vpfe_capture driver
29 * to configure module parameters. This file is named DM644x so that other
30 * variants such DM6443 may be supported using the same module.
32 * TODO: Test Raw bayer parameter settings and bayer capture
33 * Split module parameter structure to module specific ioctl structs
34 * investigate if enum used for user space type definition
35 * to be replaced by #defines or integer
37 #include <linux/platform_device.h>
38 #include <linux/uaccess.h>
39 #include <linux/videodev2.h>
40 #include <linux/gfp.h>
41 #include <linux/clk.h>
42 #include <linux/err.h>
43 #include <linux/module.h>
45 #include <media/davinci/dm644x_ccdc.h>
46 #include <media/davinci/vpss.h>
48 #include "dm644x_ccdc_regs.h"
49 #include "ccdc_hw_device.h"
51 MODULE_LICENSE("GPL");
52 MODULE_DESCRIPTION("CCDC Driver for DM6446");
53 MODULE_AUTHOR("Texas Instruments");
55 static struct ccdc_oper_config {
57 /* CCDC interface type */
58 enum vpfe_hw_if_type if_type;
59 /* Raw Bayer configuration */
60 struct ccdc_params_raw bayer;
61 /* YCbCr configuration */
62 struct ccdc_params_ycbcr ycbcr;
67 /* ccdc base address */
68 void __iomem *base_addr;
70 /* Raw configurations */
72 .pix_fmt = CCDC_PIXFMT_RAW,
73 .frm_fmt = CCDC_FRMFMT_PROGRESSIVE,
75 .fid_pol = VPFE_PINPOL_POSITIVE,
76 .vd_pol = VPFE_PINPOL_POSITIVE,
77 .hd_pol = VPFE_PINPOL_POSITIVE,
79 .data_sz = CCDC_DATA_10BITS,
83 .pix_fmt = CCDC_PIXFMT_YCBCR_8BIT,
84 .frm_fmt = CCDC_FRMFMT_INTERLACED,
86 .fid_pol = VPFE_PINPOL_POSITIVE,
87 .vd_pol = VPFE_PINPOL_POSITIVE,
88 .hd_pol = VPFE_PINPOL_POSITIVE,
90 .pix_order = CCDC_PIXORDER_CBYCRY,
91 .buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED
95 #define CCDC_MAX_RAW_YUV_FORMATS 2
97 /* Raw Bayer formats */
98 static u32 ccdc_raw_bayer_pix_formats[] =
99 {V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16};
101 /* Raw YUV formats */
102 static u32 ccdc_raw_yuv_pix_formats[] =
103 {V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV};
105 /* CCDC Save/Restore context */
106 static u32 ccdc_ctx[CCDC_REG_END / sizeof(u32)];
108 /* register access routines */
109 static inline u32 regr(u32 offset)
111 return __raw_readl(ccdc_cfg.base_addr + offset);
114 static inline void regw(u32 val, u32 offset)
116 __raw_writel(val, ccdc_cfg.base_addr + offset);
119 static void ccdc_enable(int flag)
121 regw(flag, CCDC_PCR);
124 static void ccdc_enable_vport(int flag)
127 /* enable video port */
128 regw(CCDC_ENABLE_VIDEO_PORT, CCDC_FMTCFG);
130 regw(CCDC_DISABLE_VIDEO_PORT, CCDC_FMTCFG);
135 * This function will configure the window size
136 * to be capture in CCDC reg
138 void ccdc_setwin(struct v4l2_rect *image_win,
139 enum ccdc_frmfmt frm_fmt,
142 int horz_start, horz_nr_pixels;
143 int vert_start, vert_nr_lines;
144 int val = 0, mid_img = 0;
146 dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_setwin...");
148 * ppc - per pixel count. indicates how many pixels per cell
149 * output to SDRAM. example, for ycbcr, it is one y and one c, so 2.
150 * raw capture this is 1
152 horz_start = image_win->left << (ppc - 1);
153 horz_nr_pixels = (image_win->width << (ppc - 1)) - 1;
154 regw((horz_start << CCDC_HORZ_INFO_SPH_SHIFT) | horz_nr_pixels,
157 vert_start = image_win->top;
159 if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
160 vert_nr_lines = (image_win->height >> 1) - 1;
162 /* Since first line doesn't have any data */
164 /* configure VDINT0 */
165 val = (vert_start << CCDC_VDINT_VDINT0_SHIFT);
166 regw(val, CCDC_VDINT);
169 /* Since first line doesn't have any data */
171 vert_nr_lines = image_win->height - 1;
173 * configure VDINT0 and VDINT1. VDINT1 will be at half
176 mid_img = vert_start + (image_win->height / 2);
177 val = (vert_start << CCDC_VDINT_VDINT0_SHIFT) |
178 (mid_img & CCDC_VDINT_VDINT1_MASK);
179 regw(val, CCDC_VDINT);
182 regw((vert_start << CCDC_VERT_START_SLV0_SHIFT) | vert_start,
184 regw(vert_nr_lines, CCDC_VERT_LINES);
185 dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_setwin...");
188 static void ccdc_readregs(void)
190 unsigned int val = 0;
192 val = regr(CCDC_ALAW);
193 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to ALAW...\n", val);
194 val = regr(CCDC_CLAMP);
195 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to CLAMP...\n", val);
196 val = regr(CCDC_DCSUB);
197 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to DCSUB...\n", val);
198 val = regr(CCDC_BLKCMP);
199 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to BLKCMP...\n", val);
200 val = regr(CCDC_FPC_ADDR);
201 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FPC_ADDR...\n", val);
202 val = regr(CCDC_FPC);
203 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FPC...\n", val);
204 val = regr(CCDC_FMTCFG);
205 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMTCFG...\n", val);
206 val = regr(CCDC_COLPTN);
207 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to COLPTN...\n", val);
208 val = regr(CCDC_FMT_HORZ);
209 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMT_HORZ...\n", val);
210 val = regr(CCDC_FMT_VERT);
211 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMT_VERT...\n", val);
212 val = regr(CCDC_HSIZE_OFF);
213 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to HSIZE_OFF...\n", val);
214 val = regr(CCDC_SDOFST);
215 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to SDOFST...\n", val);
216 val = regr(CCDC_VP_OUT);
217 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VP_OUT...\n", val);
218 val = regr(CCDC_SYN_MODE);
219 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to SYN_MODE...\n", val);
220 val = regr(CCDC_HORZ_INFO);
221 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to HORZ_INFO...\n", val);
222 val = regr(CCDC_VERT_START);
223 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VERT_START...\n", val);
224 val = regr(CCDC_VERT_LINES);
225 dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VERT_LINES...\n", val);
228 static int validate_ccdc_param(struct ccdc_config_params_raw *ccdcparam)
230 if (ccdcparam->alaw.enable) {
231 u8 max_gamma = ccdc_gamma_width_max_bit(ccdcparam->alaw.gamma_wd);
232 u8 max_data = ccdc_data_size_max_bit(ccdcparam->data_sz);
234 if ((ccdcparam->alaw.gamma_wd > CCDC_GAMMA_BITS_09_0) ||
235 (ccdcparam->alaw.gamma_wd < CCDC_GAMMA_BITS_15_6) ||
236 (max_gamma > max_data)) {
237 dev_dbg(ccdc_cfg.dev, "\nInvalid data line select");
244 static int ccdc_update_raw_params(struct ccdc_config_params_raw *raw_params)
246 struct ccdc_config_params_raw *config_params =
247 &ccdc_cfg.bayer.config_params;
248 unsigned int *fpc_virtaddr = NULL;
249 unsigned int *fpc_physaddr = NULL;
251 memcpy(config_params, raw_params, sizeof(*raw_params));
253 * allocate memory for fault pixel table and copy the user
254 * values to the table
256 if (!config_params->fault_pxl.enable)
259 fpc_physaddr = (unsigned int *)config_params->fault_pxl.fpc_table_addr;
260 fpc_virtaddr = (unsigned int *)phys_to_virt(
261 (unsigned long)fpc_physaddr);
263 * Allocate memory for FPC table if current
264 * FPC table buffer is not big enough to
265 * accommodate FPC Number requested
267 if (raw_params->fault_pxl.fp_num != config_params->fault_pxl.fp_num) {
268 if (fpc_physaddr != NULL) {
269 free_pages((unsigned long)fpc_physaddr,
271 (config_params->fault_pxl.fp_num *
275 /* Allocate memory for FPC table */
277 (unsigned int *)__get_free_pages(GFP_KERNEL | GFP_DMA,
278 get_order(raw_params->
282 if (fpc_virtaddr == NULL) {
283 dev_dbg(ccdc_cfg.dev,
284 "\nUnable to allocate memory for FPC");
288 (unsigned int *)virt_to_phys((void *)fpc_virtaddr);
291 /* Copy number of fault pixels and FPC table */
292 config_params->fault_pxl.fp_num = raw_params->fault_pxl.fp_num;
293 if (copy_from_user(fpc_virtaddr,
294 (void __user *)raw_params->fault_pxl.fpc_table_addr,
295 config_params->fault_pxl.fp_num * FP_NUM_BYTES)) {
296 dev_dbg(ccdc_cfg.dev, "\n copy_from_user failed");
299 config_params->fault_pxl.fpc_table_addr = (unsigned int)fpc_physaddr;
303 static int ccdc_close(struct device *dev)
305 struct ccdc_config_params_raw *config_params =
306 &ccdc_cfg.bayer.config_params;
307 unsigned int *fpc_physaddr = NULL, *fpc_virtaddr = NULL;
309 fpc_physaddr = (unsigned int *)config_params->fault_pxl.fpc_table_addr;
311 if (fpc_physaddr != NULL) {
312 fpc_virtaddr = (unsigned int *)
313 phys_to_virt((unsigned long)fpc_physaddr);
314 free_pages((unsigned long)fpc_virtaddr,
315 get_order(config_params->fault_pxl.fp_num *
322 * ccdc_restore_defaults()
323 * This function will write defaults to all CCDC registers
325 static void ccdc_restore_defaults(void)
331 /* set all registers to default value */
332 for (i = 4; i <= 0x94; i += 4)
334 regw(CCDC_NO_CULLING, CCDC_CULLING);
335 regw(CCDC_GAMMA_BITS_11_2, CCDC_ALAW);
338 static int ccdc_open(struct device *device)
340 ccdc_restore_defaults();
341 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
342 ccdc_enable_vport(1);
346 static void ccdc_sbl_reset(void)
348 vpss_clear_wbl_overflow(VPSS_PCR_CCDC_WBL_O);
351 /* Parameter operations */
352 static int ccdc_set_params(void __user *params)
354 struct ccdc_config_params_raw ccdc_raw_params;
357 if (ccdc_cfg.if_type != VPFE_RAW_BAYER)
360 x = copy_from_user(&ccdc_raw_params, params, sizeof(ccdc_raw_params));
362 dev_dbg(ccdc_cfg.dev, "ccdc_set_params: error in copying"
363 "ccdc params, %d\n", x);
367 if (!validate_ccdc_param(&ccdc_raw_params)) {
368 if (!ccdc_update_raw_params(&ccdc_raw_params))
375 * ccdc_config_ycbcr()
376 * This function will configure CCDC for YCbCr video capture
378 void ccdc_config_ycbcr(void)
380 struct ccdc_params_ycbcr *params = &ccdc_cfg.ycbcr;
383 dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_ycbcr...");
385 * first restore the CCDC registers to default values
386 * This is important since we assume default values to be set in
387 * a lot of registers that we didn't touch
389 ccdc_restore_defaults();
392 * configure pixel format, frame format, configure video frame
393 * format, enable output to SDRAM, enable internal timing generator
396 syn_mode = (((params->pix_fmt & CCDC_SYN_MODE_INPMOD_MASK) <<
397 CCDC_SYN_MODE_INPMOD_SHIFT) |
398 ((params->frm_fmt & CCDC_SYN_FLDMODE_MASK) <<
399 CCDC_SYN_FLDMODE_SHIFT) | CCDC_VDHDEN_ENABLE |
400 CCDC_WEN_ENABLE | CCDC_DATA_PACK_ENABLE);
402 /* setup BT.656 sync mode */
403 if (params->bt656_enable) {
404 regw(CCDC_REC656IF_BT656_EN, CCDC_REC656IF);
407 * configure the FID, VD, HD pin polarity,
408 * fld,hd pol positive, vd negative, 8-bit data
410 syn_mode |= CCDC_SYN_MODE_VD_POL_NEGATIVE;
411 if (ccdc_cfg.if_type == VPFE_BT656_10BIT)
412 syn_mode |= CCDC_SYN_MODE_10BITS;
414 syn_mode |= CCDC_SYN_MODE_8BITS;
416 /* y/c external sync mode */
417 syn_mode |= (((params->fid_pol & CCDC_FID_POL_MASK) <<
418 CCDC_FID_POL_SHIFT) |
419 ((params->hd_pol & CCDC_HD_POL_MASK) <<
421 ((params->vd_pol & CCDC_VD_POL_MASK) <<
424 regw(syn_mode, CCDC_SYN_MODE);
426 /* configure video window */
427 ccdc_setwin(¶ms->win, params->frm_fmt, 2);
430 * configure the order of y cb cr in SDRAM, and disable latch
431 * internal register on vsync
433 if (ccdc_cfg.if_type == VPFE_BT656_10BIT)
434 regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) |
435 CCDC_LATCH_ON_VSYNC_DISABLE | CCDC_CCDCFG_BW656_10BIT,
438 regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) |
439 CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG);
442 * configure the horizontal line offset. This should be a
443 * on 32 byte boundary. So clear LSB 5 bits
445 regw(((params->win.width * 2 + 31) & ~0x1f), CCDC_HSIZE_OFF);
447 /* configure the memory line offset */
448 if (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED)
449 /* two fields are interleaved in memory */
450 regw(CCDC_SDOFST_FIELD_INTERLEAVED, CCDC_SDOFST);
453 dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_config_ycbcr...\n");
456 static void ccdc_config_black_clamp(struct ccdc_black_clamp *bclamp)
460 if (!bclamp->enable) {
461 /* configure DCSub */
462 val = (bclamp->dc_sub) & CCDC_BLK_DC_SUB_MASK;
463 regw(val, CCDC_DCSUB);
464 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to DCSUB...\n", val);
465 regw(CCDC_CLAMP_DEFAULT_VAL, CCDC_CLAMP);
466 dev_dbg(ccdc_cfg.dev, "\nWriting 0x0000 to CLAMP...\n");
470 * Configure gain, Start pixel, No of line to be avg,
471 * No of pixel/line to be avg, & Enable the Black clamping
473 val = ((bclamp->sgain & CCDC_BLK_SGAIN_MASK) |
474 ((bclamp->start_pixel & CCDC_BLK_ST_PXL_MASK) <<
475 CCDC_BLK_ST_PXL_SHIFT) |
476 ((bclamp->sample_ln & CCDC_BLK_SAMPLE_LINE_MASK) <<
477 CCDC_BLK_SAMPLE_LINE_SHIFT) |
478 ((bclamp->sample_pixel & CCDC_BLK_SAMPLE_LN_MASK) <<
479 CCDC_BLK_SAMPLE_LN_SHIFT) | CCDC_BLK_CLAMP_ENABLE);
480 regw(val, CCDC_CLAMP);
481 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to CLAMP...\n", val);
482 /* If Black clamping is enable then make dcsub 0 */
483 regw(CCDC_DCSUB_DEFAULT_VAL, CCDC_DCSUB);
484 dev_dbg(ccdc_cfg.dev, "\nWriting 0x00000000 to DCSUB...\n");
487 static void ccdc_config_black_compense(struct ccdc_black_compensation *bcomp)
491 val = ((bcomp->b & CCDC_BLK_COMP_MASK) |
492 ((bcomp->gb & CCDC_BLK_COMP_MASK) <<
493 CCDC_BLK_COMP_GB_COMP_SHIFT) |
494 ((bcomp->gr & CCDC_BLK_COMP_MASK) <<
495 CCDC_BLK_COMP_GR_COMP_SHIFT) |
496 ((bcomp->r & CCDC_BLK_COMP_MASK) <<
497 CCDC_BLK_COMP_R_COMP_SHIFT));
498 regw(val, CCDC_BLKCMP);
501 static void ccdc_config_fpc(struct ccdc_fault_pixel *fpc)
505 /* Initially disable FPC */
506 val = CCDC_FPC_DISABLE;
512 /* Configure Fault pixel if needed */
513 regw(fpc->fpc_table_addr, CCDC_FPC_ADDR);
514 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FPC_ADDR...\n",
515 (fpc->fpc_table_addr));
516 /* Write the FPC params with FPC disable */
517 val = fpc->fp_num & CCDC_FPC_FPC_NUM_MASK;
520 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FPC...\n", val);
521 /* read the FPC register */
522 val = regr(CCDC_FPC) | CCDC_FPC_ENABLE;
524 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FPC...\n", val);
529 * This function will configure CCDC for Raw capture mode
531 void ccdc_config_raw(void)
533 struct ccdc_params_raw *params = &ccdc_cfg.bayer;
534 struct ccdc_config_params_raw *config_params =
535 &ccdc_cfg.bayer.config_params;
536 unsigned int syn_mode = 0;
539 dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_raw...");
542 ccdc_restore_defaults();
544 /* Disable latching function registers on VSYNC */
545 regw(CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG);
548 * Configure the vertical sync polarity(SYN_MODE.VDPOL),
549 * horizontal sync polarity (SYN_MODE.HDPOL), frame id polarity
550 * (SYN_MODE.FLDPOL), frame format(progressive or interlace),
551 * data size(SYNMODE.DATSIZ), &pixel format (Input mode), output
552 * SDRAM, enable internal timing generator
555 (((params->vd_pol & CCDC_VD_POL_MASK) << CCDC_VD_POL_SHIFT) |
556 ((params->hd_pol & CCDC_HD_POL_MASK) << CCDC_HD_POL_SHIFT) |
557 ((params->fid_pol & CCDC_FID_POL_MASK) << CCDC_FID_POL_SHIFT) |
558 ((params->frm_fmt & CCDC_FRM_FMT_MASK) << CCDC_FRM_FMT_SHIFT) |
559 ((config_params->data_sz & CCDC_DATA_SZ_MASK) <<
560 CCDC_DATA_SZ_SHIFT) |
561 ((params->pix_fmt & CCDC_PIX_FMT_MASK) << CCDC_PIX_FMT_SHIFT) |
562 CCDC_WEN_ENABLE | CCDC_VDHDEN_ENABLE);
564 /* Enable and configure aLaw register if needed */
565 if (config_params->alaw.enable) {
566 val = ((config_params->alaw.gamma_wd &
567 CCDC_ALAW_GAMMA_WD_MASK) | CCDC_ALAW_ENABLE);
568 regw(val, CCDC_ALAW);
569 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to ALAW...\n", val);
572 /* Configure video window */
573 ccdc_setwin(¶ms->win, params->frm_fmt, CCDC_PPC_RAW);
575 /* Configure Black Clamp */
576 ccdc_config_black_clamp(&config_params->blk_clamp);
578 /* Configure Black level compensation */
579 ccdc_config_black_compense(&config_params->blk_comp);
581 /* Configure Fault Pixel Correction */
582 ccdc_config_fpc(&config_params->fault_pxl);
584 /* If data size is 8 bit then pack the data */
585 if ((config_params->data_sz == CCDC_DATA_8BITS) ||
586 config_params->alaw.enable)
587 syn_mode |= CCDC_DATA_PACK_ENABLE;
589 #ifdef CONFIG_DM644X_VIDEO_PORT_ENABLE
590 /* enable video port */
591 val = CCDC_ENABLE_VIDEO_PORT;
593 /* disable video port */
594 val = CCDC_DISABLE_VIDEO_PORT;
597 if (config_params->data_sz == CCDC_DATA_8BITS)
598 val |= (CCDC_DATA_10BITS & CCDC_FMTCFG_VPIN_MASK)
599 << CCDC_FMTCFG_VPIN_SHIFT;
601 val |= (config_params->data_sz & CCDC_FMTCFG_VPIN_MASK)
602 << CCDC_FMTCFG_VPIN_SHIFT;
603 /* Write value in FMTCFG */
604 regw(val, CCDC_FMTCFG);
606 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMTCFG...\n", val);
607 /* Configure the color pattern according to mt9t001 sensor */
608 regw(CCDC_COLPTN_VAL, CCDC_COLPTN);
610 dev_dbg(ccdc_cfg.dev, "\nWriting 0xBB11BB11 to COLPTN...\n");
612 * Configure Data formatter(Video port) pixel selection
613 * (FMT_HORZ, FMT_VERT)
615 val = ((params->win.left & CCDC_FMT_HORZ_FMTSPH_MASK) <<
616 CCDC_FMT_HORZ_FMTSPH_SHIFT) |
617 (params->win.width & CCDC_FMT_HORZ_FMTLNH_MASK);
618 regw(val, CCDC_FMT_HORZ);
620 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMT_HORZ...\n", val);
621 val = (params->win.top & CCDC_FMT_VERT_FMTSLV_MASK)
622 << CCDC_FMT_VERT_FMTSLV_SHIFT;
623 if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE)
624 val |= (params->win.height) & CCDC_FMT_VERT_FMTLNV_MASK;
626 val |= (params->win.height >> 1) & CCDC_FMT_VERT_FMTLNV_MASK;
628 dev_dbg(ccdc_cfg.dev, "\nparams->win.height 0x%x ...\n",
630 regw(val, CCDC_FMT_VERT);
632 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMT_VERT...\n", val);
634 dev_dbg(ccdc_cfg.dev, "\nbelow regw(val, FMT_VERT)...");
637 * Configure Horizontal offset register. If pack 8 is enabled then
638 * 1 pixel will take 1 byte
640 if ((config_params->data_sz == CCDC_DATA_8BITS) ||
641 config_params->alaw.enable)
642 regw((params->win.width + CCDC_32BYTE_ALIGN_VAL) &
643 CCDC_HSIZE_OFF_MASK, CCDC_HSIZE_OFF);
645 /* else one pixel will take 2 byte */
646 regw(((params->win.width * CCDC_TWO_BYTES_PER_PIXEL) +
647 CCDC_32BYTE_ALIGN_VAL) & CCDC_HSIZE_OFF_MASK,
650 /* Set value for SDOFST */
651 if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) {
652 if (params->image_invert_enable) {
653 /* For intelace inverse mode */
654 regw(CCDC_INTERLACED_IMAGE_INVERT, CCDC_SDOFST);
655 dev_dbg(ccdc_cfg.dev, "\nWriting 0x4B6D to SDOFST..\n");
659 /* For intelace non inverse mode */
660 regw(CCDC_INTERLACED_NO_IMAGE_INVERT, CCDC_SDOFST);
661 dev_dbg(ccdc_cfg.dev, "\nWriting 0x0249 to SDOFST..\n");
663 } else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) {
664 regw(CCDC_PROGRESSIVE_NO_IMAGE_INVERT, CCDC_SDOFST);
665 dev_dbg(ccdc_cfg.dev, "\nWriting 0x0000 to SDOFST...\n");
669 * Configure video port pixel selection (VPOUT)
670 * Here -1 is to make the height value less than FMT_VERT.FMTLNV
672 if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE)
673 val = (((params->win.height - 1) & CCDC_VP_OUT_VERT_NUM_MASK))
674 << CCDC_VP_OUT_VERT_NUM_SHIFT;
677 ((((params->win.height >> CCDC_INTERLACED_HEIGHT_SHIFT) -
678 1) & CCDC_VP_OUT_VERT_NUM_MASK)) <<
679 CCDC_VP_OUT_VERT_NUM_SHIFT;
681 val |= ((((params->win.width))) & CCDC_VP_OUT_HORZ_NUM_MASK)
682 << CCDC_VP_OUT_HORZ_NUM_SHIFT;
683 val |= (params->win.left) & CCDC_VP_OUT_HORZ_ST_MASK;
684 regw(val, CCDC_VP_OUT);
686 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to VP_OUT...\n", val);
687 regw(syn_mode, CCDC_SYN_MODE);
688 dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to SYN_MODE...\n", syn_mode);
691 dev_dbg(ccdc_cfg.dev, "\nend of ccdc_config_raw...");
695 static int ccdc_configure(void)
697 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
704 static int ccdc_set_buftype(enum ccdc_buftype buf_type)
706 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
707 ccdc_cfg.bayer.buf_type = buf_type;
709 ccdc_cfg.ycbcr.buf_type = buf_type;
713 static enum ccdc_buftype ccdc_get_buftype(void)
715 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
716 return ccdc_cfg.bayer.buf_type;
717 return ccdc_cfg.ycbcr.buf_type;
720 static int ccdc_enum_pix(u32 *pix, int i)
723 if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
724 if (i < ARRAY_SIZE(ccdc_raw_bayer_pix_formats)) {
725 *pix = ccdc_raw_bayer_pix_formats[i];
729 if (i < ARRAY_SIZE(ccdc_raw_yuv_pix_formats)) {
730 *pix = ccdc_raw_yuv_pix_formats[i];
737 static int ccdc_set_pixel_format(u32 pixfmt)
739 if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
740 ccdc_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW;
741 if (pixfmt == V4L2_PIX_FMT_SBGGR8)
742 ccdc_cfg.bayer.config_params.alaw.enable = 1;
743 else if (pixfmt != V4L2_PIX_FMT_SBGGR16)
746 if (pixfmt == V4L2_PIX_FMT_YUYV)
747 ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_YCBYCR;
748 else if (pixfmt == V4L2_PIX_FMT_UYVY)
749 ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
756 static u32 ccdc_get_pixel_format(void)
758 struct ccdc_a_law *alaw = &ccdc_cfg.bayer.config_params.alaw;
761 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
763 pixfmt = V4L2_PIX_FMT_SBGGR8;
765 pixfmt = V4L2_PIX_FMT_SBGGR16;
767 if (ccdc_cfg.ycbcr.pix_order == CCDC_PIXORDER_YCBYCR)
768 pixfmt = V4L2_PIX_FMT_YUYV;
770 pixfmt = V4L2_PIX_FMT_UYVY;
775 static int ccdc_set_image_window(struct v4l2_rect *win)
777 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
778 ccdc_cfg.bayer.win = *win;
780 ccdc_cfg.ycbcr.win = *win;
784 static void ccdc_get_image_window(struct v4l2_rect *win)
786 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
787 *win = ccdc_cfg.bayer.win;
789 *win = ccdc_cfg.ycbcr.win;
792 static unsigned int ccdc_get_line_length(void)
794 struct ccdc_config_params_raw *config_params =
795 &ccdc_cfg.bayer.config_params;
798 if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
799 if ((config_params->alaw.enable) ||
800 (config_params->data_sz == CCDC_DATA_8BITS))
801 len = ccdc_cfg.bayer.win.width;
803 len = ccdc_cfg.bayer.win.width * 2;
805 len = ccdc_cfg.ycbcr.win.width * 2;
806 return ALIGN(len, 32);
809 static int ccdc_set_frame_format(enum ccdc_frmfmt frm_fmt)
811 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
812 ccdc_cfg.bayer.frm_fmt = frm_fmt;
814 ccdc_cfg.ycbcr.frm_fmt = frm_fmt;
818 static enum ccdc_frmfmt ccdc_get_frame_format(void)
820 if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
821 return ccdc_cfg.bayer.frm_fmt;
823 return ccdc_cfg.ycbcr.frm_fmt;
826 static int ccdc_getfid(void)
828 return (regr(CCDC_SYN_MODE) >> 15) & 1;
831 /* misc operations */
832 static inline void ccdc_setfbaddr(unsigned long addr)
834 regw(addr & 0xffffffe0, CCDC_SDR_ADDR);
837 static int ccdc_set_hw_if_params(struct vpfe_hw_if_param *params)
839 ccdc_cfg.if_type = params->if_type;
841 switch (params->if_type) {
843 case VPFE_YCBCR_SYNC_16:
844 case VPFE_YCBCR_SYNC_8:
845 case VPFE_BT656_10BIT:
846 ccdc_cfg.ycbcr.vd_pol = params->vdpol;
847 ccdc_cfg.ycbcr.hd_pol = params->hdpol;
850 /* TODO add support for raw bayer here */
856 static void ccdc_save_context(void)
858 ccdc_ctx[CCDC_PCR >> 2] = regr(CCDC_PCR);
859 ccdc_ctx[CCDC_SYN_MODE >> 2] = regr(CCDC_SYN_MODE);
860 ccdc_ctx[CCDC_HD_VD_WID >> 2] = regr(CCDC_HD_VD_WID);
861 ccdc_ctx[CCDC_PIX_LINES >> 2] = regr(CCDC_PIX_LINES);
862 ccdc_ctx[CCDC_HORZ_INFO >> 2] = regr(CCDC_HORZ_INFO);
863 ccdc_ctx[CCDC_VERT_START >> 2] = regr(CCDC_VERT_START);
864 ccdc_ctx[CCDC_VERT_LINES >> 2] = regr(CCDC_VERT_LINES);
865 ccdc_ctx[CCDC_CULLING >> 2] = regr(CCDC_CULLING);
866 ccdc_ctx[CCDC_HSIZE_OFF >> 2] = regr(CCDC_HSIZE_OFF);
867 ccdc_ctx[CCDC_SDOFST >> 2] = regr(CCDC_SDOFST);
868 ccdc_ctx[CCDC_SDR_ADDR >> 2] = regr(CCDC_SDR_ADDR);
869 ccdc_ctx[CCDC_CLAMP >> 2] = regr(CCDC_CLAMP);
870 ccdc_ctx[CCDC_DCSUB >> 2] = regr(CCDC_DCSUB);
871 ccdc_ctx[CCDC_COLPTN >> 2] = regr(CCDC_COLPTN);
872 ccdc_ctx[CCDC_BLKCMP >> 2] = regr(CCDC_BLKCMP);
873 ccdc_ctx[CCDC_FPC >> 2] = regr(CCDC_FPC);
874 ccdc_ctx[CCDC_FPC_ADDR >> 2] = regr(CCDC_FPC_ADDR);
875 ccdc_ctx[CCDC_VDINT >> 2] = regr(CCDC_VDINT);
876 ccdc_ctx[CCDC_ALAW >> 2] = regr(CCDC_ALAW);
877 ccdc_ctx[CCDC_REC656IF >> 2] = regr(CCDC_REC656IF);
878 ccdc_ctx[CCDC_CCDCFG >> 2] = regr(CCDC_CCDCFG);
879 ccdc_ctx[CCDC_FMTCFG >> 2] = regr(CCDC_FMTCFG);
880 ccdc_ctx[CCDC_FMT_HORZ >> 2] = regr(CCDC_FMT_HORZ);
881 ccdc_ctx[CCDC_FMT_VERT >> 2] = regr(CCDC_FMT_VERT);
882 ccdc_ctx[CCDC_FMT_ADDR0 >> 2] = regr(CCDC_FMT_ADDR0);
883 ccdc_ctx[CCDC_FMT_ADDR1 >> 2] = regr(CCDC_FMT_ADDR1);
884 ccdc_ctx[CCDC_FMT_ADDR2 >> 2] = regr(CCDC_FMT_ADDR2);
885 ccdc_ctx[CCDC_FMT_ADDR3 >> 2] = regr(CCDC_FMT_ADDR3);
886 ccdc_ctx[CCDC_FMT_ADDR4 >> 2] = regr(CCDC_FMT_ADDR4);
887 ccdc_ctx[CCDC_FMT_ADDR5 >> 2] = regr(CCDC_FMT_ADDR5);
888 ccdc_ctx[CCDC_FMT_ADDR6 >> 2] = regr(CCDC_FMT_ADDR6);
889 ccdc_ctx[CCDC_FMT_ADDR7 >> 2] = regr(CCDC_FMT_ADDR7);
890 ccdc_ctx[CCDC_PRGEVEN_0 >> 2] = regr(CCDC_PRGEVEN_0);
891 ccdc_ctx[CCDC_PRGEVEN_1 >> 2] = regr(CCDC_PRGEVEN_1);
892 ccdc_ctx[CCDC_PRGODD_0 >> 2] = regr(CCDC_PRGODD_0);
893 ccdc_ctx[CCDC_PRGODD_1 >> 2] = regr(CCDC_PRGODD_1);
894 ccdc_ctx[CCDC_VP_OUT >> 2] = regr(CCDC_VP_OUT);
897 static void ccdc_restore_context(void)
899 regw(ccdc_ctx[CCDC_SYN_MODE >> 2], CCDC_SYN_MODE);
900 regw(ccdc_ctx[CCDC_HD_VD_WID >> 2], CCDC_HD_VD_WID);
901 regw(ccdc_ctx[CCDC_PIX_LINES >> 2], CCDC_PIX_LINES);
902 regw(ccdc_ctx[CCDC_HORZ_INFO >> 2], CCDC_HORZ_INFO);
903 regw(ccdc_ctx[CCDC_VERT_START >> 2], CCDC_VERT_START);
904 regw(ccdc_ctx[CCDC_VERT_LINES >> 2], CCDC_VERT_LINES);
905 regw(ccdc_ctx[CCDC_CULLING >> 2], CCDC_CULLING);
906 regw(ccdc_ctx[CCDC_HSIZE_OFF >> 2], CCDC_HSIZE_OFF);
907 regw(ccdc_ctx[CCDC_SDOFST >> 2], CCDC_SDOFST);
908 regw(ccdc_ctx[CCDC_SDR_ADDR >> 2], CCDC_SDR_ADDR);
909 regw(ccdc_ctx[CCDC_CLAMP >> 2], CCDC_CLAMP);
910 regw(ccdc_ctx[CCDC_DCSUB >> 2], CCDC_DCSUB);
911 regw(ccdc_ctx[CCDC_COLPTN >> 2], CCDC_COLPTN);
912 regw(ccdc_ctx[CCDC_BLKCMP >> 2], CCDC_BLKCMP);
913 regw(ccdc_ctx[CCDC_FPC >> 2], CCDC_FPC);
914 regw(ccdc_ctx[CCDC_FPC_ADDR >> 2], CCDC_FPC_ADDR);
915 regw(ccdc_ctx[CCDC_VDINT >> 2], CCDC_VDINT);
916 regw(ccdc_ctx[CCDC_ALAW >> 2], CCDC_ALAW);
917 regw(ccdc_ctx[CCDC_REC656IF >> 2], CCDC_REC656IF);
918 regw(ccdc_ctx[CCDC_CCDCFG >> 2], CCDC_CCDCFG);
919 regw(ccdc_ctx[CCDC_FMTCFG >> 2], CCDC_FMTCFG);
920 regw(ccdc_ctx[CCDC_FMT_HORZ >> 2], CCDC_FMT_HORZ);
921 regw(ccdc_ctx[CCDC_FMT_VERT >> 2], CCDC_FMT_VERT);
922 regw(ccdc_ctx[CCDC_FMT_ADDR0 >> 2], CCDC_FMT_ADDR0);
923 regw(ccdc_ctx[CCDC_FMT_ADDR1 >> 2], CCDC_FMT_ADDR1);
924 regw(ccdc_ctx[CCDC_FMT_ADDR2 >> 2], CCDC_FMT_ADDR2);
925 regw(ccdc_ctx[CCDC_FMT_ADDR3 >> 2], CCDC_FMT_ADDR3);
926 regw(ccdc_ctx[CCDC_FMT_ADDR4 >> 2], CCDC_FMT_ADDR4);
927 regw(ccdc_ctx[CCDC_FMT_ADDR5 >> 2], CCDC_FMT_ADDR5);
928 regw(ccdc_ctx[CCDC_FMT_ADDR6 >> 2], CCDC_FMT_ADDR6);
929 regw(ccdc_ctx[CCDC_FMT_ADDR7 >> 2], CCDC_FMT_ADDR7);
930 regw(ccdc_ctx[CCDC_PRGEVEN_0 >> 2], CCDC_PRGEVEN_0);
931 regw(ccdc_ctx[CCDC_PRGEVEN_1 >> 2], CCDC_PRGEVEN_1);
932 regw(ccdc_ctx[CCDC_PRGODD_0 >> 2], CCDC_PRGODD_0);
933 regw(ccdc_ctx[CCDC_PRGODD_1 >> 2], CCDC_PRGODD_1);
934 regw(ccdc_ctx[CCDC_VP_OUT >> 2], CCDC_VP_OUT);
935 regw(ccdc_ctx[CCDC_PCR >> 2], CCDC_PCR);
937 static struct ccdc_hw_device ccdc_hw_dev = {
938 .name = "DM6446 CCDC",
939 .owner = THIS_MODULE,
943 .reset = ccdc_sbl_reset,
944 .enable = ccdc_enable,
945 .set_hw_if_params = ccdc_set_hw_if_params,
946 .set_params = ccdc_set_params,
947 .configure = ccdc_configure,
948 .set_buftype = ccdc_set_buftype,
949 .get_buftype = ccdc_get_buftype,
950 .enum_pix = ccdc_enum_pix,
951 .set_pixel_format = ccdc_set_pixel_format,
952 .get_pixel_format = ccdc_get_pixel_format,
953 .set_frame_format = ccdc_set_frame_format,
954 .get_frame_format = ccdc_get_frame_format,
955 .set_image_window = ccdc_set_image_window,
956 .get_image_window = ccdc_get_image_window,
957 .get_line_length = ccdc_get_line_length,
958 .setfbaddr = ccdc_setfbaddr,
959 .getfid = ccdc_getfid,
963 static int dm644x_ccdc_probe(struct platform_device *pdev)
965 struct resource *res;
969 * first try to register with vpfe. If not correct platform, then we
970 * don't have to iomap
972 status = vpfe_register_ccdc_device(&ccdc_hw_dev);
976 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
982 res = request_mem_region(res->start, resource_size(res), res->name);
988 ccdc_cfg.base_addr = ioremap_nocache(res->start, resource_size(res));
989 if (!ccdc_cfg.base_addr) {
994 /* Get and enable Master clock */
995 ccdc_cfg.mclk = clk_get(&pdev->dev, "master");
996 if (IS_ERR(ccdc_cfg.mclk)) {
997 status = PTR_ERR(ccdc_cfg.mclk);
1000 if (clk_prepare_enable(ccdc_cfg.mclk)) {
1005 /* Get and enable Slave clock */
1006 ccdc_cfg.sclk = clk_get(&pdev->dev, "slave");
1007 if (IS_ERR(ccdc_cfg.sclk)) {
1008 status = PTR_ERR(ccdc_cfg.sclk);
1011 if (clk_prepare_enable(ccdc_cfg.sclk)) {
1015 ccdc_cfg.dev = &pdev->dev;
1016 printk(KERN_NOTICE "%s is registered with vpfe.\n", ccdc_hw_dev.name);
1019 clk_disable_unprepare(ccdc_cfg.sclk);
1020 clk_put(ccdc_cfg.sclk);
1022 clk_disable_unprepare(ccdc_cfg.mclk);
1023 clk_put(ccdc_cfg.mclk);
1025 iounmap(ccdc_cfg.base_addr);
1027 release_mem_region(res->start, resource_size(res));
1029 vpfe_unregister_ccdc_device(&ccdc_hw_dev);
1033 static int dm644x_ccdc_remove(struct platform_device *pdev)
1035 struct resource *res;
1037 clk_disable_unprepare(ccdc_cfg.mclk);
1038 clk_disable_unprepare(ccdc_cfg.sclk);
1039 clk_put(ccdc_cfg.mclk);
1040 clk_put(ccdc_cfg.sclk);
1041 iounmap(ccdc_cfg.base_addr);
1042 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1044 release_mem_region(res->start, resource_size(res));
1045 vpfe_unregister_ccdc_device(&ccdc_hw_dev);
1049 static int dm644x_ccdc_suspend(struct device *dev)
1051 /* Save CCDC context */
1052 ccdc_save_context();
1055 /* Disable both master and slave clock */
1056 clk_disable_unprepare(ccdc_cfg.mclk);
1057 clk_disable_unprepare(ccdc_cfg.sclk);
1062 static int dm644x_ccdc_resume(struct device *dev)
1064 /* Enable both master and slave clock */
1065 clk_prepare_enable(ccdc_cfg.mclk);
1066 clk_prepare_enable(ccdc_cfg.sclk);
1067 /* Restore CCDC context */
1068 ccdc_restore_context();
1073 static const struct dev_pm_ops dm644x_ccdc_pm_ops = {
1074 .suspend = dm644x_ccdc_suspend,
1075 .resume = dm644x_ccdc_resume,
1078 static struct platform_driver dm644x_ccdc_driver = {
1080 .name = "dm644x_ccdc",
1081 .owner = THIS_MODULE,
1082 .pm = &dm644x_ccdc_pm_ops,
1084 .remove = dm644x_ccdc_remove,
1085 .probe = dm644x_ccdc_probe,
1088 module_platform_driver(dm644x_ccdc_driver);