Pileus Git - ~andy/linux/blob - drivers/media/platform/coda.c

   1 /*
   2  * Coda multi-standard codec IP
   3  *
   4  * Copyright (C) 2012 Vista Silicon S.L.
   5  *    Javier Martin, <javier.martin@vista-silicon.com>
   6  *    Xavier Duret
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/firmware.h>
  17 #include <linux/genalloc.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/io.h>
  20 #include <linux/irq.h>
  21 #include <linux/kfifo.h>
  22 #include <linux/module.h>
  23 #include <linux/of_device.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26 #include <linux/videodev2.h>
  27 #include <linux/of.h>
  28 #include <linux/platform_data/coda.h>
  29
  30 #include <media/v4l2-ctrls.h>
  31 #include <media/v4l2-device.h>
  32 #include <media/v4l2-ioctl.h>
  33 #include <media/v4l2-mem2mem.h>
  34 #include <media/videobuf2-core.h>
  35 #include <media/videobuf2-dma-contig.h>
  36
  37 #include "coda.h"
  38
  39 #define CODA_NAME               "coda"
  40
  41 #define CODA_MAX_INSTANCES      4
  42
  43 #define CODA_FMO_BUF_SIZE       32
  44 #define CODADX6_WORK_BUF_SIZE   (288 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
  45 #define CODA7_WORK_BUF_SIZE     (128 * 1024)
  46 #define CODA7_TEMP_BUF_SIZE     (304 * 1024)
  47 #define CODA_PARA_BUF_SIZE      (10 * 1024)
  48 #define CODA_ISRAM_SIZE (2048 * 2)
  49 #define CODADX6_IRAM_SIZE       0xb000
  50 #define CODA7_IRAM_SIZE         0x14000 /* 81920 bytes */
  51
  52 #define CODA_MAX_FRAMEBUFFERS   2
  53
  54 #define MAX_W           8192
  55 #define MAX_H           8192
  56 #define CODA_MAX_FRAME_SIZE     0x100000
  57 #define FMO_SLICE_SAVE_BUF_SIZE         (32)
  58 #define CODA_DEFAULT_GAMMA              4096
  59
  60 #define MIN_W 176
  61 #define MIN_H 144
  62
  63 #define S_ALIGN         1 /* multiple of 2 */
  64 #define W_ALIGN         1 /* multiple of 2 */
  65 #define H_ALIGN         1 /* multiple of 2 */
  66
  67 #define fh_to_ctx(__fh) container_of(__fh, struct coda_ctx, fh)
  68
  69 static int coda_debug;
  70 module_param(coda_debug, int, 0644);
  71 MODULE_PARM_DESC(coda_debug, "Debug level (0-1)");
  72
  73 enum {
  74         V4L2_M2M_SRC = 0,
  75         V4L2_M2M_DST = 1,
  76 };
  77
  78 enum coda_inst_type {
  79         CODA_INST_ENCODER,
  80         CODA_INST_DECODER,
  81 };
  82
  83 enum coda_product {
  84         CODA_DX6 = 0xf001,
  85         CODA_7541 = 0xf012,
  86 };
  87
  88 struct coda_fmt {
  89         char *name;
  90         u32 fourcc;
  91 };
  92
  93 struct coda_codec {
  94         u32 mode;
  95         u32 src_fourcc;
  96         u32 dst_fourcc;
  97         u32 max_w;
  98         u32 max_h;
  99 };
 100
 101 struct coda_devtype {
 102         char                    *firmware;
 103         enum coda_product       product;
 104         struct coda_codec       *codecs;
 105         unsigned int            num_codecs;
 106         size_t                  workbuf_size;
 107 };
 108
 109 /* Per-queue, driver-specific private data */
 110 struct coda_q_data {
 111         unsigned int            width;
 112         unsigned int            height;
 113         unsigned int            sizeimage;
 114         unsigned int            fourcc;
 115 };
 116
 117 struct coda_aux_buf {
 118         void                    *vaddr;
 119         dma_addr_t              paddr;
 120         u32                     size;
 121 };
 122
 123 struct coda_dev {
 124         struct v4l2_device      v4l2_dev;
 125         struct video_device     vfd;
 126         struct platform_device  *plat_dev;
 127         const struct coda_devtype *devtype;
 128
 129         void __iomem            *regs_base;
 130         struct clk              *clk_per;
 131         struct clk              *clk_ahb;
 132
 133         struct coda_aux_buf     codebuf;
 134         struct coda_aux_buf     tempbuf;
 135         struct coda_aux_buf     workbuf;
 136         struct gen_pool         *iram_pool;
 137         long unsigned int       iram_vaddr;
 138         long unsigned int       iram_paddr;
 139         unsigned long           iram_size;
 140
 141         spinlock_t              irqlock;
 142         struct mutex            dev_mutex;
 143         struct mutex            coda_mutex;
 144         struct v4l2_m2m_dev     *m2m_dev;
 145         struct vb2_alloc_ctx    *alloc_ctx;
 146         struct list_head        instances;
 147         unsigned long           instance_mask;
 148         struct delayed_work     timeout;
 149 };
 150
 151 struct coda_params {
 152         u8                      rot_mode;
 153         u8                      h264_intra_qp;
 154         u8                      h264_inter_qp;
 155         u8                      mpeg4_intra_qp;
 156         u8                      mpeg4_inter_qp;
 157         u8                      gop_size;
 158         int                     codec_mode;
 159         int                     codec_mode_aux;
 160         enum v4l2_mpeg_video_multi_slice_mode slice_mode;
 161         u32                     framerate;
 162         u16                     bitrate;
 163         u32                     slice_max_bits;
 164         u32                     slice_max_mb;
 165 };
 166
 167 struct coda_iram_info {
 168         u32             axi_sram_use;
 169         phys_addr_t     buf_bit_use;
 170         phys_addr_t     buf_ip_ac_dc_use;
 171         phys_addr_t     buf_dbk_y_use;
 172         phys_addr_t     buf_dbk_c_use;
 173         phys_addr_t     buf_ovl_use;
 174         phys_addr_t     buf_btp_use;
 175         phys_addr_t     search_ram_paddr;
 176         int             search_ram_size;
 177 };
 178
 179 struct coda_ctx {
 180         struct coda_dev                 *dev;
 181         struct list_head                list;
 182         int                             aborting;
 183         int                             streamon_out;
 184         int                             streamon_cap;
 185         u32                             isequence;
 186         u32                             qsequence;
 187         struct coda_q_data              q_data[2];
 188         enum coda_inst_type             inst_type;
 189         struct coda_codec               *codec;
 190         enum v4l2_colorspace            colorspace;
 191         struct coda_params              params;
 192         struct v4l2_m2m_ctx             *m2m_ctx;
 193         struct v4l2_ctrl_handler        ctrls;
 194         struct v4l2_fh                  fh;
 195         int                             gopcounter;
 196         char                            vpu_header[3][64];
 197         int                             vpu_header_size[3];
 198         struct kfifo                    bitstream_fifo;
 199         struct mutex                    bitstream_mutex;
 200         struct coda_aux_buf             bitstream;
 201         struct coda_aux_buf             parabuf;
 202         struct coda_aux_buf             internal_frames[CODA_MAX_FRAMEBUFFERS];
 203         struct coda_aux_buf             workbuf;
 204         int                             num_internal_frames;
 205         int                             idx;
 206         int                             reg_idx;
 207         struct coda_iram_info           iram_info;
 208         u32                             bit_stream_param;
 209 };
 210
 211 static const u8 coda_filler_nal[14] = { 0x00, 0x00, 0x00, 0x01, 0x0c, 0xff,
 212                         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x80 };
 213 static const u8 coda_filler_size[8] = { 0, 7, 14, 13, 12, 11, 10, 9 };
 214
 215 static inline void coda_write(struct coda_dev *dev, u32 data, u32 reg)
 216 {
 217         v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
 218                  "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
 219         writel(data, dev->regs_base + reg);
 220 }
 221
 222 static inline unsigned int coda_read(struct coda_dev *dev, u32 reg)
 223 {
 224         u32 data;
 225         data = readl(dev->regs_base + reg);
 226         v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
 227                  "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
 228         return data;
 229 }
 230
 231 static inline unsigned long coda_isbusy(struct coda_dev *dev)
 232 {
 233         return coda_read(dev, CODA_REG_BIT_BUSY);
 234 }
 235
 236 static inline int coda_is_initialized(struct coda_dev *dev)
 237 {
 238         return (coda_read(dev, CODA_REG_BIT_CUR_PC) != 0);
 239 }
 240
 241 static int coda_wait_timeout(struct coda_dev *dev)
 242 {
 243         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 244
 245         while (coda_isbusy(dev)) {
 246                 if (time_after(jiffies, timeout))
 247                         return -ETIMEDOUT;
 248         }
 249         return 0;
 250 }
 251
 252 static void coda_command_async(struct coda_ctx *ctx, int cmd)
 253 {
 254         struct coda_dev *dev = ctx->dev;
 255
 256         if (dev->devtype->product == CODA_7541) {
 257                 /* Restore context related registers to CODA */
 258                 coda_write(dev, ctx->bit_stream_param,
 259                                 CODA_REG_BIT_BIT_STREAM_PARAM);
 260                 coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
 261         }
 262
 263         coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
 264
 265         coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
 266         coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
 267         coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
 268
 269         coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
 270 }
 271
 272 static int coda_command_sync(struct coda_ctx *ctx, int cmd)
 273 {
 274         struct coda_dev *dev = ctx->dev;
 275
 276         coda_command_async(ctx, cmd);
 277         return coda_wait_timeout(dev);
 278 }
 279
 280 static struct coda_q_data *get_q_data(struct coda_ctx *ctx,
 281                                          enum v4l2_buf_type type)
 282 {
 283         switch (type) {
 284         case V4L2_BUF_TYPE_VIDEO_OUTPUT:
 285                 return &(ctx->q_data[V4L2_M2M_SRC]);
 286         case V4L2_BUF_TYPE_VIDEO_CAPTURE:
 287                 return &(ctx->q_data[V4L2_M2M_DST]);
 288         default:
 289                 BUG();
 290         }
 291         return NULL;
 292 }
 293
 294 /*
 295  * Array of all formats supported by any version of Coda:
 296  */
 297 static struct coda_fmt coda_formats[] = {
 298         {
 299                 .name = "YUV 4:2:0 Planar, YCbCr",
 300                 .fourcc = V4L2_PIX_FMT_YUV420,
 301         },
 302         {
 303                 .name = "YUV 4:2:0 Planar, YCrCb",
 304                 .fourcc = V4L2_PIX_FMT_YVU420,
 305         },
 306         {
 307                 .name = "H264 Encoded Stream",
 308                 .fourcc = V4L2_PIX_FMT_H264,
 309         },
 310         {
 311                 .name = "MPEG4 Encoded Stream",
 312                 .fourcc = V4L2_PIX_FMT_MPEG4,
 313         },
 314 };
 315
 316 #define CODA_CODEC(mode, src_fourcc, dst_fourcc, max_w, max_h) \
 317         { mode, src_fourcc, dst_fourcc, max_w, max_h }
 318
 319 /*
 320  * Arrays of codecs supported by each given version of Coda:
 321  *  i.MX27 -> codadx6
 322  *  i.MX5x -> coda7
 323  *  i.MX6  -> coda960
 324  * Use V4L2_PIX_FMT_YUV420 as placeholder for all supported YUV 4:2:0 variants
 325  */
 326 static struct coda_codec codadx6_codecs[] = {
 327         CODA_CODEC(CODADX6_MODE_ENCODE_H264, V4L2_PIX_FMT_YUV420, V4L2_PIX_FMT_H264,  720, 576),
 328         CODA_CODEC(CODADX6_MODE_ENCODE_MP4,  V4L2_PIX_FMT_YUV420, V4L2_PIX_FMT_MPEG4, 720, 576),
 329 };
 330
 331 static struct coda_codec coda7_codecs[] = {
 332         CODA_CODEC(CODA7_MODE_ENCODE_H264, V4L2_PIX_FMT_YUV420, V4L2_PIX_FMT_H264,   1280, 720),
 333         CODA_CODEC(CODA7_MODE_ENCODE_MP4,  V4L2_PIX_FMT_YUV420, V4L2_PIX_FMT_MPEG4,  1280, 720),
 334 };
 335
 336 static bool coda_format_is_yuv(u32 fourcc)
 337 {
 338         switch (fourcc) {
 339         case V4L2_PIX_FMT_YUV420:
 340         case V4L2_PIX_FMT_YVU420:
 341                 return true;
 342         default:
 343                 return false;
 344         }
 345 }
 346
 347 /*
 348  * Normalize all supported YUV 4:2:0 formats to the value used in the codec
 349  * tables.
 350  */
 351 static u32 coda_format_normalize_yuv(u32 fourcc)
 352 {
 353         return coda_format_is_yuv(fourcc) ? V4L2_PIX_FMT_YUV420 : fourcc;
 354 }
 355
 356 static struct coda_codec *coda_find_codec(struct coda_dev *dev, int src_fourcc,
 357                                           int dst_fourcc)
 358 {
 359         struct coda_codec *codecs = dev->devtype->codecs;
 360         int num_codecs = dev->devtype->num_codecs;
 361         int k;
 362
 363         src_fourcc = coda_format_normalize_yuv(src_fourcc);
 364         dst_fourcc = coda_format_normalize_yuv(dst_fourcc);
 365         if (src_fourcc == dst_fourcc)
 366                 return NULL;
 367
 368         for (k = 0; k < num_codecs; k++) {
 369                 if (codecs[k].src_fourcc == src_fourcc &&
 370                     codecs[k].dst_fourcc == dst_fourcc)
 371                         break;
 372         }
 373
 374         if (k == num_codecs)
 375                 return NULL;
 376
 377         return &codecs[k];
 378 }
 379
 380 /*
 381  * V4L2 ioctl() operations.
 382  */
 383 static int vidioc_querycap(struct file *file, void *priv,
 384                            struct v4l2_capability *cap)
 385 {
 386         strlcpy(cap->driver, CODA_NAME, sizeof(cap->driver));
 387         strlcpy(cap->card, CODA_NAME, sizeof(cap->card));
 388         strlcpy(cap->bus_info, "platform:" CODA_NAME, sizeof(cap->bus_info));
 389         /*
 390          * This is only a mem-to-mem video device. The capture and output
 391          * device capability flags are left only for backward compatibility
 392          * and are scheduled for removal.
 393          */
 394         cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
 395                            V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
 396         cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
 397
 398         return 0;
 399 }
 400
 401 static int enum_fmt(void *priv, struct v4l2_fmtdesc *f,
 402                         enum v4l2_buf_type type)
 403 {
 404         struct coda_ctx *ctx = fh_to_ctx(priv);
 405         struct coda_codec *codecs = ctx->dev->devtype->codecs;
 406         struct coda_fmt *formats = coda_formats;
 407         struct coda_fmt *fmt;
 408         int num_codecs = ctx->dev->devtype->num_codecs;
 409         int num_formats = ARRAY_SIZE(coda_formats);
 410         int i, k, num = 0;
 411
 412         for (i = 0; i < num_formats; i++) {
 413                 /* Both uncompressed formats are always supported */
 414                 if (coda_format_is_yuv(formats[i].fourcc)) {
 415                         if (num == f->index)
 416                                 break;
 417                         ++num;
 418                         continue;
 419                 }
 420                 /* Compressed formats may be supported, check the codec list */
 421                 for (k = 0; k < num_codecs; k++) {
 422                         if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE &&
 423                             formats[i].fourcc == codecs[k].dst_fourcc)
 424                                 break;
 425                         if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT &&
 426                             formats[i].fourcc == codecs[k].src_fourcc)
 427                                 break;
 428                 }
 429                 if (k < num_codecs) {
 430                         if (num == f->index)
 431                                 break;
 432                         ++num;
 433                 }
 434         }
 435
 436         if (i < num_formats) {
 437                 fmt = &formats[i];
 438                 strlcpy(f->description, fmt->name, sizeof(f->description));
 439                 f->pixelformat = fmt->fourcc;
 440                 return 0;
 441         }
 442
 443         /* Format not found */
 444         return -EINVAL;
 445 }
 446
 447 static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
 448                                    struct v4l2_fmtdesc *f)
 449 {
 450         return enum_fmt(priv, f, V4L2_BUF_TYPE_VIDEO_CAPTURE);
 451 }
 452
 453 static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
 454                                    struct v4l2_fmtdesc *f)
 455 {
 456         return enum_fmt(priv, f, V4L2_BUF_TYPE_VIDEO_OUTPUT);
 457 }
 458
 459 static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
 460 {
 461         struct vb2_queue *vq;
 462         struct coda_q_data *q_data;
 463         struct coda_ctx *ctx = fh_to_ctx(priv);
 464
 465         vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
 466         if (!vq)
 467                 return -EINVAL;
 468
 469         q_data = get_q_data(ctx, f->type);
 470
 471         f->fmt.pix.field        = V4L2_FIELD_NONE;
 472         f->fmt.pix.pixelformat  = q_data->fourcc;
 473         f->fmt.pix.width        = q_data->width;
 474         f->fmt.pix.height       = q_data->height;
 475         if (coda_format_is_yuv(f->fmt.pix.pixelformat))
 476                 f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
 477         else /* encoded formats h.264/mpeg4 */
 478                 f->fmt.pix.bytesperline = 0;
 479
 480         f->fmt.pix.sizeimage    = q_data->sizeimage;
 481         f->fmt.pix.colorspace   = ctx->colorspace;
 482
 483         return 0;
 484 }
 485
 486 static int vidioc_try_fmt(struct coda_codec *codec, struct v4l2_format *f)
 487 {
 488         unsigned int max_w, max_h;
 489         enum v4l2_field field;
 490
 491         field = f->fmt.pix.field;
 492         if (field == V4L2_FIELD_ANY)
 493                 field = V4L2_FIELD_NONE;
 494         else if (V4L2_FIELD_NONE != field)
 495                 return -EINVAL;
 496
 497         /* V4L2 specification suggests the driver corrects the format struct
 498          * if any of the dimensions is unsupported */
 499         f->fmt.pix.field = field;
 500
 501         if (codec) {
 502                 max_w = codec->max_w;
 503                 max_h = codec->max_h;
 504         } else {
 505                 max_w = MAX_W;
 506                 max_h = MAX_H;
 507         }
 508         v4l_bound_align_image(&f->fmt.pix.width, MIN_W, max_w,
 509                               W_ALIGN, &f->fmt.pix.height,
 510                               MIN_H, max_h, H_ALIGN, S_ALIGN);
 511
 512         if (coda_format_is_yuv(f->fmt.pix.pixelformat)) {
 513                 /* Frame stride must be multiple of 8 */
 514                 f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 8);
 515                 f->fmt.pix.sizeimage = f->fmt.pix.bytesperline *
 516                                         f->fmt.pix.height * 3 / 2;
 517         } else { /*encoded formats h.264/mpeg4 */
 518                 f->fmt.pix.bytesperline = 0;
 519                 f->fmt.pix.sizeimage = CODA_MAX_FRAME_SIZE;
 520         }
 521
 522         return 0;
 523 }
 524
 525 static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
 526                                   struct v4l2_format *f)
 527 {
 528         struct coda_ctx *ctx = fh_to_ctx(priv);
 529         struct coda_codec *codec = NULL;
 530
 531         /* Determine codec by the encoded format */
 532         codec = coda_find_codec(ctx->dev, V4L2_PIX_FMT_YUV420,
 533                                 f->fmt.pix.pixelformat);
 534
 535         f->fmt.pix.colorspace = ctx->colorspace;
 536
 537         return vidioc_try_fmt(codec, f);
 538 }
 539
 540 static int vidioc_try_fmt_vid_out(struct file *file, void *priv,
 541                                   struct v4l2_format *f)
 542 {
 543         struct coda_ctx *ctx = fh_to_ctx(priv);
 544         struct coda_codec *codec;
 545
 546         /* Determine codec by encoded format, returns NULL if raw or invalid */
 547         codec = coda_find_codec(ctx->dev, f->fmt.pix.pixelformat,
 548                                 V4L2_PIX_FMT_YUV420);
 549
 550         if (!f->fmt.pix.colorspace)
 551                 f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
 552
 553         return vidioc_try_fmt(codec, f);
 554 }
 555
 556 static int vidioc_s_fmt(struct coda_ctx *ctx, struct v4l2_format *f)
 557 {
 558         struct coda_q_data *q_data;
 559         struct vb2_queue *vq;
 560
 561         vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
 562         if (!vq)
 563                 return -EINVAL;
 564
 565         q_data = get_q_data(ctx, f->type);
 566         if (!q_data)
 567                 return -EINVAL;
 568
 569         if (vb2_is_busy(vq)) {
 570                 v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
 571                 return -EBUSY;
 572         }
 573
 574         q_data->fourcc = f->fmt.pix.pixelformat;
 575         q_data->width = f->fmt.pix.width;
 576         q_data->height = f->fmt.pix.height;
 577         q_data->sizeimage = f->fmt.pix.sizeimage;
 578
 579         v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
 580                 "Setting format for type %d, wxh: %dx%d, fmt: %d\n",
 581                 f->type, q_data->width, q_data->height, q_data->fourcc);
 582
 583         return 0;
 584 }
 585
 586 static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
 587                                 struct v4l2_format *f)
 588 {
 589         struct coda_ctx *ctx = fh_to_ctx(priv);
 590         int ret;
 591
 592         ret = vidioc_try_fmt_vid_cap(file, priv, f);
 593         if (ret)
 594                 return ret;
 595
 596         return vidioc_s_fmt(ctx, f);
 597 }
 598
 599 static int vidioc_s_fmt_vid_out(struct file *file, void *priv,
 600                                 struct v4l2_format *f)
 601 {
 602         struct coda_ctx *ctx = fh_to_ctx(priv);
 603         int ret;
 604
 605         ret = vidioc_try_fmt_vid_out(file, priv, f);
 606         if (ret)
 607                 return ret;
 608
 609         ret = vidioc_s_fmt(ctx, f);
 610         if (ret)
 611                 ctx->colorspace = f->fmt.pix.colorspace;
 612
 613         return ret;
 614 }
 615
 616 static int vidioc_reqbufs(struct file *file, void *priv,
 617                           struct v4l2_requestbuffers *reqbufs)
 618 {
 619         struct coda_ctx *ctx = fh_to_ctx(priv);
 620
 621         return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
 622 }
 623
 624 static int vidioc_querybuf(struct file *file, void *priv,
 625                            struct v4l2_buffer *buf)
 626 {
 627         struct coda_ctx *ctx = fh_to_ctx(priv);
 628
 629         return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
 630 }
 631
 632 static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
 633 {
 634         struct coda_ctx *ctx = fh_to_ctx(priv);
 635
 636         return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
 637 }
 638
 639 static int vidioc_expbuf(struct file *file, void *priv,
 640                          struct v4l2_exportbuffer *eb)
 641 {
 642         struct coda_ctx *ctx = fh_to_ctx(priv);
 643
 644         return v4l2_m2m_expbuf(file, ctx->m2m_ctx, eb);
 645 }
 646
 647 static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
 648 {
 649         struct coda_ctx *ctx = fh_to_ctx(priv);
 650
 651         return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
 652 }
 653
 654 static int vidioc_create_bufs(struct file *file, void *priv,
 655                               struct v4l2_create_buffers *create)
 656 {
 657         struct coda_ctx *ctx = fh_to_ctx(priv);
 658
 659         return v4l2_m2m_create_bufs(file, ctx->m2m_ctx, create);
 660 }
 661
 662 static int vidioc_streamon(struct file *file, void *priv,
 663                            enum v4l2_buf_type type)
 664 {
 665         struct coda_ctx *ctx = fh_to_ctx(priv);
 666
 667         return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
 668 }
 669
 670 static int vidioc_streamoff(struct file *file, void *priv,
 671                             enum v4l2_buf_type type)
 672 {
 673         struct coda_ctx *ctx = fh_to_ctx(priv);
 674
 675         return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
 676 }
 677
 678 static const struct v4l2_ioctl_ops coda_ioctl_ops = {
 679         .vidioc_querycap        = vidioc_querycap,
 680
 681         .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
 682         .vidioc_g_fmt_vid_cap   = vidioc_g_fmt,
 683         .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
 684         .vidioc_s_fmt_vid_cap   = vidioc_s_fmt_vid_cap,
 685
 686         .vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
 687         .vidioc_g_fmt_vid_out   = vidioc_g_fmt,
 688         .vidioc_try_fmt_vid_out = vidioc_try_fmt_vid_out,
 689         .vidioc_s_fmt_vid_out   = vidioc_s_fmt_vid_out,
 690
 691         .vidioc_reqbufs         = vidioc_reqbufs,
 692         .vidioc_querybuf        = vidioc_querybuf,
 693
 694         .vidioc_qbuf            = vidioc_qbuf,
 695         .vidioc_expbuf          = vidioc_expbuf,
 696         .vidioc_dqbuf           = vidioc_dqbuf,
 697         .vidioc_create_bufs     = vidioc_create_bufs,
 698
 699         .vidioc_streamon        = vidioc_streamon,
 700         .vidioc_streamoff       = vidioc_streamoff,
 701 };
 702
 703 static inline int coda_get_bitstream_payload(struct coda_ctx *ctx)
 704 {
 705         return kfifo_len(&ctx->bitstream_fifo);
 706 }
 707
 708 static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
 709 {
 710         struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
 711         struct coda_dev *dev = ctx->dev;
 712         u32 rd_ptr;
 713
 714         rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
 715         kfifo->out = (kfifo->in & ~kfifo->mask) |
 716                       (rd_ptr - ctx->bitstream.paddr);
 717         if (kfifo->out > kfifo->in)
 718                 kfifo->out -= kfifo->mask + 1;
 719 }
 720
 721 static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
 722 {
 723         struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
 724         struct coda_dev *dev = ctx->dev;
 725         u32 rd_ptr, wr_ptr;
 726
 727         rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
 728         coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
 729         wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
 730         coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
 731 }
 732
 733 static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
 734 {
 735         struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
 736         struct coda_dev *dev = ctx->dev;
 737         u32 wr_ptr;
 738
 739         wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
 740         coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
 741 }
 742
 743 static int coda_bitstream_queue(struct coda_ctx *ctx, struct vb2_buffer *src_buf)
 744 {
 745         u32 src_size = vb2_get_plane_payload(src_buf, 0);
 746         u32 n;
 747
 748         n = kfifo_in(&ctx->bitstream_fifo, vb2_plane_vaddr(src_buf, 0), src_size);
 749         if (n < src_size)
 750                 return -ENOSPC;
 751
 752         dma_sync_single_for_device(&ctx->dev->plat_dev->dev, ctx->bitstream.paddr,
 753                                    ctx->bitstream.size, DMA_TO_DEVICE);
 754
 755         ctx->qsequence++;
 756
 757         return 0;
 758 }
 759
 760 static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
 761                                      struct vb2_buffer *src_buf)
 762 {
 763         int ret;
 764
 765         if (coda_get_bitstream_payload(ctx) +
 766             vb2_get_plane_payload(src_buf, 0) + 512 >= ctx->bitstream.size)
 767                 return false;
 768
 769         if (vb2_plane_vaddr(src_buf, 0) == NULL) {
 770                 v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
 771                 return true;
 772         }
 773
 774         ret = coda_bitstream_queue(ctx, src_buf);
 775         if (ret < 0) {
 776                 v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
 777                 return false;
 778         }
 779         /* Sync read pointer to device */
 780         if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
 781                 coda_kfifo_sync_to_device_write(ctx);
 782
 783         return true;
 784 }
 785
 786 static void coda_fill_bitstream(struct coda_ctx *ctx)
 787 {
 788         struct vb2_buffer *src_buf;
 789
 790         while (v4l2_m2m_num_src_bufs_ready(ctx->m2m_ctx) > 0) {
 791                 src_buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
 792
 793                 if (coda_bitstream_try_queue(ctx, src_buf)) {
 794                         src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
 795                         v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
 796                 } else {
 797                         break;
 798                 }
 799         }
 800 }
 801
 802 /*
 803  * Mem-to-mem operations.
 804  */
 805 static void coda_device_run(void *m2m_priv)
 806 {
 807         struct coda_ctx *ctx = m2m_priv;
 808         struct coda_q_data *q_data_src, *q_data_dst;
 809         struct vb2_buffer *src_buf, *dst_buf;
 810         struct coda_dev *dev = ctx->dev;
 811         int force_ipicture;
 812         int quant_param = 0;
 813         u32 picture_y, picture_cb, picture_cr;
 814         u32 pic_stream_buffer_addr, pic_stream_buffer_size;
 815         u32 dst_fourcc;
 816
 817         mutex_lock(&dev->coda_mutex);
 818
 819         src_buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
 820         dst_buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
 821         q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
 822         q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
 823         dst_fourcc = q_data_dst->fourcc;
 824
 825         src_buf->v4l2_buf.sequence = ctx->isequence;
 826         dst_buf->v4l2_buf.sequence = ctx->isequence;
 827         ctx->isequence++;
 828
 829         /*
 830          * Workaround coda firmware BUG that only marks the first
 831          * frame as IDR. This is a problem for some decoders that can't
 832          * recover when a frame is lost.
 833          */
 834         if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
 835                 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
 836                 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
 837         } else {
 838                 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
 839                 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
 840         }
 841
 842         /*
 843          * Copy headers at the beginning of the first frame for H.264 only.
 844          * In MPEG4 they are already copied by the coda.
 845          */
 846         if (src_buf->v4l2_buf.sequence == 0) {
 847                 pic_stream_buffer_addr =
 848                         vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
 849                         ctx->vpu_header_size[0] +
 850                         ctx->vpu_header_size[1] +
 851                         ctx->vpu_header_size[2];
 852                 pic_stream_buffer_size = CODA_MAX_FRAME_SIZE -
 853                         ctx->vpu_header_size[0] -
 854                         ctx->vpu_header_size[1] -
 855                         ctx->vpu_header_size[2];
 856                 memcpy(vb2_plane_vaddr(dst_buf, 0),
 857                        &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
 858                 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
 859                        &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
 860                 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
 861                         ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
 862                         ctx->vpu_header_size[2]);
 863         } else {
 864                 pic_stream_buffer_addr =
 865                         vb2_dma_contig_plane_dma_addr(dst_buf, 0);
 866                 pic_stream_buffer_size = CODA_MAX_FRAME_SIZE;
 867         }
 868
 869         if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
 870                 force_ipicture = 1;
 871                 switch (dst_fourcc) {
 872                 case V4L2_PIX_FMT_H264:
 873                         quant_param = ctx->params.h264_intra_qp;
 874                         break;
 875                 case V4L2_PIX_FMT_MPEG4:
 876                         quant_param = ctx->params.mpeg4_intra_qp;
 877                         break;
 878                 default:
 879                         v4l2_warn(&ctx->dev->v4l2_dev,
 880                                 "cannot set intra qp, fmt not supported\n");
 881                         break;
 882                 }
 883         } else {
 884                 force_ipicture = 0;
 885                 switch (dst_fourcc) {
 886                 case V4L2_PIX_FMT_H264:
 887                         quant_param = ctx->params.h264_inter_qp;
 888                         break;
 889                 case V4L2_PIX_FMT_MPEG4:
 890                         quant_param = ctx->params.mpeg4_inter_qp;
 891                         break;
 892                 default:
 893                         v4l2_warn(&ctx->dev->v4l2_dev,
 894                                 "cannot set inter qp, fmt not supported\n");
 895                         break;
 896                 }
 897         }
 898
 899         /* submit */
 900         coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
 901         coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
 902
 903
 904         picture_y = vb2_dma_contig_plane_dma_addr(src_buf, 0);
 905         switch (q_data_src->fourcc) {
 906         case V4L2_PIX_FMT_YVU420:
 907                 /* Switch Cb and Cr for YVU420 format */
 908                 picture_cr = picture_y + q_data_src->width * q_data_src->height;
 909                 picture_cb = picture_cr + q_data_src->width / 2 *
 910                                 q_data_src->height / 2;
 911                 break;
 912         case V4L2_PIX_FMT_YUV420:
 913         default:
 914                 picture_cb = picture_y + q_data_src->width * q_data_src->height;
 915                 picture_cr = picture_cb + q_data_src->width / 2 *
 916                                 q_data_src->height / 2;
 917                 break;
 918         }
 919
 920         coda_write(dev, picture_y, CODA_CMD_ENC_PIC_SRC_ADDR_Y);
 921         coda_write(dev, picture_cb, CODA_CMD_ENC_PIC_SRC_ADDR_CB);
 922         coda_write(dev, picture_cr, CODA_CMD_ENC_PIC_SRC_ADDR_CR);
 923         coda_write(dev, force_ipicture << 1 & 0x2,
 924                    CODA_CMD_ENC_PIC_OPTION);
 925
 926         coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
 927         coda_write(dev, pic_stream_buffer_size / 1024,
 928                    CODA_CMD_ENC_PIC_BB_SIZE);
 929
 930         if (dev->devtype->product == CODA_7541) {
 931                 coda_write(dev, CODA7_USE_BIT_ENABLE | CODA7_USE_HOST_BIT_ENABLE |
 932                                 CODA7_USE_ME_ENABLE | CODA7_USE_HOST_ME_ENABLE,
 933                                 CODA7_REG_BIT_AXI_SRAM_USE);
 934         }
 935
 936         if (dev->devtype->product != CODA_DX6)
 937                 coda_write(dev, ctx->iram_info.axi_sram_use,
 938                                 CODA7_REG_BIT_AXI_SRAM_USE);
 939
 940         /* 1 second timeout in case CODA locks up */
 941         schedule_delayed_work(&dev->timeout, HZ);
 942
 943         coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
 944 }
 945
 946 static int coda_job_ready(void *m2m_priv)
 947 {
 948         struct coda_ctx *ctx = m2m_priv;
 949
 950         /*
 951          * For both 'P' and 'key' frame cases 1 picture
 952          * and 1 frame are needed. In the decoder case,
 953          * the compressed frame can be in the bitstream.
 954          */
 955         if (!v4l2_m2m_num_src_bufs_ready(ctx->m2m_ctx) &&
 956             ctx->inst_type != CODA_INST_DECODER) {
 957                 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
 958                          "not ready: not enough video buffers.\n");
 959                 return 0;
 960         }
 961
 962         if (!v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx)) {
 963                 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
 964                          "not ready: not enough video capture buffers.\n");
 965                 return 0;
 966         }
 967
 968         if (ctx->aborting) {
 969                 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
 970                          "not ready: aborting\n");
 971                 return 0;
 972         }
 973
 974         v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
 975                         "job ready\n");
 976         return 1;
 977 }
 978
 979 static void coda_job_abort(void *priv)
 980 {
 981         struct coda_ctx *ctx = priv;
 982
 983         ctx->aborting = 1;
 984
 985         v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
 986                  "Aborting task\n");
 987 }
 988
 989 static void coda_lock(void *m2m_priv)
 990 {
 991         struct coda_ctx *ctx = m2m_priv;
 992         struct coda_dev *pcdev = ctx->dev;
 993         mutex_lock(&pcdev->dev_mutex);
 994 }
 995
 996 static void coda_unlock(void *m2m_priv)
 997 {
 998         struct coda_ctx *ctx = m2m_priv;
 999         struct coda_dev *pcdev = ctx->dev;
1000         mutex_unlock(&pcdev->dev_mutex);
1001 }
1002
1003 static struct v4l2_m2m_ops coda_m2m_ops = {
1004         .device_run     = coda_device_run,
1005         .job_ready      = coda_job_ready,
1006         .job_abort      = coda_job_abort,
1007         .lock           = coda_lock,
1008         .unlock         = coda_unlock,
1009 };
1010
1011 static void set_default_params(struct coda_ctx *ctx)
1012 {
1013         int max_w;
1014         int max_h;
1015
1016         ctx->codec = &ctx->dev->devtype->codecs[0];
1017         max_w = ctx->codec->max_w;
1018         max_h = ctx->codec->max_h;
1019
1020         ctx->params.codec_mode = CODA_MODE_INVALID;
1021         ctx->colorspace = V4L2_COLORSPACE_REC709;
1022         ctx->params.framerate = 30;
1023         ctx->aborting = 0;
1024
1025         /* Default formats for output and input queues */
1026         ctx->q_data[V4L2_M2M_SRC].fourcc = ctx->codec->src_fourcc;
1027         ctx->q_data[V4L2_M2M_DST].fourcc = ctx->codec->dst_fourcc;
1028         ctx->q_data[V4L2_M2M_SRC].width = max_w;
1029         ctx->q_data[V4L2_M2M_SRC].height = max_h;
1030         ctx->q_data[V4L2_M2M_SRC].sizeimage = (max_w * max_h * 3) / 2;
1031         ctx->q_data[V4L2_M2M_DST].width = max_w;
1032         ctx->q_data[V4L2_M2M_DST].height = max_h;
1033         ctx->q_data[V4L2_M2M_DST].sizeimage = CODA_MAX_FRAME_SIZE;
1034 }
1035
1036 /*
1037  * Queue operations
1038  */
1039 static int coda_queue_setup(struct vb2_queue *vq,
1040                                 const struct v4l2_format *fmt,
1041                                 unsigned int *nbuffers, unsigned int *nplanes,
1042                                 unsigned int sizes[], void *alloc_ctxs[])
1043 {
1044         struct coda_ctx *ctx = vb2_get_drv_priv(vq);
1045         struct coda_q_data *q_data;
1046         unsigned int size;
1047
1048         q_data = get_q_data(ctx, vq->type);
1049         size = q_data->sizeimage;
1050
1051         *nplanes = 1;
1052         sizes[0] = size;
1053
1054         alloc_ctxs[0] = ctx->dev->alloc_ctx;
1055
1056         v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1057                  "get %d buffer(s) of size %d each.\n", *nbuffers, size);
1058
1059         return 0;
1060 }
1061
1062 static int coda_buf_prepare(struct vb2_buffer *vb)
1063 {
1064         struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1065         struct coda_q_data *q_data;
1066
1067         q_data = get_q_data(ctx, vb->vb2_queue->type);
1068
1069         if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
1070                 v4l2_warn(&ctx->dev->v4l2_dev,
1071                           "%s data will not fit into plane (%lu < %lu)\n",
1072                           __func__, vb2_plane_size(vb, 0),
1073                           (long)q_data->sizeimage);
1074                 return -EINVAL;
1075         }
1076
1077         return 0;
1078 }
1079
1080 static void coda_buf_queue(struct vb2_buffer *vb)
1081 {
1082         struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1083         v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
1084 }
1085
1086 static void coda_wait_prepare(struct vb2_queue *q)
1087 {
1088         struct coda_ctx *ctx = vb2_get_drv_priv(q);
1089         coda_unlock(ctx);
1090 }
1091
1092 static void coda_wait_finish(struct vb2_queue *q)
1093 {
1094         struct coda_ctx *ctx = vb2_get_drv_priv(q);
1095         coda_lock(ctx);
1096 }
1097
1098 static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
1099 {
1100         struct coda_dev *dev = ctx->dev;
1101         u32 *p = ctx->parabuf.vaddr;
1102
1103         if (dev->devtype->product == CODA_DX6)
1104                 p[index] = value;
1105         else
1106                 p[index ^ 1] = value;
1107 }
1108
1109 static int coda_alloc_aux_buf(struct coda_dev *dev,
1110                               struct coda_aux_buf *buf, size_t size)
1111 {
1112         buf->vaddr = dma_alloc_coherent(&dev->plat_dev->dev, size, &buf->paddr,
1113                                         GFP_KERNEL);
1114         if (!buf->vaddr)
1115                 return -ENOMEM;
1116
1117         buf->size = size;
1118
1119         return 0;
1120 }
1121
1122 static inline int coda_alloc_context_buf(struct coda_ctx *ctx,
1123                                          struct coda_aux_buf *buf, size_t size)
1124 {
1125         return coda_alloc_aux_buf(ctx->dev, buf, size);
1126 }
1127
1128 static void coda_free_aux_buf(struct coda_dev *dev,
1129                               struct coda_aux_buf *buf)
1130 {
1131         if (buf->vaddr) {
1132                 dma_free_coherent(&dev->plat_dev->dev, buf->size,
1133                                   buf->vaddr, buf->paddr);
1134                 buf->vaddr = NULL;
1135                 buf->size = 0;
1136         }
1137 }
1138
1139 static void coda_free_framebuffers(struct coda_ctx *ctx)
1140 {
1141         int i;
1142
1143         for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
1144                 coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
1145 }
1146
1147 static int coda_alloc_framebuffers(struct coda_ctx *ctx, struct coda_q_data *q_data, u32 fourcc)
1148 {
1149         struct coda_dev *dev = ctx->dev;
1150         int height = q_data->height;
1151         dma_addr_t paddr;
1152         int ysize;
1153         int ret;
1154         int i;
1155
1156         if (ctx->codec && ctx->codec->src_fourcc == V4L2_PIX_FMT_H264)
1157                 height = round_up(height, 16);
1158         ysize = round_up(q_data->width, 8) * height;
1159
1160         /* Allocate frame buffers */
1161         for (i = 0; i < ctx->num_internal_frames; i++) {
1162                 size_t size;
1163
1164                 size = q_data->sizeimage;
1165                 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
1166                     dev->devtype->product != CODA_DX6)
1167                         ctx->internal_frames[i].size += ysize/4;
1168                 ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i], size);
1169                 if (ret < 0) {
1170                         coda_free_framebuffers(ctx);
1171                         return ret;
1172                 }
1173         }
1174
1175         /* Register frame buffers in the parameter buffer */
1176         for (i = 0; i < ctx->num_internal_frames; i++) {
1177                 paddr = ctx->internal_frames[i].paddr;
1178                 coda_parabuf_write(ctx, i * 3 + 0, paddr); /* Y */
1179                 coda_parabuf_write(ctx, i * 3 + 1, paddr + ysize); /* Cb */
1180                 coda_parabuf_write(ctx, i * 3 + 2, paddr + ysize + ysize/4); /* Cr */
1181
1182                 /* mvcol buffer for h.264 */
1183                 if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
1184                     dev->devtype->product != CODA_DX6)
1185                         coda_parabuf_write(ctx, 96 + i,
1186                                            ctx->internal_frames[i].paddr +
1187                                            ysize + ysize/4 + ysize/4);
1188         }
1189
1190         /* mvcol buffer for mpeg4 */
1191         if ((dev->devtype->product != CODA_DX6) &&
1192             (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4))
1193                 coda_parabuf_write(ctx, 97, ctx->internal_frames[i].paddr +
1194                                             ysize + ysize/4 + ysize/4);
1195
1196         return 0;
1197 }
1198
1199 static int coda_h264_padding(int size, char *p)
1200 {
1201         int nal_size;
1202         int diff;
1203
1204         diff = size - (size & ~0x7);
1205         if (diff == 0)
1206                 return 0;
1207
1208         nal_size = coda_filler_size[diff];
1209         memcpy(p, coda_filler_nal, nal_size);
1210
1211         /* Add rbsp stop bit and trailing at the end */
1212         *(p + nal_size - 1) = 0x80;
1213
1214         return nal_size;
1215 }
1216
1217 static void coda_setup_iram(struct coda_ctx *ctx)
1218 {
1219         struct coda_iram_info *iram_info = &ctx->iram_info;
1220         struct coda_dev *dev = ctx->dev;
1221         int ipacdc_size;
1222         int bitram_size;
1223         int dbk_size;
1224         int mb_width;
1225         int me_size;
1226         int size;
1227
1228         memset(iram_info, 0, sizeof(*iram_info));
1229         size = dev->iram_size;
1230
1231         if (dev->devtype->product == CODA_DX6)
1232                 return;
1233
1234         if (ctx->inst_type == CODA_INST_ENCODER) {
1235                 struct coda_q_data *q_data_src;
1236
1237                 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1238                 mb_width = DIV_ROUND_UP(q_data_src->width, 16);
1239
1240                 /* Prioritize in case IRAM is too small for everything */
1241                 me_size = round_up(round_up(q_data_src->width, 16) * 36 + 2048,
1242                                    1024);
1243                 iram_info->search_ram_size = me_size;
1244                 if (size >= iram_info->search_ram_size) {
1245                         if (dev->devtype->product == CODA_7541)
1246                                 iram_info->axi_sram_use |= CODA7_USE_HOST_ME_ENABLE;
1247                         iram_info->search_ram_paddr = dev->iram_paddr;
1248                         size -= iram_info->search_ram_size;
1249                 } else {
1250                         pr_err("IRAM is smaller than the search ram size\n");
1251                         goto out;
1252                 }
1253
1254                 /* Only H.264BP and H.263P3 are considered */
1255                 dbk_size = round_up(128 * mb_width, 1024);
1256                 if (size >= dbk_size) {
1257                         iram_info->axi_sram_use |= CODA7_USE_HOST_DBK_ENABLE;
1258                         iram_info->buf_dbk_y_use = dev->iram_paddr +
1259                                                    iram_info->search_ram_size;
1260                         iram_info->buf_dbk_c_use = iram_info->buf_dbk_y_use +
1261                                                    dbk_size / 2;
1262                         size -= dbk_size;
1263                 } else {
1264                         goto out;
1265                 }
1266
1267                 bitram_size = round_up(128 * mb_width, 1024);
1268                 if (size >= bitram_size) {
1269                         iram_info->axi_sram_use |= CODA7_USE_HOST_BIT_ENABLE;
1270                         iram_info->buf_bit_use = iram_info->buf_dbk_c_use +
1271                                                  dbk_size / 2;
1272                         size -= bitram_size;
1273                 } else {
1274                         goto out;
1275                 }
1276
1277                 ipacdc_size = round_up(128 * mb_width, 1024);
1278                 if (size >= ipacdc_size) {
1279                         iram_info->axi_sram_use |= CODA7_USE_HOST_IP_ENABLE;
1280                         iram_info->buf_ip_ac_dc_use = iram_info->buf_bit_use +
1281                                                       bitram_size;
1282                         size -= ipacdc_size;
1283                 }
1284
1285                 /* OVL disabled for encoder */
1286         }
1287
1288 out:
1289         switch (dev->devtype->product) {
1290         case CODA_DX6:
1291                 break;
1292         case CODA_7541:
1293                 /* i.MX53 uses secondary AXI for IRAM access */
1294                 if (iram_info->axi_sram_use & CODA7_USE_HOST_BIT_ENABLE)
1295                         iram_info->axi_sram_use |= CODA7_USE_BIT_ENABLE;
1296                 if (iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE)
1297                         iram_info->axi_sram_use |= CODA7_USE_IP_ENABLE;
1298                 if (iram_info->axi_sram_use & CODA7_USE_HOST_DBK_ENABLE)
1299                         iram_info->axi_sram_use |= CODA7_USE_DBK_ENABLE;
1300                 if (iram_info->axi_sram_use & CODA7_USE_HOST_OVL_ENABLE)
1301                         iram_info->axi_sram_use |= CODA7_USE_OVL_ENABLE;
1302                 if (iram_info->axi_sram_use & CODA7_USE_HOST_ME_ENABLE)
1303                         iram_info->axi_sram_use |= CODA7_USE_ME_ENABLE;
1304         }
1305
1306         if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
1307                 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1308                          "IRAM smaller than needed\n");
1309
1310         if (dev->devtype->product == CODA_7541) {
1311                 /* TODO - Enabling these causes picture errors on CODA7541 */
1312                 if (ctx->inst_type == CODA_INST_ENCODER) {
1313                         iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
1314                                                      CODA7_USE_HOST_DBK_ENABLE |
1315                                                      CODA7_USE_IP_ENABLE |
1316                                                      CODA7_USE_DBK_ENABLE);
1317                 }
1318         }
1319 }
1320
1321 static void coda_free_context_buffers(struct coda_ctx *ctx)
1322 {
1323         struct coda_dev *dev = ctx->dev;
1324
1325         if (dev->devtype->product != CODA_DX6)
1326                 coda_free_aux_buf(dev, &ctx->workbuf);
1327 }
1328
1329 static int coda_alloc_context_buffers(struct coda_ctx *ctx,
1330                                       struct coda_q_data *q_data)
1331 {
1332         struct coda_dev *dev = ctx->dev;
1333         size_t size;
1334         int ret;
1335
1336         switch (dev->devtype->product) {
1337         case CODA_7541:
1338                 size = CODA7_WORK_BUF_SIZE;
1339                 break;
1340         default:
1341                 return 0;
1342         }
1343
1344         if (ctx->workbuf.vaddr) {
1345                 v4l2_err(&dev->v4l2_dev, "context buffer still allocated\n");
1346                 ret = -EBUSY;
1347                 return -ENOMEM;
1348         }
1349
1350         ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size);
1351         if (ret < 0) {
1352                 v4l2_err(&dev->v4l2_dev, "failed to allocate %d byte context buffer",
1353                          ctx->workbuf.size);
1354                 goto err;
1355         }
1356
1357         return 0;
1358
1359 err:
1360         coda_free_context_buffers(ctx);
1361         return ret;
1362 }
1363
1364 static int coda_encode_header(struct coda_ctx *ctx, struct vb2_buffer *buf,
1365                               int header_code, u8 *header, int *size)
1366 {
1367         struct coda_dev *dev = ctx->dev;
1368         int ret;
1369
1370         coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0),
1371                    CODA_CMD_ENC_HEADER_BB_START);
1372         coda_write(dev, vb2_plane_size(buf, 0), CODA_CMD_ENC_HEADER_BB_SIZE);
1373         coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
1374         ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
1375         if (ret < 0) {
1376                 v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
1377                 return ret;
1378         }
1379         *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
1380                 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
1381         memcpy(header, vb2_plane_vaddr(buf, 0), *size);
1382
1383         return 0;
1384 }
1385
1386 static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
1387 {
1388         struct coda_ctx *ctx = vb2_get_drv_priv(q);
1389         struct v4l2_device *v4l2_dev = &ctx->dev->v4l2_dev;
1390         u32 bitstream_buf, bitstream_size;
1391         struct coda_dev *dev = ctx->dev;
1392         struct coda_q_data *q_data_src, *q_data_dst;
1393         struct vb2_buffer *buf;
1394         u32 dst_fourcc;
1395         u32 value;
1396         int ret = 0;
1397
1398         if (count < 1)
1399                 return -EINVAL;
1400
1401         if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1402                 ctx->streamon_out = 1;
1403         else
1404                 ctx->streamon_cap = 1;
1405
1406         q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1407         if (ctx->streamon_out) {
1408                 if (coda_format_is_yuv(q_data_src->fourcc))
1409                         ctx->inst_type = CODA_INST_ENCODER;
1410                 else
1411                         ctx->inst_type = CODA_INST_DECODER;
1412         }
1413
1414         /* Don't start the coda unless both queues are on */
1415         if (!(ctx->streamon_out & ctx->streamon_cap))
1416                 return 0;
1417
1418         ctx->gopcounter = ctx->params.gop_size - 1;
1419         buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
1420         bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
1421         q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
1422         bitstream_size = q_data_dst->sizeimage;
1423         dst_fourcc = q_data_dst->fourcc;
1424
1425         ctx->codec = coda_find_codec(ctx->dev, q_data_src->fourcc,
1426                                      q_data_dst->fourcc);
1427         if (!ctx->codec) {
1428                 v4l2_err(v4l2_dev, "couldn't tell instance type.\n");
1429                 return -EINVAL;
1430         }
1431
1432         /* Allocate per-instance buffers */
1433         ret = coda_alloc_context_buffers(ctx, q_data_src);
1434         if (ret < 0)
1435                 return ret;
1436
1437         if (!coda_is_initialized(dev)) {
1438                 v4l2_err(v4l2_dev, "coda is not initialized.\n");
1439                 return -EFAULT;
1440         }
1441
1442         mutex_lock(&dev->coda_mutex);
1443
1444         coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
1445         coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
1446         coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
1447         switch (dev->devtype->product) {
1448         case CODA_DX6:
1449                 coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
1450                         CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
1451                 break;
1452         default:
1453                 coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
1454                         CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
1455         }
1456
1457         if (dev->devtype->product == CODA_DX6) {
1458                 /* Configure the coda */
1459                 coda_write(dev, dev->iram_paddr, CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
1460         }
1461
1462         /* Could set rotation here if needed */
1463         switch (dev->devtype->product) {
1464         case CODA_DX6:
1465                 value = (q_data_src->width & CODADX6_PICWIDTH_MASK) << CODADX6_PICWIDTH_OFFSET;
1466                 value |= (q_data_src->height & CODADX6_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
1467                 break;
1468         default:
1469                 value = (q_data_src->width & CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
1470                 value |= (q_data_src->height & CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
1471         }
1472         coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
1473         coda_write(dev, ctx->params.framerate,
1474                    CODA_CMD_ENC_SEQ_SRC_F_RATE);
1475
1476         ctx->params.codec_mode = ctx->codec->mode;
1477         switch (dst_fourcc) {
1478         case V4L2_PIX_FMT_MPEG4:
1479                 coda_write(dev, CODA_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD);
1480                 coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
1481                 break;
1482         case V4L2_PIX_FMT_H264:
1483                 coda_write(dev, CODA_STD_H264, CODA_CMD_ENC_SEQ_COD_STD);
1484                 coda_write(dev, 0, CODA_CMD_ENC_SEQ_264_PARA);
1485                 break;
1486         default:
1487                 v4l2_err(v4l2_dev,
1488                          "dst format (0x%08x) invalid.\n", dst_fourcc);
1489                 ret = -EINVAL;
1490                 goto out;
1491         }
1492
1493         switch (ctx->params.slice_mode) {
1494         case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
1495                 value = 0;
1496                 break;
1497         case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
1498                 value  = (ctx->params.slice_max_mb & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
1499                 value |= (1 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
1500                 value |=  1 & CODA_SLICING_MODE_MASK;
1501                 break;
1502         case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
1503                 value  = (ctx->params.slice_max_bits & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
1504                 value |= (0 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
1505                 value |=  1 & CODA_SLICING_MODE_MASK;
1506                 break;
1507         }
1508         coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
1509         value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
1510         coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
1511
1512         if (ctx->params.bitrate) {
1513                 /* Rate control enabled */
1514                 value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK) << CODA_RATECONTROL_BITRATE_OFFSET;
1515                 value |=  1 & CODA_RATECONTROL_ENABLE_MASK;
1516         } else {
1517                 value = 0;
1518         }
1519         coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
1520
1521         coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
1522         coda_write(dev, 0, CODA_CMD_ENC_SEQ_INTRA_REFRESH);
1523
1524         coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
1525         coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
1526
1527         /* set default gamma */
1528         value = (CODA_DEFAULT_GAMMA & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET;
1529         coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_GAMMA);
1530
1531         if (CODA_DEFAULT_GAMMA > 0) {
1532                 if (dev->devtype->product == CODA_DX6)
1533                         value  = 1 << CODADX6_OPTION_GAMMA_OFFSET;
1534                 else
1535                         value  = 1 << CODA7_OPTION_GAMMA_OFFSET;
1536         } else {
1537                 value = 0;
1538         }
1539         coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
1540
1541         coda_setup_iram(ctx);
1542
1543         if (dst_fourcc == V4L2_PIX_FMT_H264) {
1544                 value  = (FMO_SLICE_SAVE_BUF_SIZE << 7);
1545                 value |= (0 & CODA_FMOPARAM_TYPE_MASK) << CODA_FMOPARAM_TYPE_OFFSET;
1546                 value |=  0 & CODA_FMOPARAM_SLICENUM_MASK;
1547                 if (dev->devtype->product == CODA_DX6) {
1548                         coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
1549                 } else {
1550                         coda_write(dev, ctx->iram_info.search_ram_paddr,
1551                                         CODA7_CMD_ENC_SEQ_SEARCH_BASE);
1552                         coda_write(dev, ctx->iram_info.search_ram_size,
1553                                         CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
1554                 }
1555         }
1556
1557         ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
1558         if (ret < 0) {
1559                 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1560                 goto out;
1561         }
1562
1563         if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
1564                 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
1565                 ret = -EFAULT;
1566                 goto out;
1567         }
1568
1569         ctx->num_internal_frames = 2;
1570         ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
1571         if (ret < 0) {
1572                 v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
1573                 goto out;
1574         }
1575
1576         coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
1577         coda_write(dev, round_up(q_data_src->width, 8), CODA_CMD_SET_FRAME_BUF_STRIDE);
1578         if (dev->devtype->product != CODA_DX6) {
1579                 coda_write(dev, ctx->iram_info.buf_bit_use,
1580                                 CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1581                 coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
1582                                 CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1583                 coda_write(dev, ctx->iram_info.buf_dbk_y_use,
1584                                 CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1585                 coda_write(dev, ctx->iram_info.buf_dbk_c_use,
1586                                 CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1587                 coda_write(dev, ctx->iram_info.buf_ovl_use,
1588                                 CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1589         }
1590         ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
1591         if (ret < 0) {
1592                 v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1593                 goto out;
1594         }
1595
1596         /* Save stream headers */
1597         buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
1598         switch (dst_fourcc) {
1599         case V4L2_PIX_FMT_H264:
1600                 /*
1601                  * Get SPS in the first frame and copy it to an
1602                  * intermediate buffer.
1603                  */
1604                 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
1605                                          &ctx->vpu_header[0][0],
1606                                          &ctx->vpu_header_size[0]);
1607                 if (ret < 0)
1608                         goto out;
1609
1610                 /*
1611                  * Get PPS in the first frame and copy it to an
1612                  * intermediate buffer.
1613                  */
1614                 ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
1615                                          &ctx->vpu_header[1][0],
1616                                          &ctx->vpu_header_size[1]);
1617                 if (ret < 0)
1618                         goto out;
1619
1620                 /*
1621                  * Length of H.264 headers is variable and thus it might not be
1622                  * aligned for the coda to append the encoded frame. In that is
1623                  * the case a filler NAL must be added to header 2.
1624                  */
1625                 ctx->vpu_header_size[2] = coda_h264_padding(
1626                                         (ctx->vpu_header_size[0] +
1627                                          ctx->vpu_header_size[1]),
1628                                          ctx->vpu_header[2]);
1629                 break;
1630         case V4L2_PIX_FMT_MPEG4:
1631                 /*
1632                  * Get VOS in the first frame and copy it to an
1633                  * intermediate buffer
1634                  */
1635                 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
1636                                          &ctx->vpu_header[0][0],
1637                                          &ctx->vpu_header_size[0]);
1638                 if (ret < 0)
1639                         goto out;
1640
1641                 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
1642                                          &ctx->vpu_header[1][0],
1643                                          &ctx->vpu_header_size[1]);
1644                 if (ret < 0)
1645                         goto out;
1646
1647                 ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
1648                                          &ctx->vpu_header[2][0],
1649                                          &ctx->vpu_header_size[2]);
1650                 if (ret < 0)
1651                         goto out;
1652                 break;
1653         default:
1654                 /* No more formats need to save headers at the moment */
1655                 break;
1656         }
1657
1658 out:
1659         mutex_unlock(&dev->coda_mutex);
1660         return ret;
1661 }
1662
1663 static int coda_stop_streaming(struct vb2_queue *q)
1664 {
1665         struct coda_ctx *ctx = vb2_get_drv_priv(q);
1666         struct coda_dev *dev = ctx->dev;
1667
1668         if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
1669                 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1670                          "%s: output\n", __func__);
1671                 ctx->streamon_out = 0;
1672         } else {
1673                 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1674                          "%s: capture\n", __func__);
1675                 ctx->streamon_cap = 0;
1676         }
1677
1678         /* Don't stop the coda unless both queues are off */
1679         if (ctx->streamon_out || ctx->streamon_cap)
1680                 return 0;
1681
1682         cancel_delayed_work(&dev->timeout);
1683
1684         mutex_lock(&dev->coda_mutex);
1685         v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1686                  "%s: sent command 'SEQ_END' to coda\n", __func__);
1687         if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
1688                 v4l2_err(&dev->v4l2_dev,
1689                          "CODA_COMMAND_SEQ_END failed\n");
1690                 return -ETIMEDOUT;
1691         }
1692         mutex_unlock(&dev->coda_mutex);
1693
1694         coda_free_framebuffers(ctx);
1695
1696         return 0;
1697 }
1698
1699 static struct vb2_ops coda_qops = {
1700         .queue_setup            = coda_queue_setup,
1701         .buf_prepare            = coda_buf_prepare,
1702         .buf_queue              = coda_buf_queue,
1703         .wait_prepare           = coda_wait_prepare,
1704         .wait_finish            = coda_wait_finish,
1705         .start_streaming        = coda_start_streaming,
1706         .stop_streaming         = coda_stop_streaming,
1707 };
1708
1709 static int coda_s_ctrl(struct v4l2_ctrl *ctrl)
1710 {
1711         struct coda_ctx *ctx =
1712                         container_of(ctrl->handler, struct coda_ctx, ctrls);
1713
1714         v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1715                  "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
1716
1717         switch (ctrl->id) {
1718         case V4L2_CID_HFLIP:
1719                 if (ctrl->val)
1720                         ctx->params.rot_mode |= CODA_MIR_HOR;
1721                 else
1722                         ctx->params.rot_mode &= ~CODA_MIR_HOR;
1723                 break;
1724         case V4L2_CID_VFLIP:
1725                 if (ctrl->val)
1726                         ctx->params.rot_mode |= CODA_MIR_VER;
1727                 else
1728                         ctx->params.rot_mode &= ~CODA_MIR_VER;
1729                 break;
1730         case V4L2_CID_MPEG_VIDEO_BITRATE:
1731                 ctx->params.bitrate = ctrl->val / 1000;
1732                 break;
1733         case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
1734                 ctx->params.gop_size = ctrl->val;
1735                 break;
1736         case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
1737                 ctx->params.h264_intra_qp = ctrl->val;
1738                 break;
1739         case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
1740                 ctx->params.h264_inter_qp = ctrl->val;
1741                 break;
1742         case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP:
1743                 ctx->params.mpeg4_intra_qp = ctrl->val;
1744                 break;
1745         case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP:
1746                 ctx->params.mpeg4_inter_qp = ctrl->val;
1747                 break;
1748         case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE:
1749                 ctx->params.slice_mode = ctrl->val;
1750                 break;
1751         case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB:
1752                 ctx->params.slice_max_mb = ctrl->val;
1753                 break;
1754         case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES:
1755                 ctx->params.slice_max_bits = ctrl->val * 8;
1756                 break;
1757         case V4L2_CID_MPEG_VIDEO_HEADER_MODE:
1758                 break;
1759         default:
1760                 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1761                         "Invalid control, id=%d, val=%d\n",
1762                         ctrl->id, ctrl->val);
1763                 return -EINVAL;
1764         }
1765
1766         return 0;
1767 }
1768
1769 static struct v4l2_ctrl_ops coda_ctrl_ops = {
1770         .s_ctrl = coda_s_ctrl,
1771 };
1772
1773 static int coda_ctrls_setup(struct coda_ctx *ctx)
1774 {
1775         v4l2_ctrl_handler_init(&ctx->ctrls, 9);
1776
1777         v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1778                 V4L2_CID_HFLIP, 0, 1, 1, 0);
1779         v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1780                 V4L2_CID_VFLIP, 0, 1, 1, 0);
1781         v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1782                 V4L2_CID_MPEG_VIDEO_BITRATE, 0, 32767000, 1, 0);
1783         v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1784                 V4L2_CID_MPEG_VIDEO_GOP_SIZE, 1, 60, 1, 16);
1785         v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1786                 V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, 1, 51, 1, 25);
1787         v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1788                 V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP, 1, 51, 1, 25);
1789         v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1790                 V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP, 1, 31, 1, 2);
1791         v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1792                 V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP, 1, 31, 1, 2);
1793         v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
1794                 V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE,
1795                 V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES, 0x0,
1796                 V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE);
1797         v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1798                 V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, 1, 0x3fffffff, 1, 1);
1799         v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1800                 V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES, 1, 0x3fffffff, 1, 500);
1801         v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
1802                 V4L2_CID_MPEG_VIDEO_HEADER_MODE,
1803                 V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
1804                 (1 << V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE),
1805                 V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME);
1806
1807         if (ctx->ctrls.error) {
1808                 v4l2_err(&ctx->dev->v4l2_dev, "control initialization error (%d)",
1809                         ctx->ctrls.error);
1810                 return -EINVAL;
1811         }
1812
1813         return v4l2_ctrl_handler_setup(&ctx->ctrls);
1814 }
1815
1816 static int coda_queue_init(void *priv, struct vb2_queue *src_vq,
1817                       struct vb2_queue *dst_vq)
1818 {
1819         struct coda_ctx *ctx = priv;
1820         int ret;
1821
1822         src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
1823         src_vq->io_modes = VB2_DMABUF | VB2_MMAP | VB2_USERPTR;
1824         src_vq->drv_priv = ctx;
1825         src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1826         src_vq->ops = &coda_qops;
1827         src_vq->mem_ops = &vb2_dma_contig_memops;
1828         src_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1829
1830         ret = vb2_queue_init(src_vq);
1831         if (ret)
1832                 return ret;
1833
1834         dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1835         dst_vq->io_modes = VB2_DMABUF | VB2_MMAP | VB2_USERPTR;
1836         dst_vq->drv_priv = ctx;
1837         dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1838         dst_vq->ops = &coda_qops;
1839         dst_vq->mem_ops = &vb2_dma_contig_memops;
1840         dst_vq->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_COPY;
1841
1842         return vb2_queue_init(dst_vq);
1843 }
1844
1845 static int coda_next_free_instance(struct coda_dev *dev)
1846 {
1847         return ffz(dev->instance_mask);
1848 }
1849
1850 static int coda_open(struct file *file)
1851 {
1852         struct coda_dev *dev = video_drvdata(file);
1853         struct coda_ctx *ctx = NULL;
1854         int ret = 0;
1855         int idx;
1856
1857         idx = coda_next_free_instance(dev);
1858         if (idx >= CODA_MAX_INSTANCES)
1859                 return -EBUSY;
1860         set_bit(idx, &dev->instance_mask);
1861
1862         ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1863         if (!ctx)
1864                 return -ENOMEM;
1865
1866         v4l2_fh_init(&ctx->fh, video_devdata(file));
1867         file->private_data = &ctx->fh;
1868         v4l2_fh_add(&ctx->fh);
1869         ctx->dev = dev;
1870         ctx->idx = idx;
1871         switch (dev->devtype->product) {
1872         case CODA_7541:
1873                 ctx->reg_idx = 0;
1874                 break;
1875         default:
1876                 ctx->reg_idx = idx;
1877         }
1878         set_default_params(ctx);
1879         ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx,
1880                                          &coda_queue_init);
1881         if (IS_ERR(ctx->m2m_ctx)) {
1882                 ret = PTR_ERR(ctx->m2m_ctx);
1883
1884                 v4l2_err(&dev->v4l2_dev, "%s return error (%d)\n",
1885                          __func__, ret);
1886                 goto err;
1887         }
1888         ret = coda_ctrls_setup(ctx);
1889         if (ret) {
1890                 v4l2_err(&dev->v4l2_dev, "failed to setup coda controls\n");
1891                 goto err;
1892         }
1893
1894         ctx->fh.ctrl_handler = &ctx->ctrls;
1895
1896         ret = coda_alloc_context_buf(ctx, &ctx->parabuf, CODA_PARA_BUF_SIZE);
1897         if (ret < 0) {
1898                 v4l2_err(&dev->v4l2_dev, "failed to allocate parabuf");
1899                 goto err;
1900         }
1901
1902         ctx->bitstream.size = CODA_MAX_FRAME_SIZE;
1903         ctx->bitstream.vaddr = dma_alloc_writecombine(&dev->plat_dev->dev,
1904                         ctx->bitstream.size, &ctx->bitstream.paddr, GFP_KERNEL);
1905         if (!ctx->bitstream.vaddr) {
1906                 v4l2_err(&dev->v4l2_dev, "failed to allocate bitstream ringbuffer");
1907                 ret = -ENOMEM;
1908                 goto err;
1909         }
1910         kfifo_init(&ctx->bitstream_fifo,
1911                 ctx->bitstream.vaddr, ctx->bitstream.size);
1912         mutex_init(&ctx->bitstream_mutex);
1913
1914         coda_lock(ctx);
1915         list_add(&ctx->list, &dev->instances);
1916         coda_unlock(ctx);
1917
1918         clk_prepare_enable(dev->clk_per);
1919         clk_prepare_enable(dev->clk_ahb);
1920
1921         v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Created instance %d (%p)\n",
1922                  ctx->idx, ctx);
1923
1924         return 0;
1925
1926 err:
1927         v4l2_fh_del(&ctx->fh);
1928         v4l2_fh_exit(&ctx->fh);
1929         kfree(ctx);
1930         return ret;
1931 }
1932
1933 static int coda_release(struct file *file)
1934 {
1935         struct coda_dev *dev = video_drvdata(file);
1936         struct coda_ctx *ctx = fh_to_ctx(file->private_data);
1937
1938         v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Releasing instance %p\n",
1939                  ctx);
1940
1941         coda_lock(ctx);
1942         list_del(&ctx->list);
1943         coda_unlock(ctx);
1944
1945         dma_free_writecombine(&dev->plat_dev->dev, ctx->bitstream.size,
1946                 ctx->bitstream.vaddr, ctx->bitstream.paddr);
1947         coda_free_context_buffers(ctx);
1948         if (ctx->dev->devtype->product == CODA_DX6)
1949                 coda_free_aux_buf(dev, &ctx->workbuf);
1950
1951         coda_free_aux_buf(dev, &ctx->parabuf);
1952         v4l2_ctrl_handler_free(&ctx->ctrls);
1953         clk_disable_unprepare(dev->clk_per);
1954         clk_disable_unprepare(dev->clk_ahb);
1955         v4l2_fh_del(&ctx->fh);
1956         v4l2_fh_exit(&ctx->fh);
1957         clear_bit(ctx->idx, &dev->instance_mask);
1958         kfree(ctx);
1959
1960         return 0;
1961 }
1962
1963 static unsigned int coda_poll(struct file *file,
1964                                  struct poll_table_struct *wait)
1965 {
1966         struct coda_ctx *ctx = fh_to_ctx(file->private_data);
1967         int ret;
1968
1969         coda_lock(ctx);
1970         ret = v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1971         coda_unlock(ctx);
1972         return ret;
1973 }
1974
1975 static int coda_mmap(struct file *file, struct vm_area_struct *vma)
1976 {
1977         struct coda_ctx *ctx = fh_to_ctx(file->private_data);
1978
1979         return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1980 }
1981
1982 static const struct v4l2_file_operations coda_fops = {
1983         .owner          = THIS_MODULE,
1984         .open           = coda_open,
1985         .release        = coda_release,
1986         .poll           = coda_poll,
1987         .unlocked_ioctl = video_ioctl2,
1988         .mmap           = coda_mmap,
1989 };
1990
1991 static irqreturn_t coda_irq_handler(int irq, void *data)
1992 {
1993         struct vb2_buffer *src_buf, *dst_buf;
1994         struct coda_dev *dev = data;
1995         u32 wr_ptr, start_ptr;
1996         struct coda_ctx *ctx;
1997
1998         cancel_delayed_work(&dev->timeout);
1999
2000         /* read status register to attend the IRQ */
2001         coda_read(dev, CODA_REG_BIT_INT_STATUS);
2002         coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
2003                       CODA_REG_BIT_INT_CLEAR);
2004
2005         ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
2006         if (ctx == NULL) {
2007                 v4l2_err(&dev->v4l2_dev, "Instance released before the end of transaction\n");
2008                 mutex_unlock(&dev->coda_mutex);
2009                 return IRQ_HANDLED;
2010         }
2011
2012         if (ctx->aborting) {
2013                 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
2014                          "task has been aborted\n");
2015                 mutex_unlock(&dev->coda_mutex);
2016                 return IRQ_HANDLED;
2017         }
2018
2019         if (coda_isbusy(ctx->dev)) {
2020                 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
2021                          "coda is still busy!!!!\n");
2022                 return IRQ_NONE;
2023         }
2024
2025         src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
2026         dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
2027
2028         /* Get results from the coda */
2029         coda_read(dev, CODA_RET_ENC_PIC_TYPE);
2030         start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
2031         wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
2032
2033         /* Calculate bytesused field */
2034         if (dst_buf->v4l2_buf.sequence == 0) {
2035                 vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr +
2036                                         ctx->vpu_header_size[0] +
2037                                         ctx->vpu_header_size[1] +
2038                                         ctx->vpu_header_size[2]);
2039         } else {
2040                 vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr);
2041         }
2042
2043         v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
2044                  wr_ptr - start_ptr);
2045
2046         coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
2047         coda_read(dev, CODA_RET_ENC_PIC_FLAG);
2048
2049         if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
2050                 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
2051                 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
2052         } else {
2053                 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
2054                 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
2055         }
2056
2057         dst_buf->v4l2_buf.timestamp = src_buf->v4l2_buf.timestamp;
2058         dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode;
2059
2060         v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
2061         v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
2062
2063         ctx->gopcounter--;
2064         if (ctx->gopcounter < 0)
2065                 ctx->gopcounter = ctx->params.gop_size - 1;
2066
2067         v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
2068                 "job finished: encoding frame (%d) (%s)\n",
2069                 dst_buf->v4l2_buf.sequence,
2070                 (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
2071                 "KEYFRAME" : "PFRAME");
2072
2073         mutex_unlock(&dev->coda_mutex);
2074
2075         v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->m2m_ctx);
2076
2077         return IRQ_HANDLED;
2078 }
2079
2080 static void coda_timeout(struct work_struct *work)
2081 {
2082         struct coda_ctx *ctx;
2083         struct coda_dev *dev = container_of(to_delayed_work(work),
2084                                             struct coda_dev, timeout);
2085
2086         dev_err(&dev->plat_dev->dev, "CODA PIC_RUN timeout, stopping all streams\n");
2087
2088         mutex_lock(&dev->dev_mutex);
2089         list_for_each_entry(ctx, &dev->instances, list) {
2090                 v4l2_m2m_streamoff(NULL, ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
2091                 v4l2_m2m_streamoff(NULL, ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
2092         }
2093         mutex_unlock(&dev->dev_mutex);
2094
2095         mutex_unlock(&dev->coda_mutex);
2096         ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
2097         v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->m2m_ctx);
2098 }
2099
2100 static u32 coda_supported_firmwares[] = {
2101         CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
2102         CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
2103 };
2104
2105 static bool coda_firmware_supported(u32 vernum)
2106 {
2107         int i;
2108
2109         for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
2110                 if (vernum == coda_supported_firmwares[i])
2111                         return true;
2112         return false;
2113 }
2114
2115 static char *coda_product_name(int product)
2116 {
2117         static char buf[9];
2118
2119         switch (product) {
2120         case CODA_DX6:
2121                 return "CodaDx6";
2122         case CODA_7541:
2123                 return "CODA7541";
2124         default:
2125                 snprintf(buf, sizeof(buf), "(0x%04x)", product);
2126                 return buf;
2127         }
2128 }
2129
2130 static int coda_hw_init(struct coda_dev *dev)
2131 {
2132         u16 product, major, minor, release;
2133         u32 data;
2134         u16 *p;
2135         int i;
2136
2137         clk_prepare_enable(dev->clk_per);
2138         clk_prepare_enable(dev->clk_ahb);
2139
2140         /*
2141          * Copy the first CODA_ISRAM_SIZE in the internal SRAM.
2142          * The 16-bit chars in the code buffer are in memory access
2143          * order, re-sort them to CODA order for register download.
2144          * Data in this SRAM survives a reboot.
2145          */
2146         p = (u16 *)dev->codebuf.vaddr;
2147         if (dev->devtype->product == CODA_DX6) {
2148                 for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++)  {
2149                         data = CODA_DOWN_ADDRESS_SET(i) |
2150                                 CODA_DOWN_DATA_SET(p[i ^ 1]);
2151                         coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
2152                 }
2153         } else {
2154                 for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
2155                         data = CODA_DOWN_ADDRESS_SET(i) |
2156                                 CODA_DOWN_DATA_SET(p[round_down(i, 4) +
2157                                                         3 - (i % 4)]);
2158                         coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
2159                 }
2160         }
2161
2162         /* Clear registers */
2163         for (i = 0; i < 64; i++)
2164                 coda_write(dev, 0, CODA_REG_BIT_CODE_BUF_ADDR + i * 4);
2165
2166         /* Tell the BIT where to find everything it needs */
2167         if (dev->devtype->product == CODA_7541) {
2168                 coda_write(dev, dev->tempbuf.paddr,
2169                                 CODA_REG_BIT_TEMP_BUF_ADDR);
2170         } else {
2171                 coda_write(dev, dev->workbuf.paddr,
2172                               CODA_REG_BIT_WORK_BUF_ADDR);
2173         }
2174         coda_write(dev, dev->codebuf.paddr,
2175                       CODA_REG_BIT_CODE_BUF_ADDR);
2176         coda_write(dev, 0, CODA_REG_BIT_CODE_RUN);
2177
2178         /* Set default values */
2179         switch (dev->devtype->product) {
2180         case CODA_DX6:
2181                 coda_write(dev, CODADX6_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
2182                 break;
2183         default:
2184                 coda_write(dev, CODA7_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
2185         }
2186         coda_write(dev, 0, CODA_REG_BIT_FRAME_MEM_CTRL);
2187
2188         if (dev->devtype->product != CODA_DX6)
2189                 coda_write(dev, 0, CODA7_REG_BIT_AXI_SRAM_USE);
2190
2191         coda_write(dev, CODA_INT_INTERRUPT_ENABLE,
2192                       CODA_REG_BIT_INT_ENABLE);
2193
2194         /* Reset VPU and start processor */
2195         data = coda_read(dev, CODA_REG_BIT_CODE_RESET);
2196         data |= CODA_REG_RESET_ENABLE;
2197         coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
2198         udelay(10);
2199         data &= ~CODA_REG_RESET_ENABLE;
2200         coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
2201         coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
2202
2203         /* Load firmware */
2204         coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
2205         coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
2206         coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
2207         coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
2208         coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
2209         if (coda_wait_timeout(dev)) {
2210                 clk_disable_unprepare(dev->clk_per);
2211                 clk_disable_unprepare(dev->clk_ahb);
2212                 v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
2213                 return -EIO;
2214         }
2215
2216         /* Check we are compatible with the loaded firmware */
2217         data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
2218         product = CODA_FIRMWARE_PRODUCT(data);
2219         major = CODA_FIRMWARE_MAJOR(data);
2220         minor = CODA_FIRMWARE_MINOR(data);
2221         release = CODA_FIRMWARE_RELEASE(data);
2222
2223         clk_disable_unprepare(dev->clk_per);
2224         clk_disable_unprepare(dev->clk_ahb);
2225
2226         if (product != dev->devtype->product) {
2227                 v4l2_err(&dev->v4l2_dev, "Wrong firmware. Hw: %s, Fw: %s,"
2228                          " Version: %u.%u.%u\n",
2229                          coda_product_name(dev->devtype->product),
2230                          coda_product_name(product), major, minor, release);
2231                 return -EINVAL;
2232         }
2233
2234         v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
2235                   coda_product_name(product));
2236
2237         if (coda_firmware_supported(data)) {
2238                 v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
2239                           major, minor, release);
2240         } else {
2241                 v4l2_warn(&dev->v4l2_dev, "Unsupported firmware version: "
2242                           "%u.%u.%u\n", major, minor, release);
2243         }
2244
2245         return 0;
2246 }
2247
2248 static void coda_fw_callback(const struct firmware *fw, void *context)
2249 {
2250         struct coda_dev *dev = context;
2251         struct platform_device *pdev = dev->plat_dev;
2252         int ret;
2253
2254         if (!fw) {
2255                 v4l2_err(&dev->v4l2_dev, "firmware request failed\n");
2256                 return;
2257         }
2258
2259         /* allocate auxiliary per-device code buffer for the BIT processor */
2260         ret = coda_alloc_aux_buf(dev, &dev->codebuf, fw->size);
2261         if (ret < 0) {
2262                 dev_err(&pdev->dev, "failed to allocate code buffer\n");
2263                 return;
2264         }
2265
2266         /* Copy the whole firmware image to the code buffer */
2267         memcpy(dev->codebuf.vaddr, fw->data, fw->size);
2268         release_firmware(fw);
2269
2270         ret = coda_hw_init(dev);
2271         if (ret) {
2272                 v4l2_err(&dev->v4l2_dev, "HW initialization failed\n");
2273                 return;
2274         }
2275
2276         dev->vfd.fops   = &coda_fops,
2277         dev->vfd.ioctl_ops      = &coda_ioctl_ops;
2278         dev->vfd.release        = video_device_release_empty,
2279         dev->vfd.lock   = &dev->dev_mutex;
2280         dev->vfd.v4l2_dev       = &dev->v4l2_dev;
2281         dev->vfd.vfl_dir        = VFL_DIR_M2M;
2282         snprintf(dev->vfd.name, sizeof(dev->vfd.name), "%s", CODA_NAME);
2283         video_set_drvdata(&dev->vfd, dev);
2284
2285         dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
2286         if (IS_ERR(dev->alloc_ctx)) {
2287                 v4l2_err(&dev->v4l2_dev, "Failed to alloc vb2 context\n");
2288                 return;
2289         }
2290
2291         dev->m2m_dev = v4l2_m2m_init(&coda_m2m_ops);
2292         if (IS_ERR(dev->m2m_dev)) {
2293                 v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
2294                 goto rel_ctx;
2295         }
2296
2297         ret = video_register_device(&dev->vfd, VFL_TYPE_GRABBER, 0);
2298         if (ret) {
2299                 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
2300                 goto rel_m2m;
2301         }
2302         v4l2_info(&dev->v4l2_dev, "codec registered as /dev/video%d\n",
2303                   dev->vfd.num);
2304
2305         return;
2306
2307 rel_m2m:
2308         v4l2_m2m_release(dev->m2m_dev);
2309 rel_ctx:
2310         vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
2311 }
2312
2313 static int coda_firmware_request(struct coda_dev *dev)
2314 {
2315         char *fw = dev->devtype->firmware;
2316
2317         dev_dbg(&dev->plat_dev->dev, "requesting firmware '%s' for %s\n", fw,
2318                 coda_product_name(dev->devtype->product));
2319
2320         return request_firmware_nowait(THIS_MODULE, true,
2321                 fw, &dev->plat_dev->dev, GFP_KERNEL, dev, coda_fw_callback);
2322 }
2323
2324 enum coda_platform {
2325         CODA_IMX27,
2326         CODA_IMX53,
2327 };
2328
2329 static const struct coda_devtype coda_devdata[] = {
2330         [CODA_IMX27] = {
2331                 .firmware   = "v4l-codadx6-imx27.bin",
2332                 .product    = CODA_DX6,
2333                 .codecs     = codadx6_codecs,
2334                 .num_codecs = ARRAY_SIZE(codadx6_codecs),
2335         },
2336         [CODA_IMX53] = {
2337                 .firmware   = "v4l-coda7541-imx53.bin",
2338                 .product    = CODA_7541,
2339                 .codecs     = coda7_codecs,
2340                 .num_codecs = ARRAY_SIZE(coda7_codecs),
2341         },
2342 };
2343
2344 static struct platform_device_id coda_platform_ids[] = {
2345         { .name = "coda-imx27", .driver_data = CODA_IMX27 },
2346         { .name = "coda-imx53", .driver_data = CODA_IMX53 },
2347         { /* sentinel */ }
2348 };
2349 MODULE_DEVICE_TABLE(platform, coda_platform_ids);
2350
2351 #ifdef CONFIG_OF
2352 static const struct of_device_id coda_dt_ids[] = {
2353         { .compatible = "fsl,imx27-vpu", .data = &coda_platform_ids[CODA_IMX27] },
2354         { .compatible = "fsl,imx53-vpu", .data = &coda_devdata[CODA_IMX53] },
2355         { /* sentinel */ }
2356 };
2357 MODULE_DEVICE_TABLE(of, coda_dt_ids);
2358 #endif
2359
2360 static int coda_probe(struct platform_device *pdev)
2361 {
2362         const struct of_device_id *of_id =
2363                         of_match_device(of_match_ptr(coda_dt_ids), &pdev->dev);
2364         const struct platform_device_id *pdev_id;
2365         struct coda_platform_data *pdata = pdev->dev.platform_data;
2366         struct device_node *np = pdev->dev.of_node;
2367         struct gen_pool *pool;
2368         struct coda_dev *dev;
2369         struct resource *res;
2370         int ret, irq;
2371
2372         dev = devm_kzalloc(&pdev->dev, sizeof *dev, GFP_KERNEL);
2373         if (!dev) {
2374                 dev_err(&pdev->dev, "Not enough memory for %s\n",
2375                         CODA_NAME);
2376                 return -ENOMEM;
2377         }
2378
2379         spin_lock_init(&dev->irqlock);
2380         INIT_LIST_HEAD(&dev->instances);
2381         INIT_DELAYED_WORK(&dev->timeout, coda_timeout);
2382
2383         dev->plat_dev = pdev;
2384         dev->clk_per = devm_clk_get(&pdev->dev, "per");
2385         if (IS_ERR(dev->clk_per)) {
2386                 dev_err(&pdev->dev, "Could not get per clock\n");
2387                 return PTR_ERR(dev->clk_per);
2388         }
2389
2390         dev->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2391         if (IS_ERR(dev->clk_ahb)) {
2392                 dev_err(&pdev->dev, "Could not get ahb clock\n");
2393                 return PTR_ERR(dev->clk_ahb);
2394         }
2395
2396         /* Get  memory for physical registers */
2397         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2398         if (res == NULL) {
2399                 dev_err(&pdev->dev, "failed to get memory region resource\n");
2400                 return -ENOENT;
2401         }
2402
2403         dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
2404         if (IS_ERR(dev->regs_base))
2405                 return PTR_ERR(dev->regs_base);
2406
2407         /* IRQ */
2408         irq = platform_get_irq(pdev, 0);
2409         if (irq < 0) {
2410                 dev_err(&pdev->dev, "failed to get irq resource\n");
2411                 return -ENOENT;
2412         }
2413
2414         if (devm_request_irq(&pdev->dev, irq, coda_irq_handler,
2415                 0, CODA_NAME, dev) < 0) {
2416                 dev_err(&pdev->dev, "failed to request irq\n");
2417                 return -ENOENT;
2418         }
2419
2420         /* Get IRAM pool from device tree or platform data */
2421         pool = of_get_named_gen_pool(np, "iram", 0);
2422         if (!pool && pdata)
2423                 pool = dev_get_gen_pool(pdata->iram_dev);
2424         if (!pool) {
2425                 dev_err(&pdev->dev, "iram pool not available\n");
2426                 return -ENOMEM;
2427         }
2428         dev->iram_pool = pool;
2429
2430         ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
2431         if (ret)
2432                 return ret;
2433
2434         mutex_init(&dev->dev_mutex);
2435         mutex_init(&dev->coda_mutex);
2436
2437         pdev_id = of_id ? of_id->data : platform_get_device_id(pdev);
2438
2439         if (of_id) {
2440                 dev->devtype = of_id->data;
2441         } else if (pdev_id) {
2442                 dev->devtype = &coda_devdata[pdev_id->driver_data];
2443         } else {
2444                 v4l2_device_unregister(&dev->v4l2_dev);
2445                 return -EINVAL;
2446         }
2447
2448         /* allocate auxiliary per-device buffers for the BIT processor */
2449         switch (dev->devtype->product) {
2450         case CODA_DX6:
2451                 ret = coda_alloc_aux_buf(dev, &dev->workbuf,
2452                                          CODADX6_WORK_BUF_SIZE);
2453                 if (ret < 0) {
2454                         dev_err(&pdev->dev, "failed to allocate work buffer\n");
2455                         v4l2_device_unregister(&dev->v4l2_dev);
2456                         return ret;
2457                 }
2458                 break;
2459         case CODA_7541:
2460                 dev->tempbuf.size = CODA7_TEMP_BUF_SIZE;
2461                 break;
2462         }
2463         if (dev->tempbuf.size) {
2464                 ret = coda_alloc_aux_buf(dev, &dev->tempbuf,
2465                                          dev->tempbuf.size);
2466                 if (ret < 0) {
2467                         dev_err(&pdev->dev, "failed to allocate temp buffer\n");
2468                         v4l2_device_unregister(&dev->v4l2_dev);
2469                         return ret;
2470                 }
2471         }
2472
2473         if (dev->devtype->product == CODA_DX6)
2474                 dev->iram_size = CODADX6_IRAM_SIZE;
2475         else
2476                 dev->iram_size = CODA7_IRAM_SIZE;
2477         dev->iram_vaddr = gen_pool_alloc(dev->iram_pool, dev->iram_size);
2478         if (!dev->iram_vaddr) {
2479                 dev_err(&pdev->dev, "unable to alloc iram\n");
2480                 return -ENOMEM;
2481         }
2482         dev->iram_paddr = gen_pool_virt_to_phys(dev->iram_pool,
2483                                                 dev->iram_vaddr);
2484
2485         platform_set_drvdata(pdev, dev);
2486
2487         return coda_firmware_request(dev);
2488 }
2489
2490 static int coda_remove(struct platform_device *pdev)
2491 {
2492         struct coda_dev *dev = platform_get_drvdata(pdev);
2493
2494         video_unregister_device(&dev->vfd);
2495         if (dev->m2m_dev)
2496                 v4l2_m2m_release(dev->m2m_dev);
2497         if (dev->alloc_ctx)
2498                 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
2499         v4l2_device_unregister(&dev->v4l2_dev);
2500         if (dev->iram_vaddr)
2501                 gen_pool_free(dev->iram_pool, dev->iram_vaddr, dev->iram_size);
2502         coda_free_aux_buf(dev, &dev->codebuf);
2503         coda_free_aux_buf(dev, &dev->tempbuf);
2504         coda_free_aux_buf(dev, &dev->workbuf);
2505         return 0;
2506 }
2507
2508 static struct platform_driver coda_driver = {
2509         .probe  = coda_probe,
2510         .remove = coda_remove,
2511         .driver = {
2512                 .name   = CODA_NAME,
2513                 .owner  = THIS_MODULE,
2514                 .of_match_table = of_match_ptr(coda_dt_ids),
2515         },
2516         .id_table = coda_platform_ids,
2517 };
2518
2519 module_platform_driver(coda_driver);
2520
2521 MODULE_LICENSE("GPL");
2522 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
2523 MODULE_DESCRIPTION("Coda multi-standard codec V4L2 driver");