Pileus Git - ~andy/linux/blob - drivers/media/i2c/saa7115.c

   1 /* saa711x - Philips SAA711x video decoder driver
   2  * This driver can work with saa7111, saa7111a, saa7113, saa7114,
   3  *                           saa7115 and saa7118.
   4  *
   5  * Based on saa7114 driver by Maxim Yevtyushkin, which is based on
   6  * the saa7111 driver by Dave Perks.
   7  *
   8  * Copyright (C) 1998 Dave Perks <dperks@ibm.net>
   9  * Copyright (C) 2002 Maxim Yevtyushkin <max@linuxmedialabs.com>
  10  *
  11  * Slight changes for video timing and attachment output by
  12  * Wolfgang Scherr <scherr@net4you.net>
  13  *
  14  * Moved over to the linux >= 2.4.x i2c protocol (1/1/2003)
  15  * by Ronald Bultje <rbultje@ronald.bitfreak.net>
  16  *
  17  * Added saa7115 support by Kevin Thayer <nufan_wfk at yahoo.com>
  18  * (2/17/2003)
  19  *
  20  * VBI support (2004) and cleanups (2005) by Hans Verkuil <hverkuil@xs4all.nl>
  21  *
  22  * Copyright (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org>
  23  *      SAA7111, SAA7113 and SAA7118 support
  24  *
  25  * This program is free software; you can redistribute it and/or
  26  * modify it under the terms of the GNU General Public License
  27  * as published by the Free Software Foundation; either version 2
  28  * of the License, or (at your option) any later version.
  29  *
  30  * This program is distributed in the hope that it will be useful,
  31  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  32  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  33  * GNU General Public License for more details.
  34  *
  35  * You should have received a copy of the GNU General Public License
  36  * along with this program; if not, write to the Free Software
  37  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  38  */
  39
  40 #include "saa711x_regs.h"
  41
  42 #include <linux/kernel.h>
  43 #include <linux/module.h>
  44 #include <linux/slab.h>
  45 #include <linux/i2c.h>
  46 #include <linux/videodev2.h>
  47 #include <media/v4l2-device.h>
  48 #include <media/v4l2-ctrls.h>
  49 #include <media/v4l2-chip-ident.h>
  50 #include <media/saa7115.h>
  51 #include <asm/div64.h>
  52
  53 #define VRES_60HZ       (480+16)
  54
  55 MODULE_DESCRIPTION("Philips SAA7111/SAA7113/SAA7114/SAA7115/SAA7118 video decoder driver");
  56 MODULE_AUTHOR(  "Maxim Yevtyushkin, Kevin Thayer, Chris Kennedy, "
  57                 "Hans Verkuil, Mauro Carvalho Chehab");
  58 MODULE_LICENSE("GPL");
  59
  60 static bool debug;
  61 module_param(debug, bool, 0644);
  62
  63 MODULE_PARM_DESC(debug, "Debug level (0-1)");
  64
  65
  66 struct saa711x_state {
  67         struct v4l2_subdev sd;
  68         struct v4l2_ctrl_handler hdl;
  69
  70         struct {
  71                 /* chroma gain control cluster */
  72                 struct v4l2_ctrl *agc;
  73                 struct v4l2_ctrl *gain;
  74         };
  75
  76         v4l2_std_id std;
  77         int input;
  78         int output;
  79         int enable;
  80         int radio;
  81         int width;
  82         int height;
  83         u32 ident;
  84         u32 audclk_freq;
  85         u32 crystal_freq;
  86         u8 ucgc;
  87         u8 cgcdiv;
  88         u8 apll;
  89 };
  90
  91 static inline struct saa711x_state *to_state(struct v4l2_subdev *sd)
  92 {
  93         return container_of(sd, struct saa711x_state, sd);
  94 }
  95
  96 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
  97 {
  98         return &container_of(ctrl->handler, struct saa711x_state, hdl)->sd;
  99 }
 100
 101 /* ----------------------------------------------------------------------- */
 102
 103 static inline int saa711x_write(struct v4l2_subdev *sd, u8 reg, u8 value)
 104 {
 105         struct i2c_client *client = v4l2_get_subdevdata(sd);
 106
 107         return i2c_smbus_write_byte_data(client, reg, value);
 108 }
 109
 110 /* Sanity routine to check if a register is present */
 111 static int saa711x_has_reg(const int id, const u8 reg)
 112 {
 113         if (id == V4L2_IDENT_SAA7111)
 114                 return reg < 0x20 && reg != 0x01 && reg != 0x0f &&
 115                        (reg < 0x13 || reg > 0x19) && reg != 0x1d && reg != 0x1e;
 116         if (id == V4L2_IDENT_SAA7111A)
 117                 return reg < 0x20 && reg != 0x01 && reg != 0x0f &&
 118                        reg != 0x14 && reg != 0x18 && reg != 0x19 &&
 119                        reg != 0x1d && reg != 0x1e;
 120
 121         /* common for saa7113/4/5/8 */
 122         if (unlikely((reg >= 0x3b && reg <= 0x3f) || reg == 0x5c || reg == 0x5f ||
 123             reg == 0xa3 || reg == 0xa7 || reg == 0xab || reg == 0xaf || (reg >= 0xb5 && reg <= 0xb7) ||
 124             reg == 0xd3 || reg == 0xd7 || reg == 0xdb || reg == 0xdf || (reg >= 0xe5 && reg <= 0xe7) ||
 125             reg == 0x82 || (reg >= 0x89 && reg <= 0x8e)))
 126                 return 0;
 127
 128         switch (id) {
 129         case V4L2_IDENT_SAA7113:
 130                 return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && (reg < 0x20 || reg > 0x3f) &&
 131                        reg != 0x5d && reg < 0x63;
 132         case V4L2_IDENT_SAA7114:
 133                 return (reg < 0x1a || reg > 0x1e) && (reg < 0x20 || reg > 0x2f) &&
 134                        (reg < 0x63 || reg > 0x7f) && reg != 0x33 && reg != 0x37 &&
 135                        reg != 0x81 && reg < 0xf0;
 136         case V4L2_IDENT_SAA7115:
 137                 return (reg < 0x20 || reg > 0x2f) && reg != 0x65 && (reg < 0xfc || reg > 0xfe);
 138         case V4L2_IDENT_SAA7118:
 139                 return (reg < 0x1a || reg > 0x1d) && (reg < 0x20 || reg > 0x22) &&
 140                        (reg < 0x26 || reg > 0x28) && reg != 0x33 && reg != 0x37 &&
 141                        (reg < 0x63 || reg > 0x7f) && reg != 0x81 && reg < 0xf0;
 142         }
 143         return 1;
 144 }
 145
 146 static int saa711x_writeregs(struct v4l2_subdev *sd, const unsigned char *regs)
 147 {
 148         struct saa711x_state *state = to_state(sd);
 149         unsigned char reg, data;
 150
 151         while (*regs != 0x00) {
 152                 reg = *(regs++);
 153                 data = *(regs++);
 154
 155                 /* According with datasheets, reserved regs should be
 156                    filled with 0 - seems better not to touch on they */
 157                 if (saa711x_has_reg(state->ident, reg)) {
 158                         if (saa711x_write(sd, reg, data) < 0)
 159                                 return -1;
 160                 } else {
 161                         v4l2_dbg(1, debug, sd, "tried to access reserved reg 0x%02x\n", reg);
 162                 }
 163         }
 164         return 0;
 165 }
 166
 167 static inline int saa711x_read(struct v4l2_subdev *sd, u8 reg)
 168 {
 169         struct i2c_client *client = v4l2_get_subdevdata(sd);
 170
 171         return i2c_smbus_read_byte_data(client, reg);
 172 }
 173
 174 /* ----------------------------------------------------------------------- */
 175
 176 /* SAA7111 initialization table */
 177 static const unsigned char saa7111_init[] = {
 178         R_01_INC_DELAY, 0x00,           /* reserved */
 179
 180         /*front end */
 181         R_02_INPUT_CNTL_1, 0xd0,        /* FUSE=3, GUDL=2, MODE=0 */
 182         R_03_INPUT_CNTL_2, 0x23,        /* HLNRS=0, VBSL=1, WPOFF=0, HOLDG=0,
 183                                          * GAFIX=0, GAI1=256, GAI2=256 */
 184         R_04_INPUT_CNTL_3, 0x00,        /* GAI1=256 */
 185         R_05_INPUT_CNTL_4, 0x00,        /* GAI2=256 */
 186
 187         /* decoder */
 188         R_06_H_SYNC_START, 0xf3,        /* HSB at  13(50Hz) /  17(60Hz)
 189                                          * pixels after end of last line */
 190         R_07_H_SYNC_STOP, 0xe8,         /* HSS seems to be needed to
 191                                          * work with NTSC, too */
 192         R_08_SYNC_CNTL, 0xc8,           /* AUFD=1, FSEL=1, EXFIL=0,
 193                                          * VTRC=1, HPLL=0, VNOI=0 */
 194         R_09_LUMA_CNTL, 0x01,           /* BYPS=0, PREF=0, BPSS=0,
 195                                          * VBLB=0, UPTCV=0, APER=1 */
 196         R_0A_LUMA_BRIGHT_CNTL, 0x80,
 197         R_0B_LUMA_CONTRAST_CNTL, 0x47,  /* 0b - CONT=1.109 */
 198         R_0C_CHROMA_SAT_CNTL, 0x40,
 199         R_0D_CHROMA_HUE_CNTL, 0x00,
 200         R_0E_CHROMA_CNTL_1, 0x01,       /* 0e - CDTO=0, CSTD=0, DCCF=0,
 201                                          * FCTC=0, CHBW=1 */
 202         R_0F_CHROMA_GAIN_CNTL, 0x00,    /* reserved */
 203         R_10_CHROMA_CNTL_2, 0x48,       /* 10 - OFTS=1, HDEL=0, VRLN=1, YDEL=0 */
 204         R_11_MODE_DELAY_CNTL, 0x1c,     /* 11 - GPSW=0, CM99=0, FECO=0, COMPO=1,
 205                                          * OEYC=1, OEHV=1, VIPB=0, COLO=0 */
 206         R_12_RT_SIGNAL_CNTL, 0x00,      /* 12 - output control 2 */
 207         R_13_RT_X_PORT_OUT_CNTL, 0x00,  /* 13 - output control 3 */
 208         R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
 209         R_15_VGATE_START_FID_CHG, 0x00,
 210         R_16_VGATE_STOP, 0x00,
 211         R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
 212
 213         0x00, 0x00
 214 };
 215
 216 /* SAA7113 init codes */
 217 static const unsigned char saa7113_init[] = {
 218         R_01_INC_DELAY, 0x08,
 219         R_02_INPUT_CNTL_1, 0xc2,
 220         R_03_INPUT_CNTL_2, 0x30,
 221         R_04_INPUT_CNTL_3, 0x00,
 222         R_05_INPUT_CNTL_4, 0x00,
 223         R_06_H_SYNC_START, 0x89,
 224         R_07_H_SYNC_STOP, 0x0d,
 225         R_08_SYNC_CNTL, 0x88,
 226         R_09_LUMA_CNTL, 0x01,
 227         R_0A_LUMA_BRIGHT_CNTL, 0x80,
 228         R_0B_LUMA_CONTRAST_CNTL, 0x47,
 229         R_0C_CHROMA_SAT_CNTL, 0x40,
 230         R_0D_CHROMA_HUE_CNTL, 0x00,
 231         R_0E_CHROMA_CNTL_1, 0x01,
 232         R_0F_CHROMA_GAIN_CNTL, 0x2a,
 233         R_10_CHROMA_CNTL_2, 0x08,
 234         R_11_MODE_DELAY_CNTL, 0x0c,
 235         R_12_RT_SIGNAL_CNTL, 0x07,
 236         R_13_RT_X_PORT_OUT_CNTL, 0x00,
 237         R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
 238         R_15_VGATE_START_FID_CHG, 0x00,
 239         R_16_VGATE_STOP, 0x00,
 240         R_17_MISC_VGATE_CONF_AND_MSB, 0x00,
 241
 242         0x00, 0x00
 243 };
 244
 245 /* If a value differs from the Hauppauge driver values, then the comment starts with
 246    'was 0xXX' to denote the Hauppauge value. Otherwise the value is identical to what the
 247    Hauppauge driver sets. */
 248
 249 /* SAA7114 and SAA7115 initialization table */
 250 static const unsigned char saa7115_init_auto_input[] = {
 251                 /* Front-End Part */
 252         R_01_INC_DELAY, 0x48,                   /* white peak control disabled */
 253         R_03_INPUT_CNTL_2, 0x20,                /* was 0x30. 0x20: long vertical blanking */
 254         R_04_INPUT_CNTL_3, 0x90,                /* analog gain set to 0 */
 255         R_05_INPUT_CNTL_4, 0x90,                /* analog gain set to 0 */
 256                 /* Decoder Part */
 257         R_06_H_SYNC_START, 0xeb,                /* horiz sync begin = -21 */
 258         R_07_H_SYNC_STOP, 0xe0,                 /* horiz sync stop = -17 */
 259         R_09_LUMA_CNTL, 0x53,                   /* 0x53, was 0x56 for 60hz. luminance control */
 260         R_0A_LUMA_BRIGHT_CNTL, 0x80,            /* was 0x88. decoder brightness, 0x80 is itu standard */
 261         R_0B_LUMA_CONTRAST_CNTL, 0x44,          /* was 0x48. decoder contrast, 0x44 is itu standard */
 262         R_0C_CHROMA_SAT_CNTL, 0x40,             /* was 0x47. decoder saturation, 0x40 is itu standard */
 263         R_0D_CHROMA_HUE_CNTL, 0x00,
 264         R_0F_CHROMA_GAIN_CNTL, 0x00,            /* use automatic gain  */
 265         R_10_CHROMA_CNTL_2, 0x06,               /* chroma: active adaptive combfilter */
 266         R_11_MODE_DELAY_CNTL, 0x00,
 267         R_12_RT_SIGNAL_CNTL, 0x9d,              /* RTS0 output control: VGATE */
 268         R_13_RT_X_PORT_OUT_CNTL, 0x80,          /* ITU656 standard mode, RTCO output enable RTCE */
 269         R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
 270         R_18_RAW_DATA_GAIN_CNTL, 0x40,          /* gain 0x00 = nominal */
 271         R_19_RAW_DATA_OFF_CNTL, 0x80,
 272         R_1A_COLOR_KILL_LVL_CNTL, 0x77,         /* recommended value */
 273         R_1B_MISC_TVVCRDET, 0x42,               /* recommended value */
 274         R_1C_ENHAN_COMB_CTRL1, 0xa9,            /* recommended value */
 275         R_1D_ENHAN_COMB_CTRL2, 0x01,            /* recommended value */
 276
 277
 278         R_80_GLOBAL_CNTL_1, 0x0,                /* No tasks enabled at init */
 279
 280                 /* Power Device Control */
 281         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,    /* reset device */
 282         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,    /* set device programmed, all in operational mode */
 283         0x00, 0x00
 284 };
 285
 286 /* Used to reset saa7113, saa7114 and saa7115 */
 287 static const unsigned char saa7115_cfg_reset_scaler[] = {
 288         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00,    /* disable I-port output */
 289         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,            /* reset scaler */
 290         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,            /* activate scaler */
 291         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,    /* enable I-port output */
 292         0x00, 0x00
 293 };
 294
 295 /* ============== SAA7715 VIDEO templates =============  */
 296
 297 static const unsigned char saa7115_cfg_60hz_video[] = {
 298         R_80_GLOBAL_CNTL_1, 0x00,                       /* reset tasks */
 299         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,            /* reset scaler */
 300
 301         R_15_VGATE_START_FID_CHG, 0x03,
 302         R_16_VGATE_STOP, 0x11,
 303         R_17_MISC_VGATE_CONF_AND_MSB, 0x9c,
 304
 305         R_08_SYNC_CNTL, 0x68,                   /* 0xBO: auto detection, 0x68 = NTSC */
 306         R_0E_CHROMA_CNTL_1, 0x07,               /* video autodetection is on */
 307
 308         R_5A_V_OFF_FOR_SLICER, 0x06,            /* standard 60hz value for ITU656 line counting */
 309
 310         /* Task A */
 311         R_90_A_TASK_HANDLING_CNTL, 0x80,
 312         R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
 313         R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
 314         R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
 315
 316         /* hoffset low (input), 0x0002 is minimum */
 317         R_94_A_HORIZ_INPUT_WINDOW_START, 0x01,
 318         R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
 319
 320         /* hsize low (input), 0x02d0 = 720 */
 321         R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
 322         R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
 323
 324         R_98_A_VERT_INPUT_WINDOW_START, 0x05,
 325         R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
 326
 327         R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x0c,
 328         R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
 329
 330         R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
 331         R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,
 332
 333         R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c,
 334         R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
 335
 336         /* Task B */
 337         R_C0_B_TASK_HANDLING_CNTL, 0x00,
 338         R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
 339         R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
 340         R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
 341
 342         /* 0x0002 is minimum */
 343         R_C4_B_HORIZ_INPUT_WINDOW_START, 0x02,
 344         R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
 345
 346         /* 0x02d0 = 720 */
 347         R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
 348         R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
 349
 350         /* vwindow start 0x12 = 18 */
 351         R_C8_B_VERT_INPUT_WINDOW_START, 0x12,
 352         R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
 353
 354         /* vwindow length 0xf8 = 248 */
 355         R_CA_B_VERT_INPUT_WINDOW_LENGTH, VRES_60HZ>>1,
 356         R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, VRES_60HZ>>9,
 357
 358         /* hwindow 0x02d0 = 720 */
 359         R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
 360         R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
 361
 362         R_F0_LFCO_PER_LINE, 0xad,               /* Set PLL Register. 60hz 525 lines per frame, 27 MHz */
 363         R_F1_P_I_PARAM_SELECT, 0x05,            /* low bit with 0xF0 */
 364         R_F5_PULSGEN_LINE_LENGTH, 0xad,
 365         R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
 366
 367         0x00, 0x00
 368 };
 369
 370 static const unsigned char saa7115_cfg_50hz_video[] = {
 371         R_80_GLOBAL_CNTL_1, 0x00,
 372         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,    /* reset scaler */
 373
 374         R_15_VGATE_START_FID_CHG, 0x37,         /* VGATE start */
 375         R_16_VGATE_STOP, 0x16,
 376         R_17_MISC_VGATE_CONF_AND_MSB, 0x99,
 377
 378         R_08_SYNC_CNTL, 0x28,                   /* 0x28 = PAL */
 379         R_0E_CHROMA_CNTL_1, 0x07,
 380
 381         R_5A_V_OFF_FOR_SLICER, 0x03,            /* standard 50hz value */
 382
 383         /* Task A */
 384         R_90_A_TASK_HANDLING_CNTL, 0x81,
 385         R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
 386         R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
 387         R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,
 388
 389         /* This is weird: the datasheet says that you should use 2 as the minimum value, */
 390         /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
 391         /* hoffset low (input), 0x0002 is minimum */
 392         R_94_A_HORIZ_INPUT_WINDOW_START, 0x00,
 393         R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
 394
 395         /* hsize low (input), 0x02d0 = 720 */
 396         R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
 397         R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
 398
 399         R_98_A_VERT_INPUT_WINDOW_START, 0x03,
 400         R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,
 401
 402         /* vsize 0x12 = 18 */
 403         R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x12,
 404         R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,
 405
 406         /* hsize 0x05a0 = 1440 */
 407         R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
 408         R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,    /* hsize hi (output) */
 409         R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12,         /* vsize low (output), 0x12 = 18 */
 410         R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,     /* vsize hi (output) */
 411
 412         /* Task B */
 413         R_C0_B_TASK_HANDLING_CNTL, 0x00,
 414         R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
 415         R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
 416         R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,
 417
 418         /* This is weird: the datasheet says that you should use 2 as the minimum value, */
 419         /* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
 420         /* hoffset low (input), 0x0002 is minimum. See comment above. */
 421         R_C4_B_HORIZ_INPUT_WINDOW_START, 0x00,
 422         R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,
 423
 424         /* hsize 0x02d0 = 720 */
 425         R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
 426         R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,
 427
 428         /* voffset 0x16 = 22 */
 429         R_C8_B_VERT_INPUT_WINDOW_START, 0x16,
 430         R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,
 431
 432         /* vsize 0x0120 = 288 */
 433         R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0x20,
 434         R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01,
 435
 436         /* hsize 0x02d0 = 720 */
 437         R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
 438         R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,
 439
 440         R_F0_LFCO_PER_LINE, 0xb0,               /* Set PLL Register. 50hz 625 lines per frame, 27 MHz */
 441         R_F1_P_I_PARAM_SELECT, 0x05,            /* low bit with 0xF0, (was 0x05) */
 442         R_F5_PULSGEN_LINE_LENGTH, 0xb0,
 443         R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,
 444
 445         0x00, 0x00
 446 };
 447
 448 /* ============== SAA7715 VIDEO templates (end) =======  */
 449
 450 static const unsigned char saa7115_cfg_vbi_on[] = {
 451         R_80_GLOBAL_CNTL_1, 0x00,                       /* reset tasks */
 452         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,            /* reset scaler */
 453         R_80_GLOBAL_CNTL_1, 0x30,                       /* Activate both tasks */
 454         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,            /* activate scaler */
 455         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,    /* Enable I-port output */
 456
 457         0x00, 0x00
 458 };
 459
 460 static const unsigned char saa7115_cfg_vbi_off[] = {
 461         R_80_GLOBAL_CNTL_1, 0x00,                       /* reset tasks */
 462         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,            /* reset scaler */
 463         R_80_GLOBAL_CNTL_1, 0x20,                       /* Activate only task "B" */
 464         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,            /* activate scaler */
 465         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,    /* Enable I-port output */
 466
 467         0x00, 0x00
 468 };
 469
 470
 471 static const unsigned char saa7115_init_misc[] = {
 472         R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01,
 473         R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 0x01,
 474         R_84_I_PORT_SIGNAL_DEF, 0x20,
 475         R_85_I_PORT_SIGNAL_POLAR, 0x21,
 476         R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT, 0xc5,
 477         R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,
 478
 479         /* Task A */
 480         R_A0_A_HORIZ_PRESCALING, 0x01,
 481         R_A1_A_ACCUMULATION_LENGTH, 0x00,
 482         R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
 483
 484         /* Configure controls at nominal value*/
 485         R_A4_A_LUMA_BRIGHTNESS_CNTL, 0x80,
 486         R_A5_A_LUMA_CONTRAST_CNTL, 0x40,
 487         R_A6_A_CHROMA_SATURATION_CNTL, 0x40,
 488
 489         /* note: 2 x zoom ensures that VBI lines have same length as video lines. */
 490         R_A8_A_HORIZ_LUMA_SCALING_INC, 0x00,
 491         R_A9_A_HORIZ_LUMA_SCALING_INC_MSB, 0x02,
 492
 493         R_AA_A_HORIZ_LUMA_PHASE_OFF, 0x00,
 494
 495         /* must be horiz lum scaling / 2 */
 496         R_AC_A_HORIZ_CHROMA_SCALING_INC, 0x00,
 497         R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01,
 498
 499         /* must be offset luma / 2 */
 500         R_AE_A_HORIZ_CHROMA_PHASE_OFF, 0x00,
 501
 502         R_B0_A_VERT_LUMA_SCALING_INC, 0x00,
 503         R_B1_A_VERT_LUMA_SCALING_INC_MSB, 0x04,
 504
 505         R_B2_A_VERT_CHROMA_SCALING_INC, 0x00,
 506         R_B3_A_VERT_CHROMA_SCALING_INC_MSB, 0x04,
 507
 508         R_B4_A_VERT_SCALING_MODE_CNTL, 0x01,
 509
 510         R_B8_A_VERT_CHROMA_PHASE_OFF_00, 0x00,
 511         R_B9_A_VERT_CHROMA_PHASE_OFF_01, 0x00,
 512         R_BA_A_VERT_CHROMA_PHASE_OFF_10, 0x00,
 513         R_BB_A_VERT_CHROMA_PHASE_OFF_11, 0x00,
 514
 515         R_BC_A_VERT_LUMA_PHASE_OFF_00, 0x00,
 516         R_BD_A_VERT_LUMA_PHASE_OFF_01, 0x00,
 517         R_BE_A_VERT_LUMA_PHASE_OFF_10, 0x00,
 518         R_BF_A_VERT_LUMA_PHASE_OFF_11, 0x00,
 519
 520         /* Task B */
 521         R_D0_B_HORIZ_PRESCALING, 0x01,
 522         R_D1_B_ACCUMULATION_LENGTH, 0x00,
 523         R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,
 524
 525         /* Configure controls at nominal value*/
 526         R_D4_B_LUMA_BRIGHTNESS_CNTL, 0x80,
 527         R_D5_B_LUMA_CONTRAST_CNTL, 0x40,
 528         R_D6_B_CHROMA_SATURATION_CNTL, 0x40,
 529
 530         /* hor lum scaling 0x0400 = 1 */
 531         R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,
 532         R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,
 533
 534         R_DA_B_HORIZ_LUMA_PHASE_OFF, 0x00,
 535
 536         /* must be hor lum scaling / 2 */
 537         R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
 538         R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,
 539
 540         /* must be offset luma / 2 */
 541         R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00,
 542
 543         R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
 544         R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,
 545
 546         R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
 547         R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,
 548
 549         R_E4_B_VERT_SCALING_MODE_CNTL, 0x01,
 550
 551         R_E8_B_VERT_CHROMA_PHASE_OFF_00, 0x00,
 552         R_E9_B_VERT_CHROMA_PHASE_OFF_01, 0x00,
 553         R_EA_B_VERT_CHROMA_PHASE_OFF_10, 0x00,
 554         R_EB_B_VERT_CHROMA_PHASE_OFF_11, 0x00,
 555
 556         R_EC_B_VERT_LUMA_PHASE_OFF_00, 0x00,
 557         R_ED_B_VERT_LUMA_PHASE_OFF_01, 0x00,
 558         R_EE_B_VERT_LUMA_PHASE_OFF_10, 0x00,
 559         R_EF_B_VERT_LUMA_PHASE_OFF_11, 0x00,
 560
 561         R_F2_NOMINAL_PLL2_DTO, 0x50,            /* crystal clock = 24.576 MHz, target = 27MHz */
 562         R_F3_PLL_INCREMENT, 0x46,
 563         R_F4_PLL2_STATUS, 0x00,
 564         R_F7_PULSE_A_POS_MSB, 0x4b,             /* not the recommended settings! */
 565         R_F8_PULSE_B_POS, 0x00,
 566         R_F9_PULSE_B_POS_MSB, 0x4b,
 567         R_FA_PULSE_C_POS, 0x00,
 568         R_FB_PULSE_C_POS_MSB, 0x4b,
 569
 570         /* PLL2 lock detection settings: 71 lines 50% phase error */
 571         R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88,
 572
 573         /* Turn off VBI */
 574         R_40_SLICER_CNTL_1, 0x20,             /* No framing code errors allowed. */
 575         R_41_LCR_BASE, 0xff,
 576         R_41_LCR_BASE+1, 0xff,
 577         R_41_LCR_BASE+2, 0xff,
 578         R_41_LCR_BASE+3, 0xff,
 579         R_41_LCR_BASE+4, 0xff,
 580         R_41_LCR_BASE+5, 0xff,
 581         R_41_LCR_BASE+6, 0xff,
 582         R_41_LCR_BASE+7, 0xff,
 583         R_41_LCR_BASE+8, 0xff,
 584         R_41_LCR_BASE+9, 0xff,
 585         R_41_LCR_BASE+10, 0xff,
 586         R_41_LCR_BASE+11, 0xff,
 587         R_41_LCR_BASE+12, 0xff,
 588         R_41_LCR_BASE+13, 0xff,
 589         R_41_LCR_BASE+14, 0xff,
 590         R_41_LCR_BASE+15, 0xff,
 591         R_41_LCR_BASE+16, 0xff,
 592         R_41_LCR_BASE+17, 0xff,
 593         R_41_LCR_BASE+18, 0xff,
 594         R_41_LCR_BASE+19, 0xff,
 595         R_41_LCR_BASE+20, 0xff,
 596         R_41_LCR_BASE+21, 0xff,
 597         R_41_LCR_BASE+22, 0xff,
 598         R_58_PROGRAM_FRAMING_CODE, 0x40,
 599         R_59_H_OFF_FOR_SLICER, 0x47,
 600         R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF, 0x83,
 601         R_5D_DID, 0xbd,
 602         R_5E_SDID, 0x35,
 603
 604         R_02_INPUT_CNTL_1, 0xc4, /* input tuner -> input 4, amplifier active */
 605
 606         R_80_GLOBAL_CNTL_1, 0x20,               /* enable task B */
 607         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,
 608         R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,
 609         0x00, 0x00
 610 };
 611
 612 static int saa711x_odd_parity(u8 c)
 613 {
 614         c ^= (c >> 4);
 615         c ^= (c >> 2);
 616         c ^= (c >> 1);
 617
 618         return c & 1;
 619 }
 620
 621 static int saa711x_decode_vps(u8 *dst, u8 *p)
 622 {
 623         static const u8 biphase_tbl[] = {
 624                 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
 625                 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
 626                 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
 627                 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
 628                 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
 629                 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
 630                 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
 631                 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
 632                 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
 633                 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
 634                 0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87,
 635                 0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3,
 636                 0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85,
 637                 0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1,
 638                 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
 639                 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
 640                 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
 641                 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
 642                 0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86,
 643                 0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2,
 644                 0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84,
 645                 0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0,
 646                 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
 647                 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
 648                 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
 649                 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
 650                 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
 651                 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
 652                 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
 653                 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
 654                 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
 655                 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
 656         };
 657         int i;
 658         u8 c, err = 0;
 659
 660         for (i = 0; i < 2 * 13; i += 2) {
 661                 err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]];
 662                 c = (biphase_tbl[p[i + 1]] & 0xf) | ((biphase_tbl[p[i]] & 0xf) << 4);
 663                 dst[i / 2] = c;
 664         }
 665         return err & 0xf0;
 666 }
 667
 668 static int saa711x_decode_wss(u8 *p)
 669 {
 670         static const int wss_bits[8] = {
 671                 0, 0, 0, 1, 0, 1, 1, 1
 672         };
 673         unsigned char parity;
 674         int wss = 0;
 675         int i;
 676
 677         for (i = 0; i < 16; i++) {
 678                 int b1 = wss_bits[p[i] & 7];
 679                 int b2 = wss_bits[(p[i] >> 3) & 7];
 680
 681                 if (b1 == b2)
 682                         return -1;
 683                 wss |= b2 << i;
 684         }
 685         parity = wss & 15;
 686         parity ^= parity >> 2;
 687         parity ^= parity >> 1;
 688
 689         if (!(parity & 1))
 690                 return -1;
 691
 692         return wss;
 693 }
 694
 695 static int saa711x_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
 696 {
 697         struct saa711x_state *state = to_state(sd);
 698         u32 acpf;
 699         u32 acni;
 700         u32 hz;
 701         u64 f;
 702         u8 acc = 0;     /* reg 0x3a, audio clock control */
 703
 704         /* Checks for chips that don't have audio clock (saa7111, saa7113) */
 705         if (!saa711x_has_reg(state->ident, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD))
 706                 return 0;
 707
 708         v4l2_dbg(1, debug, sd, "set audio clock freq: %d\n", freq);
 709
 710         /* sanity check */
 711         if (freq < 32000 || freq > 48000)
 712                 return -EINVAL;
 713
 714         /* hz is the refresh rate times 100 */
 715         hz = (state->std & V4L2_STD_525_60) ? 5994 : 5000;
 716         /* acpf = (256 * freq) / field_frequency == (256 * 100 * freq) / hz */
 717         acpf = (25600 * freq) / hz;
 718         /* acni = (256 * freq * 2^23) / crystal_frequency =
 719                   (freq * 2^(8+23)) / crystal_frequency =
 720                   (freq << 31) / crystal_frequency */
 721         f = freq;
 722         f = f << 31;
 723         do_div(f, state->crystal_freq);
 724         acni = f;
 725         if (state->ucgc) {
 726                 acpf = acpf * state->cgcdiv / 16;
 727                 acni = acni * state->cgcdiv / 16;
 728                 acc = 0x80;
 729                 if (state->cgcdiv == 3)
 730                         acc |= 0x40;
 731         }
 732         if (state->apll)
 733                 acc |= 0x08;
 734
 735         saa711x_write(sd, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03);
 736         saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10);
 737         saa711x_write(sd, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc);
 738
 739         saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff);
 740         saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1,
 741                                                         (acpf >> 8) & 0xff);
 742         saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2,
 743                                                         (acpf >> 16) & 0x03);
 744
 745         saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff);
 746         saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff);
 747         saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f);
 748         state->audclk_freq = freq;
 749         return 0;
 750 }
 751
 752 static int saa711x_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
 753 {
 754         struct v4l2_subdev *sd = to_sd(ctrl);
 755         struct saa711x_state *state = to_state(sd);
 756
 757         switch (ctrl->id) {
 758         case V4L2_CID_CHROMA_AGC:
 759                 /* chroma gain cluster */
 760                 if (state->agc->val)
 761                         state->gain->val =
 762                                 saa711x_read(sd, R_0F_CHROMA_GAIN_CNTL) & 0x7f;
 763                 break;
 764         }
 765         return 0;
 766 }
 767
 768 static int saa711x_s_ctrl(struct v4l2_ctrl *ctrl)
 769 {
 770         struct v4l2_subdev *sd = to_sd(ctrl);
 771         struct saa711x_state *state = to_state(sd);
 772
 773         switch (ctrl->id) {
 774         case V4L2_CID_BRIGHTNESS:
 775                 saa711x_write(sd, R_0A_LUMA_BRIGHT_CNTL, ctrl->val);
 776                 break;
 777
 778         case V4L2_CID_CONTRAST:
 779                 saa711x_write(sd, R_0B_LUMA_CONTRAST_CNTL, ctrl->val);
 780                 break;
 781
 782         case V4L2_CID_SATURATION:
 783                 saa711x_write(sd, R_0C_CHROMA_SAT_CNTL, ctrl->val);
 784                 break;
 785
 786         case V4L2_CID_HUE:
 787                 saa711x_write(sd, R_0D_CHROMA_HUE_CNTL, ctrl->val);
 788                 break;
 789
 790         case V4L2_CID_CHROMA_AGC:
 791                 /* chroma gain cluster */
 792                 if (state->agc->val)
 793                         saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val);
 794                 else
 795                         saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val | 0x80);
 796                 break;
 797
 798         default:
 799                 return -EINVAL;
 800         }
 801
 802         return 0;
 803 }
 804
 805 static int saa711x_set_size(struct v4l2_subdev *sd, int width, int height)
 806 {
 807         struct saa711x_state *state = to_state(sd);
 808         int HPSC, HFSC;
 809         int VSCY;
 810         int res;
 811         int is_50hz = state->std & V4L2_STD_625_50;
 812         int Vsrc = is_50hz ? 576 : 480;
 813
 814         v4l2_dbg(1, debug, sd, "decoder set size to %ix%i\n", width, height);
 815
 816         /* FIXME need better bounds checking here */
 817         if ((width < 1) || (width > 1440))
 818                 return -EINVAL;
 819         if ((height < 1) || (height > Vsrc))
 820                 return -EINVAL;
 821
 822         if (!saa711x_has_reg(state->ident, R_D0_B_HORIZ_PRESCALING)) {
 823                 /* Decoder only supports 720 columns and 480 or 576 lines */
 824                 if (width != 720)
 825                         return -EINVAL;
 826                 if (height != Vsrc)
 827                         return -EINVAL;
 828         }
 829
 830         state->width = width;
 831         state->height = height;
 832
 833         if (!saa711x_has_reg(state->ident, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH))
 834                 return 0;
 835
 836         /* probably have a valid size, let's set it */
 837         /* Set output width/height */
 838         /* width */
 839
 840         saa711x_write(sd, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,
 841                                         (u8) (width & 0xff));
 842         saa711x_write(sd, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB,
 843                                         (u8) ((width >> 8) & 0xff));
 844
 845         /* Vertical Scaling uses height/2 */
 846         res = height / 2;
 847
 848         /* On 60Hz, it is using a higher Vertical Output Size */
 849         if (!is_50hz)
 850                 res += (VRES_60HZ - 480) >> 1;
 851
 852                 /* height */
 853         saa711x_write(sd, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,
 854                                         (u8) (res & 0xff));
 855         saa711x_write(sd, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB,
 856                                         (u8) ((res >> 8) & 0xff));
 857
 858         /* Scaling settings */
 859         /* Hprescaler is floor(inres/outres) */
 860         HPSC = (int)(720 / width);
 861         /* 0 is not allowed (div. by zero) */
 862         HPSC = HPSC ? HPSC : 1;
 863         HFSC = (int)((1024 * 720) / (HPSC * width));
 864         /* FIXME hardcodes to "Task B"
 865          * write H prescaler integer */
 866         saa711x_write(sd, R_D0_B_HORIZ_PRESCALING,
 867                                 (u8) (HPSC & 0x3f));
 868
 869         v4l2_dbg(1, debug, sd, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC);
 870         /* write H fine-scaling (luminance) */
 871         saa711x_write(sd, R_D8_B_HORIZ_LUMA_SCALING_INC,
 872                                 (u8) (HFSC & 0xff));
 873         saa711x_write(sd, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB,
 874                                 (u8) ((HFSC >> 8) & 0xff));
 875         /* write H fine-scaling (chrominance)
 876          * must be lum/2, so i'll just bitshift :) */
 877         saa711x_write(sd, R_DC_B_HORIZ_CHROMA_SCALING,
 878                                 (u8) ((HFSC >> 1) & 0xff));
 879         saa711x_write(sd, R_DD_B_HORIZ_CHROMA_SCALING_MSB,
 880                                 (u8) ((HFSC >> 9) & 0xff));
 881
 882         VSCY = (int)((1024 * Vsrc) / height);
 883         v4l2_dbg(1, debug, sd, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY);
 884
 885         /* Correct Contrast and Luminance */
 886         saa711x_write(sd, R_D5_B_LUMA_CONTRAST_CNTL,
 887                                         (u8) (64 * 1024 / VSCY));
 888         saa711x_write(sd, R_D6_B_CHROMA_SATURATION_CNTL,
 889                                         (u8) (64 * 1024 / VSCY));
 890
 891                 /* write V fine-scaling (luminance) */
 892         saa711x_write(sd, R_E0_B_VERT_LUMA_SCALING_INC,
 893                                         (u8) (VSCY & 0xff));
 894         saa711x_write(sd, R_E1_B_VERT_LUMA_SCALING_INC_MSB,
 895                                         (u8) ((VSCY >> 8) & 0xff));
 896                 /* write V fine-scaling (chrominance) */
 897         saa711x_write(sd, R_E2_B_VERT_CHROMA_SCALING_INC,
 898                                         (u8) (VSCY & 0xff));
 899         saa711x_write(sd, R_E3_B_VERT_CHROMA_SCALING_INC_MSB,
 900                                         (u8) ((VSCY >> 8) & 0xff));
 901
 902         saa711x_writeregs(sd, saa7115_cfg_reset_scaler);
 903
 904         /* Activates task "B" */
 905         saa711x_write(sd, R_80_GLOBAL_CNTL_1,
 906                                 saa711x_read(sd, R_80_GLOBAL_CNTL_1) | 0x20);
 907
 908         return 0;
 909 }
 910
 911 static void saa711x_set_v4lstd(struct v4l2_subdev *sd, v4l2_std_id std)
 912 {
 913         struct saa711x_state *state = to_state(sd);
 914
 915         /* Prevent unnecessary standard changes. During a standard
 916            change the I-Port is temporarily disabled. Any devices
 917            reading from that port can get confused.
 918            Note that s_std is also used to switch from
 919            radio to TV mode, so if a s_std is broadcast to
 920            all I2C devices then you do not want to have an unwanted
 921            side-effect here. */
 922         if (std == state->std)
 923                 return;
 924
 925         state->std = std;
 926
 927         // This works for NTSC-M, SECAM-L and the 50Hz PAL variants.
 928         if (std & V4L2_STD_525_60) {
 929                 v4l2_dbg(1, debug, sd, "decoder set standard 60 Hz\n");
 930                 saa711x_writeregs(sd, saa7115_cfg_60hz_video);
 931                 saa711x_set_size(sd, 720, 480);
 932         } else {
 933                 v4l2_dbg(1, debug, sd, "decoder set standard 50 Hz\n");
 934                 saa711x_writeregs(sd, saa7115_cfg_50hz_video);
 935                 saa711x_set_size(sd, 720, 576);
 936         }
 937
 938         /* Register 0E - Bits D6-D4 on NO-AUTO mode
 939                 (SAA7111 and SAA7113 doesn't have auto mode)
 940             50 Hz / 625 lines           60 Hz / 525 lines
 941         000 PAL BGDHI (4.43Mhz)         NTSC M (3.58MHz)
 942         001 NTSC 4.43 (50 Hz)           PAL 4.43 (60 Hz)
 943         010 Combination-PAL N (3.58MHz) NTSC 4.43 (60 Hz)
 944         011 NTSC N (3.58MHz)            PAL M (3.58MHz)
 945         100 reserved                    NTSC-Japan (3.58MHz)
 946         */
 947         if (state->ident <= V4L2_IDENT_SAA7113) {
 948                 u8 reg = saa711x_read(sd, R_0E_CHROMA_CNTL_1) & 0x8f;
 949
 950                 if (std == V4L2_STD_PAL_M) {
 951                         reg |= 0x30;
 952                 } else if (std == V4L2_STD_PAL_Nc) {
 953                         reg |= 0x20;
 954                 } else if (std == V4L2_STD_PAL_60) {
 955                         reg |= 0x10;
 956                 } else if (std == V4L2_STD_NTSC_M_JP) {
 957                         reg |= 0x40;
 958                 } else if (std & V4L2_STD_SECAM) {
 959                         reg |= 0x50;
 960                 }
 961                 saa711x_write(sd, R_0E_CHROMA_CNTL_1, reg);
 962         } else {
 963                 /* restart task B if needed */
 964                 int taskb = saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10;
 965
 966                 if (taskb && state->ident == V4L2_IDENT_SAA7114) {
 967                         saa711x_writeregs(sd, saa7115_cfg_vbi_on);
 968                 }
 969
 970                 /* switch audio mode too! */
 971                 saa711x_s_clock_freq(sd, state->audclk_freq);
 972         }
 973 }
 974
 975 /* setup the sliced VBI lcr registers according to the sliced VBI format */
 976 static void saa711x_set_lcr(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt)
 977 {
 978         struct saa711x_state *state = to_state(sd);
 979         int is_50hz = (state->std & V4L2_STD_625_50);
 980         u8 lcr[24];
 981         int i, x;
 982
 983 #if 1
 984         /* saa7113/7114/7118 VBI support are experimental */
 985         if (!saa711x_has_reg(state->ident, R_41_LCR_BASE))
 986                 return;
 987
 988 #else
 989         /* SAA7113 and SAA7118 also should support VBI - Need testing */
 990         if (state->ident != V4L2_IDENT_SAA7115)
 991                 return;
 992 #endif
 993
 994         for (i = 0; i <= 23; i++)
 995                 lcr[i] = 0xff;
 996
 997         if (fmt == NULL) {
 998                 /* raw VBI */
 999                 if (is_50hz)
1000                         for (i = 6; i <= 23; i++)
1001                                 lcr[i] = 0xdd;
1002                 else
1003                         for (i = 10; i <= 21; i++)
1004                                 lcr[i] = 0xdd;
1005         } else {
1006                 /* sliced VBI */
1007                 /* first clear lines that cannot be captured */
1008                 if (is_50hz) {
1009                         for (i = 0; i <= 5; i++)
1010                                 fmt->service_lines[0][i] =
1011                                         fmt->service_lines[1][i] = 0;
1012                 }
1013                 else {
1014                         for (i = 0; i <= 9; i++)
1015                                 fmt->service_lines[0][i] =
1016                                         fmt->service_lines[1][i] = 0;
1017                         for (i = 22; i <= 23; i++)
1018                                 fmt->service_lines[0][i] =
1019                                         fmt->service_lines[1][i] = 0;
1020                 }
1021
1022                 /* Now set the lcr values according to the specified service */
1023                 for (i = 6; i <= 23; i++) {
1024                         lcr[i] = 0;
1025                         for (x = 0; x <= 1; x++) {
1026                                 switch (fmt->service_lines[1-x][i]) {
1027                                         case 0:
1028                                                 lcr[i] |= 0xf << (4 * x);
1029                                                 break;
1030                                         case V4L2_SLICED_TELETEXT_B:
1031                                                 lcr[i] |= 1 << (4 * x);
1032                                                 break;
1033                                         case V4L2_SLICED_CAPTION_525:
1034                                                 lcr[i] |= 4 << (4 * x);
1035                                                 break;
1036                                         case V4L2_SLICED_WSS_625:
1037                                                 lcr[i] |= 5 << (4 * x);
1038                                                 break;
1039                                         case V4L2_SLICED_VPS:
1040                                                 lcr[i] |= 7 << (4 * x);
1041                                                 break;
1042                                 }
1043                         }
1044                 }
1045         }
1046
1047         /* write the lcr registers */
1048         for (i = 2; i <= 23; i++) {
1049                 saa711x_write(sd, i - 2 + R_41_LCR_BASE, lcr[i]);
1050         }
1051
1052         /* enable/disable raw VBI capturing */
1053         saa711x_writeregs(sd, fmt == NULL ?
1054                                 saa7115_cfg_vbi_on :
1055                                 saa7115_cfg_vbi_off);
1056 }
1057
1058 static int saa711x_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *sliced)
1059 {
1060         static u16 lcr2vbi[] = {
1061                 0, V4L2_SLICED_TELETEXT_B, 0,   /* 1 */
1062                 0, V4L2_SLICED_CAPTION_525,     /* 4 */
1063                 V4L2_SLICED_WSS_625, 0,         /* 5 */
1064                 V4L2_SLICED_VPS, 0, 0, 0, 0,    /* 7 */
1065                 0, 0, 0, 0
1066         };
1067         int i;
1068
1069         memset(sliced->service_lines, 0, sizeof(sliced->service_lines));
1070         sliced->service_set = 0;
1071         /* done if using raw VBI */
1072         if (saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10)
1073                 return 0;
1074         for (i = 2; i <= 23; i++) {
1075                 u8 v = saa711x_read(sd, i - 2 + R_41_LCR_BASE);
1076
1077                 sliced->service_lines[0][i] = lcr2vbi[v >> 4];
1078                 sliced->service_lines[1][i] = lcr2vbi[v & 0xf];
1079                 sliced->service_set |=
1080                         sliced->service_lines[0][i] | sliced->service_lines[1][i];
1081         }
1082         return 0;
1083 }
1084
1085 static int saa711x_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt)
1086 {
1087         saa711x_set_lcr(sd, NULL);
1088         return 0;
1089 }
1090
1091 static int saa711x_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt)
1092 {
1093         saa711x_set_lcr(sd, fmt);
1094         return 0;
1095 }
1096
1097 static int saa711x_s_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
1098 {
1099         if (fmt->code != V4L2_MBUS_FMT_FIXED)
1100                 return -EINVAL;
1101         fmt->field = V4L2_FIELD_INTERLACED;
1102         fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
1103         return saa711x_set_size(sd, fmt->width, fmt->height);
1104 }
1105
1106 /* Decode the sliced VBI data stream as created by the saa7115.
1107    The format is described in the saa7115 datasheet in Tables 25 and 26
1108    and in Figure 33.
1109    The current implementation uses SAV/EAV codes and not the ancillary data
1110    headers. The vbi->p pointer points to the R_5E_SDID byte right after the SAV
1111    code. */
1112 static int saa711x_decode_vbi_line(struct v4l2_subdev *sd, struct v4l2_decode_vbi_line *vbi)
1113 {
1114         struct saa711x_state *state = to_state(sd);
1115         static const char vbi_no_data_pattern[] = {
1116                 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0
1117         };
1118         u8 *p = vbi->p;
1119         u32 wss;
1120         int id1, id2;   /* the ID1 and ID2 bytes from the internal header */
1121
1122         vbi->type = 0;  /* mark result as a failure */
1123         id1 = p[2];
1124         id2 = p[3];
1125         /* Note: the field bit is inverted for 60 Hz video */
1126         if (state->std & V4L2_STD_525_60)
1127                 id1 ^= 0x40;
1128
1129         /* Skip internal header, p now points to the start of the payload */
1130         p += 4;
1131         vbi->p = p;
1132
1133         /* calculate field and line number of the VBI packet (1-23) */
1134         vbi->is_second_field = ((id1 & 0x40) != 0);
1135         vbi->line = (id1 & 0x3f) << 3;
1136         vbi->line |= (id2 & 0x70) >> 4;
1137
1138         /* Obtain data type */
1139         id2 &= 0xf;
1140
1141         /* If the VBI slicer does not detect any signal it will fill up
1142            the payload buffer with 0xa0 bytes. */
1143         if (!memcmp(p, vbi_no_data_pattern, sizeof(vbi_no_data_pattern)))
1144                 return 0;
1145
1146         /* decode payloads */
1147         switch (id2) {
1148         case 1:
1149                 vbi->type = V4L2_SLICED_TELETEXT_B;
1150                 break;
1151         case 4:
1152                 if (!saa711x_odd_parity(p[0]) || !saa711x_odd_parity(p[1]))
1153                         return 0;
1154                 vbi->type = V4L2_SLICED_CAPTION_525;
1155                 break;
1156         case 5:
1157                 wss = saa711x_decode_wss(p);
1158                 if (wss == -1)
1159                         return 0;
1160                 p[0] = wss & 0xff;
1161                 p[1] = wss >> 8;
1162                 vbi->type = V4L2_SLICED_WSS_625;
1163                 break;
1164         case 7:
1165                 if (saa711x_decode_vps(p, p) != 0)
1166                         return 0;
1167                 vbi->type = V4L2_SLICED_VPS;
1168                 break;
1169         default:
1170                 break;
1171         }
1172         return 0;
1173 }
1174
1175 /* ============ SAA7115 AUDIO settings (end) ============= */
1176
1177 static int saa711x_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1178 {
1179         struct saa711x_state *state = to_state(sd);
1180         int status;
1181
1182         if (state->radio)
1183                 return 0;
1184         status = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1185
1186         v4l2_dbg(1, debug, sd, "status: 0x%02x\n", status);
1187         vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0;
1188         return 0;
1189 }
1190
1191 static int saa711x_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1192 {
1193         struct saa711x_state *state = to_state(sd);
1194
1195         state->radio = 0;
1196         saa711x_set_v4lstd(sd, std);
1197         return 0;
1198 }
1199
1200 static int saa711x_s_radio(struct v4l2_subdev *sd)
1201 {
1202         struct saa711x_state *state = to_state(sd);
1203
1204         state->radio = 1;
1205         return 0;
1206 }
1207
1208 static int saa711x_s_routing(struct v4l2_subdev *sd,
1209                              u32 input, u32 output, u32 config)
1210 {
1211         struct saa711x_state *state = to_state(sd);
1212         u8 mask = (state->ident <= V4L2_IDENT_SAA7111A) ? 0xf8 : 0xf0;
1213
1214         v4l2_dbg(1, debug, sd, "decoder set input %d output %d\n",
1215                 input, output);
1216
1217         /* saa7111/3 does not have these inputs */
1218         if (state->ident <= V4L2_IDENT_SAA7113 &&
1219             (input == SAA7115_COMPOSITE4 ||
1220              input == SAA7115_COMPOSITE5)) {
1221                 return -EINVAL;
1222         }
1223         if (input > SAA7115_SVIDEO3)
1224                 return -EINVAL;
1225         if (state->input == input && state->output == output)
1226                 return 0;
1227         v4l2_dbg(1, debug, sd, "now setting %s input %s output\n",
1228                 (input >= SAA7115_SVIDEO0) ? "S-Video" : "Composite",
1229                 (output == SAA7115_IPORT_ON) ? "iport on" : "iport off");
1230         state->input = input;
1231
1232         /* saa7111 has slightly different input numbering */
1233         if (state->ident <= V4L2_IDENT_SAA7111A) {
1234                 if (input >= SAA7115_COMPOSITE4)
1235                         input -= 2;
1236                 /* saa7111 specific */
1237                 saa711x_write(sd, R_10_CHROMA_CNTL_2,
1238                                 (saa711x_read(sd, R_10_CHROMA_CNTL_2) & 0x3f) |
1239                                 ((output & 0xc0) ^ 0x40));
1240                 saa711x_write(sd, R_13_RT_X_PORT_OUT_CNTL,
1241                                 (saa711x_read(sd, R_13_RT_X_PORT_OUT_CNTL) & 0xf0) |
1242                                 ((output & 2) ? 0x0a : 0));
1243         }
1244
1245         /* select mode */
1246         saa711x_write(sd, R_02_INPUT_CNTL_1,
1247                       (saa711x_read(sd, R_02_INPUT_CNTL_1) & mask) |
1248                        input);
1249
1250         /* bypass chrominance trap for S-Video modes */
1251         saa711x_write(sd, R_09_LUMA_CNTL,
1252                         (saa711x_read(sd, R_09_LUMA_CNTL) & 0x7f) |
1253                         (state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0));
1254
1255         state->output = output;
1256         if (state->ident == V4L2_IDENT_SAA7114 ||
1257                         state->ident == V4L2_IDENT_SAA7115) {
1258                 saa711x_write(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK,
1259                                 (saa711x_read(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK) & 0xfe) |
1260                                 (state->output & 0x01));
1261         }
1262         if (state->ident > V4L2_IDENT_SAA7111A) {
1263                 if (config & SAA7115_IDQ_IS_DEFAULT)
1264                         saa711x_write(sd, R_85_I_PORT_SIGNAL_POLAR, 0x20);
1265                 else
1266                         saa711x_write(sd, R_85_I_PORT_SIGNAL_POLAR, 0x21);
1267         }
1268         return 0;
1269 }
1270
1271 static int saa711x_s_gpio(struct v4l2_subdev *sd, u32 val)
1272 {
1273         struct saa711x_state *state = to_state(sd);
1274
1275         if (state->ident > V4L2_IDENT_SAA7111A)
1276                 return -EINVAL;
1277         saa711x_write(sd, 0x11, (saa711x_read(sd, 0x11) & 0x7f) |
1278                 (val ? 0x80 : 0));
1279         return 0;
1280 }
1281
1282 static int saa711x_s_stream(struct v4l2_subdev *sd, int enable)
1283 {
1284         struct saa711x_state *state = to_state(sd);
1285
1286         v4l2_dbg(1, debug, sd, "%s output\n",
1287                         enable ? "enable" : "disable");
1288
1289         if (state->enable == enable)
1290                 return 0;
1291         state->enable = enable;
1292         if (!saa711x_has_reg(state->ident, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED))
1293                 return 0;
1294         saa711x_write(sd, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, state->enable);
1295         return 0;
1296 }
1297
1298 static int saa711x_s_crystal_freq(struct v4l2_subdev *sd, u32 freq, u32 flags)
1299 {
1300         struct saa711x_state *state = to_state(sd);
1301
1302         if (freq != SAA7115_FREQ_32_11_MHZ && freq != SAA7115_FREQ_24_576_MHZ)
1303                 return -EINVAL;
1304         state->crystal_freq = freq;
1305         state->cgcdiv = (flags & SAA7115_FREQ_FL_CGCDIV) ? 3 : 4;
1306         state->ucgc = (flags & SAA7115_FREQ_FL_UCGC) ? 1 : 0;
1307         state->apll = (flags & SAA7115_FREQ_FL_APLL) ? 1 : 0;
1308         saa711x_s_clock_freq(sd, state->audclk_freq);
1309         return 0;
1310 }
1311
1312 static int saa711x_reset(struct v4l2_subdev *sd, u32 val)
1313 {
1314         v4l2_dbg(1, debug, sd, "decoder RESET\n");
1315         saa711x_writeregs(sd, saa7115_cfg_reset_scaler);
1316         return 0;
1317 }
1318
1319 static int saa711x_g_vbi_data(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_data *data)
1320 {
1321         /* Note: the internal field ID is inverted for NTSC,
1322            so data->field 0 maps to the saa7115 even field,
1323            whereas for PAL it maps to the saa7115 odd field. */
1324         switch (data->id) {
1325         case V4L2_SLICED_WSS_625:
1326                 if (saa711x_read(sd, 0x6b) & 0xc0)
1327                         return -EIO;
1328                 data->data[0] = saa711x_read(sd, 0x6c);
1329                 data->data[1] = saa711x_read(sd, 0x6d);
1330                 return 0;
1331         case V4L2_SLICED_CAPTION_525:
1332                 if (data->field == 0) {
1333                         /* CC */
1334                         if (saa711x_read(sd, 0x66) & 0x30)
1335                                 return -EIO;
1336                         data->data[0] = saa711x_read(sd, 0x69);
1337                         data->data[1] = saa711x_read(sd, 0x6a);
1338                         return 0;
1339                 }
1340                 /* XDS */
1341                 if (saa711x_read(sd, 0x66) & 0xc0)
1342                         return -EIO;
1343                 data->data[0] = saa711x_read(sd, 0x67);
1344                 data->data[1] = saa711x_read(sd, 0x68);
1345                 return 0;
1346         default:
1347                 return -EINVAL;
1348         }
1349 }
1350
1351 static int saa711x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
1352 {
1353         struct saa711x_state *state = to_state(sd);
1354         int reg1f, reg1e;
1355
1356         /*
1357          * The V4L2 core already initializes std with all supported
1358          * Standards. All driver needs to do is to mask it, to remove
1359          * standards that don't apply from the mask
1360          */
1361
1362         reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1363         v4l2_dbg(1, debug, sd, "Status byte 2 (0x1f)=0x%02x\n", reg1f);
1364
1365         /* horizontal/vertical not locked */
1366         if (reg1f & 0x40)
1367                 goto ret;
1368
1369         if (reg1f & 0x20)
1370                 *std &= V4L2_STD_525_60;
1371         else
1372                 *std &= V4L2_STD_625_50;
1373
1374         if (state->ident != V4L2_IDENT_SAA7115)
1375                 goto ret;
1376
1377         reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC);
1378
1379         switch (reg1e & 0x03) {
1380         case 1:
1381                 *std &= V4L2_STD_NTSC;
1382                 break;
1383         case 2:
1384                 /*
1385                  * V4L2_STD_PAL just cover the european PAL standards.
1386                  * This is wrong, as the device could also be using an
1387                  * other PAL standard.
1388                  */
1389                 *std &= V4L2_STD_PAL   | V4L2_STD_PAL_N  | V4L2_STD_PAL_Nc |
1390                         V4L2_STD_PAL_M | V4L2_STD_PAL_60;
1391                 break;
1392         case 3:
1393                 *std &= V4L2_STD_SECAM;
1394                 break;
1395         default:
1396                 /* Can't detect anything */
1397                 break;
1398         }
1399
1400         v4l2_dbg(1, debug, sd, "Status byte 1 (0x1e)=0x%02x\n", reg1e);
1401
1402 ret:
1403         v4l2_dbg(1, debug, sd, "detected std mask = %08Lx\n", *std);
1404
1405         return 0;
1406 }
1407
1408 static int saa711x_g_input_status(struct v4l2_subdev *sd, u32 *status)
1409 {
1410         struct saa711x_state *state = to_state(sd);
1411         int reg1e = 0x80;
1412         int reg1f;
1413
1414         *status = V4L2_IN_ST_NO_SIGNAL;
1415         if (state->ident == V4L2_IDENT_SAA7115)
1416                 reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC);
1417         reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1418         if ((reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80)
1419                 *status = 0;
1420         return 0;
1421 }
1422
1423 #ifdef CONFIG_VIDEO_ADV_DEBUG
1424 static int saa711x_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1425 {
1426         struct i2c_client *client = v4l2_get_subdevdata(sd);
1427
1428         if (!v4l2_chip_match_i2c_client(client, &reg->match))
1429                 return -EINVAL;
1430         if (!capable(CAP_SYS_ADMIN))
1431                 return -EPERM;
1432         reg->val = saa711x_read(sd, reg->reg & 0xff);
1433         reg->size = 1;
1434         return 0;
1435 }
1436
1437 static int saa711x_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
1438 {
1439         struct i2c_client *client = v4l2_get_subdevdata(sd);
1440
1441         if (!v4l2_chip_match_i2c_client(client, &reg->match))
1442                 return -EINVAL;
1443         if (!capable(CAP_SYS_ADMIN))
1444                 return -EPERM;
1445         saa711x_write(sd, reg->reg & 0xff, reg->val & 0xff);
1446         return 0;
1447 }
1448 #endif
1449
1450 static int saa711x_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
1451 {
1452         struct saa711x_state *state = to_state(sd);
1453         struct i2c_client *client = v4l2_get_subdevdata(sd);
1454
1455         return v4l2_chip_ident_i2c_client(client, chip, state->ident, 0);
1456 }
1457
1458 static int saa711x_log_status(struct v4l2_subdev *sd)
1459 {
1460         struct saa711x_state *state = to_state(sd);
1461         int reg1e, reg1f;
1462         int signalOk;
1463         int vcr;
1464
1465         v4l2_info(sd, "Audio frequency: %d Hz\n", state->audclk_freq);
1466         if (state->ident != V4L2_IDENT_SAA7115) {
1467                 /* status for the saa7114 */
1468                 reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1469                 signalOk = (reg1f & 0xc1) == 0x81;
1470                 v4l2_info(sd, "Video signal:    %s\n", signalOk ? "ok" : "bad");
1471                 v4l2_info(sd, "Frequency:       %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
1472                 return 0;
1473         }
1474
1475         /* status for the saa7115 */
1476         reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC);
1477         reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1478
1479         signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80;
1480         vcr = !(reg1f & 0x10);
1481
1482         if (state->input >= 6)
1483                 v4l2_info(sd, "Input:           S-Video %d\n", state->input - 6);
1484         else
1485                 v4l2_info(sd, "Input:           Composite %d\n", state->input);
1486         v4l2_info(sd, "Video signal:    %s\n", signalOk ? (vcr ? "VCR" : "broadcast/DVD") : "bad");
1487         v4l2_info(sd, "Frequency:       %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
1488
1489         switch (reg1e & 0x03) {
1490         case 1:
1491                 v4l2_info(sd, "Detected format: NTSC\n");
1492                 break;
1493         case 2:
1494                 v4l2_info(sd, "Detected format: PAL\n");
1495                 break;
1496         case 3:
1497                 v4l2_info(sd, "Detected format: SECAM\n");
1498                 break;
1499         default:
1500                 v4l2_info(sd, "Detected format: BW/No color\n");
1501                 break;
1502         }
1503         v4l2_info(sd, "Width, Height:   %d, %d\n", state->width, state->height);
1504         v4l2_ctrl_handler_log_status(&state->hdl, sd->name);
1505         return 0;
1506 }
1507
1508 /* ----------------------------------------------------------------------- */
1509
1510 static const struct v4l2_ctrl_ops saa711x_ctrl_ops = {
1511         .s_ctrl = saa711x_s_ctrl,
1512         .g_volatile_ctrl = saa711x_g_volatile_ctrl,
1513 };
1514
1515 static const struct v4l2_subdev_core_ops saa711x_core_ops = {
1516         .log_status = saa711x_log_status,
1517         .g_chip_ident = saa711x_g_chip_ident,
1518         .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1519         .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1520         .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1521         .g_ctrl = v4l2_subdev_g_ctrl,
1522         .s_ctrl = v4l2_subdev_s_ctrl,
1523         .queryctrl = v4l2_subdev_queryctrl,
1524         .querymenu = v4l2_subdev_querymenu,
1525         .s_std = saa711x_s_std,
1526         .reset = saa711x_reset,
1527         .s_gpio = saa711x_s_gpio,
1528 #ifdef CONFIG_VIDEO_ADV_DEBUG
1529         .g_register = saa711x_g_register,
1530         .s_register = saa711x_s_register,
1531 #endif
1532 };
1533
1534 static const struct v4l2_subdev_tuner_ops saa711x_tuner_ops = {
1535         .s_radio = saa711x_s_radio,
1536         .g_tuner = saa711x_g_tuner,
1537 };
1538
1539 static const struct v4l2_subdev_audio_ops saa711x_audio_ops = {
1540         .s_clock_freq = saa711x_s_clock_freq,
1541 };
1542
1543 static const struct v4l2_subdev_video_ops saa711x_video_ops = {
1544         .s_routing = saa711x_s_routing,
1545         .s_crystal_freq = saa711x_s_crystal_freq,
1546         .s_mbus_fmt = saa711x_s_mbus_fmt,
1547         .s_stream = saa711x_s_stream,
1548         .querystd = saa711x_querystd,
1549         .g_input_status = saa711x_g_input_status,
1550 };
1551
1552 static const struct v4l2_subdev_vbi_ops saa711x_vbi_ops = {
1553         .g_vbi_data = saa711x_g_vbi_data,
1554         .decode_vbi_line = saa711x_decode_vbi_line,
1555         .g_sliced_fmt = saa711x_g_sliced_fmt,
1556         .s_sliced_fmt = saa711x_s_sliced_fmt,
1557         .s_raw_fmt = saa711x_s_raw_fmt,
1558 };
1559
1560 static const struct v4l2_subdev_ops saa711x_ops = {
1561         .core = &saa711x_core_ops,
1562         .tuner = &saa711x_tuner_ops,
1563         .audio = &saa711x_audio_ops,
1564         .video = &saa711x_video_ops,
1565         .vbi = &saa711x_vbi_ops,
1566 };
1567
1568 /* ----------------------------------------------------------------------- */
1569
1570 static int saa711x_probe(struct i2c_client *client,
1571                          const struct i2c_device_id *id)
1572 {
1573         struct saa711x_state *state;
1574         struct v4l2_subdev *sd;
1575         struct v4l2_ctrl_handler *hdl;
1576         int i;
1577         char name[17];
1578         char chip_id;
1579         int autodetect = !id || id->driver_data == 1;
1580
1581         /* Check if the adapter supports the needed features */
1582         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1583                 return -EIO;
1584
1585         for (i = 0; i < 0x0f; i++) {
1586                 i2c_smbus_write_byte_data(client, 0, i);
1587                 name[i] = (i2c_smbus_read_byte_data(client, 0) & 0x0f) + '0';
1588                 if (name[i] > '9')
1589                         name[i] += 'a' - '9' - 1;
1590         }
1591         name[i] = '\0';
1592
1593         chip_id = name[5];
1594
1595         /* Check whether this chip is part of the saa711x series */
1596         if (memcmp(name + 1, "f711", 4)) {
1597                 v4l_dbg(1, debug, client, "chip found @ 0x%x (ID %s) does not match a known saa711x chip.\n",
1598                         client->addr << 1, name);
1599                 return -ENODEV;
1600         }
1601
1602         /* Safety check */
1603         if (!autodetect && id->name[6] != chip_id) {
1604                 v4l_warn(client, "found saa711%c while %s was expected\n",
1605                          chip_id, id->name);
1606         }
1607         snprintf(client->name, sizeof(client->name), "saa711%c", chip_id);
1608         v4l_info(client, "saa711%c found (%s) @ 0x%x (%s)\n", chip_id, name,
1609                  client->addr << 1, client->adapter->name);
1610
1611         state = kzalloc(sizeof(struct saa711x_state), GFP_KERNEL);
1612         if (state == NULL)
1613                 return -ENOMEM;
1614         sd = &state->sd;
1615         v4l2_i2c_subdev_init(sd, client, &saa711x_ops);
1616
1617         hdl = &state->hdl;
1618         v4l2_ctrl_handler_init(hdl, 6);
1619         /* add in ascending ID order */
1620         v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1621                         V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1622         v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1623                         V4L2_CID_CONTRAST, 0, 127, 1, 64);
1624         v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1625                         V4L2_CID_SATURATION, 0, 127, 1, 64);
1626         v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1627                         V4L2_CID_HUE, -128, 127, 1, 0);
1628         state->agc = v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1629                         V4L2_CID_CHROMA_AGC, 0, 1, 1, 1);
1630         state->gain = v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
1631                         V4L2_CID_CHROMA_GAIN, 0, 127, 1, 40);
1632         sd->ctrl_handler = hdl;
1633         if (hdl->error) {
1634                 int err = hdl->error;
1635
1636                 v4l2_ctrl_handler_free(hdl);
1637                 kfree(state);
1638                 return err;
1639         }
1640         v4l2_ctrl_auto_cluster(2, &state->agc, 0, true);
1641
1642         state->input = -1;
1643         state->output = SAA7115_IPORT_ON;
1644         state->enable = 1;
1645         state->radio = 0;
1646         switch (chip_id) {
1647         case '1':
1648                 state->ident = V4L2_IDENT_SAA7111;
1649                 if (saa711x_read(sd, R_00_CHIP_VERSION) & 0xf0) {
1650                         v4l_info(client, "saa7111a variant found\n");
1651                         state->ident = V4L2_IDENT_SAA7111A;
1652                 }
1653                 break;
1654         case '3':
1655                 state->ident = V4L2_IDENT_SAA7113;
1656                 break;
1657         case '4':
1658                 state->ident = V4L2_IDENT_SAA7114;
1659                 break;
1660         case '5':
1661                 state->ident = V4L2_IDENT_SAA7115;
1662                 break;
1663         case '8':
1664                 state->ident = V4L2_IDENT_SAA7118;
1665                 break;
1666         default:
1667                 state->ident = V4L2_IDENT_SAA7111;
1668                 v4l2_info(sd, "WARNING: Chip is not known - Falling back to saa7111\n");
1669                 break;
1670         }
1671
1672         state->audclk_freq = 48000;
1673
1674         v4l2_dbg(1, debug, sd, "writing init values\n");
1675
1676         /* init to 60hz/48khz */
1677         state->crystal_freq = SAA7115_FREQ_24_576_MHZ;
1678         switch (state->ident) {
1679         case V4L2_IDENT_SAA7111:
1680         case V4L2_IDENT_SAA7111A:
1681                 saa711x_writeregs(sd, saa7111_init);
1682                 break;
1683         case V4L2_IDENT_SAA7113:
1684                 saa711x_writeregs(sd, saa7113_init);
1685                 break;
1686         default:
1687                 state->crystal_freq = SAA7115_FREQ_32_11_MHZ;
1688                 saa711x_writeregs(sd, saa7115_init_auto_input);
1689         }
1690         if (state->ident > V4L2_IDENT_SAA7111A)
1691                 saa711x_writeregs(sd, saa7115_init_misc);
1692         saa711x_set_v4lstd(sd, V4L2_STD_NTSC);
1693         v4l2_ctrl_handler_setup(hdl);
1694
1695         v4l2_dbg(1, debug, sd, "status: (1E) 0x%02x, (1F) 0x%02x\n",
1696                 saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC),
1697                 saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC));
1698         return 0;
1699 }
1700
1701 /* ----------------------------------------------------------------------- */
1702
1703 static int saa711x_remove(struct i2c_client *client)
1704 {
1705         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1706
1707         v4l2_device_unregister_subdev(sd);
1708         v4l2_ctrl_handler_free(sd->ctrl_handler);
1709         kfree(to_state(sd));
1710         return 0;
1711 }
1712
1713 static const struct i2c_device_id saa711x_id[] = {
1714         { "saa7115_auto", 1 }, /* autodetect */
1715         { "saa7111", 0 },
1716         { "saa7113", 0 },
1717         { "saa7114", 0 },
1718         { "saa7115", 0 },
1719         { "saa7118", 0 },
1720         { }
1721 };
1722 MODULE_DEVICE_TABLE(i2c, saa711x_id);
1723
1724 static struct i2c_driver saa711x_driver = {
1725         .driver = {
1726                 .owner  = THIS_MODULE,
1727                 .name   = "saa7115",
1728         },
1729         .probe          = saa711x_probe,
1730         .remove         = saa711x_remove,
1731         .id_table       = saa711x_id,
1732 };
1733
1734 module_i2c_driver(saa711x_driver);