Pileus Git - ~andy/linux/blob - drivers/media/i2c/adv7604.c

   1 /*
   2  * adv7604 - Analog Devices ADV7604 video decoder driver
   3  *
   4  * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17  * SOFTWARE.
  18  *
  19  */
  20
  21 /*
  22  * References (c = chapter, p = page):
  23  * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
  24  *              Revision 2.5, June 2010
  25  * REF_02 - Analog devices, Register map documentation, Documentation of
  26  *              the register maps, Software manual, Rev. F, June 2010
  27  * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
  28  */
  29
  30
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/slab.h>
  34 #include <linux/i2c.h>
  35 #include <linux/delay.h>
  36 #include <linux/videodev2.h>
  37 #include <linux/workqueue.h>
  38 #include <linux/v4l2-dv-timings.h>
  39 #include <media/v4l2-device.h>
  40 #include <media/v4l2-ctrls.h>
  41 #include <media/v4l2-dv-timings.h>
  42 #include <media/adv7604.h>
  43
  44 static int debug;
  45 module_param(debug, int, 0644);
  46 MODULE_PARM_DESC(debug, "debug level (0-2)");
  47
  48 MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
  49 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  50 MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
  51 MODULE_LICENSE("GPL");
  52
  53 /* ADV7604 system clock frequency */
  54 #define ADV7604_fsc (28636360)
  55
  56 /*
  57  **********************************************************************
  58  *
  59  *  Arrays with configuration parameters for the ADV7604
  60  *
  61  **********************************************************************
  62  */
  63 struct adv7604_state {
  64         struct adv7604_platform_data pdata;
  65         struct v4l2_subdev sd;
  66         struct media_pad pad;
  67         struct v4l2_ctrl_handler hdl;
  68         enum adv7604_input_port selected_input;
  69         struct v4l2_dv_timings timings;
  70         struct {
  71                 u8 edid[256];
  72                 u32 present;
  73                 unsigned blocks;
  74         } edid;
  75         u16 spa_port_a[2];
  76         struct v4l2_fract aspect_ratio;
  77         u32 rgb_quantization_range;
  78         struct workqueue_struct *work_queues;
  79         struct delayed_work delayed_work_enable_hotplug;
  80         bool restart_stdi_once;
  81
  82         /* i2c clients */
  83         struct i2c_client *i2c_avlink;
  84         struct i2c_client *i2c_cec;
  85         struct i2c_client *i2c_infoframe;
  86         struct i2c_client *i2c_esdp;
  87         struct i2c_client *i2c_dpp;
  88         struct i2c_client *i2c_afe;
  89         struct i2c_client *i2c_repeater;
  90         struct i2c_client *i2c_edid;
  91         struct i2c_client *i2c_hdmi;
  92         struct i2c_client *i2c_test;
  93         struct i2c_client *i2c_cp;
  94         struct i2c_client *i2c_vdp;
  95
  96         /* controls */
  97         struct v4l2_ctrl *detect_tx_5v_ctrl;
  98         struct v4l2_ctrl *analog_sampling_phase_ctrl;
  99         struct v4l2_ctrl *free_run_color_manual_ctrl;
 100         struct v4l2_ctrl *free_run_color_ctrl;
 101         struct v4l2_ctrl *rgb_quantization_range_ctrl;
 102 };
 103
 104 /* Supported CEA and DMT timings */
 105 static const struct v4l2_dv_timings adv7604_timings[] = {
 106         V4L2_DV_BT_CEA_720X480P59_94,
 107         V4L2_DV_BT_CEA_720X576P50,
 108         V4L2_DV_BT_CEA_1280X720P24,
 109         V4L2_DV_BT_CEA_1280X720P25,
 110         V4L2_DV_BT_CEA_1280X720P50,
 111         V4L2_DV_BT_CEA_1280X720P60,
 112         V4L2_DV_BT_CEA_1920X1080P24,
 113         V4L2_DV_BT_CEA_1920X1080P25,
 114         V4L2_DV_BT_CEA_1920X1080P30,
 115         V4L2_DV_BT_CEA_1920X1080P50,
 116         V4L2_DV_BT_CEA_1920X1080P60,
 117
 118         /* sorted by DMT ID */
 119         V4L2_DV_BT_DMT_640X350P85,
 120         V4L2_DV_BT_DMT_640X400P85,
 121         V4L2_DV_BT_DMT_720X400P85,
 122         V4L2_DV_BT_DMT_640X480P60,
 123         V4L2_DV_BT_DMT_640X480P72,
 124         V4L2_DV_BT_DMT_640X480P75,
 125         V4L2_DV_BT_DMT_640X480P85,
 126         V4L2_DV_BT_DMT_800X600P56,
 127         V4L2_DV_BT_DMT_800X600P60,
 128         V4L2_DV_BT_DMT_800X600P72,
 129         V4L2_DV_BT_DMT_800X600P75,
 130         V4L2_DV_BT_DMT_800X600P85,
 131         V4L2_DV_BT_DMT_848X480P60,
 132         V4L2_DV_BT_DMT_1024X768P60,
 133         V4L2_DV_BT_DMT_1024X768P70,
 134         V4L2_DV_BT_DMT_1024X768P75,
 135         V4L2_DV_BT_DMT_1024X768P85,
 136         V4L2_DV_BT_DMT_1152X864P75,
 137         V4L2_DV_BT_DMT_1280X768P60_RB,
 138         V4L2_DV_BT_DMT_1280X768P60,
 139         V4L2_DV_BT_DMT_1280X768P75,
 140         V4L2_DV_BT_DMT_1280X768P85,
 141         V4L2_DV_BT_DMT_1280X800P60_RB,
 142         V4L2_DV_BT_DMT_1280X800P60,
 143         V4L2_DV_BT_DMT_1280X800P75,
 144         V4L2_DV_BT_DMT_1280X800P85,
 145         V4L2_DV_BT_DMT_1280X960P60,
 146         V4L2_DV_BT_DMT_1280X960P85,
 147         V4L2_DV_BT_DMT_1280X1024P60,
 148         V4L2_DV_BT_DMT_1280X1024P75,
 149         V4L2_DV_BT_DMT_1280X1024P85,
 150         V4L2_DV_BT_DMT_1360X768P60,
 151         V4L2_DV_BT_DMT_1400X1050P60_RB,
 152         V4L2_DV_BT_DMT_1400X1050P60,
 153         V4L2_DV_BT_DMT_1400X1050P75,
 154         V4L2_DV_BT_DMT_1400X1050P85,
 155         V4L2_DV_BT_DMT_1440X900P60_RB,
 156         V4L2_DV_BT_DMT_1440X900P60,
 157         V4L2_DV_BT_DMT_1600X1200P60,
 158         V4L2_DV_BT_DMT_1680X1050P60_RB,
 159         V4L2_DV_BT_DMT_1680X1050P60,
 160         V4L2_DV_BT_DMT_1792X1344P60,
 161         V4L2_DV_BT_DMT_1856X1392P60,
 162         V4L2_DV_BT_DMT_1920X1200P60_RB,
 163         V4L2_DV_BT_DMT_1366X768P60_RB,
 164         V4L2_DV_BT_DMT_1366X768P60,
 165         V4L2_DV_BT_DMT_1920X1080P60,
 166         { },
 167 };
 168
 169 struct adv7604_video_standards {
 170         struct v4l2_dv_timings timings;
 171         u8 vid_std;
 172         u8 v_freq;
 173 };
 174
 175 /* sorted by number of lines */
 176 static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
 177         /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
 178         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 179         { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
 180         { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
 181         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 182         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 183         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 184         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 185         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 186         /* TODO add 1920x1080P60_RB (CVT timing) */
 187         { },
 188 };
 189
 190 /* sorted by number of lines */
 191 static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
 192         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 193         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 194         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 195         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 196         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 197         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 198         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 199         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 200         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 201         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 202         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 203         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 204         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 205         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 206         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 207         { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
 208         { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
 209         { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
 210         { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
 211         { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
 212         /* TODO add 1600X1200P60_RB (not a DMT timing) */
 213         { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
 214         { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
 215         { },
 216 };
 217
 218 /* sorted by number of lines */
 219 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
 220         { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
 221         { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
 222         { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
 223         { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
 224         { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
 225         { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
 226         { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
 227         { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
 228         { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
 229         { },
 230 };
 231
 232 /* sorted by number of lines */
 233 static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
 234         { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
 235         { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
 236         { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
 237         { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
 238         { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
 239         { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
 240         { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
 241         { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
 242         { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
 243         { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
 244         { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
 245         { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
 246         { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
 247         { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
 248         { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
 249         { },
 250 };
 251
 252 /* ----------------------------------------------------------------------- */
 253
 254 static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
 255 {
 256         return container_of(sd, struct adv7604_state, sd);
 257 }
 258
 259 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 260 {
 261         return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
 262 }
 263
 264 static inline unsigned hblanking(const struct v4l2_bt_timings *t)
 265 {
 266         return V4L2_DV_BT_BLANKING_WIDTH(t);
 267 }
 268
 269 static inline unsigned htotal(const struct v4l2_bt_timings *t)
 270 {
 271         return V4L2_DV_BT_FRAME_WIDTH(t);
 272 }
 273
 274 static inline unsigned vblanking(const struct v4l2_bt_timings *t)
 275 {
 276         return V4L2_DV_BT_BLANKING_HEIGHT(t);
 277 }
 278
 279 static inline unsigned vtotal(const struct v4l2_bt_timings *t)
 280 {
 281         return V4L2_DV_BT_FRAME_HEIGHT(t);
 282 }
 283
 284 /* ----------------------------------------------------------------------- */
 285
 286 static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
 287                 u8 command, bool check)
 288 {
 289         union i2c_smbus_data data;
 290
 291         if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 292                         I2C_SMBUS_READ, command,
 293                         I2C_SMBUS_BYTE_DATA, &data))
 294                 return data.byte;
 295         if (check)
 296                 v4l_err(client, "error reading %02x, %02x\n",
 297                                 client->addr, command);
 298         return -EIO;
 299 }
 300
 301 static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
 302 {
 303         return adv_smbus_read_byte_data_check(client, command, true);
 304 }
 305
 306 static s32 adv_smbus_write_byte_data(struct i2c_client *client,
 307                                         u8 command, u8 value)
 308 {
 309         union i2c_smbus_data data;
 310         int err;
 311         int i;
 312
 313         data.byte = value;
 314         for (i = 0; i < 3; i++) {
 315                 err = i2c_smbus_xfer(client->adapter, client->addr,
 316                                 client->flags,
 317                                 I2C_SMBUS_WRITE, command,
 318                                 I2C_SMBUS_BYTE_DATA, &data);
 319                 if (!err)
 320                         break;
 321         }
 322         if (err < 0)
 323                 v4l_err(client, "error writing %02x, %02x, %02x\n",
 324                                 client->addr, command, value);
 325         return err;
 326 }
 327
 328 static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
 329                u8 command, unsigned length, const u8 *values)
 330 {
 331         union i2c_smbus_data data;
 332
 333         if (length > I2C_SMBUS_BLOCK_MAX)
 334                 length = I2C_SMBUS_BLOCK_MAX;
 335         data.block[0] = length;
 336         memcpy(data.block + 1, values, length);
 337         return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
 338                               I2C_SMBUS_WRITE, command,
 339                               I2C_SMBUS_I2C_BLOCK_DATA, &data);
 340 }
 341
 342 /* ----------------------------------------------------------------------- */
 343
 344 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
 345 {
 346         struct i2c_client *client = v4l2_get_subdevdata(sd);
 347
 348         return adv_smbus_read_byte_data(client, reg);
 349 }
 350
 351 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 352 {
 353         struct i2c_client *client = v4l2_get_subdevdata(sd);
 354
 355         return adv_smbus_write_byte_data(client, reg, val);
 356 }
 357
 358 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 359 {
 360         return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
 361 }
 362
 363 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
 364 {
 365         struct adv7604_state *state = to_state(sd);
 366
 367         return adv_smbus_read_byte_data(state->i2c_avlink, reg);
 368 }
 369
 370 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 371 {
 372         struct adv7604_state *state = to_state(sd);
 373
 374         return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
 375 }
 376
 377 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
 378 {
 379         struct adv7604_state *state = to_state(sd);
 380
 381         return adv_smbus_read_byte_data(state->i2c_cec, reg);
 382 }
 383
 384 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 385 {
 386         struct adv7604_state *state = to_state(sd);
 387
 388         return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
 389 }
 390
 391 static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 392 {
 393         return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
 394 }
 395
 396 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
 397 {
 398         struct adv7604_state *state = to_state(sd);
 399
 400         return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
 401 }
 402
 403 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 404 {
 405         struct adv7604_state *state = to_state(sd);
 406
 407         return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
 408 }
 409
 410 static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
 411 {
 412         struct adv7604_state *state = to_state(sd);
 413
 414         return adv_smbus_read_byte_data(state->i2c_esdp, reg);
 415 }
 416
 417 static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 418 {
 419         struct adv7604_state *state = to_state(sd);
 420
 421         return adv_smbus_write_byte_data(state->i2c_esdp, reg, val);
 422 }
 423
 424 static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
 425 {
 426         struct adv7604_state *state = to_state(sd);
 427
 428         return adv_smbus_read_byte_data(state->i2c_dpp, reg);
 429 }
 430
 431 static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 432 {
 433         struct adv7604_state *state = to_state(sd);
 434
 435         return adv_smbus_write_byte_data(state->i2c_dpp, reg, val);
 436 }
 437
 438 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
 439 {
 440         struct adv7604_state *state = to_state(sd);
 441
 442         return adv_smbus_read_byte_data(state->i2c_afe, reg);
 443 }
 444
 445 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 446 {
 447         struct adv7604_state *state = to_state(sd);
 448
 449         return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
 450 }
 451
 452 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
 453 {
 454         struct adv7604_state *state = to_state(sd);
 455
 456         return adv_smbus_read_byte_data(state->i2c_repeater, reg);
 457 }
 458
 459 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 460 {
 461         struct adv7604_state *state = to_state(sd);
 462
 463         return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
 464 }
 465
 466 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 467 {
 468         return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
 469 }
 470
 471 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
 472 {
 473         struct adv7604_state *state = to_state(sd);
 474
 475         return adv_smbus_read_byte_data(state->i2c_edid, reg);
 476 }
 477
 478 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 479 {
 480         struct adv7604_state *state = to_state(sd);
 481
 482         return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
 483 }
 484
 485 static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
 486 {
 487         struct adv7604_state *state = to_state(sd);
 488         struct i2c_client *client = state->i2c_edid;
 489         u8 msgbuf0[1] = { 0 };
 490         u8 msgbuf1[256];
 491         struct i2c_msg msg[2] = {
 492                 {
 493                         .addr = client->addr,
 494                         .len = 1,
 495                         .buf = msgbuf0
 496                 },
 497                 {
 498                         .addr = client->addr,
 499                         .flags = I2C_M_RD,
 500                         .len = len,
 501                         .buf = msgbuf1
 502                 },
 503         };
 504
 505         if (i2c_transfer(client->adapter, msg, 2) < 0)
 506                 return -EIO;
 507         memcpy(val, msgbuf1, len);
 508         return 0;
 509 }
 510
 511 static inline int edid_write_block(struct v4l2_subdev *sd,
 512                                         unsigned len, const u8 *val)
 513 {
 514         struct adv7604_state *state = to_state(sd);
 515         int err = 0;
 516         int i;
 517
 518         v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
 519
 520         for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
 521                 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
 522                                 I2C_SMBUS_BLOCK_MAX, val + i);
 523         return err;
 524 }
 525
 526 static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
 527 {
 528         struct delayed_work *dwork = to_delayed_work(work);
 529         struct adv7604_state *state = container_of(dwork, struct adv7604_state,
 530                                                 delayed_work_enable_hotplug);
 531         struct v4l2_subdev *sd = &state->sd;
 532
 533         v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
 534
 535         v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
 536 }
 537
 538 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
 539 {
 540         struct adv7604_state *state = to_state(sd);
 541
 542         return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
 543 }
 544
 545 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 546 {
 547         struct adv7604_state *state = to_state(sd);
 548
 549         return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
 550 }
 551
 552 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 553 {
 554         return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
 555 }
 556
 557 static inline int test_read(struct v4l2_subdev *sd, u8 reg)
 558 {
 559         struct adv7604_state *state = to_state(sd);
 560
 561         return adv_smbus_read_byte_data(state->i2c_test, reg);
 562 }
 563
 564 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 565 {
 566         struct adv7604_state *state = to_state(sd);
 567
 568         return adv_smbus_write_byte_data(state->i2c_test, reg, val);
 569 }
 570
 571 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
 572 {
 573         struct adv7604_state *state = to_state(sd);
 574
 575         return adv_smbus_read_byte_data(state->i2c_cp, reg);
 576 }
 577
 578 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 579 {
 580         struct adv7604_state *state = to_state(sd);
 581
 582         return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
 583 }
 584
 585 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
 586 {
 587         return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
 588 }
 589
 590 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
 591 {
 592         struct adv7604_state *state = to_state(sd);
 593
 594         return adv_smbus_read_byte_data(state->i2c_vdp, reg);
 595 }
 596
 597 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
 598 {
 599         struct adv7604_state *state = to_state(sd);
 600
 601         return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
 602 }
 603
 604 /* ----------------------------------------------------------------------- */
 605
 606 static inline bool is_analog_input(struct v4l2_subdev *sd)
 607 {
 608         struct adv7604_state *state = to_state(sd);
 609
 610         return state->selected_input == ADV7604_INPUT_VGA_RGB ||
 611                state->selected_input == ADV7604_INPUT_VGA_COMP;
 612 }
 613
 614 static inline bool is_digital_input(struct v4l2_subdev *sd)
 615 {
 616         struct adv7604_state *state = to_state(sd);
 617
 618         return state->selected_input == ADV7604_INPUT_HDMI_PORT_A ||
 619                state->selected_input == ADV7604_INPUT_HDMI_PORT_B ||
 620                state->selected_input == ADV7604_INPUT_HDMI_PORT_C ||
 621                state->selected_input == ADV7604_INPUT_HDMI_PORT_D;
 622 }
 623
 624 /* ----------------------------------------------------------------------- */
 625
 626 #ifdef CONFIG_VIDEO_ADV_DEBUG
 627 static void adv7604_inv_register(struct v4l2_subdev *sd)
 628 {
 629         v4l2_info(sd, "0x000-0x0ff: IO Map\n");
 630         v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
 631         v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
 632         v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
 633         v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
 634         v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
 635         v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
 636         v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
 637         v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
 638         v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
 639         v4l2_info(sd, "0xa00-0xaff: Test Map\n");
 640         v4l2_info(sd, "0xb00-0xbff: CP Map\n");
 641         v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
 642 }
 643
 644 static int adv7604_g_register(struct v4l2_subdev *sd,
 645                                         struct v4l2_dbg_register *reg)
 646 {
 647         reg->size = 1;
 648         switch (reg->reg >> 8) {
 649         case 0:
 650                 reg->val = io_read(sd, reg->reg & 0xff);
 651                 break;
 652         case 1:
 653                 reg->val = avlink_read(sd, reg->reg & 0xff);
 654                 break;
 655         case 2:
 656                 reg->val = cec_read(sd, reg->reg & 0xff);
 657                 break;
 658         case 3:
 659                 reg->val = infoframe_read(sd, reg->reg & 0xff);
 660                 break;
 661         case 4:
 662                 reg->val = esdp_read(sd, reg->reg & 0xff);
 663                 break;
 664         case 5:
 665                 reg->val = dpp_read(sd, reg->reg & 0xff);
 666                 break;
 667         case 6:
 668                 reg->val = afe_read(sd, reg->reg & 0xff);
 669                 break;
 670         case 7:
 671                 reg->val = rep_read(sd, reg->reg & 0xff);
 672                 break;
 673         case 8:
 674                 reg->val = edid_read(sd, reg->reg & 0xff);
 675                 break;
 676         case 9:
 677                 reg->val = hdmi_read(sd, reg->reg & 0xff);
 678                 break;
 679         case 0xa:
 680                 reg->val = test_read(sd, reg->reg & 0xff);
 681                 break;
 682         case 0xb:
 683                 reg->val = cp_read(sd, reg->reg & 0xff);
 684                 break;
 685         case 0xc:
 686                 reg->val = vdp_read(sd, reg->reg & 0xff);
 687                 break;
 688         default:
 689                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 690                 adv7604_inv_register(sd);
 691                 break;
 692         }
 693         return 0;
 694 }
 695
 696 static int adv7604_s_register(struct v4l2_subdev *sd,
 697                                         const struct v4l2_dbg_register *reg)
 698 {
 699         u8 val = reg->val & 0xff;
 700
 701         switch (reg->reg >> 8) {
 702         case 0:
 703                 io_write(sd, reg->reg & 0xff, val);
 704                 break;
 705         case 1:
 706                 avlink_write(sd, reg->reg & 0xff, val);
 707                 break;
 708         case 2:
 709                 cec_write(sd, reg->reg & 0xff, val);
 710                 break;
 711         case 3:
 712                 infoframe_write(sd, reg->reg & 0xff, val);
 713                 break;
 714         case 4:
 715                 esdp_write(sd, reg->reg & 0xff, val);
 716                 break;
 717         case 5:
 718                 dpp_write(sd, reg->reg & 0xff, val);
 719                 break;
 720         case 6:
 721                 afe_write(sd, reg->reg & 0xff, val);
 722                 break;
 723         case 7:
 724                 rep_write(sd, reg->reg & 0xff, val);
 725                 break;
 726         case 8:
 727                 edid_write(sd, reg->reg & 0xff, val);
 728                 break;
 729         case 9:
 730                 hdmi_write(sd, reg->reg & 0xff, val);
 731                 break;
 732         case 0xa:
 733                 test_write(sd, reg->reg & 0xff, val);
 734                 break;
 735         case 0xb:
 736                 cp_write(sd, reg->reg & 0xff, val);
 737                 break;
 738         case 0xc:
 739                 vdp_write(sd, reg->reg & 0xff, val);
 740                 break;
 741         default:
 742                 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
 743                 adv7604_inv_register(sd);
 744                 break;
 745         }
 746         return 0;
 747 }
 748 #endif
 749
 750 static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
 751 {
 752         struct adv7604_state *state = to_state(sd);
 753         u8 reg_io_6f = io_read(sd, 0x6f);
 754
 755         return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
 756                         ((reg_io_6f & 0x10) >> 4) |
 757                         ((reg_io_6f & 0x08) >> 2) |
 758                         (reg_io_6f & 0x04) |
 759                         ((reg_io_6f & 0x02) << 2));
 760 }
 761
 762 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
 763                 u8 prim_mode,
 764                 const struct adv7604_video_standards *predef_vid_timings,
 765                 const struct v4l2_dv_timings *timings)
 766 {
 767         int i;
 768
 769         for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
 770                 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
 771                                         is_digital_input(sd) ? 250000 : 1000000))
 772                         continue;
 773                 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
 774                 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
 775                                 prim_mode); /* v_freq and prim mode */
 776                 return 0;
 777         }
 778
 779         return -1;
 780 }
 781
 782 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
 783                 struct v4l2_dv_timings *timings)
 784 {
 785         struct adv7604_state *state = to_state(sd);
 786         int err;
 787
 788         v4l2_dbg(1, debug, sd, "%s", __func__);
 789
 790         /* reset to default values */
 791         io_write(sd, 0x16, 0x43);
 792         io_write(sd, 0x17, 0x5a);
 793         /* disable embedded syncs for auto graphics mode */
 794         cp_write_and_or(sd, 0x81, 0xef, 0x00);
 795         cp_write(sd, 0x8f, 0x00);
 796         cp_write(sd, 0x90, 0x00);
 797         cp_write(sd, 0xa2, 0x00);
 798         cp_write(sd, 0xa3, 0x00);
 799         cp_write(sd, 0xa4, 0x00);
 800         cp_write(sd, 0xa5, 0x00);
 801         cp_write(sd, 0xa6, 0x00);
 802         cp_write(sd, 0xa7, 0x00);
 803         cp_write(sd, 0xab, 0x00);
 804         cp_write(sd, 0xac, 0x00);
 805
 806         if (is_analog_input(sd)) {
 807                 err = find_and_set_predefined_video_timings(sd,
 808                                 0x01, adv7604_prim_mode_comp, timings);
 809                 if (err)
 810                         err = find_and_set_predefined_video_timings(sd,
 811                                         0x02, adv7604_prim_mode_gr, timings);
 812         } else if (is_digital_input(sd)) {
 813                 err = find_and_set_predefined_video_timings(sd,
 814                                 0x05, adv7604_prim_mode_hdmi_comp, timings);
 815                 if (err)
 816                         err = find_and_set_predefined_video_timings(sd,
 817                                         0x06, adv7604_prim_mode_hdmi_gr, timings);
 818         } else {
 819                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
 820                                 __func__, state->selected_input);
 821                 err = -1;
 822         }
 823
 824
 825         return err;
 826 }
 827
 828 static void configure_custom_video_timings(struct v4l2_subdev *sd,
 829                 const struct v4l2_bt_timings *bt)
 830 {
 831         struct adv7604_state *state = to_state(sd);
 832         struct i2c_client *client = v4l2_get_subdevdata(sd);
 833         u32 width = htotal(bt);
 834         u32 height = vtotal(bt);
 835         u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
 836         u16 cp_start_eav = width - bt->hfrontporch;
 837         u16 cp_start_vbi = height - bt->vfrontporch;
 838         u16 cp_end_vbi = bt->vsync + bt->vbackporch;
 839         u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
 840                 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
 841         const u8 pll[2] = {
 842                 0xc0 | ((width >> 8) & 0x1f),
 843                 width & 0xff
 844         };
 845
 846         v4l2_dbg(2, debug, sd, "%s\n", __func__);
 847
 848         if (is_analog_input(sd)) {
 849                 /* auto graphics */
 850                 io_write(sd, 0x00, 0x07); /* video std */
 851                 io_write(sd, 0x01, 0x02); /* prim mode */
 852                 /* enable embedded syncs for auto graphics mode */
 853                 cp_write_and_or(sd, 0x81, 0xef, 0x10);
 854
 855                 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
 856                 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
 857                 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
 858                 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll))
 859                         v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
 860
 861                 /* active video - horizontal timing */
 862                 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
 863                 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
 864                                    ((cp_start_eav >> 8) & 0x0f));
 865                 cp_write(sd, 0xa4, cp_start_eav & 0xff);
 866
 867                 /* active video - vertical timing */
 868                 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
 869                 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
 870                                    ((cp_end_vbi >> 8) & 0xf));
 871                 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
 872         } else if (is_digital_input(sd)) {
 873                 /* set default prim_mode/vid_std for HDMI
 874                    according to [REF_03, c. 4.2] */
 875                 io_write(sd, 0x00, 0x02); /* video std */
 876                 io_write(sd, 0x01, 0x06); /* prim mode */
 877         } else {
 878                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
 879                                 __func__, state->selected_input);
 880         }
 881
 882         cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
 883         cp_write(sd, 0x90, ch1_fr_ll & 0xff);
 884         cp_write(sd, 0xab, (height >> 4) & 0xff);
 885         cp_write(sd, 0xac, (height & 0x0f) << 4);
 886 }
 887
 888 static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
 889 {
 890         struct adv7604_state *state = to_state(sd);
 891         u8 offset_buf[4];
 892
 893         if (auto_offset) {
 894                 offset_a = 0x3ff;
 895                 offset_b = 0x3ff;
 896                 offset_c = 0x3ff;
 897         }
 898
 899         v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
 900                         __func__, auto_offset ? "Auto" : "Manual",
 901                         offset_a, offset_b, offset_c);
 902
 903         offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
 904         offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
 905         offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
 906         offset_buf[3] = offset_c & 0x0ff;
 907
 908         /* Registers must be written in this order with no i2c access in between */
 909         if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf))
 910                 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
 911 }
 912
 913 static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
 914 {
 915         struct adv7604_state *state = to_state(sd);
 916         u8 gain_buf[4];
 917         u8 gain_man = 1;
 918         u8 agc_mode_man = 1;
 919
 920         if (auto_gain) {
 921                 gain_man = 0;
 922                 agc_mode_man = 0;
 923                 gain_a = 0x100;
 924                 gain_b = 0x100;
 925                 gain_c = 0x100;
 926         }
 927
 928         v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
 929                         __func__, auto_gain ? "Auto" : "Manual",
 930                         gain_a, gain_b, gain_c);
 931
 932         gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
 933         gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
 934         gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
 935         gain_buf[3] = ((gain_c & 0x0ff));
 936
 937         /* Registers must be written in this order with no i2c access in between */
 938         if (adv_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf))
 939                 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
 940 }
 941
 942 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
 943 {
 944         struct adv7604_state *state = to_state(sd);
 945         bool rgb_output = io_read(sd, 0x02) & 0x02;
 946         bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
 947
 948         v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
 949                         __func__, state->rgb_quantization_range,
 950                         rgb_output, hdmi_signal);
 951
 952         adv7604_set_gain(sd, true, 0x0, 0x0, 0x0);
 953         adv7604_set_offset(sd, true, 0x0, 0x0, 0x0);
 954
 955         switch (state->rgb_quantization_range) {
 956         case V4L2_DV_RGB_RANGE_AUTO:
 957                 if (state->selected_input == ADV7604_INPUT_VGA_RGB) {
 958                         /* Receiving analog RGB signal
 959                          * Set RGB full range (0-255) */
 960                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
 961                         break;
 962                 }
 963
 964                 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
 965                         /* Receiving analog YPbPr signal
 966                          * Set automode */
 967                         io_write_and_or(sd, 0x02, 0x0f, 0xf0);
 968                         break;
 969                 }
 970
 971                 if (hdmi_signal) {
 972                         /* Receiving HDMI signal
 973                          * Set automode */
 974                         io_write_and_or(sd, 0x02, 0x0f, 0xf0);
 975                         break;
 976                 }
 977
 978                 /* Receiving DVI-D signal
 979                  * ADV7604 selects RGB limited range regardless of
 980                  * input format (CE/IT) in automatic mode */
 981                 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
 982                         /* RGB limited range (16-235) */
 983                         io_write_and_or(sd, 0x02, 0x0f, 0x00);
 984                 } else {
 985                         /* RGB full range (0-255) */
 986                         io_write_and_or(sd, 0x02, 0x0f, 0x10);
 987
 988                         if (is_digital_input(sd) && rgb_output) {
 989                                 adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
 990                         } else {
 991                                 adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
 992                                 adv7604_set_offset(sd, false, 0x70, 0x70, 0x70);
 993                         }
 994                 }
 995                 break;
 996         case V4L2_DV_RGB_RANGE_LIMITED:
 997                 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
 998                         /* YCrCb limited range (16-235) */
 999                         io_write_and_or(sd, 0x02, 0x0f, 0x20);
1000                         break;
1001                 }
1002
1003                 /* RGB limited range (16-235) */
1004                 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1005
1006                 break;
1007         case V4L2_DV_RGB_RANGE_FULL:
1008                 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
1009                         /* YCrCb full range (0-255) */
1010                         io_write_and_or(sd, 0x02, 0x0f, 0x60);
1011                         break;
1012                 }
1013
1014                 /* RGB full range (0-255) */
1015                 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1016
1017                 if (is_analog_input(sd) || hdmi_signal)
1018                         break;
1019
1020                 /* Adjust gain/offset for DVI-D signals only */
1021                 if (rgb_output) {
1022                         adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
1023                 } else {
1024                         adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1025                         adv7604_set_offset(sd, false, 0x70, 0x70, 0x70);
1026                 }
1027                 break;
1028         }
1029 }
1030
1031 static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
1032 {
1033         struct v4l2_subdev *sd = to_sd(ctrl);
1034         struct adv7604_state *state = to_state(sd);
1035
1036         switch (ctrl->id) {
1037         case V4L2_CID_BRIGHTNESS:
1038                 cp_write(sd, 0x3c, ctrl->val);
1039                 return 0;
1040         case V4L2_CID_CONTRAST:
1041                 cp_write(sd, 0x3a, ctrl->val);
1042                 return 0;
1043         case V4L2_CID_SATURATION:
1044                 cp_write(sd, 0x3b, ctrl->val);
1045                 return 0;
1046         case V4L2_CID_HUE:
1047                 cp_write(sd, 0x3d, ctrl->val);
1048                 return 0;
1049         case  V4L2_CID_DV_RX_RGB_RANGE:
1050                 state->rgb_quantization_range = ctrl->val;
1051                 set_rgb_quantization_range(sd);
1052                 return 0;
1053         case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1054                 /* Set the analog sampling phase. This is needed to find the
1055                    best sampling phase for analog video: an application or
1056                    driver has to try a number of phases and analyze the picture
1057                    quality before settling on the best performing phase. */
1058                 afe_write(sd, 0xc8, ctrl->val);
1059                 return 0;
1060         case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1061                 /* Use the default blue color for free running mode,
1062                    or supply your own. */
1063                 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1064                 return 0;
1065         case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1066                 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1067                 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1068                 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1069                 return 0;
1070         }
1071         return -EINVAL;
1072 }
1073
1074 /* ----------------------------------------------------------------------- */
1075
1076 static inline bool no_power(struct v4l2_subdev *sd)
1077 {
1078         /* Entire chip or CP powered off */
1079         return io_read(sd, 0x0c) & 0x24;
1080 }
1081
1082 static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1083 {
1084         struct adv7604_state *state = to_state(sd);
1085
1086         return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1087 }
1088
1089 static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1090 {
1091         return (io_read(sd, 0x6a) & 0xe0) != 0xe0;
1092 }
1093
1094 static inline bool is_hdmi(struct v4l2_subdev *sd)
1095 {
1096         return hdmi_read(sd, 0x05) & 0x80;
1097 }
1098
1099 static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1100 {
1101         /* TODO channel 2 */
1102         return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1103 }
1104
1105 static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1106 {
1107         /* TODO channel 2 */
1108         return !(cp_read(sd, 0xb1) & 0x80);
1109 }
1110
1111 static inline bool no_signal(struct v4l2_subdev *sd)
1112 {
1113         bool ret;
1114
1115         ret = no_power(sd);
1116
1117         ret |= no_lock_stdi(sd);
1118         ret |= no_lock_sspd(sd);
1119
1120         if (is_digital_input(sd)) {
1121                 ret |= no_lock_tmds(sd);
1122                 ret |= no_signal_tmds(sd);
1123         }
1124
1125         return ret;
1126 }
1127
1128 static inline bool no_lock_cp(struct v4l2_subdev *sd)
1129 {
1130         /* CP has detected a non standard number of lines on the incoming
1131            video compared to what it is configured to receive by s_dv_timings */
1132         return io_read(sd, 0x12) & 0x01;
1133 }
1134
1135 static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1136 {
1137         *status = 0;
1138         *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1139         *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1140         if (no_lock_cp(sd))
1141                 *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1142
1143         v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1144
1145         return 0;
1146 }
1147
1148 /* ----------------------------------------------------------------------- */
1149
1150 struct stdi_readback {
1151         u16 bl, lcf, lcvs;
1152         u8 hs_pol, vs_pol;
1153         bool interlaced;
1154 };
1155
1156 static int stdi2dv_timings(struct v4l2_subdev *sd,
1157                 struct stdi_readback *stdi,
1158                 struct v4l2_dv_timings *timings)
1159 {
1160         struct adv7604_state *state = to_state(sd);
1161         u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1162         u32 pix_clk;
1163         int i;
1164
1165         for (i = 0; adv7604_timings[i].bt.height; i++) {
1166                 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1167                         continue;
1168                 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1169                         continue;
1170
1171                 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1172
1173                 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1174                     (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1175                         *timings = adv7604_timings[i];
1176                         return 0;
1177                 }
1178         }
1179
1180         if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1181                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1182                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1183                         timings))
1184                 return 0;
1185         if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1186                         (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1187                         (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1188                         state->aspect_ratio, timings))
1189                 return 0;
1190
1191         v4l2_dbg(2, debug, sd,
1192                 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1193                 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1194                 stdi->hs_pol, stdi->vs_pol);
1195         return -1;
1196 }
1197
1198 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1199 {
1200         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1201                 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1202                 return -1;
1203         }
1204
1205         /* read STDI */
1206         stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1207         stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1208         stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1209         stdi->interlaced = io_read(sd, 0x12) & 0x10;
1210
1211         /* read SSPD */
1212         if ((cp_read(sd, 0xb5) & 0x03) == 0x01) {
1213                 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1214                                 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1215                 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1216                                 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1217         } else {
1218                 stdi->hs_pol = 'x';
1219                 stdi->vs_pol = 'x';
1220         }
1221
1222         if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1223                 v4l2_dbg(2, debug, sd,
1224                         "%s: signal lost during readout of STDI/SSPD\n", __func__);
1225                 return -1;
1226         }
1227
1228         if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1229                 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1230                 memset(stdi, 0, sizeof(struct stdi_readback));
1231                 return -1;
1232         }
1233
1234         v4l2_dbg(2, debug, sd,
1235                 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1236                 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1237                 stdi->hs_pol, stdi->vs_pol,
1238                 stdi->interlaced ? "interlaced" : "progressive");
1239
1240         return 0;
1241 }
1242
1243 static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1244                         struct v4l2_enum_dv_timings *timings)
1245 {
1246         if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1247                 return -EINVAL;
1248         memset(timings->reserved, 0, sizeof(timings->reserved));
1249         timings->timings = adv7604_timings[timings->index];
1250         return 0;
1251 }
1252
1253 static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1254                         struct v4l2_dv_timings_cap *cap)
1255 {
1256         cap->type = V4L2_DV_BT_656_1120;
1257         cap->bt.max_width = 1920;
1258         cap->bt.max_height = 1200;
1259         cap->bt.min_pixelclock = 25000000;
1260         if (is_digital_input(sd))
1261                 cap->bt.max_pixelclock = 225000000;
1262         else
1263                 cap->bt.max_pixelclock = 170000000;
1264         cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1265                          V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1266         cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1267                 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1268         return 0;
1269 }
1270
1271 /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1272    if the format is listed in adv7604_timings[] */
1273 static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1274                 struct v4l2_dv_timings *timings)
1275 {
1276         int i;
1277
1278         for (i = 0; adv7604_timings[i].bt.width; i++) {
1279                 if (v4l2_match_dv_timings(timings, &adv7604_timings[i],
1280                                         is_digital_input(sd) ? 250000 : 1000000)) {
1281                         *timings = adv7604_timings[i];
1282                         break;
1283                 }
1284         }
1285 }
1286
1287 static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1288                         struct v4l2_dv_timings *timings)
1289 {
1290         struct adv7604_state *state = to_state(sd);
1291         struct v4l2_bt_timings *bt = &timings->bt;
1292         struct stdi_readback stdi;
1293
1294         if (!timings)
1295                 return -EINVAL;
1296
1297         memset(timings, 0, sizeof(struct v4l2_dv_timings));
1298
1299         if (no_signal(sd)) {
1300                 state->restart_stdi_once = true;
1301                 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1302                 return -ENOLINK;
1303         }
1304
1305         /* read STDI */
1306         if (read_stdi(sd, &stdi)) {
1307                 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1308                 return -ENOLINK;
1309         }
1310         bt->interlaced = stdi.interlaced ?
1311                 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1312
1313         if (is_digital_input(sd)) {
1314                 uint32_t freq;
1315
1316                 timings->type = V4L2_DV_BT_656_1120;
1317
1318                 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1319                 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1320                 freq = (hdmi_read(sd, 0x06) * 1000000) +
1321                         ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
1322                 if (is_hdmi(sd)) {
1323                         /* adjust for deep color mode */
1324                         unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1325
1326                         freq = freq * 8 / bits_per_channel;
1327                 }
1328                 bt->pixelclock = freq;
1329                 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1330                         hdmi_read(sd, 0x21);
1331                 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1332                         hdmi_read(sd, 0x23);
1333                 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1334                         hdmi_read(sd, 0x25);
1335                 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1336                         hdmi_read(sd, 0x2b)) / 2;
1337                 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1338                         hdmi_read(sd, 0x2f)) / 2;
1339                 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1340                         hdmi_read(sd, 0x33)) / 2;
1341                 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1342                         ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1343                 if (bt->interlaced == V4L2_DV_INTERLACED) {
1344                         bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1345                                         hdmi_read(sd, 0x0c);
1346                         bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1347                                         hdmi_read(sd, 0x2d)) / 2;
1348                         bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1349                                         hdmi_read(sd, 0x31)) / 2;
1350                         bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1351                                         hdmi_read(sd, 0x35)) / 2;
1352                 }
1353                 adv7604_fill_optional_dv_timings_fields(sd, timings);
1354         } else {
1355                 /* find format
1356                  * Since LCVS values are inaccurate [REF_03, p. 275-276],
1357                  * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1358                  */
1359                 if (!stdi2dv_timings(sd, &stdi, timings))
1360                         goto found;
1361                 stdi.lcvs += 1;
1362                 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1363                 if (!stdi2dv_timings(sd, &stdi, timings))
1364                         goto found;
1365                 stdi.lcvs -= 2;
1366                 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1367                 if (stdi2dv_timings(sd, &stdi, timings)) {
1368                         /*
1369                          * The STDI block may measure wrong values, especially
1370                          * for lcvs and lcf. If the driver can not find any
1371                          * valid timing, the STDI block is restarted to measure
1372                          * the video timings again. The function will return an
1373                          * error, but the restart of STDI will generate a new
1374                          * STDI interrupt and the format detection process will
1375                          * restart.
1376                          */
1377                         if (state->restart_stdi_once) {
1378                                 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1379                                 /* TODO restart STDI for Sync Channel 2 */
1380                                 /* enter one-shot mode */
1381                                 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1382                                 /* trigger STDI restart */
1383                                 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1384                                 /* reset to continuous mode */
1385                                 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1386                                 state->restart_stdi_once = false;
1387                                 return -ENOLINK;
1388                         }
1389                         v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1390                         return -ERANGE;
1391                 }
1392                 state->restart_stdi_once = true;
1393         }
1394 found:
1395
1396         if (no_signal(sd)) {
1397                 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1398                 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1399                 return -ENOLINK;
1400         }
1401
1402         if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1403                         (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1404                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1405                                 __func__, (u32)bt->pixelclock);
1406                 return -ERANGE;
1407         }
1408
1409         if (debug > 1)
1410                 v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ",
1411                                       timings, true);
1412
1413         return 0;
1414 }
1415
1416 static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1417                 struct v4l2_dv_timings *timings)
1418 {
1419         struct adv7604_state *state = to_state(sd);
1420         struct v4l2_bt_timings *bt;
1421         int err;
1422
1423         if (!timings)
1424                 return -EINVAL;
1425
1426         if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1427                 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1428                 return 0;
1429         }
1430
1431         bt = &timings->bt;
1432
1433         if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1434                         (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1435                 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1436                                 __func__, (u32)bt->pixelclock);
1437                 return -ERANGE;
1438         }
1439
1440         adv7604_fill_optional_dv_timings_fields(sd, timings);
1441
1442         state->timings = *timings;
1443
1444         cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10);
1445
1446         /* Use prim_mode and vid_std when available */
1447         err = configure_predefined_video_timings(sd, timings);
1448         if (err) {
1449                 /* custom settings when the video format
1450                  does not have prim_mode/vid_std */
1451                 configure_custom_video_timings(sd, bt);
1452         }
1453
1454         set_rgb_quantization_range(sd);
1455
1456         if (debug > 1)
1457                 v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ",
1458                                       timings, true);
1459         return 0;
1460 }
1461
1462 static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1463                 struct v4l2_dv_timings *timings)
1464 {
1465         struct adv7604_state *state = to_state(sd);
1466
1467         *timings = state->timings;
1468         return 0;
1469 }
1470
1471 static void enable_input(struct v4l2_subdev *sd)
1472 {
1473         struct adv7604_state *state = to_state(sd);
1474
1475         if (is_analog_input(sd)) {
1476                 io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1477         } else if (is_digital_input(sd)) {
1478                 hdmi_write_and_or(sd, 0x00, 0xfc, state->selected_input);
1479                 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1480                 io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1481                 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
1482         } else {
1483                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1484                                 __func__, state->selected_input);
1485         }
1486 }
1487
1488 static void disable_input(struct v4l2_subdev *sd)
1489 {
1490         hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio */
1491         msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
1492         io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1493         hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1494 }
1495
1496 static void select_input(struct v4l2_subdev *sd)
1497 {
1498         struct adv7604_state *state = to_state(sd);
1499
1500         if (is_analog_input(sd)) {
1501                 /* reset ADI recommended settings for HDMI: */
1502                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1503                 hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */
1504                 hdmi_write(sd, 0x3d, 0x00); /* DDC bus active pull-up control */
1505                 hdmi_write(sd, 0x3e, 0x74); /* TMDS PLL optimization */
1506                 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1507                 hdmi_write(sd, 0x57, 0x74); /* TMDS PLL optimization */
1508                 hdmi_write(sd, 0x58, 0x63); /* TMDS PLL optimization */
1509                 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1510                 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1511                 hdmi_write(sd, 0x93, 0x88); /* equaliser */
1512                 hdmi_write(sd, 0x94, 0x2e); /* equaliser */
1513                 hdmi_write(sd, 0x96, 0x00); /* enable automatic EQ changing */
1514
1515                 afe_write(sd, 0x00, 0x08); /* power up ADC */
1516                 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1517                 afe_write(sd, 0xc8, 0x00); /* phase control */
1518
1519                 /* set ADI recommended settings for digitizer */
1520                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1521                 afe_write(sd, 0x12, 0x7b); /* ADC noise shaping filter controls */
1522                 afe_write(sd, 0x0c, 0x1f); /* CP core gain controls */
1523                 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1524                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1525                 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1526         } else if (is_digital_input(sd)) {
1527                 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1528
1529                 /* set ADI recommended settings for HDMI: */
1530                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1531                 hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */
1532                 hdmi_write(sd, 0x3d, 0x10); /* DDC bus active pull-up control */
1533                 hdmi_write(sd, 0x3e, 0x39); /* TMDS PLL optimization */
1534                 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1535                 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1536                 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1537                 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1538                 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1539                 hdmi_write(sd, 0x93, 0x8b); /* equaliser */
1540                 hdmi_write(sd, 0x94, 0x2d); /* equaliser */
1541                 hdmi_write(sd, 0x96, 0x01); /* enable automatic EQ changing */
1542
1543                 afe_write(sd, 0x00, 0xff); /* power down ADC */
1544                 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1545                 afe_write(sd, 0xc8, 0x40); /* phase control */
1546
1547                 /* reset ADI recommended settings for digitizer */
1548                 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1549                 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1550                 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1551                 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1552                 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1553                 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1554         } else {
1555                 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1556                                 __func__, state->selected_input);
1557         }
1558 }
1559
1560 static int adv7604_s_routing(struct v4l2_subdev *sd,
1561                 u32 input, u32 output, u32 config)
1562 {
1563         struct adv7604_state *state = to_state(sd);
1564
1565         v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1566                         __func__, input, state->selected_input);
1567
1568         if (input == state->selected_input)
1569                 return 0;
1570
1571         state->selected_input = input;
1572
1573         disable_input(sd);
1574
1575         select_input(sd);
1576
1577         enable_input(sd);
1578
1579         return 0;
1580 }
1581
1582 static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1583                              enum v4l2_mbus_pixelcode *code)
1584 {
1585         if (index)
1586                 return -EINVAL;
1587         /* Good enough for now */
1588         *code = V4L2_MBUS_FMT_FIXED;
1589         return 0;
1590 }
1591
1592 static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd,
1593                 struct v4l2_mbus_framefmt *fmt)
1594 {
1595         struct adv7604_state *state = to_state(sd);
1596
1597         fmt->width = state->timings.bt.width;
1598         fmt->height = state->timings.bt.height;
1599         fmt->code = V4L2_MBUS_FMT_FIXED;
1600         fmt->field = V4L2_FIELD_NONE;
1601         if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1602                 fmt->colorspace = (state->timings.bt.height <= 576) ?
1603                         V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1604         }
1605         return 0;
1606 }
1607
1608 static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1609 {
1610         const u8 irq_reg_0x43 = io_read(sd, 0x43);
1611         const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1612         const u8 irq_reg_0x70 = io_read(sd, 0x70);
1613         u8 fmt_change_digital;
1614         u8 fmt_change;
1615         u8 tx_5v;
1616
1617         if (irq_reg_0x43)
1618                 io_write(sd, 0x44, irq_reg_0x43);
1619         if (irq_reg_0x70)
1620                 io_write(sd, 0x71, irq_reg_0x70);
1621         if (irq_reg_0x6b)
1622                 io_write(sd, 0x6c, irq_reg_0x6b);
1623
1624         v4l2_dbg(2, debug, sd, "%s: ", __func__);
1625
1626         /* format change */
1627         fmt_change = irq_reg_0x43 & 0x98;
1628         fmt_change_digital = is_digital_input(sd) ? (irq_reg_0x6b & 0xc0) : 0;
1629
1630         if (fmt_change || fmt_change_digital) {
1631                 v4l2_dbg(1, debug, sd,
1632                         "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1633                         __func__, fmt_change, fmt_change_digital);
1634
1635                 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
1636
1637                 if (handled)
1638                         *handled = true;
1639         }
1640         /* HDMI/DVI mode */
1641         if (irq_reg_0x6b & 0x01) {
1642                 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
1643                         (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
1644                 set_rgb_quantization_range(sd);
1645                 if (handled)
1646                         *handled = true;
1647         }
1648
1649         /* tx 5v detect */
1650         tx_5v = io_read(sd, 0x70) & 0x1e;
1651         if (tx_5v) {
1652                 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1653                 io_write(sd, 0x71, tx_5v);
1654                 adv7604_s_detect_tx_5v_ctrl(sd);
1655                 if (handled)
1656                         *handled = true;
1657         }
1658         return 0;
1659 }
1660
1661 static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1662 {
1663         struct adv7604_state *state = to_state(sd);
1664         u8 *data = NULL;
1665
1666         if (edid->pad > ADV7604_EDID_PORT_D)
1667                 return -EINVAL;
1668         if (edid->blocks == 0)
1669                 return -EINVAL;
1670         if (edid->blocks > 2)
1671                 return -EINVAL;
1672         if (edid->start_block > 1)
1673                 return -EINVAL;
1674         if (edid->start_block == 1)
1675                 edid->blocks = 1;
1676         if (!edid->edid)
1677                 return -EINVAL;
1678
1679         if (edid->blocks > state->edid.blocks)
1680                 edid->blocks = state->edid.blocks;
1681
1682         switch (edid->pad) {
1683         case ADV7604_EDID_PORT_A:
1684         case ADV7604_EDID_PORT_B:
1685         case ADV7604_EDID_PORT_C:
1686         case ADV7604_EDID_PORT_D:
1687                 if (state->edid.present & (1 << edid->pad))
1688                         data = state->edid.edid;
1689                 break;
1690         default:
1691                 return -EINVAL;
1692                 break;
1693         }
1694         if (!data)
1695                 return -ENODATA;
1696
1697         memcpy(edid->edid,
1698                data + edid->start_block * 128,
1699                edid->blocks * 128);
1700         return 0;
1701 }
1702
1703 static int get_edid_spa_location(const u8 *edid)
1704 {
1705         u8 d;
1706
1707         if ((edid[0x7e] != 1) ||
1708             (edid[0x80] != 0x02) ||
1709             (edid[0x81] != 0x03)) {
1710                 return -1;
1711         }
1712
1713         /* search Vendor Specific Data Block (tag 3) */
1714         d = edid[0x82] & 0x7f;
1715         if (d > 4) {
1716                 int i = 0x84;
1717                 int end = 0x80 + d;
1718
1719                 do {
1720                         u8 tag = edid[i] >> 5;
1721                         u8 len = edid[i] & 0x1f;
1722
1723                         if ((tag == 3) && (len >= 5))
1724                                 return i + 4;
1725                         i += len + 1;
1726                 } while (i < end);
1727         }
1728         return -1;
1729 }
1730
1731 static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1732 {
1733         struct adv7604_state *state = to_state(sd);
1734         int spa_loc;
1735         int tmp = 0;
1736         int err;
1737         int i;
1738
1739         if (edid->pad > ADV7604_EDID_PORT_D)
1740                 return -EINVAL;
1741         if (edid->start_block != 0)
1742                 return -EINVAL;
1743         if (edid->blocks == 0) {
1744                 /* Disable hotplug and I2C access to EDID RAM from DDC port */
1745                 state->edid.present &= ~(1 << edid->pad);
1746                 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
1747                 rep_write_and_or(sd, 0x77, 0xf0, state->edid.present);
1748
1749                 /* Fall back to a 16:9 aspect ratio */
1750                 state->aspect_ratio.numerator = 16;
1751                 state->aspect_ratio.denominator = 9;
1752
1753                 if (!state->edid.present)
1754                         state->edid.blocks = 0;
1755
1756                 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
1757                                 __func__, edid->pad, state->edid.present);
1758                 return 0;
1759         }
1760         if (edid->blocks > 2) {
1761                 edid->blocks = 2;
1762                 return -E2BIG;
1763         }
1764         if (!edid->edid)
1765                 return -EINVAL;
1766
1767         v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
1768                         __func__, edid->pad, state->edid.present);
1769
1770         /* Disable hotplug and I2C access to EDID RAM from DDC port */
1771         cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
1772         v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&tmp);
1773         rep_write_and_or(sd, 0x77, 0xf0, 0x00);
1774
1775         spa_loc = get_edid_spa_location(edid->edid);
1776         if (spa_loc < 0)
1777                 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
1778
1779         switch (edid->pad) {
1780         case ADV7604_EDID_PORT_A:
1781                 state->spa_port_a[0] = edid->edid[spa_loc];
1782                 state->spa_port_a[1] = edid->edid[spa_loc + 1];
1783                 break;
1784         case ADV7604_EDID_PORT_B:
1785                 rep_write(sd, 0x70, edid->edid[spa_loc]);
1786                 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
1787                 break;
1788         case ADV7604_EDID_PORT_C:
1789                 rep_write(sd, 0x72, edid->edid[spa_loc]);
1790                 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
1791                 break;
1792         case ADV7604_EDID_PORT_D:
1793                 rep_write(sd, 0x74, edid->edid[spa_loc]);
1794                 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
1795                 break;
1796         default:
1797                 return -EINVAL;
1798         }
1799         rep_write(sd, 0x76, spa_loc & 0xff);
1800         rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
1801
1802         edid->edid[spa_loc] = state->spa_port_a[0];
1803         edid->edid[spa_loc + 1] = state->spa_port_a[1];
1804
1805         memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
1806         state->edid.blocks = edid->blocks;
1807         state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
1808                         edid->edid[0x16]);
1809         state->edid.present |= 1 << edid->pad;
1810
1811         err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
1812         if (err < 0) {
1813                 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
1814                 return err;
1815         }
1816
1817         /* adv7604 calculates the checksums and enables I2C access to internal
1818            EDID RAM from DDC port. */
1819         rep_write_and_or(sd, 0x77, 0xf0, state->edid.present);
1820
1821         for (i = 0; i < 1000; i++) {
1822                 if (rep_read(sd, 0x7d) & state->edid.present)
1823                         break;
1824                 mdelay(1);
1825         }
1826         if (i == 1000) {
1827                 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
1828                 return -EIO;
1829         }
1830
1831
1832         /* enable hotplug after 100 ms */
1833         queue_delayed_work(state->work_queues,
1834                         &state->delayed_work_enable_hotplug, HZ / 10);
1835         return 0;
1836 }
1837
1838 /*********** avi info frame CEA-861-E **************/
1839
1840 static void print_avi_infoframe(struct v4l2_subdev *sd)
1841 {
1842         int i;
1843         u8 buf[14];
1844         u8 avi_len;
1845         u8 avi_ver;
1846
1847         if (!is_hdmi(sd)) {
1848                 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
1849                 return;
1850         }
1851         if (!(io_read(sd, 0x60) & 0x01)) {
1852                 v4l2_info(sd, "AVI infoframe not received\n");
1853                 return;
1854         }
1855
1856         if (io_read(sd, 0x83) & 0x01) {
1857                 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
1858                 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1859                 if (io_read(sd, 0x83) & 0x01) {
1860                         v4l2_info(sd, "AVI infoframe checksum error still present\n");
1861                         io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1862                 }
1863         }
1864
1865         avi_len = infoframe_read(sd, 0xe2);
1866         avi_ver = infoframe_read(sd, 0xe1);
1867         v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
1868                         avi_ver, avi_len);
1869
1870         if (avi_ver != 0x02)
1871                 return;
1872
1873         for (i = 0; i < 14; i++)
1874                 buf[i] = infoframe_read(sd, i);
1875
1876         v4l2_info(sd,
1877                 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
1878                 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
1879                 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
1880 }
1881
1882 static int adv7604_log_status(struct v4l2_subdev *sd)
1883 {
1884         struct adv7604_state *state = to_state(sd);
1885         struct v4l2_dv_timings timings;
1886         struct stdi_readback stdi;
1887         u8 reg_io_0x02 = io_read(sd, 0x02);
1888
1889         char *csc_coeff_sel_rb[16] = {
1890                 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
1891                 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
1892                 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
1893                 "reserved", "reserved", "reserved", "reserved", "manual"
1894         };
1895         char *input_color_space_txt[16] = {
1896                 "RGB limited range (16-235)", "RGB full range (0-255)",
1897                 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
1898                 "xvYCC Bt.601", "xvYCC Bt.709",
1899                 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
1900                 "invalid", "invalid", "invalid", "invalid", "invalid",
1901                 "invalid", "invalid", "automatic"
1902         };
1903         char *rgb_quantization_range_txt[] = {
1904                 "Automatic",
1905                 "RGB limited range (16-235)",
1906                 "RGB full range (0-255)",
1907         };
1908         char *deep_color_mode_txt[4] = {
1909                 "8-bits per channel",
1910                 "10-bits per channel",
1911                 "12-bits per channel",
1912                 "16-bits per channel (not supported)"
1913         };
1914
1915         v4l2_info(sd, "-----Chip status-----\n");
1916         v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
1917         v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
1918                         ((rep_read(sd, 0x7d) & 0x01) ? "Yes" : "No"),
1919                         ((rep_read(sd, 0x7d) & 0x02) ? "Yes" : "No"),
1920                         ((rep_read(sd, 0x7d) & 0x04) ? "Yes" : "No"),
1921                         ((rep_read(sd, 0x7d) & 0x08) ? "Yes" : "No"));
1922         v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
1923                         "enabled" : "disabled");
1924
1925         v4l2_info(sd, "-----Signal status-----\n");
1926         v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
1927                         ((io_read(sd, 0x6f) & 0x10) ? "Yes" : "No"),
1928                         ((io_read(sd, 0x6f) & 0x08) ? "Yes" : "No"),
1929                         ((io_read(sd, 0x6f) & 0x04) ? "Yes" : "No"),
1930                         ((io_read(sd, 0x6f) & 0x02) ? "Yes" : "No"));
1931         v4l2_info(sd, "TMDS signal detected: %s\n",
1932                         no_signal_tmds(sd) ? "false" : "true");
1933         v4l2_info(sd, "TMDS signal locked: %s\n",
1934                         no_lock_tmds(sd) ? "false" : "true");
1935         v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
1936         v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
1937         v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
1938         v4l2_info(sd, "CP free run: %s\n",
1939                         (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
1940         v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
1941                         io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
1942                         (io_read(sd, 0x01) & 0x70) >> 4);
1943
1944         v4l2_info(sd, "-----Video Timings-----\n");
1945         if (read_stdi(sd, &stdi))
1946                 v4l2_info(sd, "STDI: not locked\n");
1947         else
1948                 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
1949                                 stdi.lcf, stdi.bl, stdi.lcvs,
1950                                 stdi.interlaced ? "interlaced" : "progressive",
1951                                 stdi.hs_pol, stdi.vs_pol);
1952         if (adv7604_query_dv_timings(sd, &timings))
1953                 v4l2_info(sd, "No video detected\n");
1954         else
1955                 v4l2_print_dv_timings(sd->name, "Detected format: ",
1956                                       &timings, true);
1957         v4l2_print_dv_timings(sd->name, "Configured format: ",
1958                               &state->timings, true);
1959
1960         if (no_signal(sd))
1961                 return 0;
1962
1963         v4l2_info(sd, "-----Color space-----\n");
1964         v4l2_info(sd, "RGB quantization range ctrl: %s\n",
1965                         rgb_quantization_range_txt[state->rgb_quantization_range]);
1966         v4l2_info(sd, "Input color space: %s\n",
1967                         input_color_space_txt[reg_io_0x02 >> 4]);
1968         v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
1969                         (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
1970                         (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
1971                         ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
1972                                 "enabled" : "disabled");
1973         v4l2_info(sd, "Color space conversion: %s\n",
1974                         csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
1975
1976         if (!is_digital_input(sd))
1977                 return 0;
1978
1979         v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1980         v4l2_info(sd, "Digital video port selected: %c\n",
1981                         (hdmi_read(sd, 0x00) & 0x03) + 'A');
1982         v4l2_info(sd, "HDCP encrypted content: %s\n",
1983                         (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
1984         v4l2_info(sd, "HDCP keys read: %s%s\n",
1985                         (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
1986                         (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
1987         if (!is_hdmi(sd)) {
1988                 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
1989                 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
1990                 bool audio_mute = io_read(sd, 0x65) & 0x40;
1991
1992                 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
1993                                 audio_pll_locked ? "locked" : "not locked",
1994                                 audio_sample_packet_detect ? "detected" : "not detected",
1995                                 audio_mute ? "muted" : "enabled");
1996                 if (audio_pll_locked && audio_sample_packet_detect) {
1997                         v4l2_info(sd, "Audio format: %s\n",
1998                                         (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
1999                 }
2000                 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2001                                 (hdmi_read(sd, 0x5c) << 8) +
2002                                 (hdmi_read(sd, 0x5d) & 0xf0));
2003                 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2004                                 (hdmi_read(sd, 0x5e) << 8) +
2005                                 hdmi_read(sd, 0x5f));
2006                 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2007
2008                 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2009
2010                 print_avi_infoframe(sd);
2011         }
2012
2013         return 0;
2014 }
2015
2016 /* ----------------------------------------------------------------------- */
2017
2018 static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
2019         .s_ctrl = adv7604_s_ctrl,
2020 };
2021
2022 static const struct v4l2_subdev_core_ops adv7604_core_ops = {
2023         .log_status = adv7604_log_status,
2024         .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
2025         .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
2026         .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
2027         .g_ctrl = v4l2_subdev_g_ctrl,
2028         .s_ctrl = v4l2_subdev_s_ctrl,
2029         .queryctrl = v4l2_subdev_queryctrl,
2030         .querymenu = v4l2_subdev_querymenu,
2031         .interrupt_service_routine = adv7604_isr,
2032 #ifdef CONFIG_VIDEO_ADV_DEBUG
2033         .g_register = adv7604_g_register,
2034         .s_register = adv7604_s_register,
2035 #endif
2036 };
2037
2038 static const struct v4l2_subdev_video_ops adv7604_video_ops = {
2039         .s_routing = adv7604_s_routing,
2040         .g_input_status = adv7604_g_input_status,
2041         .s_dv_timings = adv7604_s_dv_timings,
2042         .g_dv_timings = adv7604_g_dv_timings,
2043         .query_dv_timings = adv7604_query_dv_timings,
2044         .enum_dv_timings = adv7604_enum_dv_timings,
2045         .dv_timings_cap = adv7604_dv_timings_cap,
2046         .enum_mbus_fmt = adv7604_enum_mbus_fmt,
2047         .g_mbus_fmt = adv7604_g_mbus_fmt,
2048         .try_mbus_fmt = adv7604_g_mbus_fmt,
2049         .s_mbus_fmt = adv7604_g_mbus_fmt,
2050 };
2051
2052 static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
2053         .get_edid = adv7604_get_edid,
2054         .set_edid = adv7604_set_edid,
2055 };
2056
2057 static const struct v4l2_subdev_ops adv7604_ops = {
2058         .core = &adv7604_core_ops,
2059         .video = &adv7604_video_ops,
2060         .pad = &adv7604_pad_ops,
2061 };
2062
2063 /* -------------------------- custom ctrls ---------------------------------- */
2064
2065 static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2066         .ops = &adv7604_ctrl_ops,
2067         .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2068         .name = "Analog Sampling Phase",
2069         .type = V4L2_CTRL_TYPE_INTEGER,
2070         .min = 0,
2071         .max = 0x1f,
2072         .step = 1,
2073         .def = 0,
2074 };
2075
2076 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
2077         .ops = &adv7604_ctrl_ops,
2078         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2079         .name = "Free Running Color, Manual",
2080         .type = V4L2_CTRL_TYPE_BOOLEAN,
2081         .min = false,
2082         .max = true,
2083         .step = 1,
2084         .def = false,
2085 };
2086
2087 static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
2088         .ops = &adv7604_ctrl_ops,
2089         .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2090         .name = "Free Running Color",
2091         .type = V4L2_CTRL_TYPE_INTEGER,
2092         .min = 0x0,
2093         .max = 0xffffff,
2094         .step = 0x1,
2095         .def = 0x0,
2096 };
2097
2098 /* ----------------------------------------------------------------------- */
2099
2100 static int adv7604_core_init(struct v4l2_subdev *sd)
2101 {
2102         struct adv7604_state *state = to_state(sd);
2103         struct adv7604_platform_data *pdata = &state->pdata;
2104
2105         hdmi_write(sd, 0x48,
2106                 (pdata->disable_pwrdnb ? 0x80 : 0) |
2107                 (pdata->disable_cable_det_rst ? 0x40 : 0));
2108
2109         disable_input(sd);
2110
2111         /* power */
2112         io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
2113         io_write(sd, 0x0b, 0x44);   /* Power down ESDP block */
2114         cp_write(sd, 0xcf, 0x01);   /* Power down macrovision */
2115
2116         /* video format */
2117         io_write_and_or(sd, 0x02, 0xf0,
2118                         pdata->alt_gamma << 3 |
2119                         pdata->op_656_range << 2 |
2120                         pdata->rgb_out << 1 |
2121                         pdata->alt_data_sat << 0);
2122         io_write(sd, 0x03, pdata->op_format_sel);
2123         io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
2124         io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2125                                         pdata->insert_av_codes << 2 |
2126                                         pdata->replicate_av_codes << 1 |
2127                                         pdata->invert_cbcr << 0);
2128
2129         cp_write(sd, 0x69, 0x30);   /* Enable CP CSC */
2130
2131         /* VS, HS polarities */
2132         io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | pdata->inv_hs_pol << 1);
2133
2134         /* Adjust drive strength */
2135         io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2136                                 pdata->dr_str_clk << 2 |
2137                                 pdata->dr_str_sync);
2138
2139         cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2140         cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2141         cp_write(sd, 0xf9, 0x23); /*  STDI ch. 1 - LCVS change threshold -
2142                                       ADI recommended setting [REF_01, c. 2.3.3] */
2143         cp_write(sd, 0x45, 0x23); /*  STDI ch. 2 - LCVS change threshold -
2144                                       ADI recommended setting [REF_01, c. 2.3.3] */
2145         cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2146                                      for digital formats */
2147
2148         /* HDMI audio */
2149         hdmi_write_and_or(sd, 0x15, 0xfc, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2150         hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
2151         hdmi_write_and_or(sd, 0x68, 0xf9, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2152
2153         /* TODO from platform data */
2154         afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */
2155
2156         afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2157         io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2158
2159         /* interrupts */
2160         io_write(sd, 0x40, 0xc2); /* Configure INT1 */
2161         io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2162         io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2163         io_write(sd, 0x6e, 0xc1); /* Enable V_LOCKED, DE_REGEN_LCK, HDMI_MODE interrupts */
2164         io_write(sd, 0x73, 0x1e); /* Enable CABLE_DET_A_ST (+5v) interrupts */
2165
2166         return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2167 }
2168
2169 static void adv7604_unregister_clients(struct adv7604_state *state)
2170 {
2171         if (state->i2c_avlink)
2172                 i2c_unregister_device(state->i2c_avlink);
2173         if (state->i2c_cec)
2174                 i2c_unregister_device(state->i2c_cec);
2175         if (state->i2c_infoframe)
2176                 i2c_unregister_device(state->i2c_infoframe);
2177         if (state->i2c_esdp)
2178                 i2c_unregister_device(state->i2c_esdp);
2179         if (state->i2c_dpp)
2180                 i2c_unregister_device(state->i2c_dpp);
2181         if (state->i2c_afe)
2182                 i2c_unregister_device(state->i2c_afe);
2183         if (state->i2c_repeater)
2184                 i2c_unregister_device(state->i2c_repeater);
2185         if (state->i2c_edid)
2186                 i2c_unregister_device(state->i2c_edid);
2187         if (state->i2c_hdmi)
2188                 i2c_unregister_device(state->i2c_hdmi);
2189         if (state->i2c_test)
2190                 i2c_unregister_device(state->i2c_test);
2191         if (state->i2c_cp)
2192                 i2c_unregister_device(state->i2c_cp);
2193         if (state->i2c_vdp)
2194                 i2c_unregister_device(state->i2c_vdp);
2195 }
2196
2197 static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
2198                                                         u8 addr, u8 io_reg)
2199 {
2200         struct i2c_client *client = v4l2_get_subdevdata(sd);
2201
2202         if (addr)
2203                 io_write(sd, io_reg, addr << 1);
2204         return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2205 }
2206
2207 static int adv7604_probe(struct i2c_client *client,
2208                          const struct i2c_device_id *id)
2209 {
2210         static const struct v4l2_dv_timings cea640x480 =
2211                 V4L2_DV_BT_CEA_640X480P59_94;
2212         struct adv7604_state *state;
2213         struct adv7604_platform_data *pdata = client->dev.platform_data;
2214         struct v4l2_ctrl_handler *hdl;
2215         struct v4l2_subdev *sd;
2216         int err;
2217
2218         /* Check if the adapter supports the needed features */
2219         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2220                 return -EIO;
2221         v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
2222                         client->addr << 1);
2223
2224         state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
2225         if (!state) {
2226                 v4l_err(client, "Could not allocate adv7604_state memory!\n");
2227                 return -ENOMEM;
2228         }
2229
2230         /* initialize variables */
2231         state->restart_stdi_once = true;
2232         state->selected_input = ~0;
2233
2234         /* platform data */
2235         if (!pdata) {
2236                 v4l_err(client, "No platform data!\n");
2237                 return -ENODEV;
2238         }
2239         state->pdata = *pdata;
2240         state->timings = cea640x480;
2241
2242         sd = &state->sd;
2243         v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
2244         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
2245
2246         /* i2c access to adv7604? */
2247         if (adv_smbus_read_byte_data_check(client, 0xfb, false) != 0x68) {
2248                 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2249                                 client->addr << 1);
2250                 return -ENODEV;
2251         }
2252
2253         /* control handlers */
2254         hdl = &state->hdl;
2255         v4l2_ctrl_handler_init(hdl, 9);
2256
2257         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2258                         V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2259         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2260                         V4L2_CID_CONTRAST, 0, 255, 1, 128);
2261         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2262                         V4L2_CID_SATURATION, 0, 255, 1, 128);
2263         v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2264                         V4L2_CID_HUE, 0, 128, 1, 0);
2265
2266         /* private controls */
2267         state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2268                         V4L2_CID_DV_RX_POWER_PRESENT, 0, 0x0f, 0, 0);
2269         state->rgb_quantization_range_ctrl =
2270                 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
2271                         V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2272                         0, V4L2_DV_RGB_RANGE_AUTO);
2273
2274         /* custom controls */
2275         state->analog_sampling_phase_ctrl =
2276                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
2277         state->free_run_color_manual_ctrl =
2278                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
2279         state->free_run_color_ctrl =
2280                 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
2281
2282         sd->ctrl_handler = hdl;
2283         if (hdl->error) {
2284                 err = hdl->error;
2285                 goto err_hdl;
2286         }
2287         state->detect_tx_5v_ctrl->is_private = true;
2288         state->rgb_quantization_range_ctrl->is_private = true;
2289         state->analog_sampling_phase_ctrl->is_private = true;
2290         state->free_run_color_manual_ctrl->is_private = true;
2291         state->free_run_color_ctrl->is_private = true;
2292
2293         if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2294                 err = -ENODEV;
2295                 goto err_hdl;
2296         }
2297
2298         state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2299         state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4);
2300         state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2301         state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6);
2302         state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7);
2303         state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8);
2304         state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2305         state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa);
2306         state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2307         state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc);
2308         state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd);
2309         state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2310         if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2311             !state->i2c_esdp || !state->i2c_dpp || !state->i2c_afe ||
2312             !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2313             !state->i2c_test || !state->i2c_cp || !state->i2c_vdp) {
2314                 err = -ENOMEM;
2315                 v4l2_err(sd, "failed to create all i2c clients\n");
2316                 goto err_i2c;
2317         }
2318
2319         /* work queues */
2320         state->work_queues = create_singlethread_workqueue(client->name);
2321         if (!state->work_queues) {
2322                 v4l2_err(sd, "Could not create work queue\n");
2323                 err = -ENOMEM;
2324                 goto err_i2c;
2325         }
2326
2327         INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2328                         adv7604_delayed_work_enable_hotplug);
2329
2330         state->pad.flags = MEDIA_PAD_FL_SOURCE;
2331         err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2332         if (err)
2333                 goto err_work_queues;
2334
2335         err = adv7604_core_init(sd);
2336         if (err)
2337                 goto err_entity;
2338         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2339                         client->addr << 1, client->adapter->name);
2340         return 0;
2341
2342 err_entity:
2343         media_entity_cleanup(&sd->entity);
2344 err_work_queues:
2345         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2346         destroy_workqueue(state->work_queues);
2347 err_i2c:
2348         adv7604_unregister_clients(state);
2349 err_hdl:
2350         v4l2_ctrl_handler_free(hdl);
2351         return err;
2352 }
2353
2354 /* ----------------------------------------------------------------------- */
2355
2356 static int adv7604_remove(struct i2c_client *client)
2357 {
2358         struct v4l2_subdev *sd = i2c_get_clientdata(client);
2359         struct adv7604_state *state = to_state(sd);
2360
2361         cancel_delayed_work(&state->delayed_work_enable_hotplug);
2362         destroy_workqueue(state->work_queues);
2363         v4l2_device_unregister_subdev(sd);
2364         media_entity_cleanup(&sd->entity);
2365         adv7604_unregister_clients(to_state(sd));
2366         v4l2_ctrl_handler_free(sd->ctrl_handler);
2367         return 0;
2368 }
2369
2370 /* ----------------------------------------------------------------------- */
2371
2372 static struct i2c_device_id adv7604_id[] = {
2373         { "adv7604", 0 },
2374         { }
2375 };
2376 MODULE_DEVICE_TABLE(i2c, adv7604_id);
2377
2378 static struct i2c_driver adv7604_driver = {
2379         .driver = {
2380                 .owner = THIS_MODULE,
2381                 .name = "adv7604",
2382         },
2383         .probe = adv7604_probe,
2384         .remove = adv7604_remove,
2385         .id_table = adv7604_id,
2386 };
2387
2388 module_i2c_driver(adv7604_driver);