Pileus Git - ~andy/linux/blob - drivers/media/dvb/ttpci/budget-ci.c

   1 /*
   2  * budget-ci.c: driver for the SAA7146 based Budget DVB cards
   3  *
   4  * Compiled from various sources by Michael Hunold <michael@mihu.de>
   5  *
   6  *     msp430 IR support contributed by Jack Thomasson <jkt@Helius.COM>
   7  *     partially based on the Siemens DVB driver by Ralph+Marcus Metzler
   8  *
   9  * CI interface support (c) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License
  13  * as published by the Free Software Foundation; either version 2
  14  * of the License, or (at your option) any later version.
  15  *
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  26  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  27  *
  28  *
  29  * the project's page is at http://www.linuxtv.org/dvb/
  30  */
  31
  32 #include <linux/module.h>
  33 #include <linux/errno.h>
  34 #include <linux/slab.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/input.h>
  37 #include <linux/spinlock.h>
  38 #include <media/ir-common.h>
  39
  40 #include "budget.h"
  41
  42 #include "dvb_ca_en50221.h"
  43 #include "stv0299.h"
  44 #include "stv0297.h"
  45 #include "tda1004x.h"
  46 #include "stb0899_drv.h"
  47 #include "stb0899_reg.h"
  48 #include "stb0899_cfg.h"
  49 #include "stb6100.h"
  50 #include "stb6100_cfg.h"
  51 #include "lnbp21.h"
  52 #include "bsbe1.h"
  53 #include "bsru6.h"
  54 #include "tda1002x.h"
  55 #include "tda827x.h"
  56
  57 /*
  58  * Regarding DEBIADDR_IR:
  59  * Some CI modules hang if random addresses are read.
  60  * Using address 0x4000 for the IR read means that we
  61  * use the same address as for CI version, which should
  62  * be a safe default.
  63  */
  64 #define DEBIADDR_IR             0x4000
  65 #define DEBIADDR_CICONTROL      0x0000
  66 #define DEBIADDR_CIVERSION      0x4000
  67 #define DEBIADDR_IO             0x1000
  68 #define DEBIADDR_ATTR           0x3000
  69
  70 #define CICONTROL_RESET         0x01
  71 #define CICONTROL_ENABLETS      0x02
  72 #define CICONTROL_CAMDETECT     0x08
  73
  74 #define DEBICICTL               0x00420000
  75 #define DEBICICAM               0x02420000
  76
  77 #define SLOTSTATUS_NONE         1
  78 #define SLOTSTATUS_PRESENT      2
  79 #define SLOTSTATUS_RESET        4
  80 #define SLOTSTATUS_READY        8
  81 #define SLOTSTATUS_OCCUPIED     (SLOTSTATUS_PRESENT|SLOTSTATUS_RESET|SLOTSTATUS_READY)
  82
  83 /*
  84  * Milliseconds during which a key is regarded as pressed.
  85  * If an identical command arrives within this time, the timer will start over.
  86  */
  87 #define IR_KEYPRESS_TIMEOUT     250
  88
  89 /* RC5 device wildcard */
  90 #define IR_DEVICE_ANY           255
  91
  92 static int rc5_device = -1;
  93 module_param(rc5_device, int, 0644);
  94 MODULE_PARM_DESC(rc5_device, "only IR commands to given RC5 device (device = 0 - 31, any device = 255, default: autodetect)");
  95
  96 static int ir_debug;
  97 module_param(ir_debug, int, 0644);
  98 MODULE_PARM_DESC(ir_debug, "enable debugging information for IR decoding");
  99
 100 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
 101
 102 struct budget_ci_ir {
 103         struct input_dev *dev;
 104         struct tasklet_struct msp430_irq_tasklet;
 105         struct timer_list timer_keyup;
 106         char name[72]; /* 40 + 32 for (struct saa7146_dev).name */
 107         char phys[32];
 108         struct ir_input_state state;
 109         int rc5_device;
 110         u32 last_raw;
 111         u32 ir_key;
 112         bool have_command;
 113 };
 114
 115 struct budget_ci {
 116         struct budget budget;
 117         struct tasklet_struct ciintf_irq_tasklet;
 118         int slot_status;
 119         int ci_irq;
 120         struct dvb_ca_en50221 ca;
 121         struct budget_ci_ir ir;
 122         u8 tuner_pll_address; /* used for philips_tdm1316l configs */
 123 };
 124
 125 static void msp430_ir_keyup(unsigned long data)
 126 {
 127         struct budget_ci_ir *ir = (struct budget_ci_ir *) data;
 128         ir_input_nokey(ir->dev, &ir->state);
 129 }
 130
 131 static void msp430_ir_interrupt(unsigned long data)
 132 {
 133         struct budget_ci *budget_ci = (struct budget_ci *) data;
 134         struct input_dev *dev = budget_ci->ir.dev;
 135         u32 command = ttpci_budget_debiread(&budget_ci->budget, DEBINOSWAP, DEBIADDR_IR, 2, 1, 0) >> 8;
 136         u32 raw;
 137
 138         /*
 139          * The msp430 chip can generate two different bytes, command and device
 140          *
 141          * type1: X1CCCCCC, C = command bits (0 - 63)
 142          * type2: X0TDDDDD, D = device bits (0 - 31), T = RC5 toggle bit
 143          *
 144          * Each signal from the remote control can generate one or more command
 145          * bytes and one or more device bytes. For the repeated bytes, the
 146          * highest bit (X) is set. The first command byte is always generated
 147          * before the first device byte. Other than that, no specific order
 148          * seems to apply. To make life interesting, bytes can also be lost.
 149          *
 150          * Only when we have a command and device byte, a keypress is
 151          * generated.
 152          */
 153
 154         if (ir_debug)
 155                 printk("budget_ci: received byte 0x%02x\n", command);
 156
 157         /* Remove repeat bit, we use every command */
 158         command = command & 0x7f;
 159
 160         /* Is this a RC5 command byte? */
 161         if (command & 0x40) {
 162                 budget_ci->ir.have_command = true;
 163                 budget_ci->ir.ir_key = command & 0x3f;
 164                 return;
 165         }
 166
 167         /* It's a RC5 device byte */
 168         if (!budget_ci->ir.have_command)
 169                 return;
 170         budget_ci->ir.have_command = false;
 171
 172         if (budget_ci->ir.rc5_device != IR_DEVICE_ANY &&
 173             budget_ci->ir.rc5_device != (command & 0x1f))
 174                 return;
 175
 176         /* Is this a repeated key sequence? (same device, command, toggle) */
 177         raw = budget_ci->ir.ir_key | (command << 8);
 178         if (budget_ci->ir.last_raw != raw || !timer_pending(&budget_ci->ir.timer_keyup)) {
 179                 ir_input_nokey(dev, &budget_ci->ir.state);
 180                 ir_input_keydown(dev, &budget_ci->ir.state,
 181                                  budget_ci->ir.ir_key);
 182                 budget_ci->ir.last_raw = raw;
 183         }
 184
 185         mod_timer(&budget_ci->ir.timer_keyup, jiffies + msecs_to_jiffies(IR_KEYPRESS_TIMEOUT));
 186 }
 187
 188 static int msp430_ir_init(struct budget_ci *budget_ci)
 189 {
 190         struct saa7146_dev *saa = budget_ci->budget.dev;
 191         struct input_dev *input_dev = budget_ci->ir.dev;
 192         int error;
 193         struct ir_scancode_table *ir_codes;
 194
 195
 196         budget_ci->ir.dev = input_dev = input_allocate_device();
 197         if (!input_dev) {
 198                 printk(KERN_ERR "budget_ci: IR interface initialisation failed\n");
 199                 return -ENOMEM;
 200         }
 201
 202         snprintf(budget_ci->ir.name, sizeof(budget_ci->ir.name),
 203                  "Budget-CI dvb ir receiver %s", saa->name);
 204         snprintf(budget_ci->ir.phys, sizeof(budget_ci->ir.phys),
 205                  "pci-%s/ir0", pci_name(saa->pci));
 206
 207         input_dev->name = budget_ci->ir.name;
 208
 209         input_dev->phys = budget_ci->ir.phys;
 210         input_dev->id.bustype = BUS_PCI;
 211         input_dev->id.version = 1;
 212         if (saa->pci->subsystem_vendor) {
 213                 input_dev->id.vendor = saa->pci->subsystem_vendor;
 214                 input_dev->id.product = saa->pci->subsystem_device;
 215         } else {
 216                 input_dev->id.vendor = saa->pci->vendor;
 217                 input_dev->id.product = saa->pci->device;
 218         }
 219         input_dev->dev.parent = &saa->pci->dev;
 220
 221         if (rc5_device < 0)
 222                 budget_ci->ir.rc5_device = IR_DEVICE_ANY;
 223         else
 224                 budget_ci->ir.rc5_device = rc5_device;
 225
 226         /* Select keymap and address */
 227         switch (budget_ci->budget.dev->pci->subsystem_device) {
 228         case 0x100c:
 229         case 0x100f:
 230         case 0x1011:
 231         case 0x1012:
 232                 /* The hauppauge keymap is a superset of these remotes */
 233                 ir_codes = &ir_codes_hauppauge_new_table;
 234
 235                 if (rc5_device < 0)
 236                         budget_ci->ir.rc5_device = 0x1f;
 237                 break;
 238         case 0x1010:
 239         case 0x1017:
 240         case 0x101a:
 241                 /* for the Technotrend 1500 bundled remote */
 242                 ir_codes = &ir_codes_tt_1500_table;
 243                 break;
 244         default:
 245                 /* unknown remote */
 246                 ir_codes = &ir_codes_budget_ci_old_table;
 247                 break;
 248         }
 249
 250         ir_input_init(input_dev, &budget_ci->ir.state, IR_TYPE_RC5);
 251
 252         /* initialise the key-up timeout handler */
 253         init_timer(&budget_ci->ir.timer_keyup);
 254         budget_ci->ir.timer_keyup.function = msp430_ir_keyup;
 255         budget_ci->ir.timer_keyup.data = (unsigned long) &budget_ci->ir;
 256         budget_ci->ir.last_raw = 0xffff; /* An impossible value */
 257         error = ir_input_register(input_dev, ir_codes, NULL);
 258         if (error) {
 259                 printk(KERN_ERR "budget_ci: could not init driver for IR device (code %d)\n", error);
 260                 return error;
 261         }
 262
 263         /* note: these must be after input_register_device */
 264         input_dev->rep[REP_DELAY] = 400;
 265         input_dev->rep[REP_PERIOD] = 250;
 266
 267         tasklet_init(&budget_ci->ir.msp430_irq_tasklet, msp430_ir_interrupt,
 268                      (unsigned long) budget_ci);
 269
 270         SAA7146_IER_ENABLE(saa, MASK_06);
 271         saa7146_setgpio(saa, 3, SAA7146_GPIO_IRQHI);
 272
 273         return 0;
 274 }
 275
 276 static void msp430_ir_deinit(struct budget_ci *budget_ci)
 277 {
 278         struct saa7146_dev *saa = budget_ci->budget.dev;
 279         struct input_dev *dev = budget_ci->ir.dev;
 280
 281         SAA7146_IER_DISABLE(saa, MASK_06);
 282         saa7146_setgpio(saa, 3, SAA7146_GPIO_INPUT);
 283         tasklet_kill(&budget_ci->ir.msp430_irq_tasklet);
 284
 285         del_timer_sync(&dev->timer);
 286         ir_input_nokey(dev, &budget_ci->ir.state);
 287
 288         ir_input_unregister(dev);
 289 }
 290
 291 static int ciintf_read_attribute_mem(struct dvb_ca_en50221 *ca, int slot, int address)
 292 {
 293         struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
 294
 295         if (slot != 0)
 296                 return -EINVAL;
 297
 298         return ttpci_budget_debiread(&budget_ci->budget, DEBICICAM,
 299                                      DEBIADDR_ATTR | (address & 0xfff), 1, 1, 0);
 300 }
 301
 302 static int ciintf_write_attribute_mem(struct dvb_ca_en50221 *ca, int slot, int address, u8 value)
 303 {
 304         struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
 305
 306         if (slot != 0)
 307                 return -EINVAL;
 308
 309         return ttpci_budget_debiwrite(&budget_ci->budget, DEBICICAM,
 310                                       DEBIADDR_ATTR | (address & 0xfff), 1, value, 1, 0);
 311 }
 312
 313 static int ciintf_read_cam_control(struct dvb_ca_en50221 *ca, int slot, u8 address)
 314 {
 315         struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
 316
 317         if (slot != 0)
 318                 return -EINVAL;
 319
 320         return ttpci_budget_debiread(&budget_ci->budget, DEBICICAM,
 321                                      DEBIADDR_IO | (address & 3), 1, 1, 0);
 322 }
 323
 324 static int ciintf_write_cam_control(struct dvb_ca_en50221 *ca, int slot, u8 address, u8 value)
 325 {
 326         struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
 327
 328         if (slot != 0)
 329                 return -EINVAL;
 330
 331         return ttpci_budget_debiwrite(&budget_ci->budget, DEBICICAM,
 332                                       DEBIADDR_IO | (address & 3), 1, value, 1, 0);
 333 }
 334
 335 static int ciintf_slot_reset(struct dvb_ca_en50221 *ca, int slot)
 336 {
 337         struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
 338         struct saa7146_dev *saa = budget_ci->budget.dev;
 339
 340         if (slot != 0)
 341                 return -EINVAL;
 342
 343         if (budget_ci->ci_irq) {
 344                 // trigger on RISING edge during reset so we know when READY is re-asserted
 345                 saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQHI);
 346         }
 347         budget_ci->slot_status = SLOTSTATUS_RESET;
 348         ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 0, 1, 0);
 349         msleep(1);
 350         ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1,
 351                                CICONTROL_RESET, 1, 0);
 352
 353         saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTHI);
 354         ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTB);
 355         return 0;
 356 }
 357
 358 static int ciintf_slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
 359 {
 360         struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
 361         struct saa7146_dev *saa = budget_ci->budget.dev;
 362
 363         if (slot != 0)
 364                 return -EINVAL;
 365
 366         saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTHI);
 367         ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTB);
 368         return 0;
 369 }
 370
 371 static int ciintf_slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
 372 {
 373         struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
 374         struct saa7146_dev *saa = budget_ci->budget.dev;
 375         int tmp;
 376
 377         if (slot != 0)
 378                 return -EINVAL;
 379
 380         saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTLO);
 381
 382         tmp = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0);
 383         ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1,
 384                                tmp | CICONTROL_ENABLETS, 1, 0);
 385
 386         ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTA);
 387         return 0;
 388 }
 389
 390 static void ciintf_interrupt(unsigned long data)
 391 {
 392         struct budget_ci *budget_ci = (struct budget_ci *) data;
 393         struct saa7146_dev *saa = budget_ci->budget.dev;
 394         unsigned int flags;
 395
 396         // ensure we don't get spurious IRQs during initialisation
 397         if (!budget_ci->budget.ci_present)
 398                 return;
 399
 400         // read the CAM status
 401         flags = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0);
 402         if (flags & CICONTROL_CAMDETECT) {
 403
 404                 // GPIO should be set to trigger on falling edge if a CAM is present
 405                 saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQLO);
 406
 407                 if (budget_ci->slot_status & SLOTSTATUS_NONE) {
 408                         // CAM insertion IRQ
 409                         budget_ci->slot_status = SLOTSTATUS_PRESENT;
 410                         dvb_ca_en50221_camchange_irq(&budget_ci->ca, 0,
 411                                                      DVB_CA_EN50221_CAMCHANGE_INSERTED);
 412
 413                 } else if (budget_ci->slot_status & SLOTSTATUS_RESET) {
 414                         // CAM ready (reset completed)
 415                         budget_ci->slot_status = SLOTSTATUS_READY;
 416                         dvb_ca_en50221_camready_irq(&budget_ci->ca, 0);
 417
 418                 } else if (budget_ci->slot_status & SLOTSTATUS_READY) {
 419                         // FR/DA IRQ
 420                         dvb_ca_en50221_frda_irq(&budget_ci->ca, 0);
 421                 }
 422         } else {
 423
 424                 // trigger on rising edge if a CAM is not present - when a CAM is inserted, we
 425                 // only want to get the IRQ when it sets READY. If we trigger on the falling edge,
 426                 // the CAM might not actually be ready yet.
 427                 saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQHI);
 428
 429                 // generate a CAM removal IRQ if we haven't already
 430                 if (budget_ci->slot_status & SLOTSTATUS_OCCUPIED) {
 431                         // CAM removal IRQ
 432                         budget_ci->slot_status = SLOTSTATUS_NONE;
 433                         dvb_ca_en50221_camchange_irq(&budget_ci->ca, 0,
 434                                                      DVB_CA_EN50221_CAMCHANGE_REMOVED);
 435                 }
 436         }
 437 }
 438
 439 static int ciintf_poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
 440 {
 441         struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
 442         unsigned int flags;
 443
 444         // ensure we don't get spurious IRQs during initialisation
 445         if (!budget_ci->budget.ci_present)
 446                 return -EINVAL;
 447
 448         // read the CAM status
 449         flags = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0);
 450         if (flags & CICONTROL_CAMDETECT) {
 451                 // mark it as present if it wasn't before
 452                 if (budget_ci->slot_status & SLOTSTATUS_NONE) {
 453                         budget_ci->slot_status = SLOTSTATUS_PRESENT;
 454                 }
 455
 456                 // during a RESET, we check if we can read from IO memory to see when CAM is ready
 457                 if (budget_ci->slot_status & SLOTSTATUS_RESET) {
 458                         if (ciintf_read_attribute_mem(ca, slot, 0) == 0x1d) {
 459                                 budget_ci->slot_status = SLOTSTATUS_READY;
 460                         }
 461                 }
 462         } else {
 463                 budget_ci->slot_status = SLOTSTATUS_NONE;
 464         }
 465
 466         if (budget_ci->slot_status != SLOTSTATUS_NONE) {
 467                 if (budget_ci->slot_status & SLOTSTATUS_READY) {
 468                         return DVB_CA_EN50221_POLL_CAM_PRESENT | DVB_CA_EN50221_POLL_CAM_READY;
 469                 }
 470                 return DVB_CA_EN50221_POLL_CAM_PRESENT;
 471         }
 472
 473         return 0;
 474 }
 475
 476 static int ciintf_init(struct budget_ci *budget_ci)
 477 {
 478         struct saa7146_dev *saa = budget_ci->budget.dev;
 479         int flags;
 480         int result;
 481         int ci_version;
 482         int ca_flags;
 483
 484         memset(&budget_ci->ca, 0, sizeof(struct dvb_ca_en50221));
 485
 486         // enable DEBI pins
 487         saa7146_write(saa, MC1, MASK_27 | MASK_11);
 488
 489         // test if it is there
 490         ci_version = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CIVERSION, 1, 1, 0);
 491         if ((ci_version & 0xa0) != 0xa0) {
 492                 result = -ENODEV;
 493                 goto error;
 494         }
 495
 496         // determine whether a CAM is present or not
 497         flags = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0);
 498         budget_ci->slot_status = SLOTSTATUS_NONE;
 499         if (flags & CICONTROL_CAMDETECT)
 500                 budget_ci->slot_status = SLOTSTATUS_PRESENT;
 501
 502         // version 0xa2 of the CI firmware doesn't generate interrupts
 503         if (ci_version == 0xa2) {
 504                 ca_flags = 0;
 505                 budget_ci->ci_irq = 0;
 506         } else {
 507                 ca_flags = DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE |
 508                                 DVB_CA_EN50221_FLAG_IRQ_FR |
 509                                 DVB_CA_EN50221_FLAG_IRQ_DA;
 510                 budget_ci->ci_irq = 1;
 511         }
 512
 513         // register CI interface
 514         budget_ci->ca.owner = THIS_MODULE;
 515         budget_ci->ca.read_attribute_mem = ciintf_read_attribute_mem;
 516         budget_ci->ca.write_attribute_mem = ciintf_write_attribute_mem;
 517         budget_ci->ca.read_cam_control = ciintf_read_cam_control;
 518         budget_ci->ca.write_cam_control = ciintf_write_cam_control;
 519         budget_ci->ca.slot_reset = ciintf_slot_reset;
 520         budget_ci->ca.slot_shutdown = ciintf_slot_shutdown;
 521         budget_ci->ca.slot_ts_enable = ciintf_slot_ts_enable;
 522         budget_ci->ca.poll_slot_status = ciintf_poll_slot_status;
 523         budget_ci->ca.data = budget_ci;
 524         if ((result = dvb_ca_en50221_init(&budget_ci->budget.dvb_adapter,
 525                                           &budget_ci->ca,
 526                                           ca_flags, 1)) != 0) {
 527                 printk("budget_ci: CI interface detected, but initialisation failed.\n");
 528                 goto error;
 529         }
 530
 531         // Setup CI slot IRQ
 532         if (budget_ci->ci_irq) {
 533                 tasklet_init(&budget_ci->ciintf_irq_tasklet, ciintf_interrupt, (unsigned long) budget_ci);
 534                 if (budget_ci->slot_status != SLOTSTATUS_NONE) {
 535                         saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQLO);
 536                 } else {
 537                         saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQHI);
 538                 }
 539                 SAA7146_IER_ENABLE(saa, MASK_03);
 540         }
 541
 542         // enable interface
 543         ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1,
 544                                CICONTROL_RESET, 1, 0);
 545
 546         // success!
 547         printk("budget_ci: CI interface initialised\n");
 548         budget_ci->budget.ci_present = 1;
 549
 550         // forge a fake CI IRQ so the CAM state is setup correctly
 551         if (budget_ci->ci_irq) {
 552                 flags = DVB_CA_EN50221_CAMCHANGE_REMOVED;
 553                 if (budget_ci->slot_status != SLOTSTATUS_NONE)
 554                         flags = DVB_CA_EN50221_CAMCHANGE_INSERTED;
 555                 dvb_ca_en50221_camchange_irq(&budget_ci->ca, 0, flags);
 556         }
 557
 558         return 0;
 559
 560 error:
 561         saa7146_write(saa, MC1, MASK_27);
 562         return result;
 563 }
 564
 565 static void ciintf_deinit(struct budget_ci *budget_ci)
 566 {
 567         struct saa7146_dev *saa = budget_ci->budget.dev;
 568
 569         // disable CI interrupts
 570         if (budget_ci->ci_irq) {
 571                 SAA7146_IER_DISABLE(saa, MASK_03);
 572                 saa7146_setgpio(saa, 0, SAA7146_GPIO_INPUT);
 573                 tasklet_kill(&budget_ci->ciintf_irq_tasklet);
 574         }
 575
 576         // reset interface
 577         ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 0, 1, 0);
 578         msleep(1);
 579         ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1,
 580                                CICONTROL_RESET, 1, 0);
 581
 582         // disable TS data stream to CI interface
 583         saa7146_setgpio(saa, 1, SAA7146_GPIO_INPUT);
 584
 585         // release the CA device
 586         dvb_ca_en50221_release(&budget_ci->ca);
 587
 588         // disable DEBI pins
 589         saa7146_write(saa, MC1, MASK_27);
 590 }
 591
 592 static void budget_ci_irq(struct saa7146_dev *dev, u32 * isr)
 593 {
 594         struct budget_ci *budget_ci = (struct budget_ci *) dev->ext_priv;
 595
 596         dprintk(8, "dev: %p, budget_ci: %p\n", dev, budget_ci);
 597
 598         if (*isr & MASK_06)
 599                 tasklet_schedule(&budget_ci->ir.msp430_irq_tasklet);
 600
 601         if (*isr & MASK_10)
 602                 ttpci_budget_irq10_handler(dev, isr);
 603
 604         if ((*isr & MASK_03) && (budget_ci->budget.ci_present) && (budget_ci->ci_irq))
 605                 tasklet_schedule(&budget_ci->ciintf_irq_tasklet);
 606 }
 607
 608 static u8 philips_su1278_tt_inittab[] = {
 609         0x01, 0x0f,
 610         0x02, 0x30,
 611         0x03, 0x00,
 612         0x04, 0x5b,
 613         0x05, 0x85,
 614         0x06, 0x02,
 615         0x07, 0x00,
 616         0x08, 0x02,
 617         0x09, 0x00,
 618         0x0C, 0x01,
 619         0x0D, 0x81,
 620         0x0E, 0x44,
 621         0x0f, 0x14,
 622         0x10, 0x3c,
 623         0x11, 0x84,
 624         0x12, 0xda,
 625         0x13, 0x97,
 626         0x14, 0x95,
 627         0x15, 0xc9,
 628         0x16, 0x19,
 629         0x17, 0x8c,
 630         0x18, 0x59,
 631         0x19, 0xf8,
 632         0x1a, 0xfe,
 633         0x1c, 0x7f,
 634         0x1d, 0x00,
 635         0x1e, 0x00,
 636         0x1f, 0x50,
 637         0x20, 0x00,
 638         0x21, 0x00,
 639         0x22, 0x00,
 640         0x23, 0x00,
 641         0x28, 0x00,
 642         0x29, 0x28,
 643         0x2a, 0x14,
 644         0x2b, 0x0f,
 645         0x2c, 0x09,
 646         0x2d, 0x09,
 647         0x31, 0x1f,
 648         0x32, 0x19,
 649         0x33, 0xfc,
 650         0x34, 0x93,
 651         0xff, 0xff
 652 };
 653
 654 static int philips_su1278_tt_set_symbol_rate(struct dvb_frontend *fe, u32 srate, u32 ratio)
 655 {
 656         stv0299_writereg(fe, 0x0e, 0x44);
 657         if (srate >= 10000000) {
 658                 stv0299_writereg(fe, 0x13, 0x97);
 659                 stv0299_writereg(fe, 0x14, 0x95);
 660                 stv0299_writereg(fe, 0x15, 0xc9);
 661                 stv0299_writereg(fe, 0x17, 0x8c);
 662                 stv0299_writereg(fe, 0x1a, 0xfe);
 663                 stv0299_writereg(fe, 0x1c, 0x7f);
 664                 stv0299_writereg(fe, 0x2d, 0x09);
 665         } else {
 666                 stv0299_writereg(fe, 0x13, 0x99);
 667                 stv0299_writereg(fe, 0x14, 0x8d);
 668                 stv0299_writereg(fe, 0x15, 0xce);
 669                 stv0299_writereg(fe, 0x17, 0x43);
 670                 stv0299_writereg(fe, 0x1a, 0x1d);
 671                 stv0299_writereg(fe, 0x1c, 0x12);
 672                 stv0299_writereg(fe, 0x2d, 0x05);
 673         }
 674         stv0299_writereg(fe, 0x0e, 0x23);
 675         stv0299_writereg(fe, 0x0f, 0x94);
 676         stv0299_writereg(fe, 0x10, 0x39);
 677         stv0299_writereg(fe, 0x15, 0xc9);
 678
 679         stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
 680         stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
 681         stv0299_writereg(fe, 0x21, (ratio) & 0xf0);
 682
 683         return 0;
 684 }
 685
 686 static int philips_su1278_tt_tuner_set_params(struct dvb_frontend *fe,
 687                                            struct dvb_frontend_parameters *params)
 688 {
 689         struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
 690         u32 div;
 691         u8 buf[4];
 692         struct i2c_msg msg = {.addr = 0x60,.flags = 0,.buf = buf,.len = sizeof(buf) };
 693
 694         if ((params->frequency < 950000) || (params->frequency > 2150000))
 695                 return -EINVAL;
 696
 697         div = (params->frequency + (500 - 1)) / 500;    // round correctly
 698         buf[0] = (div >> 8) & 0x7f;
 699         buf[1] = div & 0xff;
 700         buf[2] = 0x80 | ((div & 0x18000) >> 10) | 2;
 701         buf[3] = 0x20;
 702
 703         if (params->u.qpsk.symbol_rate < 4000000)
 704                 buf[3] |= 1;
 705
 706         if (params->frequency < 1250000)
 707                 buf[3] |= 0;
 708         else if (params->frequency < 1550000)
 709                 buf[3] |= 0x40;
 710         else if (params->frequency < 2050000)
 711                 buf[3] |= 0x80;
 712         else if (params->frequency < 2150000)
 713                 buf[3] |= 0xC0;
 714
 715         if (fe->ops.i2c_gate_ctrl)
 716                 fe->ops.i2c_gate_ctrl(fe, 1);
 717         if (i2c_transfer(&budget_ci->budget.i2c_adap, &msg, 1) != 1)
 718                 return -EIO;
 719         return 0;
 720 }
 721
 722 static struct stv0299_config philips_su1278_tt_config = {
 723
 724         .demod_address = 0x68,
 725         .inittab = philips_su1278_tt_inittab,
 726         .mclk = 64000000UL,
 727         .invert = 0,
 728         .skip_reinit = 1,
 729         .lock_output = STV0299_LOCKOUTPUT_1,
 730         .volt13_op0_op1 = STV0299_VOLT13_OP1,
 731         .min_delay_ms = 50,
 732         .set_symbol_rate = philips_su1278_tt_set_symbol_rate,
 733 };
 734
 735
 736
 737 static int philips_tdm1316l_tuner_init(struct dvb_frontend *fe)
 738 {
 739         struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
 740         static u8 td1316_init[] = { 0x0b, 0xf5, 0x85, 0xab };
 741         static u8 disable_mc44BC374c[] = { 0x1d, 0x74, 0xa0, 0x68 };
 742         struct i2c_msg tuner_msg = {.addr = budget_ci->tuner_pll_address,.flags = 0,.buf = td1316_init,.len =
 743                         sizeof(td1316_init) };
 744
 745         // setup PLL configuration
 746         if (fe->ops.i2c_gate_ctrl)
 747                 fe->ops.i2c_gate_ctrl(fe, 1);
 748         if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1)
 749                 return -EIO;
 750         msleep(1);
 751
 752         // disable the mc44BC374c (do not check for errors)
 753         tuner_msg.addr = 0x65;
 754         tuner_msg.buf = disable_mc44BC374c;
 755         tuner_msg.len = sizeof(disable_mc44BC374c);
 756         if (fe->ops.i2c_gate_ctrl)
 757                 fe->ops.i2c_gate_ctrl(fe, 1);
 758         if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1) {
 759                 if (fe->ops.i2c_gate_ctrl)
 760                         fe->ops.i2c_gate_ctrl(fe, 1);
 761                 i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1);
 762         }
 763
 764         return 0;
 765 }
 766
 767 static int philips_tdm1316l_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
 768 {
 769         struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
 770         u8 tuner_buf[4];
 771         struct i2c_msg tuner_msg = {.addr = budget_ci->tuner_pll_address,.flags = 0,.buf = tuner_buf,.len = sizeof(tuner_buf) };
 772         int tuner_frequency = 0;
 773         u8 band, cp, filter;
 774
 775         // determine charge pump
 776         tuner_frequency = params->frequency + 36130000;
 777         if (tuner_frequency < 87000000)
 778                 return -EINVAL;
 779         else if (tuner_frequency < 130000000)
 780                 cp = 3;
 781         else if (tuner_frequency < 160000000)
 782                 cp = 5;
 783         else if (tuner_frequency < 200000000)
 784                 cp = 6;
 785         else if (tuner_frequency < 290000000)
 786                 cp = 3;
 787         else if (tuner_frequency < 420000000)
 788                 cp = 5;
 789         else if (tuner_frequency < 480000000)
 790                 cp = 6;
 791         else if (tuner_frequency < 620000000)
 792                 cp = 3;
 793         else if (tuner_frequency < 830000000)
 794                 cp = 5;
 795         else if (tuner_frequency < 895000000)
 796                 cp = 7;
 797         else
 798                 return -EINVAL;
 799
 800         // determine band
 801         if (params->frequency < 49000000)
 802                 return -EINVAL;
 803         else if (params->frequency < 159000000)
 804                 band = 1;
 805         else if (params->frequency < 444000000)
 806                 band = 2;
 807         else if (params->frequency < 861000000)
 808                 band = 4;
 809         else
 810                 return -EINVAL;
 811
 812         // setup PLL filter and TDA9889
 813         switch (params->u.ofdm.bandwidth) {
 814         case BANDWIDTH_6_MHZ:
 815                 tda1004x_writereg(fe, 0x0C, 0x14);
 816                 filter = 0;
 817                 break;
 818
 819         case BANDWIDTH_7_MHZ:
 820                 tda1004x_writereg(fe, 0x0C, 0x80);
 821                 filter = 0;
 822                 break;
 823
 824         case BANDWIDTH_8_MHZ:
 825                 tda1004x_writereg(fe, 0x0C, 0x14);
 826                 filter = 1;
 827                 break;
 828
 829         default:
 830                 return -EINVAL;
 831         }
 832
 833         // calculate divisor
 834         // ((36130000+((1000000/6)/2)) + Finput)/(1000000/6)
 835         tuner_frequency = (((params->frequency / 1000) * 6) + 217280) / 1000;
 836
 837         // setup tuner buffer
 838         tuner_buf[0] = tuner_frequency >> 8;
 839         tuner_buf[1] = tuner_frequency & 0xff;
 840         tuner_buf[2] = 0xca;
 841         tuner_buf[3] = (cp << 5) | (filter << 3) | band;
 842
 843         if (fe->ops.i2c_gate_ctrl)
 844                 fe->ops.i2c_gate_ctrl(fe, 1);
 845         if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1)
 846                 return -EIO;
 847
 848         msleep(1);
 849         return 0;
 850 }
 851
 852 static int philips_tdm1316l_request_firmware(struct dvb_frontend *fe,
 853                                              const struct firmware **fw, char *name)
 854 {
 855         struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
 856
 857         return request_firmware(fw, name, &budget_ci->budget.dev->pci->dev);
 858 }
 859
 860 static struct tda1004x_config philips_tdm1316l_config = {
 861
 862         .demod_address = 0x8,
 863         .invert = 0,
 864         .invert_oclk = 0,
 865         .xtal_freq = TDA10046_XTAL_4M,
 866         .agc_config = TDA10046_AGC_DEFAULT,
 867         .if_freq = TDA10046_FREQ_3617,
 868         .request_firmware = philips_tdm1316l_request_firmware,
 869 };
 870
 871 static struct tda1004x_config philips_tdm1316l_config_invert = {
 872
 873         .demod_address = 0x8,
 874         .invert = 1,
 875         .invert_oclk = 0,
 876         .xtal_freq = TDA10046_XTAL_4M,
 877         .agc_config = TDA10046_AGC_DEFAULT,
 878         .if_freq = TDA10046_FREQ_3617,
 879         .request_firmware = philips_tdm1316l_request_firmware,
 880 };
 881
 882 static int dvbc_philips_tdm1316l_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
 883 {
 884         struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
 885         u8 tuner_buf[5];
 886         struct i2c_msg tuner_msg = {.addr = budget_ci->tuner_pll_address,
 887                                     .flags = 0,
 888                                     .buf = tuner_buf,
 889                                     .len = sizeof(tuner_buf) };
 890         int tuner_frequency = 0;
 891         u8 band, cp, filter;
 892
 893         // determine charge pump
 894         tuner_frequency = params->frequency + 36125000;
 895         if (tuner_frequency < 87000000)
 896                 return -EINVAL;
 897         else if (tuner_frequency < 130000000) {
 898                 cp = 3;
 899                 band = 1;
 900         } else if (tuner_frequency < 160000000) {
 901                 cp = 5;
 902                 band = 1;
 903         } else if (tuner_frequency < 200000000) {
 904                 cp = 6;
 905                 band = 1;
 906         } else if (tuner_frequency < 290000000) {
 907                 cp = 3;
 908                 band = 2;
 909         } else if (tuner_frequency < 420000000) {
 910                 cp = 5;
 911                 band = 2;
 912         } else if (tuner_frequency < 480000000) {
 913                 cp = 6;
 914                 band = 2;
 915         } else if (tuner_frequency < 620000000) {
 916                 cp = 3;
 917                 band = 4;
 918         } else if (tuner_frequency < 830000000) {
 919                 cp = 5;
 920                 band = 4;
 921         } else if (tuner_frequency < 895000000) {
 922                 cp = 7;
 923                 band = 4;
 924         } else
 925                 return -EINVAL;
 926
 927         // assume PLL filter should always be 8MHz for the moment.
 928         filter = 1;
 929
 930         // calculate divisor
 931         tuner_frequency = (params->frequency + 36125000 + (62500/2)) / 62500;
 932
 933         // setup tuner buffer
 934         tuner_buf[0] = tuner_frequency >> 8;
 935         tuner_buf[1] = tuner_frequency & 0xff;
 936         tuner_buf[2] = 0xc8;
 937         tuner_buf[3] = (cp << 5) | (filter << 3) | band;
 938         tuner_buf[4] = 0x80;
 939
 940         if (fe->ops.i2c_gate_ctrl)
 941                 fe->ops.i2c_gate_ctrl(fe, 1);
 942         if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1)
 943                 return -EIO;
 944
 945         msleep(50);
 946
 947         if (fe->ops.i2c_gate_ctrl)
 948                 fe->ops.i2c_gate_ctrl(fe, 1);
 949         if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1)
 950                 return -EIO;
 951
 952         msleep(1);
 953
 954         return 0;
 955 }
 956
 957 static u8 dvbc_philips_tdm1316l_inittab[] = {
 958         0x80, 0x01,
 959         0x80, 0x00,
 960         0x81, 0x01,
 961         0x81, 0x00,
 962         0x00, 0x09,
 963         0x01, 0x69,
 964         0x03, 0x00,
 965         0x04, 0x00,
 966         0x07, 0x00,
 967         0x08, 0x00,
 968         0x20, 0x00,
 969         0x21, 0x40,
 970         0x22, 0x00,
 971         0x23, 0x00,
 972         0x24, 0x40,
 973         0x25, 0x88,
 974         0x30, 0xff,
 975         0x31, 0x00,
 976         0x32, 0xff,
 977         0x33, 0x00,
 978         0x34, 0x50,
 979         0x35, 0x7f,
 980         0x36, 0x00,
 981         0x37, 0x20,
 982         0x38, 0x00,
 983         0x40, 0x1c,
 984         0x41, 0xff,
 985         0x42, 0x29,
 986         0x43, 0x20,
 987         0x44, 0xff,
 988         0x45, 0x00,
 989         0x46, 0x00,
 990         0x49, 0x04,
 991         0x4a, 0x00,
 992         0x4b, 0x7b,
 993         0x52, 0x30,
 994         0x55, 0xae,
 995         0x56, 0x47,
 996         0x57, 0xe1,
 997         0x58, 0x3a,
 998         0x5a, 0x1e,
 999         0x5b, 0x34,
1000         0x60, 0x00,
1001         0x63, 0x00,
1002         0x64, 0x00,
1003         0x65, 0x00,
1004         0x66, 0x00,
1005         0x67, 0x00,
1006         0x68, 0x00,
1007         0x69, 0x00,
1008         0x6a, 0x02,
1009         0x6b, 0x00,
1010         0x70, 0xff,
1011         0x71, 0x00,
1012         0x72, 0x00,
1013         0x73, 0x00,
1014         0x74, 0x0c,
1015         0x80, 0x00,
1016         0x81, 0x00,
1017         0x82, 0x00,
1018         0x83, 0x00,
1019         0x84, 0x04,
1020         0x85, 0x80,
1021         0x86, 0x24,
1022         0x87, 0x78,
1023         0x88, 0x10,
1024         0x89, 0x00,
1025         0x90, 0x01,
1026         0x91, 0x01,
1027         0xa0, 0x04,
1028         0xa1, 0x00,
1029         0xa2, 0x00,
1030         0xb0, 0x91,
1031         0xb1, 0x0b,
1032         0xc0, 0x53,
1033         0xc1, 0x70,
1034         0xc2, 0x12,
1035         0xd0, 0x00,
1036         0xd1, 0x00,
1037         0xd2, 0x00,
1038         0xd3, 0x00,
1039         0xd4, 0x00,
1040         0xd5, 0x00,
1041         0xde, 0x00,
1042         0xdf, 0x00,
1043         0x61, 0x38,
1044         0x62, 0x0a,
1045         0x53, 0x13,
1046         0x59, 0x08,
1047         0xff, 0xff,
1048 };
1049
1050 static struct stv0297_config dvbc_philips_tdm1316l_config = {
1051         .demod_address = 0x1c,
1052         .inittab = dvbc_philips_tdm1316l_inittab,
1053         .invert = 0,
1054         .stop_during_read = 1,
1055 };
1056
1057 static struct tda10023_config tda10023_config = {
1058         .demod_address = 0xc,
1059         .invert = 0,
1060         .xtal = 16000000,
1061         .pll_m = 11,
1062         .pll_p = 3,
1063         .pll_n = 1,
1064         .deltaf = 0xa511,
1065 };
1066
1067 static struct tda827x_config tda827x_config = {
1068         .config = 0,
1069 };
1070
1071 /* TT S2-3200 DVB-S (STB0899) Inittab */
1072 static const struct stb0899_s1_reg tt3200_stb0899_s1_init_1[] = {
1073
1074         { STB0899_DEV_ID                , 0x81 },
1075         { STB0899_DISCNTRL1             , 0x32 },
1076         { STB0899_DISCNTRL2             , 0x80 },
1077         { STB0899_DISRX_ST0             , 0x04 },
1078         { STB0899_DISRX_ST1             , 0x00 },
1079         { STB0899_DISPARITY             , 0x00 },
1080         { STB0899_DISFIFO               , 0x00 },
1081         { STB0899_DISSTATUS             , 0x20 },
1082         { STB0899_DISF22                , 0x8c },
1083         { STB0899_DISF22RX              , 0x9a },
1084         { STB0899_SYSREG                , 0x0b },
1085         { STB0899_ACRPRESC              , 0x11 },
1086         { STB0899_ACRDIV1               , 0x0a },
1087         { STB0899_ACRDIV2               , 0x05 },
1088         { STB0899_DACR1                 , 0x00 },
1089         { STB0899_DACR2                 , 0x00 },
1090         { STB0899_OUTCFG                , 0x00 },
1091         { STB0899_MODECFG               , 0x00 },
1092         { STB0899_IRQSTATUS_3           , 0x30 },
1093         { STB0899_IRQSTATUS_2           , 0x00 },
1094         { STB0899_IRQSTATUS_1           , 0x00 },
1095         { STB0899_IRQSTATUS_0           , 0x00 },
1096         { STB0899_IRQMSK_3              , 0xf3 },
1097         { STB0899_IRQMSK_2              , 0xfc },
1098         { STB0899_IRQMSK_1              , 0xff },
1099         { STB0899_IRQMSK_0              , 0xff },
1100         { STB0899_IRQCFG                , 0x00 },
1101         { STB0899_I2CCFG                , 0x88 },
1102         { STB0899_I2CRPT                , 0x48 }, /* 12k Pullup, Repeater=16, Stop=disabled */
1103         { STB0899_IOPVALUE5             , 0x00 },
1104         { STB0899_IOPVALUE4             , 0x20 },
1105         { STB0899_IOPVALUE3             , 0xc9 },
1106         { STB0899_IOPVALUE2             , 0x90 },
1107         { STB0899_IOPVALUE1             , 0x40 },
1108         { STB0899_IOPVALUE0             , 0x00 },
1109         { STB0899_GPIO00CFG             , 0x82 },
1110         { STB0899_GPIO01CFG             , 0x82 },
1111         { STB0899_GPIO02CFG             , 0x82 },
1112         { STB0899_GPIO03CFG             , 0x82 },
1113         { STB0899_GPIO04CFG             , 0x82 },
1114         { STB0899_GPIO05CFG             , 0x82 },
1115         { STB0899_GPIO06CFG             , 0x82 },
1116         { STB0899_GPIO07CFG             , 0x82 },
1117         { STB0899_GPIO08CFG             , 0x82 },
1118         { STB0899_GPIO09CFG             , 0x82 },
1119         { STB0899_GPIO10CFG             , 0x82 },
1120         { STB0899_GPIO11CFG             , 0x82 },
1121         { STB0899_GPIO12CFG             , 0x82 },
1122         { STB0899_GPIO13CFG             , 0x82 },
1123         { STB0899_GPIO14CFG             , 0x82 },
1124         { STB0899_GPIO15CFG             , 0x82 },
1125         { STB0899_GPIO16CFG             , 0x82 },
1126         { STB0899_GPIO17CFG             , 0x82 },
1127         { STB0899_GPIO18CFG             , 0x82 },
1128         { STB0899_GPIO19CFG             , 0x82 },
1129         { STB0899_GPIO20CFG             , 0x82 },
1130         { STB0899_SDATCFG               , 0xb8 },
1131         { STB0899_SCLTCFG               , 0xba },
1132         { STB0899_AGCRFCFG              , 0x1c }, /* 0x11 */
1133         { STB0899_GPIO22                , 0x82 }, /* AGCBB2CFG */
1134         { STB0899_GPIO21                , 0x91 }, /* AGCBB1CFG */
1135         { STB0899_DIRCLKCFG             , 0x82 },
1136         { STB0899_CLKOUT27CFG           , 0x7e },
1137         { STB0899_STDBYCFG              , 0x82 },
1138         { STB0899_CS0CFG                , 0x82 },
1139         { STB0899_CS1CFG                , 0x82 },
1140         { STB0899_DISEQCOCFG            , 0x20 },
1141         { STB0899_GPIO32CFG             , 0x82 },
1142         { STB0899_GPIO33CFG             , 0x82 },
1143         { STB0899_GPIO34CFG             , 0x82 },
1144         { STB0899_GPIO35CFG             , 0x82 },
1145         { STB0899_GPIO36CFG             , 0x82 },
1146         { STB0899_GPIO37CFG             , 0x82 },
1147         { STB0899_GPIO38CFG             , 0x82 },
1148         { STB0899_GPIO39CFG             , 0x82 },
1149         { STB0899_NCOARSE               , 0x15 }, /* 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz */
1150         { STB0899_SYNTCTRL              , 0x02 }, /* 0x00 = CLK from CLKI, 0x02 = CLK from XTALI */
1151         { STB0899_FILTCTRL              , 0x00 },
1152         { STB0899_SYSCTRL               , 0x00 },
1153         { STB0899_STOPCLK1              , 0x20 },
1154         { STB0899_STOPCLK2              , 0x00 },
1155         { STB0899_INTBUFSTATUS          , 0x00 },
1156         { STB0899_INTBUFCTRL            , 0x0a },
1157         { 0xffff                        , 0xff },
1158 };
1159
1160 static const struct stb0899_s1_reg tt3200_stb0899_s1_init_3[] = {
1161         { STB0899_DEMOD                 , 0x00 },
1162         { STB0899_RCOMPC                , 0xc9 },
1163         { STB0899_AGC1CN                , 0x41 },
1164         { STB0899_AGC1REF               , 0x10 },
1165         { STB0899_RTC                   , 0x7a },
1166         { STB0899_TMGCFG                , 0x4e },
1167         { STB0899_AGC2REF               , 0x34 },
1168         { STB0899_TLSR                  , 0x84 },
1169         { STB0899_CFD                   , 0xc7 },
1170         { STB0899_ACLC                  , 0x87 },
1171         { STB0899_BCLC                  , 0x94 },
1172         { STB0899_EQON                  , 0x41 },
1173         { STB0899_LDT                   , 0xdd },
1174         { STB0899_LDT2                  , 0xc9 },
1175         { STB0899_EQUALREF              , 0xb4 },
1176         { STB0899_TMGRAMP               , 0x10 },
1177         { STB0899_TMGTHD                , 0x30 },
1178         { STB0899_IDCCOMP               , 0xfb },
1179         { STB0899_QDCCOMP               , 0x03 },
1180         { STB0899_POWERI                , 0x3b },
1181         { STB0899_POWERQ                , 0x3d },
1182         { STB0899_RCOMP                 , 0x81 },
1183         { STB0899_AGCIQIN               , 0x80 },
1184         { STB0899_AGC2I1                , 0x04 },
1185         { STB0899_AGC2I2                , 0xf5 },
1186         { STB0899_TLIR                  , 0x25 },
1187         { STB0899_RTF                   , 0x80 },
1188         { STB0899_DSTATUS               , 0x00 },
1189         { STB0899_LDI                   , 0xca },
1190         { STB0899_CFRM                  , 0xf1 },
1191         { STB0899_CFRL                  , 0xf3 },
1192         { STB0899_NIRM                  , 0x2a },
1193         { STB0899_NIRL                  , 0x05 },
1194         { STB0899_ISYMB                 , 0x17 },
1195         { STB0899_QSYMB                 , 0xfa },
1196         { STB0899_SFRH                  , 0x2f },
1197         { STB0899_SFRM                  , 0x68 },
1198         { STB0899_SFRL                  , 0x40 },
1199         { STB0899_SFRUPH                , 0x2f },
1200         { STB0899_SFRUPM                , 0x68 },
1201         { STB0899_SFRUPL                , 0x40 },
1202         { STB0899_EQUAI1                , 0xfd },
1203         { STB0899_EQUAQ1                , 0x04 },
1204         { STB0899_EQUAI2                , 0x0f },
1205         { STB0899_EQUAQ2                , 0xff },
1206         { STB0899_EQUAI3                , 0xdf },
1207         { STB0899_EQUAQ3                , 0xfa },
1208         { STB0899_EQUAI4                , 0x37 },
1209         { STB0899_EQUAQ4                , 0x0d },
1210         { STB0899_EQUAI5                , 0xbd },
1211         { STB0899_EQUAQ5                , 0xf7 },
1212         { STB0899_DSTATUS2              , 0x00 },
1213         { STB0899_VSTATUS               , 0x00 },
1214         { STB0899_VERROR                , 0xff },
1215         { STB0899_IQSWAP                , 0x2a },
1216         { STB0899_ECNT1M                , 0x00 },
1217         { STB0899_ECNT1L                , 0x00 },
1218         { STB0899_ECNT2M                , 0x00 },
1219         { STB0899_ECNT2L                , 0x00 },
1220         { STB0899_ECNT3M                , 0x00 },
1221         { STB0899_ECNT3L                , 0x00 },
1222         { STB0899_FECAUTO1              , 0x06 },
1223         { STB0899_FECM                  , 0x01 },
1224         { STB0899_VTH12                 , 0xf0 },
1225         { STB0899_VTH23                 , 0xa0 },
1226         { STB0899_VTH34                 , 0x78 },
1227         { STB0899_VTH56                 , 0x4e },
1228         { STB0899_VTH67                 , 0x48 },
1229         { STB0899_VTH78                 , 0x38 },
1230         { STB0899_PRVIT                 , 0xff },
1231         { STB0899_VITSYNC               , 0x19 },
1232         { STB0899_RSULC                 , 0xb1 }, /* DVB = 0xb1, DSS = 0xa1 */
1233         { STB0899_TSULC                 , 0x42 },
1234         { STB0899_RSLLC                 , 0x40 },
1235         { STB0899_TSLPL                 , 0x12 },
1236         { STB0899_TSCFGH                , 0x0c },
1237         { STB0899_TSCFGM                , 0x00 },
1238         { STB0899_TSCFGL                , 0x0c },
1239         { STB0899_TSOUT                 , 0x4d }, /* 0x0d for CAM */
1240         { STB0899_RSSYNCDEL             , 0x00 },
1241         { STB0899_TSINHDELH             , 0x02 },
1242         { STB0899_TSINHDELM             , 0x00 },
1243         { STB0899_TSINHDELL             , 0x00 },
1244         { STB0899_TSLLSTKM              , 0x00 },
1245         { STB0899_TSLLSTKL              , 0x00 },
1246         { STB0899_TSULSTKM              , 0x00 },
1247         { STB0899_TSULSTKL              , 0xab },
1248         { STB0899_PCKLENUL              , 0x00 },
1249         { STB0899_PCKLENLL              , 0xcc },
1250         { STB0899_RSPCKLEN              , 0xcc },
1251         { STB0899_TSSTATUS              , 0x80 },
1252         { STB0899_ERRCTRL1              , 0xb6 },
1253         { STB0899_ERRCTRL2              , 0x96 },
1254         { STB0899_ERRCTRL3              , 0x89 },
1255         { STB0899_DMONMSK1              , 0x27 },
1256         { STB0899_DMONMSK0              , 0x03 },
1257         { STB0899_DEMAPVIT              , 0x5c },
1258         { STB0899_PLPARM                , 0x1f },
1259         { STB0899_PDELCTRL              , 0x48 },
1260         { STB0899_PDELCTRL2             , 0x00 },
1261         { STB0899_BBHCTRL1              , 0x00 },
1262         { STB0899_BBHCTRL2              , 0x00 },
1263         { STB0899_HYSTTHRESH            , 0x77 },
1264         { STB0899_MATCSTM               , 0x00 },
1265         { STB0899_MATCSTL               , 0x00 },
1266         { STB0899_UPLCSTM               , 0x00 },
1267         { STB0899_UPLCSTL               , 0x00 },
1268         { STB0899_DFLCSTM               , 0x00 },
1269         { STB0899_DFLCSTL               , 0x00 },
1270         { STB0899_SYNCCST               , 0x00 },
1271         { STB0899_SYNCDCSTM             , 0x00 },
1272         { STB0899_SYNCDCSTL             , 0x00 },
1273         { STB0899_ISI_ENTRY             , 0x00 },
1274         { STB0899_ISI_BIT_EN            , 0x00 },
1275         { STB0899_MATSTRM               , 0x00 },
1276         { STB0899_MATSTRL               , 0x00 },
1277         { STB0899_UPLSTRM               , 0x00 },
1278         { STB0899_UPLSTRL               , 0x00 },
1279         { STB0899_DFLSTRM               , 0x00 },
1280         { STB0899_DFLSTRL               , 0x00 },
1281         { STB0899_SYNCSTR               , 0x00 },
1282         { STB0899_SYNCDSTRM             , 0x00 },
1283         { STB0899_SYNCDSTRL             , 0x00 },
1284         { STB0899_CFGPDELSTATUS1        , 0x10 },
1285         { STB0899_CFGPDELSTATUS2        , 0x00 },
1286         { STB0899_BBFERRORM             , 0x00 },
1287         { STB0899_BBFERRORL             , 0x00 },
1288         { STB0899_UPKTERRORM            , 0x00 },
1289         { STB0899_UPKTERRORL            , 0x00 },
1290         { 0xffff                        , 0xff },
1291 };
1292
1293 static struct stb0899_config tt3200_config = {
1294         .init_dev               = tt3200_stb0899_s1_init_1,
1295         .init_s2_demod          = stb0899_s2_init_2,
1296         .init_s1_demod          = tt3200_stb0899_s1_init_3,
1297         .init_s2_fec            = stb0899_s2_init_4,
1298         .init_tst               = stb0899_s1_init_5,
1299
1300         .postproc               = NULL,
1301
1302         .demod_address          = 0x68,
1303
1304         .xtal_freq              = 27000000,
1305         .inversion              = IQ_SWAP_ON, /* 1 */
1306
1307         .lo_clk                 = 76500000,
1308         .hi_clk                 = 99000000,
1309
1310         .esno_ave               = STB0899_DVBS2_ESNO_AVE,
1311         .esno_quant             = STB0899_DVBS2_ESNO_QUANT,
1312         .avframes_coarse        = STB0899_DVBS2_AVFRAMES_COARSE,
1313         .avframes_fine          = STB0899_DVBS2_AVFRAMES_FINE,
1314         .miss_threshold         = STB0899_DVBS2_MISS_THRESHOLD,
1315         .uwp_threshold_acq      = STB0899_DVBS2_UWP_THRESHOLD_ACQ,
1316         .uwp_threshold_track    = STB0899_DVBS2_UWP_THRESHOLD_TRACK,
1317         .uwp_threshold_sof      = STB0899_DVBS2_UWP_THRESHOLD_SOF,
1318         .sof_search_timeout     = STB0899_DVBS2_SOF_SEARCH_TIMEOUT,
1319
1320         .btr_nco_bits           = STB0899_DVBS2_BTR_NCO_BITS,
1321         .btr_gain_shift_offset  = STB0899_DVBS2_BTR_GAIN_SHIFT_OFFSET,
1322         .crl_nco_bits           = STB0899_DVBS2_CRL_NCO_BITS,
1323         .ldpc_max_iter          = STB0899_DVBS2_LDPC_MAX_ITER,
1324
1325         .tuner_get_frequency    = stb6100_get_frequency,
1326         .tuner_set_frequency    = stb6100_set_frequency,
1327         .tuner_set_bandwidth    = stb6100_set_bandwidth,
1328         .tuner_get_bandwidth    = stb6100_get_bandwidth,
1329         .tuner_set_rfsiggain    = NULL
1330 };
1331
1332 static struct stb6100_config tt3200_stb6100_config = {
1333         .tuner_address  = 0x60,
1334         .refclock       = 27000000,
1335 };
1336
1337 static void frontend_init(struct budget_ci *budget_ci)
1338 {
1339         switch (budget_ci->budget.dev->pci->subsystem_device) {
1340         case 0x100c:            // Hauppauge/TT Nova-CI budget (stv0299/ALPS BSRU6(tsa5059))
1341                 budget_ci->budget.dvb_frontend =
1342                         dvb_attach(stv0299_attach, &alps_bsru6_config, &budget_ci->budget.i2c_adap);
1343                 if (budget_ci->budget.dvb_frontend) {
1344                         budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = alps_bsru6_tuner_set_params;
1345                         budget_ci->budget.dvb_frontend->tuner_priv = &budget_ci->budget.i2c_adap;
1346                         break;
1347                 }
1348                 break;
1349
1350         case 0x100f:            // Hauppauge/TT Nova-CI budget (stv0299b/Philips su1278(tsa5059))
1351                 budget_ci->budget.dvb_frontend =
1352                         dvb_attach(stv0299_attach, &philips_su1278_tt_config, &budget_ci->budget.i2c_adap);
1353                 if (budget_ci->budget.dvb_frontend) {
1354                         budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = philips_su1278_tt_tuner_set_params;
1355                         break;
1356                 }
1357                 break;
1358
1359         case 0x1010:            // TT DVB-C CI budget (stv0297/Philips tdm1316l(tda6651tt))
1360                 budget_ci->tuner_pll_address = 0x61;
1361                 budget_ci->budget.dvb_frontend =
1362                         dvb_attach(stv0297_attach, &dvbc_philips_tdm1316l_config, &budget_ci->budget.i2c_adap);
1363                 if (budget_ci->budget.dvb_frontend) {
1364                         budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = dvbc_philips_tdm1316l_tuner_set_params;
1365                         break;
1366                 }
1367                 break;
1368
1369         case 0x1011:            // Hauppauge/TT Nova-T budget (tda10045/Philips tdm1316l(tda6651tt) + TDA9889)
1370                 budget_ci->tuner_pll_address = 0x63;
1371                 budget_ci->budget.dvb_frontend =
1372                         dvb_attach(tda10045_attach, &philips_tdm1316l_config, &budget_ci->budget.i2c_adap);
1373                 if (budget_ci->budget.dvb_frontend) {
1374                         budget_ci->budget.dvb_frontend->ops.tuner_ops.init = philips_tdm1316l_tuner_init;
1375                         budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = philips_tdm1316l_tuner_set_params;
1376                         break;
1377                 }
1378                 break;
1379
1380         case 0x1012:            // TT DVB-T CI budget (tda10046/Philips tdm1316l(tda6651tt))
1381                 budget_ci->tuner_pll_address = 0x60;
1382                 budget_ci->budget.dvb_frontend =
1383                         dvb_attach(tda10046_attach, &philips_tdm1316l_config_invert, &budget_ci->budget.i2c_adap);
1384                 if (budget_ci->budget.dvb_frontend) {
1385                         budget_ci->budget.dvb_frontend->ops.tuner_ops.init = philips_tdm1316l_tuner_init;
1386                         budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = philips_tdm1316l_tuner_set_params;
1387                         break;
1388                 }
1389                 break;
1390
1391         case 0x1017:            // TT S-1500 PCI
1392                 budget_ci->budget.dvb_frontend = dvb_attach(stv0299_attach, &alps_bsbe1_config, &budget_ci->budget.i2c_adap);
1393                 if (budget_ci->budget.dvb_frontend) {
1394                         budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = alps_bsbe1_tuner_set_params;
1395                         budget_ci->budget.dvb_frontend->tuner_priv = &budget_ci->budget.i2c_adap;
1396
1397                         budget_ci->budget.dvb_frontend->ops.dishnetwork_send_legacy_command = NULL;
1398                         if (dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, LNBP21_LLC, 0) == NULL) {
1399                                 printk("%s: No LNBP21 found!\n", __func__);
1400                                 dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1401                                 budget_ci->budget.dvb_frontend = NULL;
1402                         }
1403                 }
1404                 break;
1405
1406         case 0x101a: /* TT Budget-C-1501 (philips tda10023/philips tda8274A) */
1407                 budget_ci->budget.dvb_frontend = dvb_attach(tda10023_attach, &tda10023_config, &budget_ci->budget.i2c_adap, 0x48);
1408                 if (budget_ci->budget.dvb_frontend) {
1409                         if (dvb_attach(tda827x_attach, budget_ci->budget.dvb_frontend, 0x61, &budget_ci->budget.i2c_adap, &tda827x_config) == NULL) {
1410                                 printk(KERN_ERR "%s: No tda827x found!\n", __func__);
1411                                 dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1412                                 budget_ci->budget.dvb_frontend = NULL;
1413                         }
1414                 }
1415                 break;
1416
1417         case 0x1019:            // TT S2-3200 PCI
1418                 /*
1419                  * NOTE! on some STB0899 versions, the internal PLL takes a longer time
1420                  * to settle, aka LOCK. On the older revisions of the chip, we don't see
1421                  * this, as a result on the newer chips the entire clock tree, will not
1422                  * be stable after a freshly POWER 'ed up situation.
1423                  * In this case, we should RESET the STB0899 (Active LOW) and wait for
1424                  * PLL stabilization.
1425                  *
1426                  * On the TT S2 3200 and clones, the STB0899 demodulator's RESETB is
1427                  * connected to the SAA7146 GPIO, GPIO2, Pin 142
1428                  */
1429                 /* Reset Demodulator */
1430                 saa7146_setgpio(budget_ci->budget.dev, 2, SAA7146_GPIO_OUTLO);
1431                 /* Wait for everything to die */
1432                 msleep(50);
1433                 /* Pull it up out of Reset state */
1434                 saa7146_setgpio(budget_ci->budget.dev, 2, SAA7146_GPIO_OUTHI);
1435                 /* Wait for PLL to stabilize */
1436                 msleep(250);
1437                 /*
1438                  * PLL state should be stable now. Ideally, we should check
1439                  * for PLL LOCK status. But well, never mind!
1440                  */
1441                 budget_ci->budget.dvb_frontend = dvb_attach(stb0899_attach, &tt3200_config, &budget_ci->budget.i2c_adap);
1442                 if (budget_ci->budget.dvb_frontend) {
1443                         if (dvb_attach(stb6100_attach, budget_ci->budget.dvb_frontend, &tt3200_stb6100_config, &budget_ci->budget.i2c_adap)) {
1444                                 if (!dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, 0, 0)) {
1445                                         printk("%s: No LNBP21 found!\n", __func__);
1446                                         dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1447                                         budget_ci->budget.dvb_frontend = NULL;
1448                                 }
1449                         } else {
1450                                         dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1451                                         budget_ci->budget.dvb_frontend = NULL;
1452                         }
1453                 }
1454                 break;
1455
1456         }
1457
1458         if (budget_ci->budget.dvb_frontend == NULL) {
1459                 printk("budget-ci: A frontend driver was not found for device [%04x:%04x] subsystem [%04x:%04x]\n",
1460                        budget_ci->budget.dev->pci->vendor,
1461                        budget_ci->budget.dev->pci->device,
1462                        budget_ci->budget.dev->pci->subsystem_vendor,
1463                        budget_ci->budget.dev->pci->subsystem_device);
1464         } else {
1465                 if (dvb_register_frontend
1466                     (&budget_ci->budget.dvb_adapter, budget_ci->budget.dvb_frontend)) {
1467                         printk("budget-ci: Frontend registration failed!\n");
1468                         dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1469                         budget_ci->budget.dvb_frontend = NULL;
1470                 }
1471         }
1472 }
1473
1474 static int budget_ci_attach(struct saa7146_dev *dev, struct saa7146_pci_extension_data *info)
1475 {
1476         struct budget_ci *budget_ci;
1477         int err;
1478
1479         budget_ci = kzalloc(sizeof(struct budget_ci), GFP_KERNEL);
1480         if (!budget_ci) {
1481                 err = -ENOMEM;
1482                 goto out1;
1483         }
1484
1485         dprintk(2, "budget_ci: %p\n", budget_ci);
1486
1487         dev->ext_priv = budget_ci;
1488
1489         err = ttpci_budget_init(&budget_ci->budget, dev, info, THIS_MODULE,
1490                                 adapter_nr);
1491         if (err)
1492                 goto out2;
1493
1494         err = msp430_ir_init(budget_ci);
1495         if (err)
1496                 goto out3;
1497
1498         ciintf_init(budget_ci);
1499
1500         budget_ci->budget.dvb_adapter.priv = budget_ci;
1501         frontend_init(budget_ci);
1502
1503         ttpci_budget_init_hooks(&budget_ci->budget);
1504
1505         return 0;
1506
1507 out3:
1508         ttpci_budget_deinit(&budget_ci->budget);
1509 out2:
1510         kfree(budget_ci);
1511 out1:
1512         return err;
1513 }
1514
1515 static int budget_ci_detach(struct saa7146_dev *dev)
1516 {
1517         struct budget_ci *budget_ci = (struct budget_ci *) dev->ext_priv;
1518         struct saa7146_dev *saa = budget_ci->budget.dev;
1519         int err;
1520
1521         if (budget_ci->budget.ci_present)
1522                 ciintf_deinit(budget_ci);
1523         msp430_ir_deinit(budget_ci);
1524         if (budget_ci->budget.dvb_frontend) {
1525                 dvb_unregister_frontend(budget_ci->budget.dvb_frontend);
1526                 dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1527         }
1528         err = ttpci_budget_deinit(&budget_ci->budget);
1529
1530         // disable frontend and CI interface
1531         saa7146_setgpio(saa, 2, SAA7146_GPIO_INPUT);
1532
1533         kfree(budget_ci);
1534
1535         return err;
1536 }
1537
1538 static struct saa7146_extension budget_extension;
1539
1540 MAKE_BUDGET_INFO(ttbs2, "TT-Budget/S-1500 PCI", BUDGET_TT);
1541 MAKE_BUDGET_INFO(ttbci, "TT-Budget/WinTV-NOVA-CI PCI", BUDGET_TT_HW_DISEQC);
1542 MAKE_BUDGET_INFO(ttbt2, "TT-Budget/WinTV-NOVA-T  PCI", BUDGET_TT);
1543 MAKE_BUDGET_INFO(ttbtci, "TT-Budget-T-CI PCI", BUDGET_TT);
1544 MAKE_BUDGET_INFO(ttbcci, "TT-Budget-C-CI PCI", BUDGET_TT);
1545 MAKE_BUDGET_INFO(ttc1501, "TT-Budget C-1501 PCI", BUDGET_TT);
1546 MAKE_BUDGET_INFO(tt3200, "TT-Budget S2-3200 PCI", BUDGET_TT);
1547
1548 static struct pci_device_id pci_tbl[] = {
1549         MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100c),
1550         MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100f),
1551         MAKE_EXTENSION_PCI(ttbcci, 0x13c2, 0x1010),
1552         MAKE_EXTENSION_PCI(ttbt2, 0x13c2, 0x1011),
1553         MAKE_EXTENSION_PCI(ttbtci, 0x13c2, 0x1012),
1554         MAKE_EXTENSION_PCI(ttbs2, 0x13c2, 0x1017),
1555         MAKE_EXTENSION_PCI(ttc1501, 0x13c2, 0x101a),
1556         MAKE_EXTENSION_PCI(tt3200, 0x13c2, 0x1019),
1557         {
1558          .vendor = 0,
1559          }
1560 };
1561
1562 MODULE_DEVICE_TABLE(pci, pci_tbl);
1563
1564 static struct saa7146_extension budget_extension = {
1565         .name = "budget_ci dvb",
1566         .flags = SAA7146_USE_I2C_IRQ,
1567
1568         .module = THIS_MODULE,
1569         .pci_tbl = &pci_tbl[0],
1570         .attach = budget_ci_attach,
1571         .detach = budget_ci_detach,
1572
1573         .irq_mask = MASK_03 | MASK_06 | MASK_10,
1574         .irq_func = budget_ci_irq,
1575 };
1576
1577 static int __init budget_ci_init(void)
1578 {
1579         return saa7146_register_extension(&budget_extension);
1580 }
1581
1582 static void __exit budget_ci_exit(void)
1583 {
1584         saa7146_unregister_extension(&budget_extension);
1585 }
1586
1587 module_init(budget_ci_init);
1588 module_exit(budget_ci_exit);
1589
1590 MODULE_LICENSE("GPL");
1591 MODULE_AUTHOR("Michael Hunold, Jack Thomasson, Andrew de Quincey, others");
1592 MODULE_DESCRIPTION("driver for the SAA7146 based so-called "
1593                    "budget PCI DVB cards w/ CI-module produced by "
1594                    "Siemens, Technotrend, Hauppauge");