Pileus Git - ~andy/linux/blob - drivers/media/dvb/frontends/dib7000p.c

   1 /*
   2  * Linux-DVB Driver for DiBcom's second generation DiB7000P (PC).
   3  *
   4  * Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License as
   8  *      published by the Free Software Foundation, version 2.
   9  */
  10 #include <linux/kernel.h>
  11 #include <linux/slab.h>
  12 #include <linux/i2c.h>
  13 #include <linux/mutex.h>
  14
  15 #include "dvb_math.h"
  16 #include "dvb_frontend.h"
  17
  18 #include "dib7000p.h"
  19
  20 static int debug;
  21 module_param(debug, int, 0644);
  22 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
  23
  24 static int buggy_sfn_workaround;
  25 module_param(buggy_sfn_workaround, int, 0644);
  26 MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)");
  27
  28 #define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB7000P: "); printk(args); printk("\n"); } } while (0)
  29
  30 struct i2c_device {
  31         struct i2c_adapter *i2c_adap;
  32         u8 i2c_addr;
  33 };
  34
  35 struct dib7000p_state {
  36         struct dvb_frontend demod;
  37         struct dib7000p_config cfg;
  38
  39         u8 i2c_addr;
  40         struct i2c_adapter *i2c_adap;
  41
  42         struct dibx000_i2c_master i2c_master;
  43
  44         u16 wbd_ref;
  45
  46         u8 current_band;
  47         u32 current_bandwidth;
  48         struct dibx000_agc_config *current_agc;
  49         u32 timf;
  50
  51         u8 div_force_off:1;
  52         u8 div_state:1;
  53         u16 div_sync_wait;
  54
  55         u8 agc_state;
  56
  57         u16 gpio_dir;
  58         u16 gpio_val;
  59
  60         u8 sfn_workaround_active:1;
  61
  62 #define SOC7090 0x7090
  63         u16 version;
  64
  65         u16 tuner_enable;
  66         struct i2c_adapter dib7090_tuner_adap;
  67
  68         /* for the I2C transfer */
  69         struct i2c_msg msg[2];
  70         u8 i2c_write_buffer[4];
  71         u8 i2c_read_buffer[2];
  72         struct mutex i2c_buffer_lock;
  73
  74         u8 input_mode_mpeg;
  75 };
  76
  77 enum dib7000p_power_mode {
  78         DIB7000P_POWER_ALL = 0,
  79         DIB7000P_POWER_ANALOG_ADC,
  80         DIB7000P_POWER_INTERFACE_ONLY,
  81 };
  82
  83 /* dib7090 specific fonctions */
  84 static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode);
  85 static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff);
  86 static void dib7090_setDibTxMux(struct dib7000p_state *state, int mode);
  87 static void dib7090_setHostBusMux(struct dib7000p_state *state, int mode);
  88
  89 static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg)
  90 {
  91         u16 ret;
  92
  93         if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
  94                 dprintk("could not acquire lock");
  95                 return 0;
  96         }
  97
  98         state->i2c_write_buffer[0] = reg >> 8;
  99         state->i2c_write_buffer[1] = reg & 0xff;
 100
 101         memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
 102         state->msg[0].addr = state->i2c_addr >> 1;
 103         state->msg[0].flags = 0;
 104         state->msg[0].buf = state->i2c_write_buffer;
 105         state->msg[0].len = 2;
 106         state->msg[1].addr = state->i2c_addr >> 1;
 107         state->msg[1].flags = I2C_M_RD;
 108         state->msg[1].buf = state->i2c_read_buffer;
 109         state->msg[1].len = 2;
 110
 111         if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2)
 112                 dprintk("i2c read error on %d", reg);
 113
 114         ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
 115         mutex_unlock(&state->i2c_buffer_lock);
 116         return ret;
 117 }
 118
 119 static int dib7000p_write_word(struct dib7000p_state *state, u16 reg, u16 val)
 120 {
 121         int ret;
 122
 123         if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
 124                 dprintk("could not acquire lock");
 125                 return -EINVAL;
 126         }
 127
 128         state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
 129         state->i2c_write_buffer[1] = reg & 0xff;
 130         state->i2c_write_buffer[2] = (val >> 8) & 0xff;
 131         state->i2c_write_buffer[3] = val & 0xff;
 132
 133         memset(&state->msg[0], 0, sizeof(struct i2c_msg));
 134         state->msg[0].addr = state->i2c_addr >> 1;
 135         state->msg[0].flags = 0;
 136         state->msg[0].buf = state->i2c_write_buffer;
 137         state->msg[0].len = 4;
 138
 139         ret = (i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ?
 140                         -EREMOTEIO : 0);
 141         mutex_unlock(&state->i2c_buffer_lock);
 142         return ret;
 143 }
 144
 145 static void dib7000p_write_tab(struct dib7000p_state *state, u16 * buf)
 146 {
 147         u16 l = 0, r, *n;
 148         n = buf;
 149         l = *n++;
 150         while (l) {
 151                 r = *n++;
 152
 153                 do {
 154                         dib7000p_write_word(state, r, *n++);
 155                         r++;
 156                 } while (--l);
 157                 l = *n++;
 158         }
 159 }
 160
 161 static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode)
 162 {
 163         int ret = 0;
 164         u16 outreg, fifo_threshold, smo_mode;
 165
 166         outreg = 0;
 167         fifo_threshold = 1792;
 168         smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
 169
 170         dprintk("setting output mode for demod %p to %d", &state->demod, mode);
 171
 172         switch (mode) {
 173         case OUTMODE_MPEG2_PAR_GATED_CLK:
 174                 outreg = (1 << 10);     /* 0x0400 */
 175                 break;
 176         case OUTMODE_MPEG2_PAR_CONT_CLK:
 177                 outreg = (1 << 10) | (1 << 6);  /* 0x0440 */
 178                 break;
 179         case OUTMODE_MPEG2_SERIAL:
 180                 outreg = (1 << 10) | (2 << 6) | (0 << 1);       /* 0x0480 */
 181                 break;
 182         case OUTMODE_DIVERSITY:
 183                 if (state->cfg.hostbus_diversity)
 184                         outreg = (1 << 10) | (4 << 6);  /* 0x0500 */
 185                 else
 186                         outreg = (1 << 11);
 187                 break;
 188         case OUTMODE_MPEG2_FIFO:
 189                 smo_mode |= (3 << 1);
 190                 fifo_threshold = 512;
 191                 outreg = (1 << 10) | (5 << 6);
 192                 break;
 193         case OUTMODE_ANALOG_ADC:
 194                 outreg = (1 << 10) | (3 << 6);
 195                 break;
 196         case OUTMODE_HIGH_Z:
 197                 outreg = 0;
 198                 break;
 199         default:
 200                 dprintk("Unhandled output_mode passed to be set for demod %p", &state->demod);
 201                 break;
 202         }
 203
 204         if (state->cfg.output_mpeg2_in_188_bytes)
 205                 smo_mode |= (1 << 5);
 206
 207         ret |= dib7000p_write_word(state, 235, smo_mode);
 208         ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
 209         if (state->version != SOC7090)
 210                 ret |= dib7000p_write_word(state, 1286, outreg);        /* P_Div_active */
 211
 212         return ret;
 213 }
 214
 215 static int dib7000p_set_diversity_in(struct dvb_frontend *demod, int onoff)
 216 {
 217         struct dib7000p_state *state = demod->demodulator_priv;
 218
 219         if (state->div_force_off) {
 220                 dprintk("diversity combination deactivated - forced by COFDM parameters");
 221                 onoff = 0;
 222                 dib7000p_write_word(state, 207, 0);
 223         } else
 224                 dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
 225
 226         state->div_state = (u8) onoff;
 227
 228         if (onoff) {
 229                 dib7000p_write_word(state, 204, 6);
 230                 dib7000p_write_word(state, 205, 16);
 231                 /* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */
 232         } else {
 233                 dib7000p_write_word(state, 204, 1);
 234                 dib7000p_write_word(state, 205, 0);
 235         }
 236
 237         return 0;
 238 }
 239
 240 static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_power_mode mode)
 241 {
 242         /* by default everything is powered off */
 243         u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0x0007, reg_899 = 0x0003, reg_1280 = (0xfe00) | (dib7000p_read_word(state, 1280) & 0x01ff);
 244
 245         /* now, depending on the requested mode, we power on */
 246         switch (mode) {
 247                 /* power up everything in the demod */
 248         case DIB7000P_POWER_ALL:
 249                 reg_774 = 0x0000;
 250                 reg_775 = 0x0000;
 251                 reg_776 = 0x0;
 252                 reg_899 = 0x0;
 253                 if (state->version == SOC7090)
 254                         reg_1280 &= 0x001f;
 255                 else
 256                         reg_1280 &= 0x01ff;
 257                 break;
 258
 259         case DIB7000P_POWER_ANALOG_ADC:
 260                 /* dem, cfg, iqc, sad, agc */
 261                 reg_774 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10) | (1 << 9));
 262                 /* nud */
 263                 reg_776 &= ~((1 << 0));
 264                 /* Dout */
 265                 if (state->version != SOC7090)
 266                         reg_1280 &= ~((1 << 11));
 267                 reg_1280 &= ~(1 << 6);
 268                 /* fall through wanted to enable the interfaces */
 269
 270                 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */
 271         case DIB7000P_POWER_INTERFACE_ONLY:     /* TODO power up either SDIO or I2C */
 272                 if (state->version == SOC7090)
 273                         reg_1280 &= ~((1 << 7) | (1 << 5));
 274                 else
 275                         reg_1280 &= ~((1 << 14) | (1 << 13) | (1 << 12) | (1 << 10));
 276                 break;
 277
 278 /* TODO following stuff is just converted from the dib7000-driver - check when is used what */
 279         }
 280
 281         dib7000p_write_word(state, 774, reg_774);
 282         dib7000p_write_word(state, 775, reg_775);
 283         dib7000p_write_word(state, 776, reg_776);
 284         dib7000p_write_word(state, 1280, reg_1280);
 285         if (state->version != SOC7090)
 286                 dib7000p_write_word(state, 899, reg_899);
 287
 288         return 0;
 289 }
 290
 291 static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no)
 292 {
 293         u16 reg_908 = 0, reg_909 = 0;
 294         u16 reg;
 295
 296         if (state->version != SOC7090) {
 297                 reg_908 = dib7000p_read_word(state, 908);
 298                 reg_909 = dib7000p_read_word(state, 909);
 299         }
 300
 301         switch (no) {
 302         case DIBX000_SLOW_ADC_ON:
 303                 if (state->version == SOC7090) {
 304                         reg = dib7000p_read_word(state, 1925);
 305
 306                         dib7000p_write_word(state, 1925, reg | (1 << 4) | (1 << 2));    /* en_slowAdc = 1 & reset_sladc = 1 */
 307
 308                         reg = dib7000p_read_word(state, 1925);  /* read acces to make it works... strange ... */
 309                         msleep(200);
 310                         dib7000p_write_word(state, 1925, reg & ~(1 << 4));      /* en_slowAdc = 1 & reset_sladc = 0 */
 311
 312                         reg = dib7000p_read_word(state, 72) & ~((0x3 << 14) | (0x3 << 12));
 313                         dib7000p_write_word(state, 72, reg | (1 << 14) | (3 << 12) | 524);      /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ; (Vin2 = Vcm) */
 314                 } else {
 315                         reg_909 |= (1 << 1) | (1 << 0);
 316                         dib7000p_write_word(state, 909, reg_909);
 317                         reg_909 &= ~(1 << 1);
 318                 }
 319                 break;
 320
 321         case DIBX000_SLOW_ADC_OFF:
 322                 if (state->version == SOC7090) {
 323                         reg = dib7000p_read_word(state, 1925);
 324                         dib7000p_write_word(state, 1925, (reg & ~(1 << 2)) | (1 << 4)); /* reset_sladc = 1 en_slowAdc = 0 */
 325                 } else
 326                         reg_909 |= (1 << 1) | (1 << 0);
 327                 break;
 328
 329         case DIBX000_ADC_ON:
 330                 reg_908 &= 0x0fff;
 331                 reg_909 &= 0x0003;
 332                 break;
 333
 334         case DIBX000_ADC_OFF:
 335                 reg_908 |= (1 << 14) | (1 << 13) | (1 << 12);
 336                 reg_909 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
 337                 break;
 338
 339         case DIBX000_VBG_ENABLE:
 340                 reg_908 &= ~(1 << 15);
 341                 break;
 342
 343         case DIBX000_VBG_DISABLE:
 344                 reg_908 |= (1 << 15);
 345                 break;
 346
 347         default:
 348                 break;
 349         }
 350
 351 //      dprintk( "908: %x, 909: %x\n", reg_908, reg_909);
 352
 353         reg_909 |= (state->cfg.disable_sample_and_hold & 1) << 4;
 354         reg_908 |= (state->cfg.enable_current_mirror & 1) << 7;
 355
 356         if (state->version != SOC7090) {
 357                 dib7000p_write_word(state, 908, reg_908);
 358                 dib7000p_write_word(state, 909, reg_909);
 359         }
 360 }
 361
 362 static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw)
 363 {
 364         u32 timf;
 365
 366         // store the current bandwidth for later use
 367         state->current_bandwidth = bw;
 368
 369         if (state->timf == 0) {
 370                 dprintk("using default timf");
 371                 timf = state->cfg.bw->timf;
 372         } else {
 373                 dprintk("using updated timf");
 374                 timf = state->timf;
 375         }
 376
 377         timf = timf * (bw / 50) / 160;
 378
 379         dib7000p_write_word(state, 23, (u16) ((timf >> 16) & 0xffff));
 380         dib7000p_write_word(state, 24, (u16) ((timf) & 0xffff));
 381
 382         return 0;
 383 }
 384
 385 static int dib7000p_sad_calib(struct dib7000p_state *state)
 386 {
 387 /* internal */
 388         dib7000p_write_word(state, 73, (0 << 1) | (0 << 0));
 389
 390         if (state->version == SOC7090)
 391                 dib7000p_write_word(state, 74, 2048);
 392         else
 393                 dib7000p_write_word(state, 74, 776);
 394
 395         /* do the calibration */
 396         dib7000p_write_word(state, 73, (1 << 0));
 397         dib7000p_write_word(state, 73, (0 << 0));
 398
 399         msleep(1);
 400
 401         return 0;
 402 }
 403
 404 int dib7000p_set_wbd_ref(struct dvb_frontend *demod, u16 value)
 405 {
 406         struct dib7000p_state *state = demod->demodulator_priv;
 407         if (value > 4095)
 408                 value = 4095;
 409         state->wbd_ref = value;
 410         return dib7000p_write_word(state, 105, (dib7000p_read_word(state, 105) & 0xf000) | value);
 411 }
 412 EXPORT_SYMBOL(dib7000p_set_wbd_ref);
 413
 414 int dib7000p_get_agc_values(struct dvb_frontend *fe,
 415                 u16 *agc_global, u16 *agc1, u16 *agc2, u16 *wbd)
 416 {
 417         struct dib7000p_state *state = fe->demodulator_priv;
 418
 419         if (agc_global != NULL)
 420                 *agc_global = dib7000p_read_word(state, 394);
 421         if (agc1 != NULL)
 422                 *agc1 = dib7000p_read_word(state, 392);
 423         if (agc2 != NULL)
 424                 *agc2 = dib7000p_read_word(state, 393);
 425         if (wbd != NULL)
 426                 *wbd = dib7000p_read_word(state, 397);
 427
 428         return 0;
 429 }
 430 EXPORT_SYMBOL(dib7000p_get_agc_values);
 431
 432 static void dib7000p_reset_pll(struct dib7000p_state *state)
 433 {
 434         struct dibx000_bandwidth_config *bw = &state->cfg.bw[0];
 435         u16 clk_cfg0;
 436
 437         if (state->version == SOC7090) {
 438                 dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv));
 439
 440                 while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
 441                         ;
 442
 443                 dib7000p_write_word(state, 1857, dib7000p_read_word(state, 1857) | (!bw->pll_bypass << 15));
 444         } else {
 445                 /* force PLL bypass */
 446                 clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) |
 447                         (bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0);
 448
 449                 dib7000p_write_word(state, 900, clk_cfg0);
 450
 451                 /* P_pll_cfg */
 452                 dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset);
 453                 clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff);
 454                 dib7000p_write_word(state, 900, clk_cfg0);
 455         }
 456
 457         dib7000p_write_word(state, 18, (u16) (((bw->internal * 1000) >> 16) & 0xffff));
 458         dib7000p_write_word(state, 19, (u16) ((bw->internal * 1000) & 0xffff));
 459         dib7000p_write_word(state, 21, (u16) ((bw->ifreq >> 16) & 0xffff));
 460         dib7000p_write_word(state, 22, (u16) ((bw->ifreq) & 0xffff));
 461
 462         dib7000p_write_word(state, 72, bw->sad_cfg);
 463 }
 464
 465 static u32 dib7000p_get_internal_freq(struct dib7000p_state *state)
 466 {
 467         u32 internal = (u32) dib7000p_read_word(state, 18) << 16;
 468         internal |= (u32) dib7000p_read_word(state, 19);
 469         internal /= 1000;
 470
 471         return internal;
 472 }
 473
 474 int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw)
 475 {
 476         struct dib7000p_state *state = fe->demodulator_priv;
 477         u16 reg_1857, reg_1856 = dib7000p_read_word(state, 1856);
 478         u8 loopdiv, prediv;
 479         u32 internal, xtal;
 480
 481         /* get back old values */
 482         prediv = reg_1856 & 0x3f;
 483         loopdiv = (reg_1856 >> 6) & 0x3f;
 484
 485         if ((bw != NULL) && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) {
 486                 dprintk("Updating pll (prediv: old =  %d new = %d ; loopdiv : old = %d new = %d)", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio);
 487                 reg_1856 &= 0xf000;
 488                 reg_1857 = dib7000p_read_word(state, 1857);
 489                 dib7000p_write_word(state, 1857, reg_1857 & ~(1 << 15));
 490
 491                 dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f));
 492
 493                 /* write new system clk into P_sec_len */
 494                 internal = dib7000p_get_internal_freq(state);
 495                 xtal = (internal / loopdiv) * prediv;
 496                 internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio;      /* new internal */
 497                 dib7000p_write_word(state, 18, (u16) ((internal >> 16) & 0xffff));
 498                 dib7000p_write_word(state, 19, (u16) (internal & 0xffff));
 499
 500                 dib7000p_write_word(state, 1857, reg_1857 | (1 << 15));
 501
 502                 while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
 503                         dprintk("Waiting for PLL to lock");
 504
 505                 return 0;
 506         }
 507         return -EIO;
 508 }
 509 EXPORT_SYMBOL(dib7000p_update_pll);
 510
 511 static int dib7000p_reset_gpio(struct dib7000p_state *st)
 512 {
 513         /* reset the GPIOs */
 514         dprintk("gpio dir: %x: val: %x, pwm_pos: %x", st->gpio_dir, st->gpio_val, st->cfg.gpio_pwm_pos);
 515
 516         dib7000p_write_word(st, 1029, st->gpio_dir);
 517         dib7000p_write_word(st, 1030, st->gpio_val);
 518
 519         /* TODO 1031 is P_gpio_od */
 520
 521         dib7000p_write_word(st, 1032, st->cfg.gpio_pwm_pos);
 522
 523         dib7000p_write_word(st, 1037, st->cfg.pwm_freq_div);
 524         return 0;
 525 }
 526
 527 static int dib7000p_cfg_gpio(struct dib7000p_state *st, u8 num, u8 dir, u8 val)
 528 {
 529         st->gpio_dir = dib7000p_read_word(st, 1029);
 530         st->gpio_dir &= ~(1 << num);    /* reset the direction bit */
 531         st->gpio_dir |= (dir & 0x1) << num;     /* set the new direction */
 532         dib7000p_write_word(st, 1029, st->gpio_dir);
 533
 534         st->gpio_val = dib7000p_read_word(st, 1030);
 535         st->gpio_val &= ~(1 << num);    /* reset the direction bit */
 536         st->gpio_val |= (val & 0x01) << num;    /* set the new value */
 537         dib7000p_write_word(st, 1030, st->gpio_val);
 538
 539         return 0;
 540 }
 541
 542 int dib7000p_set_gpio(struct dvb_frontend *demod, u8 num, u8 dir, u8 val)
 543 {
 544         struct dib7000p_state *state = demod->demodulator_priv;
 545         return dib7000p_cfg_gpio(state, num, dir, val);
 546 }
 547 EXPORT_SYMBOL(dib7000p_set_gpio);
 548
 549 static u16 dib7000p_defaults[] = {
 550         // auto search configuration
 551         3, 2,
 552         0x0004,
 553         (1<<3)|(1<<11)|(1<<12)|(1<<13),
 554         0x0814,                 /* Equal Lock */
 555
 556         12, 6,
 557         0x001b,
 558         0x7740,
 559         0x005b,
 560         0x8d80,
 561         0x01c9,
 562         0xc380,
 563         0x0000,
 564         0x0080,
 565         0x0000,
 566         0x0090,
 567         0x0001,
 568         0xd4c0,
 569
 570         1, 26,
 571         0x6680,
 572
 573         /* set ADC level to -16 */
 574         11, 79,
 575         (1 << 13) - 825 - 117,
 576         (1 << 13) - 837 - 117,
 577         (1 << 13) - 811 - 117,
 578         (1 << 13) - 766 - 117,
 579         (1 << 13) - 737 - 117,
 580         (1 << 13) - 693 - 117,
 581         (1 << 13) - 648 - 117,
 582         (1 << 13) - 619 - 117,
 583         (1 << 13) - 575 - 117,
 584         (1 << 13) - 531 - 117,
 585         (1 << 13) - 501 - 117,
 586
 587         1, 142,
 588         0x0410,
 589
 590         /* disable power smoothing */
 591         8, 145,
 592         0,
 593         0,
 594         0,
 595         0,
 596         0,
 597         0,
 598         0,
 599         0,
 600
 601         1, 154,
 602         1 << 13,
 603
 604         1, 168,
 605         0x0ccd,
 606
 607         1, 183,
 608         0x200f,
 609
 610         1, 212,
 611                 0x169,
 612
 613         5, 187,
 614         0x023d,
 615         0x00a4,
 616         0x00a4,
 617         0x7ff0,
 618         0x3ccc,
 619
 620         1, 198,
 621         0x800,
 622
 623         1, 222,
 624         0x0010,
 625
 626         1, 235,
 627         0x0062,
 628
 629         0,
 630 };
 631
 632 static int dib7000p_demod_reset(struct dib7000p_state *state)
 633 {
 634         dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
 635
 636         if (state->version == SOC7090)
 637                 dibx000_reset_i2c_master(&state->i2c_master);
 638
 639         dib7000p_set_adc_state(state, DIBX000_VBG_ENABLE);
 640
 641         /* restart all parts */
 642         dib7000p_write_word(state, 770, 0xffff);
 643         dib7000p_write_word(state, 771, 0xffff);
 644         dib7000p_write_word(state, 772, 0x001f);
 645         dib7000p_write_word(state, 1280, 0x001f - ((1 << 4) | (1 << 3)));
 646
 647         dib7000p_write_word(state, 770, 0);
 648         dib7000p_write_word(state, 771, 0);
 649         dib7000p_write_word(state, 772, 0);
 650         dib7000p_write_word(state, 1280, 0);
 651
 652         if (state->version != SOC7090) {
 653                 dib7000p_write_word(state,  898, 0x0003);
 654                 dib7000p_write_word(state,  898, 0);
 655         }
 656
 657         /* default */
 658         dib7000p_reset_pll(state);
 659
 660         if (dib7000p_reset_gpio(state) != 0)
 661                 dprintk("GPIO reset was not successful.");
 662
 663         if (state->version == SOC7090) {
 664                 dib7000p_write_word(state, 899, 0);
 665
 666                 /* impulse noise */
 667                 dib7000p_write_word(state, 42, (1<<5) | 3); /* P_iqc_thsat_ipc = 1 ; P_iqc_win2 = 3 */
 668                 dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */
 669                 dib7000p_write_word(state, 44, 300); /* 300 fag P_iqc_dect_min = +280 */
 670                 dib7000p_write_word(state, 273, (0<<6) | 30);
 671         }
 672         if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
 673                 dprintk("OUTPUT_MODE could not be reset.");
 674
 675         dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
 676         dib7000p_sad_calib(state);
 677         dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
 678
 679         /* unforce divstr regardless whether i2c enumeration was done or not */
 680         dib7000p_write_word(state, 1285, dib7000p_read_word(state, 1285) & ~(1 << 1));
 681
 682         dib7000p_set_bandwidth(state, 8000);
 683
 684         if (state->version == SOC7090) {
 685                 dib7000p_write_word(state, 36, 0x0755);/* P_iqc_impnc_on =1 & P_iqc_corr_inh = 1 for impulsive noise */
 686         } else {
 687                 if (state->cfg.tuner_is_baseband)
 688                         dib7000p_write_word(state, 36, 0x0755);
 689                 else
 690                         dib7000p_write_word(state, 36, 0x1f55);
 691         }
 692
 693         dib7000p_write_tab(state, dib7000p_defaults);
 694         if (state->version != SOC7090) {
 695                 dib7000p_write_word(state, 901, 0x0006);
 696                 dib7000p_write_word(state, 902, (3 << 10) | (1 << 6));
 697                 dib7000p_write_word(state, 905, 0x2c8e);
 698         }
 699
 700         dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
 701
 702         return 0;
 703 }
 704
 705 static void dib7000p_pll_clk_cfg(struct dib7000p_state *state)
 706 {
 707         u16 tmp = 0;
 708         tmp = dib7000p_read_word(state, 903);
 709         dib7000p_write_word(state, 903, (tmp | 0x1));
 710         tmp = dib7000p_read_word(state, 900);
 711         dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6));
 712 }
 713
 714 static void dib7000p_restart_agc(struct dib7000p_state *state)
 715 {
 716         // P_restart_iqc & P_restart_agc
 717         dib7000p_write_word(state, 770, (1 << 11) | (1 << 9));
 718         dib7000p_write_word(state, 770, 0x0000);
 719 }
 720
 721 static int dib7000p_update_lna(struct dib7000p_state *state)
 722 {
 723         u16 dyn_gain;
 724
 725         if (state->cfg.update_lna) {
 726                 dyn_gain = dib7000p_read_word(state, 394);
 727                 if (state->cfg.update_lna(&state->demod, dyn_gain)) {
 728                         dib7000p_restart_agc(state);
 729                         return 1;
 730                 }
 731         }
 732
 733         return 0;
 734 }
 735
 736 static int dib7000p_set_agc_config(struct dib7000p_state *state, u8 band)
 737 {
 738         struct dibx000_agc_config *agc = NULL;
 739         int i;
 740         if (state->current_band == band && state->current_agc != NULL)
 741                 return 0;
 742         state->current_band = band;
 743
 744         for (i = 0; i < state->cfg.agc_config_count; i++)
 745                 if (state->cfg.agc[i].band_caps & band) {
 746                         agc = &state->cfg.agc[i];
 747                         break;
 748                 }
 749
 750         if (agc == NULL) {
 751                 dprintk("no valid AGC configuration found for band 0x%02x", band);
 752                 return -EINVAL;
 753         }
 754
 755         state->current_agc = agc;
 756
 757         /* AGC */
 758         dib7000p_write_word(state, 75, agc->setup);
 759         dib7000p_write_word(state, 76, agc->inv_gain);
 760         dib7000p_write_word(state, 77, agc->time_stabiliz);
 761         dib7000p_write_word(state, 100, (agc->alpha_level << 12) | agc->thlock);
 762
 763         // Demod AGC loop configuration
 764         dib7000p_write_word(state, 101, (agc->alpha_mant << 5) | agc->alpha_exp);
 765         dib7000p_write_word(state, 102, (agc->beta_mant << 6) | agc->beta_exp);
 766
 767         /* AGC continued */
 768         dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d",
 769                 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
 770
 771         if (state->wbd_ref != 0)
 772                 dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | state->wbd_ref);
 773         else
 774                 dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | agc->wbd_ref);
 775
 776         dib7000p_write_word(state, 106, (agc->wbd_sel << 13) | (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
 777
 778         dib7000p_write_word(state, 107, agc->agc1_max);
 779         dib7000p_write_word(state, 108, agc->agc1_min);
 780         dib7000p_write_word(state, 109, agc->agc2_max);
 781         dib7000p_write_word(state, 110, agc->agc2_min);
 782         dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
 783         dib7000p_write_word(state, 112, agc->agc1_pt3);
 784         dib7000p_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
 785         dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
 786         dib7000p_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
 787         return 0;
 788 }
 789
 790 static void dib7000p_set_dds(struct dib7000p_state *state, s32 offset_khz)
 791 {
 792         u32 internal = dib7000p_get_internal_freq(state);
 793         s32 unit_khz_dds_val = 67108864 / (internal);   /* 2**26 / Fsampling is the unit 1KHz offset */
 794         u32 abs_offset_khz = ABS(offset_khz);
 795         u32 dds = state->cfg.bw->ifreq & 0x1ffffff;
 796         u8 invert = !!(state->cfg.bw->ifreq & (1 << 25));
 797
 798         dprintk("setting a frequency offset of %dkHz internal freq = %d invert = %d", offset_khz, internal, invert);
 799
 800         if (offset_khz < 0)
 801                 unit_khz_dds_val *= -1;
 802
 803         /* IF tuner */
 804         if (invert)
 805                 dds -= (abs_offset_khz * unit_khz_dds_val);     /* /100 because of /100 on the unit_khz_dds_val line calc for better accuracy */
 806         else
 807                 dds += (abs_offset_khz * unit_khz_dds_val);
 808
 809         if (abs_offset_khz <= (internal / 2)) { /* Max dds offset is the half of the demod freq */
 810                 dib7000p_write_word(state, 21, (u16) (((dds >> 16) & 0x1ff) | (0 << 10) | (invert << 9)));
 811                 dib7000p_write_word(state, 22, (u16) (dds & 0xffff));
 812         }
 813 }
 814
 815 static int dib7000p_agc_startup(struct dvb_frontend *demod)
 816 {
 817         struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
 818         struct dib7000p_state *state = demod->demodulator_priv;
 819         int ret = -1;
 820         u8 *agc_state = &state->agc_state;
 821         u8 agc_split;
 822         u16 reg;
 823         u32 upd_demod_gain_period = 0x1000;
 824
 825         switch (state->agc_state) {
 826         case 0:
 827                 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
 828                 if (state->version == SOC7090) {
 829                         reg = dib7000p_read_word(state, 0x79b) & 0xff00;
 830                         dib7000p_write_word(state, 0x79a, upd_demod_gain_period & 0xFFFF);      /* lsb */
 831                         dib7000p_write_word(state, 0x79b, reg | (1 << 14) | ((upd_demod_gain_period >> 16) & 0xFF));
 832
 833                         /* enable adc i & q */
 834                         reg = dib7000p_read_word(state, 0x780);
 835                         dib7000p_write_word(state, 0x780, (reg | (0x3)) & (~(1 << 7)));
 836                 } else {
 837                         dib7000p_set_adc_state(state, DIBX000_ADC_ON);
 838                         dib7000p_pll_clk_cfg(state);
 839                 }
 840
 841                 if (dib7000p_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency / 1000)) != 0)
 842                         return -1;
 843
 844                 dib7000p_set_dds(state, 0);
 845                 ret = 7;
 846                 (*agc_state)++;
 847                 break;
 848
 849         case 1:
 850                 if (state->cfg.agc_control)
 851                         state->cfg.agc_control(&state->demod, 1);
 852
 853                 dib7000p_write_word(state, 78, 32768);
 854                 if (!state->current_agc->perform_agc_softsplit) {
 855                         /* we are using the wbd - so slow AGC startup */
 856                         /* force 0 split on WBD and restart AGC */
 857                         dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | (1 << 8));
 858                         (*agc_state)++;
 859                         ret = 5;
 860                 } else {
 861                         /* default AGC startup */
 862                         (*agc_state) = 4;
 863                         /* wait AGC rough lock time */
 864                         ret = 7;
 865                 }
 866
 867                 dib7000p_restart_agc(state);
 868                 break;
 869
 870         case 2:         /* fast split search path after 5sec */
 871                 dib7000p_write_word(state, 75, state->current_agc->setup | (1 << 4));   /* freeze AGC loop */
 872                 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (2 << 9) | (0 << 8));     /* fast split search 0.25kHz */
 873                 (*agc_state)++;
 874                 ret = 14;
 875                 break;
 876
 877         case 3:         /* split search ended */
 878                 agc_split = (u8) dib7000p_read_word(state, 396);        /* store the split value for the next time */
 879                 dib7000p_write_word(state, 78, dib7000p_read_word(state, 394)); /* set AGC gain start value */
 880
 881                 dib7000p_write_word(state, 75, state->current_agc->setup);      /* std AGC loop */
 882                 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | agc_split);        /* standard split search */
 883
 884                 dib7000p_restart_agc(state);
 885
 886                 dprintk("SPLIT %p: %hd", demod, agc_split);
 887
 888                 (*agc_state)++;
 889                 ret = 5;
 890                 break;
 891
 892         case 4:         /* LNA startup */
 893                 ret = 7;
 894
 895                 if (dib7000p_update_lna(state))
 896                         ret = 5;
 897                 else
 898                         (*agc_state)++;
 899                 break;
 900
 901         case 5:
 902                 if (state->cfg.agc_control)
 903                         state->cfg.agc_control(&state->demod, 0);
 904                 (*agc_state)++;
 905                 break;
 906         default:
 907                 break;
 908         }
 909         return ret;
 910 }
 911
 912 static void dib7000p_update_timf(struct dib7000p_state *state)
 913 {
 914         u32 timf = (dib7000p_read_word(state, 427) << 16) | dib7000p_read_word(state, 428);
 915         state->timf = timf * 160 / (state->current_bandwidth / 50);
 916         dib7000p_write_word(state, 23, (u16) (timf >> 16));
 917         dib7000p_write_word(state, 24, (u16) (timf & 0xffff));
 918         dprintk("updated timf_frequency: %d (default: %d)", state->timf, state->cfg.bw->timf);
 919
 920 }
 921
 922 u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf)
 923 {
 924         struct dib7000p_state *state = fe->demodulator_priv;
 925         switch (op) {
 926         case DEMOD_TIMF_SET:
 927                 state->timf = timf;
 928                 break;
 929         case DEMOD_TIMF_UPDATE:
 930                 dib7000p_update_timf(state);
 931                 break;
 932         case DEMOD_TIMF_GET:
 933                 break;
 934         }
 935         dib7000p_set_bandwidth(state, state->current_bandwidth);
 936         return state->timf;
 937 }
 938 EXPORT_SYMBOL(dib7000p_ctrl_timf);
 939
 940 static void dib7000p_set_channel(struct dib7000p_state *state,
 941                                  struct dtv_frontend_properties *ch, u8 seq)
 942 {
 943         u16 value, est[4];
 944
 945         dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
 946
 947         /* nfft, guard, qam, alpha */
 948         value = 0;
 949         switch (ch->transmission_mode) {
 950         case TRANSMISSION_MODE_2K:
 951                 value |= (0 << 7);
 952                 break;
 953         case TRANSMISSION_MODE_4K:
 954                 value |= (2 << 7);
 955                 break;
 956         default:
 957         case TRANSMISSION_MODE_8K:
 958                 value |= (1 << 7);
 959                 break;
 960         }
 961         switch (ch->guard_interval) {
 962         case GUARD_INTERVAL_1_32:
 963                 value |= (0 << 5);
 964                 break;
 965         case GUARD_INTERVAL_1_16:
 966                 value |= (1 << 5);
 967                 break;
 968         case GUARD_INTERVAL_1_4:
 969                 value |= (3 << 5);
 970                 break;
 971         default:
 972         case GUARD_INTERVAL_1_8:
 973                 value |= (2 << 5);
 974                 break;
 975         }
 976         switch (ch->modulation) {
 977         case QPSK:
 978                 value |= (0 << 3);
 979                 break;
 980         case QAM_16:
 981                 value |= (1 << 3);
 982                 break;
 983         default:
 984         case QAM_64:
 985                 value |= (2 << 3);
 986                 break;
 987         }
 988         switch (HIERARCHY_1) {
 989         case HIERARCHY_2:
 990                 value |= 2;
 991                 break;
 992         case HIERARCHY_4:
 993                 value |= 4;
 994                 break;
 995         default:
 996         case HIERARCHY_1:
 997                 value |= 1;
 998                 break;
 999         }
1000         dib7000p_write_word(state, 0, value);
1001         dib7000p_write_word(state, 5, (seq << 4) | 1);  /* do not force tps, search list 0 */
1002
1003         /* P_dintl_native, P_dintlv_inv, P_hrch, P_code_rate, P_select_hp */
1004         value = 0;
1005         if (1 != 0)
1006                 value |= (1 << 6);
1007         if (ch->hierarchy == 1)
1008                 value |= (1 << 4);
1009         if (1 == 1)
1010                 value |= 1;
1011         switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) {
1012         case FEC_2_3:
1013                 value |= (2 << 1);
1014                 break;
1015         case FEC_3_4:
1016                 value |= (3 << 1);
1017                 break;
1018         case FEC_5_6:
1019                 value |= (5 << 1);
1020                 break;
1021         case FEC_7_8:
1022                 value |= (7 << 1);
1023                 break;
1024         default:
1025         case FEC_1_2:
1026                 value |= (1 << 1);
1027                 break;
1028         }
1029         dib7000p_write_word(state, 208, value);
1030
1031         /* offset loop parameters */
1032         dib7000p_write_word(state, 26, 0x6680);
1033         dib7000p_write_word(state, 32, 0x0003);
1034         dib7000p_write_word(state, 29, 0x1273);
1035         dib7000p_write_word(state, 33, 0x0005);
1036
1037         /* P_dvsy_sync_wait */
1038         switch (ch->transmission_mode) {
1039         case TRANSMISSION_MODE_8K:
1040                 value = 256;
1041                 break;
1042         case TRANSMISSION_MODE_4K:
1043                 value = 128;
1044                 break;
1045         case TRANSMISSION_MODE_2K:
1046         default:
1047                 value = 64;
1048                 break;
1049         }
1050         switch (ch->guard_interval) {
1051         case GUARD_INTERVAL_1_16:
1052                 value *= 2;
1053                 break;
1054         case GUARD_INTERVAL_1_8:
1055                 value *= 4;
1056                 break;
1057         case GUARD_INTERVAL_1_4:
1058                 value *= 8;
1059                 break;
1060         default:
1061         case GUARD_INTERVAL_1_32:
1062                 value *= 1;
1063                 break;
1064         }
1065         if (state->cfg.diversity_delay == 0)
1066                 state->div_sync_wait = (value * 3) / 2 + 48;
1067         else
1068                 state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay;
1069
1070         /* deactive the possibility of diversity reception if extended interleaver */
1071         state->div_force_off = !1 && ch->transmission_mode != TRANSMISSION_MODE_8K;
1072         dib7000p_set_diversity_in(&state->demod, state->div_state);
1073
1074         /* channel estimation fine configuration */
1075         switch (ch->modulation) {
1076         case QAM_64:
1077                 est[0] = 0x0148;        /* P_adp_regul_cnt 0.04 */
1078                 est[1] = 0xfff0;        /* P_adp_noise_cnt -0.002 */
1079                 est[2] = 0x00a4;        /* P_adp_regul_ext 0.02 */
1080                 est[3] = 0xfff8;        /* P_adp_noise_ext -0.001 */
1081                 break;
1082         case QAM_16:
1083                 est[0] = 0x023d;        /* P_adp_regul_cnt 0.07 */
1084                 est[1] = 0xffdf;        /* P_adp_noise_cnt -0.004 */
1085                 est[2] = 0x00a4;        /* P_adp_regul_ext 0.02 */
1086                 est[3] = 0xfff0;        /* P_adp_noise_ext -0.002 */
1087                 break;
1088         default:
1089                 est[0] = 0x099a;        /* P_adp_regul_cnt 0.3 */
1090                 est[1] = 0xffae;        /* P_adp_noise_cnt -0.01 */
1091                 est[2] = 0x0333;        /* P_adp_regul_ext 0.1 */
1092                 est[3] = 0xfff8;        /* P_adp_noise_ext -0.002 */
1093                 break;
1094         }
1095         for (value = 0; value < 4; value++)
1096                 dib7000p_write_word(state, 187 + value, est[value]);
1097 }
1098
1099 static int dib7000p_autosearch_start(struct dvb_frontend *demod)
1100 {
1101         struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
1102         struct dib7000p_state *state = demod->demodulator_priv;
1103         struct dtv_frontend_properties schan;
1104         u32 value, factor;
1105         u32 internal = dib7000p_get_internal_freq(state);
1106
1107         schan = *ch;
1108         schan.modulation = QAM_64;
1109         schan.guard_interval = GUARD_INTERVAL_1_32;
1110         schan.transmission_mode = TRANSMISSION_MODE_8K;
1111         schan.code_rate_HP = FEC_2_3;
1112         schan.code_rate_LP = FEC_3_4;
1113         schan.hierarchy = 0;
1114
1115         dib7000p_set_channel(state, &schan, 7);
1116
1117         factor = BANDWIDTH_TO_KHZ(ch->bandwidth_hz);
1118         if (factor >= 5000) {
1119                 if (state->version == SOC7090)
1120                         factor = 2;
1121                 else
1122                         factor = 1;
1123         } else
1124                 factor = 6;
1125
1126         value = 30 * internal * factor;
1127         dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff));
1128         dib7000p_write_word(state, 7, (u16) (value & 0xffff));
1129         value = 100 * internal * factor;
1130         dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff));
1131         dib7000p_write_word(state, 9, (u16) (value & 0xffff));
1132         value = 500 * internal * factor;
1133         dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff));
1134         dib7000p_write_word(state, 11, (u16) (value & 0xffff));
1135
1136         value = dib7000p_read_word(state, 0);
1137         dib7000p_write_word(state, 0, (u16) ((1 << 9) | value));
1138         dib7000p_read_word(state, 1284);
1139         dib7000p_write_word(state, 0, (u16) value);
1140
1141         return 0;
1142 }
1143
1144 static int dib7000p_autosearch_is_irq(struct dvb_frontend *demod)
1145 {
1146         struct dib7000p_state *state = demod->demodulator_priv;
1147         u16 irq_pending = dib7000p_read_word(state, 1284);
1148
1149         if (irq_pending & 0x1)
1150                 return 1;
1151
1152         if (irq_pending & 0x2)
1153                 return 2;
1154
1155         return 0;
1156 }
1157
1158 static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw)
1159 {
1160         static s16 notch[] = { 16143, 14402, 12238, 9713, 6902, 3888, 759, -2392 };
1161         static u8 sine[] = { 0, 2, 3, 5, 6, 8, 9, 11, 13, 14, 16, 17, 19, 20, 22,
1162                 24, 25, 27, 28, 30, 31, 33, 34, 36, 38, 39, 41, 42, 44, 45, 47, 48, 50, 51,
1163                 53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 79, 80,
1164                 82, 83, 85, 86, 88, 89, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105,
1165                 107, 108, 109, 111, 112, 114, 115, 117, 118, 119, 121, 122, 123, 125, 126,
1166                 128, 129, 130, 132, 133, 134, 136, 137, 138, 140, 141, 142, 144, 145, 146,
1167                 147, 149, 150, 151, 152, 154, 155, 156, 157, 159, 160, 161, 162, 164, 165,
1168                 166, 167, 168, 170, 171, 172, 173, 174, 175, 177, 178, 179, 180, 181, 182,
1169                 183, 184, 185, 186, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198,
1170                 199, 200, 201, 202, 203, 204, 205, 206, 207, 207, 208, 209, 210, 211, 212,
1171                 213, 214, 215, 215, 216, 217, 218, 219, 220, 220, 221, 222, 223, 224, 224,
1172                 225, 226, 227, 227, 228, 229, 229, 230, 231, 231, 232, 233, 233, 234, 235,
1173                 235, 236, 237, 237, 238, 238, 239, 239, 240, 241, 241, 242, 242, 243, 243,
1174                 244, 244, 245, 245, 245, 246, 246, 247, 247, 248, 248, 248, 249, 249, 249,
1175                 250, 250, 250, 251, 251, 251, 252, 252, 252, 252, 253, 253, 253, 253, 254,
1176                 254, 254, 254, 254, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
1177                 255, 255, 255, 255, 255, 255
1178         };
1179
1180         u32 xtal = state->cfg.bw->xtal_hz / 1000;
1181         int f_rel = DIV_ROUND_CLOSEST(rf_khz, xtal) * xtal - rf_khz;
1182         int k;
1183         int coef_re[8], coef_im[8];
1184         int bw_khz = bw;
1185         u32 pha;
1186
1187         dprintk("relative position of the Spur: %dk (RF: %dk, XTAL: %dk)", f_rel, rf_khz, xtal);
1188
1189         if (f_rel < -bw_khz / 2 || f_rel > bw_khz / 2)
1190                 return;
1191
1192         bw_khz /= 100;
1193
1194         dib7000p_write_word(state, 142, 0x0610);
1195
1196         for (k = 0; k < 8; k++) {
1197                 pha = ((f_rel * (k + 1) * 112 * 80 / bw_khz) / 1000) & 0x3ff;
1198
1199                 if (pha == 0) {
1200                         coef_re[k] = 256;
1201                         coef_im[k] = 0;
1202                 } else if (pha < 256) {
1203                         coef_re[k] = sine[256 - (pha & 0xff)];
1204                         coef_im[k] = sine[pha & 0xff];
1205                 } else if (pha == 256) {
1206                         coef_re[k] = 0;
1207                         coef_im[k] = 256;
1208                 } else if (pha < 512) {
1209                         coef_re[k] = -sine[pha & 0xff];
1210                         coef_im[k] = sine[256 - (pha & 0xff)];
1211                 } else if (pha == 512) {
1212                         coef_re[k] = -256;
1213                         coef_im[k] = 0;
1214                 } else if (pha < 768) {
1215                         coef_re[k] = -sine[256 - (pha & 0xff)];
1216                         coef_im[k] = -sine[pha & 0xff];
1217                 } else if (pha == 768) {
1218                         coef_re[k] = 0;
1219                         coef_im[k] = -256;
1220                 } else {
1221                         coef_re[k] = sine[pha & 0xff];
1222                         coef_im[k] = -sine[256 - (pha & 0xff)];
1223                 }
1224
1225                 coef_re[k] *= notch[k];
1226                 coef_re[k] += (1 << 14);
1227                 if (coef_re[k] >= (1 << 24))
1228                         coef_re[k] = (1 << 24) - 1;
1229                 coef_re[k] /= (1 << 15);
1230
1231                 coef_im[k] *= notch[k];
1232                 coef_im[k] += (1 << 14);
1233                 if (coef_im[k] >= (1 << 24))
1234                         coef_im[k] = (1 << 24) - 1;
1235                 coef_im[k] /= (1 << 15);
1236
1237                 dprintk("PALF COEF: %d re: %d im: %d", k, coef_re[k], coef_im[k]);
1238
1239                 dib7000p_write_word(state, 143, (0 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
1240                 dib7000p_write_word(state, 144, coef_im[k] & 0x3ff);
1241                 dib7000p_write_word(state, 143, (1 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
1242         }
1243         dib7000p_write_word(state, 143, 0);
1244 }
1245
1246 static int dib7000p_tune(struct dvb_frontend *demod)
1247 {
1248         struct dtv_frontend_properties *ch = &demod->dtv_property_cache;
1249         struct dib7000p_state *state = demod->demodulator_priv;
1250         u16 tmp = 0;
1251
1252         if (ch != NULL)
1253                 dib7000p_set_channel(state, ch, 0);
1254         else
1255                 return -EINVAL;
1256
1257         // restart demod
1258         dib7000p_write_word(state, 770, 0x4000);
1259         dib7000p_write_word(state, 770, 0x0000);
1260         msleep(45);
1261
1262         /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */
1263         tmp = (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3);
1264         if (state->sfn_workaround_active) {
1265                 dprintk("SFN workaround is active");
1266                 tmp |= (1 << 9);
1267                 dib7000p_write_word(state, 166, 0x4000);
1268         } else {
1269                 dib7000p_write_word(state, 166, 0x0000);
1270         }
1271         dib7000p_write_word(state, 29, tmp);
1272
1273         // never achieved a lock with that bandwidth so far - wait for osc-freq to update
1274         if (state->timf == 0)
1275                 msleep(200);
1276
1277         /* offset loop parameters */
1278
1279         /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
1280         tmp = (6 << 8) | 0x80;
1281         switch (ch->transmission_mode) {
1282         case TRANSMISSION_MODE_2K:
1283                 tmp |= (2 << 12);
1284                 break;
1285         case TRANSMISSION_MODE_4K:
1286                 tmp |= (3 << 12);
1287                 break;
1288         default:
1289         case TRANSMISSION_MODE_8K:
1290                 tmp |= (4 << 12);
1291                 break;
1292         }
1293         dib7000p_write_word(state, 26, tmp);    /* timf_a(6xxx) */
1294
1295         /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
1296         tmp = (0 << 4);
1297         switch (ch->transmission_mode) {
1298         case TRANSMISSION_MODE_2K:
1299                 tmp |= 0x6;
1300                 break;
1301         case TRANSMISSION_MODE_4K:
1302                 tmp |= 0x7;
1303                 break;
1304         default:
1305         case TRANSMISSION_MODE_8K:
1306                 tmp |= 0x8;
1307                 break;
1308         }
1309         dib7000p_write_word(state, 32, tmp);
1310
1311         /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
1312         tmp = (0 << 4);
1313         switch (ch->transmission_mode) {
1314         case TRANSMISSION_MODE_2K:
1315                 tmp |= 0x6;
1316                 break;
1317         case TRANSMISSION_MODE_4K:
1318                 tmp |= 0x7;
1319                 break;
1320         default:
1321         case TRANSMISSION_MODE_8K:
1322                 tmp |= 0x8;
1323                 break;
1324         }
1325         dib7000p_write_word(state, 33, tmp);
1326
1327         tmp = dib7000p_read_word(state, 509);
1328         if (!((tmp >> 6) & 0x1)) {
1329                 /* restart the fec */
1330                 tmp = dib7000p_read_word(state, 771);
1331                 dib7000p_write_word(state, 771, tmp | (1 << 1));
1332                 dib7000p_write_word(state, 771, tmp);
1333                 msleep(40);
1334                 tmp = dib7000p_read_word(state, 509);
1335         }
1336         // we achieved a lock - it's time to update the osc freq
1337         if ((tmp >> 6) & 0x1) {
1338                 dib7000p_update_timf(state);
1339                 /* P_timf_alpha += 2 */
1340                 tmp = dib7000p_read_word(state, 26);
1341                 dib7000p_write_word(state, 26, (tmp & ~(0xf << 12)) | ((((tmp >> 12) & 0xf) + 5) << 12));
1342         }
1343
1344         if (state->cfg.spur_protect)
1345                 dib7000p_spur_protect(state, ch->frequency / 1000, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
1346
1347         dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz));
1348         return 0;
1349 }
1350
1351 static int dib7000p_wakeup(struct dvb_frontend *demod)
1352 {
1353         struct dib7000p_state *state = demod->demodulator_priv;
1354         dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
1355         dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
1356         if (state->version == SOC7090)
1357                 dib7000p_sad_calib(state);
1358         return 0;
1359 }
1360
1361 static int dib7000p_sleep(struct dvb_frontend *demod)
1362 {
1363         struct dib7000p_state *state = demod->demodulator_priv;
1364         if (state->version == SOC7090)
1365                 return dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
1366         return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
1367 }
1368
1369 static int dib7000p_identify(struct dib7000p_state *st)
1370 {
1371         u16 value;
1372         dprintk("checking demod on I2C address: %d (%x)", st->i2c_addr, st->i2c_addr);
1373
1374         if ((value = dib7000p_read_word(st, 768)) != 0x01b3) {
1375                 dprintk("wrong Vendor ID (read=0x%x)", value);
1376                 return -EREMOTEIO;
1377         }
1378
1379         if ((value = dib7000p_read_word(st, 769)) != 0x4000) {
1380                 dprintk("wrong Device ID (%x)", value);
1381                 return -EREMOTEIO;
1382         }
1383
1384         return 0;
1385 }
1386
1387 static int dib7000p_get_frontend(struct dvb_frontend *fe,
1388                                  struct dtv_frontend_properties *fep)
1389 {
1390         struct dib7000p_state *state = fe->demodulator_priv;
1391         u16 tps = dib7000p_read_word(state, 463);
1392
1393         fep->inversion = INVERSION_AUTO;
1394
1395         fep->bandwidth_hz = BANDWIDTH_TO_HZ(state->current_bandwidth);
1396
1397         switch ((tps >> 8) & 0x3) {
1398         case 0:
1399                 fep->transmission_mode = TRANSMISSION_MODE_2K;
1400                 break;
1401         case 1:
1402                 fep->transmission_mode = TRANSMISSION_MODE_8K;
1403                 break;
1404         /* case 2: fep->transmission_mode = TRANSMISSION_MODE_4K; break; */
1405         }
1406
1407         switch (tps & 0x3) {
1408         case 0:
1409                 fep->guard_interval = GUARD_INTERVAL_1_32;
1410                 break;
1411         case 1:
1412                 fep->guard_interval = GUARD_INTERVAL_1_16;
1413                 break;
1414         case 2:
1415                 fep->guard_interval = GUARD_INTERVAL_1_8;
1416                 break;
1417         case 3:
1418                 fep->guard_interval = GUARD_INTERVAL_1_4;
1419                 break;
1420         }
1421
1422         switch ((tps >> 14) & 0x3) {
1423         case 0:
1424                 fep->modulation = QPSK;
1425                 break;
1426         case 1:
1427                 fep->modulation = QAM_16;
1428                 break;
1429         case 2:
1430         default:
1431                 fep->modulation = QAM_64;
1432                 break;
1433         }
1434
1435         /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
1436         /* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */
1437
1438         fep->hierarchy = HIERARCHY_NONE;
1439         switch ((tps >> 5) & 0x7) {
1440         case 1:
1441                 fep->code_rate_HP = FEC_1_2;
1442                 break;
1443         case 2:
1444                 fep->code_rate_HP = FEC_2_3;
1445                 break;
1446         case 3:
1447                 fep->code_rate_HP = FEC_3_4;
1448                 break;
1449         case 5:
1450                 fep->code_rate_HP = FEC_5_6;
1451                 break;
1452         case 7:
1453         default:
1454                 fep->code_rate_HP = FEC_7_8;
1455                 break;
1456
1457         }
1458
1459         switch ((tps >> 2) & 0x7) {
1460         case 1:
1461                 fep->code_rate_LP = FEC_1_2;
1462                 break;
1463         case 2:
1464                 fep->code_rate_LP = FEC_2_3;
1465                 break;
1466         case 3:
1467                 fep->code_rate_LP = FEC_3_4;
1468                 break;
1469         case 5:
1470                 fep->code_rate_LP = FEC_5_6;
1471                 break;
1472         case 7:
1473         default:
1474                 fep->code_rate_LP = FEC_7_8;
1475                 break;
1476         }
1477
1478         /* native interleaver: (dib7000p_read_word(state, 464) >>  5) & 0x1 */
1479
1480         return 0;
1481 }
1482
1483 static int dib7000p_set_frontend(struct dvb_frontend *fe)
1484 {
1485         struct dtv_frontend_properties *fep = &fe->dtv_property_cache, tmp;
1486         struct dib7000p_state *state = fe->demodulator_priv;
1487         int time, ret;
1488
1489         if (state->version == SOC7090)
1490                 dib7090_set_diversity_in(fe, 0);
1491         else
1492                 dib7000p_set_output_mode(state, OUTMODE_HIGH_Z);
1493
1494         /* maybe the parameter has been changed */
1495         state->sfn_workaround_active = buggy_sfn_workaround;
1496
1497         if (fe->ops.tuner_ops.set_params)
1498                 fe->ops.tuner_ops.set_params(fe);
1499
1500         /* start up the AGC */
1501         state->agc_state = 0;
1502         do {
1503                 time = dib7000p_agc_startup(fe);
1504                 if (time != -1)
1505                         msleep(time);
1506         } while (time != -1);
1507
1508         if (fep->transmission_mode == TRANSMISSION_MODE_AUTO ||
1509                 fep->guard_interval == GUARD_INTERVAL_AUTO || fep->modulation == QAM_AUTO || fep->code_rate_HP == FEC_AUTO) {
1510                 int i = 800, found;
1511
1512                 tmp = *fep;
1513                 dib7000p_autosearch_start(fe);
1514                 do {
1515                         msleep(1);
1516                         found = dib7000p_autosearch_is_irq(fe);
1517                 } while (found == 0 && i--);
1518
1519                 dprintk("autosearch returns: %d", found);
1520                 if (found == 0 || found == 1)
1521                         return 0;
1522
1523                 dib7000p_get_frontend(fe, &tmp);
1524         }
1525
1526         ret = dib7000p_tune(fe);
1527
1528         /* make this a config parameter */
1529         if (state->version == SOC7090) {
1530                 dib7090_set_output_mode(fe, state->cfg.output_mode);
1531                 if (state->cfg.enMpegOutput == 0) {
1532                         dib7090_setDibTxMux(state, MPEG_ON_DIBTX);
1533                         dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
1534                 }
1535         } else
1536                 dib7000p_set_output_mode(state, state->cfg.output_mode);
1537
1538         return ret;
1539 }
1540
1541 static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t * stat)
1542 {
1543         struct dib7000p_state *state = fe->demodulator_priv;
1544         u16 lock = dib7000p_read_word(state, 509);
1545
1546         *stat = 0;
1547
1548         if (lock & 0x8000)
1549                 *stat |= FE_HAS_SIGNAL;
1550         if (lock & 0x3000)
1551                 *stat |= FE_HAS_CARRIER;
1552         if (lock & 0x0100)
1553                 *stat |= FE_HAS_VITERBI;
1554         if (lock & 0x0010)
1555                 *stat |= FE_HAS_SYNC;
1556         if ((lock & 0x0038) == 0x38)
1557                 *stat |= FE_HAS_LOCK;
1558
1559         return 0;
1560 }
1561
1562 static int dib7000p_read_ber(struct dvb_frontend *fe, u32 * ber)
1563 {
1564         struct dib7000p_state *state = fe->demodulator_priv;
1565         *ber = (dib7000p_read_word(state, 500) << 16) | dib7000p_read_word(state, 501);
1566         return 0;
1567 }
1568
1569 static int dib7000p_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
1570 {
1571         struct dib7000p_state *state = fe->demodulator_priv;
1572         *unc = dib7000p_read_word(state, 506);
1573         return 0;
1574 }
1575
1576 static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
1577 {
1578         struct dib7000p_state *state = fe->demodulator_priv;
1579         u16 val = dib7000p_read_word(state, 394);
1580         *strength = 65535 - val;
1581         return 0;
1582 }
1583
1584 static int dib7000p_read_snr(struct dvb_frontend *fe, u16 * snr)
1585 {
1586         struct dib7000p_state *state = fe->demodulator_priv;
1587         u16 val;
1588         s32 signal_mant, signal_exp, noise_mant, noise_exp;
1589         u32 result = 0;
1590
1591         val = dib7000p_read_word(state, 479);
1592         noise_mant = (val >> 4) & 0xff;
1593         noise_exp = ((val & 0xf) << 2);
1594         val = dib7000p_read_word(state, 480);
1595         noise_exp += ((val >> 14) & 0x3);
1596         if ((noise_exp & 0x20) != 0)
1597                 noise_exp -= 0x40;
1598
1599         signal_mant = (val >> 6) & 0xFF;
1600         signal_exp = (val & 0x3F);
1601         if ((signal_exp & 0x20) != 0)
1602                 signal_exp -= 0x40;
1603
1604         if (signal_mant != 0)
1605                 result = intlog10(2) * 10 * signal_exp + 10 * intlog10(signal_mant);
1606         else
1607                 result = intlog10(2) * 10 * signal_exp - 100;
1608
1609         if (noise_mant != 0)
1610                 result -= intlog10(2) * 10 * noise_exp + 10 * intlog10(noise_mant);
1611         else
1612                 result -= intlog10(2) * 10 * noise_exp - 100;
1613
1614         *snr = result / ((1 << 24) / 10);
1615         return 0;
1616 }
1617
1618 static int dib7000p_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
1619 {
1620         tune->min_delay_ms = 1000;
1621         return 0;
1622 }
1623
1624 static void dib7000p_release(struct dvb_frontend *demod)
1625 {
1626         struct dib7000p_state *st = demod->demodulator_priv;
1627         dibx000_exit_i2c_master(&st->i2c_master);
1628         i2c_del_adapter(&st->dib7090_tuner_adap);
1629         kfree(st);
1630 }
1631
1632 int dib7000pc_detection(struct i2c_adapter *i2c_adap)
1633 {
1634         u8 *tx, *rx;
1635         struct i2c_msg msg[2] = {
1636                 {.addr = 18 >> 1, .flags = 0, .len = 2},
1637                 {.addr = 18 >> 1, .flags = I2C_M_RD, .len = 2},
1638         };
1639         int ret = 0;
1640
1641         tx = kzalloc(2*sizeof(u8), GFP_KERNEL);
1642         if (!tx)
1643                 return -ENOMEM;
1644         rx = kzalloc(2*sizeof(u8), GFP_KERNEL);
1645         if (!rx) {
1646                 ret = -ENOMEM;
1647                 goto rx_memory_error;
1648         }
1649
1650         msg[0].buf = tx;
1651         msg[1].buf = rx;
1652
1653         tx[0] = 0x03;
1654         tx[1] = 0x00;
1655
1656         if (i2c_transfer(i2c_adap, msg, 2) == 2)
1657                 if (rx[0] == 0x01 && rx[1] == 0xb3) {
1658                         dprintk("-D-  DiB7000PC detected");
1659                         return 1;
1660                 }
1661
1662         msg[0].addr = msg[1].addr = 0x40;
1663
1664         if (i2c_transfer(i2c_adap, msg, 2) == 2)
1665                 if (rx[0] == 0x01 && rx[1] == 0xb3) {
1666                         dprintk("-D-  DiB7000PC detected");
1667                         return 1;
1668                 }
1669
1670         dprintk("-D-  DiB7000PC not detected");
1671
1672         kfree(rx);
1673 rx_memory_error:
1674         kfree(tx);
1675         return ret;
1676 }
1677 EXPORT_SYMBOL(dib7000pc_detection);
1678
1679 struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating)
1680 {
1681         struct dib7000p_state *st = demod->demodulator_priv;
1682         return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
1683 }
1684 EXPORT_SYMBOL(dib7000p_get_i2c_master);
1685
1686 int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
1687 {
1688         struct dib7000p_state *state = fe->demodulator_priv;
1689         u16 val = dib7000p_read_word(state, 235) & 0xffef;
1690         val |= (onoff & 0x1) << 4;
1691         dprintk("PID filter enabled %d", onoff);
1692         return dib7000p_write_word(state, 235, val);
1693 }
1694 EXPORT_SYMBOL(dib7000p_pid_filter_ctrl);
1695
1696 int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
1697 {
1698         struct dib7000p_state *state = fe->demodulator_priv;
1699         dprintk("PID filter: index %x, PID %d, OnOff %d", id, pid, onoff);
1700         return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0);
1701 }
1702 EXPORT_SYMBOL(dib7000p_pid_filter);
1703
1704 int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[])
1705 {
1706         struct dib7000p_state *dpst;
1707         int k = 0;
1708         u8 new_addr = 0;
1709
1710         dpst = kzalloc(sizeof(struct dib7000p_state), GFP_KERNEL);
1711         if (!dpst)
1712                 return -ENOMEM;
1713
1714         dpst->i2c_adap = i2c;
1715         mutex_init(&dpst->i2c_buffer_lock);
1716
1717         for (k = no_of_demods - 1; k >= 0; k--) {
1718                 dpst->cfg = cfg[k];
1719
1720                 /* designated i2c address */
1721                 if (cfg[k].default_i2c_addr != 0)
1722                         new_addr = cfg[k].default_i2c_addr + (k << 1);
1723                 else
1724                         new_addr = (0x40 + k) << 1;
1725                 dpst->i2c_addr = new_addr;
1726                 dib7000p_write_word(dpst, 1287, 0x0003);        /* sram lead in, rdy */
1727                 if (dib7000p_identify(dpst) != 0) {
1728                         dpst->i2c_addr = default_addr;
1729                         dib7000p_write_word(dpst, 1287, 0x0003);        /* sram lead in, rdy */
1730                         if (dib7000p_identify(dpst) != 0) {
1731                                 dprintk("DiB7000P #%d: not identified\n", k);
1732                                 kfree(dpst);
1733                                 return -EIO;
1734                         }
1735                 }
1736
1737                 /* start diversity to pull_down div_str - just for i2c-enumeration */
1738                 dib7000p_set_output_mode(dpst, OUTMODE_DIVERSITY);
1739
1740                 /* set new i2c address and force divstart */
1741                 dib7000p_write_word(dpst, 1285, (new_addr << 2) | 0x2);
1742
1743                 dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
1744         }
1745
1746         for (k = 0; k < no_of_demods; k++) {
1747                 dpst->cfg = cfg[k];
1748                 if (cfg[k].default_i2c_addr != 0)
1749                         dpst->i2c_addr = (cfg[k].default_i2c_addr + k) << 1;
1750                 else
1751                         dpst->i2c_addr = (0x40 + k) << 1;
1752
1753                 // unforce divstr
1754                 dib7000p_write_word(dpst, 1285, dpst->i2c_addr << 2);
1755
1756                 /* deactivate div - it was just for i2c-enumeration */
1757                 dib7000p_set_output_mode(dpst, OUTMODE_HIGH_Z);
1758         }
1759
1760         kfree(dpst);
1761         return 0;
1762 }
1763 EXPORT_SYMBOL(dib7000p_i2c_enumeration);
1764
1765 static const s32 lut_1000ln_mant[] = {
1766         6908, 6956, 7003, 7047, 7090, 7131, 7170, 7208, 7244, 7279, 7313, 7346, 7377, 7408, 7438, 7467, 7495, 7523, 7549, 7575, 7600
1767 };
1768
1769 static s32 dib7000p_get_adc_power(struct dvb_frontend *fe)
1770 {
1771         struct dib7000p_state *state = fe->demodulator_priv;
1772         u32 tmp_val = 0, exp = 0, mant = 0;
1773         s32 pow_i;
1774         u16 buf[2];
1775         u8 ix = 0;
1776
1777         buf[0] = dib7000p_read_word(state, 0x184);
1778         buf[1] = dib7000p_read_word(state, 0x185);
1779         pow_i = (buf[0] << 16) | buf[1];
1780         dprintk("raw pow_i = %d", pow_i);
1781
1782         tmp_val = pow_i;
1783         while (tmp_val >>= 1)
1784                 exp++;
1785
1786         mant = (pow_i * 1000 / (1 << exp));
1787         dprintk(" mant = %d exp = %d", mant / 1000, exp);
1788
1789         ix = (u8) ((mant - 1000) / 100);        /* index of the LUT */
1790         dprintk(" ix = %d", ix);
1791
1792         pow_i = (lut_1000ln_mant[ix] + 693 * (exp - 20) - 6908);
1793         pow_i = (pow_i << 8) / 1000;
1794         dprintk(" pow_i = %d", pow_i);
1795
1796         return pow_i;
1797 }
1798
1799 static int map_addr_to_serpar_number(struct i2c_msg *msg)
1800 {
1801         if ((msg->buf[0] <= 15))
1802                 msg->buf[0] -= 1;
1803         else if (msg->buf[0] == 17)
1804                 msg->buf[0] = 15;
1805         else if (msg->buf[0] == 16)
1806                 msg->buf[0] = 17;
1807         else if (msg->buf[0] == 19)
1808                 msg->buf[0] = 16;
1809         else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
1810                 msg->buf[0] -= 3;
1811         else if (msg->buf[0] == 28)
1812                 msg->buf[0] = 23;
1813         else
1814                 return -EINVAL;
1815         return 0;
1816 }
1817
1818 static int w7090p_tuner_write_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1819 {
1820         struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
1821         u8 n_overflow = 1;
1822         u16 i = 1000;
1823         u16 serpar_num = msg[0].buf[0];
1824
1825         while (n_overflow == 1 && i) {
1826                 n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
1827                 i--;
1828                 if (i == 0)
1829                         dprintk("Tuner ITF: write busy (overflow)");
1830         }
1831         dib7000p_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
1832         dib7000p_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
1833
1834         return num;
1835 }
1836
1837 static int w7090p_tuner_read_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1838 {
1839         struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
1840         u8 n_overflow = 1, n_empty = 1;
1841         u16 i = 1000;
1842         u16 serpar_num = msg[0].buf[0];
1843         u16 read_word;
1844
1845         while (n_overflow == 1 && i) {
1846                 n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
1847                 i--;
1848                 if (i == 0)
1849                         dprintk("TunerITF: read busy (overflow)");
1850         }
1851         dib7000p_write_word(state, 1985, (0 << 6) | (serpar_num & 0x3f));
1852
1853         i = 1000;
1854         while (n_empty == 1 && i) {
1855                 n_empty = dib7000p_read_word(state, 1984) & 0x1;
1856                 i--;
1857                 if (i == 0)
1858                         dprintk("TunerITF: read busy (empty)");
1859         }
1860         read_word = dib7000p_read_word(state, 1987);
1861         msg[1].buf[0] = (read_word >> 8) & 0xff;
1862         msg[1].buf[1] = (read_word) & 0xff;
1863
1864         return num;
1865 }
1866
1867 static int w7090p_tuner_rw_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1868 {
1869         if (map_addr_to_serpar_number(&msg[0]) == 0) {  /* else = Tuner regs to ignore : DIG_CFG, CTRL_RF_LT, PLL_CFG, PWM1_REG, ADCCLK, DIG_CFG_3; SLEEP_EN... */
1870                 if (num == 1) { /* write */
1871                         return w7090p_tuner_write_serpar(i2c_adap, msg, 1);
1872                 } else {        /* read */
1873                         return w7090p_tuner_read_serpar(i2c_adap, msg, 2);
1874                 }
1875         }
1876         return num;
1877 }
1878
1879 static int dib7090p_rw_on_apb(struct i2c_adapter *i2c_adap,
1880                 struct i2c_msg msg[], int num, u16 apb_address)
1881 {
1882         struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
1883         u16 word;
1884
1885         if (num == 1) {         /* write */
1886                 dib7000p_write_word(state, apb_address, ((msg[0].buf[1] << 8) | (msg[0].buf[2])));
1887         } else {
1888                 word = dib7000p_read_word(state, apb_address);
1889                 msg[1].buf[0] = (word >> 8) & 0xff;
1890                 msg[1].buf[1] = (word) & 0xff;
1891         }
1892
1893         return num;
1894 }
1895
1896 static int dib7090_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1897 {
1898         struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
1899
1900         u16 apb_address = 0, word;
1901         int i = 0;
1902         switch (msg[0].buf[0]) {
1903         case 0x12:
1904                 apb_address = 1920;
1905                 break;
1906         case 0x14:
1907                 apb_address = 1921;
1908                 break;
1909         case 0x24:
1910                 apb_address = 1922;
1911                 break;
1912         case 0x1a:
1913                 apb_address = 1923;
1914                 break;
1915         case 0x22:
1916                 apb_address = 1924;
1917                 break;
1918         case 0x33:
1919                 apb_address = 1926;
1920                 break;
1921         case 0x34:
1922                 apb_address = 1927;
1923                 break;
1924         case 0x35:
1925                 apb_address = 1928;
1926                 break;
1927         case 0x36:
1928                 apb_address = 1929;
1929                 break;
1930         case 0x37:
1931                 apb_address = 1930;
1932                 break;
1933         case 0x38:
1934                 apb_address = 1931;
1935                 break;
1936         case 0x39:
1937                 apb_address = 1932;
1938                 break;
1939         case 0x2a:
1940                 apb_address = 1935;
1941                 break;
1942         case 0x2b:
1943                 apb_address = 1936;
1944                 break;
1945         case 0x2c:
1946                 apb_address = 1937;
1947                 break;
1948         case 0x2d:
1949                 apb_address = 1938;
1950                 break;
1951         case 0x2e:
1952                 apb_address = 1939;
1953                 break;
1954         case 0x2f:
1955                 apb_address = 1940;
1956                 break;
1957         case 0x30:
1958                 apb_address = 1941;
1959                 break;
1960         case 0x31:
1961                 apb_address = 1942;
1962                 break;
1963         case 0x32:
1964                 apb_address = 1943;
1965                 break;
1966         case 0x3e:
1967                 apb_address = 1944;
1968                 break;
1969         case 0x3f:
1970                 apb_address = 1945;
1971                 break;
1972         case 0x40:
1973                 apb_address = 1948;
1974                 break;
1975         case 0x25:
1976                 apb_address = 914;
1977                 break;
1978         case 0x26:
1979                 apb_address = 915;
1980                 break;
1981         case 0x27:
1982                 apb_address = 917;
1983                 break;
1984         case 0x28:
1985                 apb_address = 916;
1986                 break;
1987         case 0x1d:
1988                 i = ((dib7000p_read_word(state, 72) >> 12) & 0x3);
1989                 word = dib7000p_read_word(state, 384 + i);
1990                 msg[1].buf[0] = (word >> 8) & 0xff;
1991                 msg[1].buf[1] = (word) & 0xff;
1992                 return num;
1993         case 0x1f:
1994                 if (num == 1) { /* write */
1995                         word = (u16) ((msg[0].buf[1] << 8) | msg[0].buf[2]);
1996                         word &= 0x3;
1997                         word = (dib7000p_read_word(state, 72) & ~(3 << 12)) | (word << 12);
1998                         dib7000p_write_word(state, 72, word);   /* Set the proper input */
1999                         return num;
2000                 }
2001         }
2002
2003         if (apb_address != 0)   /* R/W acces via APB */
2004                 return dib7090p_rw_on_apb(i2c_adap, msg, num, apb_address);
2005         else                    /* R/W access via SERPAR  */
2006                 return w7090p_tuner_rw_serpar(i2c_adap, msg, num);
2007
2008         return 0;
2009 }
2010
2011 static u32 dib7000p_i2c_func(struct i2c_adapter *adapter)
2012 {
2013         return I2C_FUNC_I2C;
2014 }
2015
2016 static struct i2c_algorithm dib7090_tuner_xfer_algo = {
2017         .master_xfer = dib7090_tuner_xfer,
2018         .functionality = dib7000p_i2c_func,
2019 };
2020
2021 struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe)
2022 {
2023         struct dib7000p_state *st = fe->demodulator_priv;
2024         return &st->dib7090_tuner_adap;
2025 }
2026 EXPORT_SYMBOL(dib7090_get_i2c_tuner);
2027
2028 static int dib7090_host_bus_drive(struct dib7000p_state *state, u8 drive)
2029 {
2030         u16 reg;
2031
2032         /* drive host bus 2, 3, 4 */
2033         reg = dib7000p_read_word(state, 1798) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
2034         reg |= (drive << 12) | (drive << 6) | drive;
2035         dib7000p_write_word(state, 1798, reg);
2036
2037         /* drive host bus 5,6 */
2038         reg = dib7000p_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
2039         reg |= (drive << 8) | (drive << 2);
2040         dib7000p_write_word(state, 1799, reg);
2041
2042         /* drive host bus 7, 8, 9 */
2043         reg = dib7000p_read_word(state, 1800) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
2044         reg |= (drive << 12) | (drive << 6) | drive;
2045         dib7000p_write_word(state, 1800, reg);
2046
2047         /* drive host bus 10, 11 */
2048         reg = dib7000p_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
2049         reg |= (drive << 8) | (drive << 2);
2050         dib7000p_write_word(state, 1801, reg);
2051
2052         /* drive host bus 12, 13, 14 */
2053         reg = dib7000p_read_word(state, 1802) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
2054         reg |= (drive << 12) | (drive << 6) | drive;
2055         dib7000p_write_word(state, 1802, reg);
2056
2057         return 0;
2058 }
2059
2060 static u32 dib7090_calcSyncFreq(u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 syncSize)
2061 {
2062         u32 quantif = 3;
2063         u32 nom = (insertExtSynchro * P_Kin + syncSize);
2064         u32 denom = P_Kout;
2065         u32 syncFreq = ((nom << quantif) / denom);
2066
2067         if ((syncFreq & ((1 << quantif) - 1)) != 0)
2068                 syncFreq = (syncFreq >> quantif) + 1;
2069         else
2070                 syncFreq = (syncFreq >> quantif);
2071
2072         if (syncFreq != 0)
2073                 syncFreq = syncFreq - 1;
2074
2075         return syncFreq;
2076 }
2077
2078 static int dib7090_cfg_DibTx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 synchroMode, u32 syncWord, u32 syncSize)
2079 {
2080         dprintk("Configure DibStream Tx");
2081
2082         dib7000p_write_word(state, 1615, 1);
2083         dib7000p_write_word(state, 1603, P_Kin);
2084         dib7000p_write_word(state, 1605, P_Kout);
2085         dib7000p_write_word(state, 1606, insertExtSynchro);
2086         dib7000p_write_word(state, 1608, synchroMode);
2087         dib7000p_write_word(state, 1609, (syncWord >> 16) & 0xffff);
2088         dib7000p_write_word(state, 1610, syncWord & 0xffff);
2089         dib7000p_write_word(state, 1612, syncSize);
2090         dib7000p_write_word(state, 1615, 0);
2091
2092         return 0;
2093 }
2094
2095 static int dib7090_cfg_DibRx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 synchroMode, u32 insertExtSynchro, u32 syncWord, u32 syncSize,
2096                 u32 dataOutRate)
2097 {
2098         u32 syncFreq;
2099
2100         dprintk("Configure DibStream Rx");
2101         if ((P_Kin != 0) && (P_Kout != 0)) {
2102                 syncFreq = dib7090_calcSyncFreq(P_Kin, P_Kout, insertExtSynchro, syncSize);
2103                 dib7000p_write_word(state, 1542, syncFreq);
2104         }
2105         dib7000p_write_word(state, 1554, 1);
2106         dib7000p_write_word(state, 1536, P_Kin);
2107         dib7000p_write_word(state, 1537, P_Kout);
2108         dib7000p_write_word(state, 1539, synchroMode);
2109         dib7000p_write_word(state, 1540, (syncWord >> 16) & 0xffff);
2110         dib7000p_write_word(state, 1541, syncWord & 0xffff);
2111         dib7000p_write_word(state, 1543, syncSize);
2112         dib7000p_write_word(state, 1544, dataOutRate);
2113         dib7000p_write_word(state, 1554, 0);
2114
2115         return 0;
2116 }
2117
2118 static void dib7090_enMpegMux(struct dib7000p_state *state, int onoff)
2119 {
2120         u16 reg_1287 = dib7000p_read_word(state, 1287);
2121
2122         switch (onoff) {
2123         case 1:
2124                         reg_1287 &= ~(1<<7);
2125                         break;
2126         case 0:
2127                         reg_1287 |= (1<<7);
2128                         break;
2129         }
2130
2131         dib7000p_write_word(state, 1287, reg_1287);
2132 }
2133
2134 static void dib7090_configMpegMux(struct dib7000p_state *state,
2135                 u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
2136 {
2137         dprintk("Enable Mpeg mux");
2138
2139         dib7090_enMpegMux(state, 0);
2140
2141         /* If the input mode is MPEG do not divide the serial clock */
2142         if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))
2143                 enSerialClkDiv2 = 0;
2144
2145         dib7000p_write_word(state, 1287, ((pulseWidth & 0x1f) << 2)
2146                         | ((enSerialMode & 0x1) << 1)
2147                         | (enSerialClkDiv2 & 0x1));
2148
2149         dib7090_enMpegMux(state, 1);
2150 }
2151
2152 static void dib7090_setDibTxMux(struct dib7000p_state *state, int mode)
2153 {
2154         u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 7);
2155
2156         switch (mode) {
2157         case MPEG_ON_DIBTX:
2158                         dprintk("SET MPEG ON DIBSTREAM TX");
2159                         dib7090_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
2160                         reg_1288 |= (1<<9);
2161                         break;
2162         case DIV_ON_DIBTX:
2163                         dprintk("SET DIV_OUT ON DIBSTREAM TX");
2164                         dib7090_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
2165                         reg_1288 |= (1<<8);
2166                         break;
2167         case ADC_ON_DIBTX:
2168                         dprintk("SET ADC_OUT ON DIBSTREAM TX");
2169                         dib7090_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
2170                         reg_1288 |= (1<<7);
2171                         break;
2172         default:
2173                         break;
2174         }
2175         dib7000p_write_word(state, 1288, reg_1288);
2176 }
2177
2178 static void dib7090_setHostBusMux(struct dib7000p_state *state, int mode)
2179 {
2180         u16 reg_1288 = dib7000p_read_word(state, 1288) & ~(0x7 << 4);
2181
2182         switch (mode) {
2183         case DEMOUT_ON_HOSTBUS:
2184                         dprintk("SET DEM OUT OLD INTERF ON HOST BUS");
2185                         dib7090_enMpegMux(state, 0);
2186                         reg_1288 |= (1<<6);
2187                         break;
2188         case DIBTX_ON_HOSTBUS:
2189                         dprintk("SET DIBSTREAM TX ON HOST BUS");
2190                         dib7090_enMpegMux(state, 0);
2191                         reg_1288 |= (1<<5);
2192                         break;
2193         case MPEG_ON_HOSTBUS:
2194                         dprintk("SET MPEG MUX ON HOST BUS");
2195                         reg_1288 |= (1<<4);
2196                         break;
2197         default:
2198                         break;
2199         }
2200         dib7000p_write_word(state, 1288, reg_1288);
2201 }
2202
2203 int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff)
2204 {
2205         struct dib7000p_state *state = fe->demodulator_priv;
2206         u16 reg_1287;
2207
2208         switch (onoff) {
2209         case 0: /* only use the internal way - not the diversity input */
2210                         dprintk("%s mode OFF : by default Enable Mpeg INPUT", __func__);
2211                         dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);
2212
2213                         /* Do not divide the serial clock of MPEG MUX */
2214                         /* in SERIAL MODE in case input mode MPEG is used */
2215                         reg_1287 = dib7000p_read_word(state, 1287);
2216                         /* enSerialClkDiv2 == 1 ? */
2217                         if ((reg_1287 & 0x1) == 1) {
2218                                 /* force enSerialClkDiv2 = 0 */
2219                                 reg_1287 &= ~0x1;
2220                                 dib7000p_write_word(state, 1287, reg_1287);
2221                         }
2222                         state->input_mode_mpeg = 1;
2223                         break;
2224         case 1: /* both ways */
2225         case 2: /* only the diversity input */
2226                         dprintk("%s ON : Enable diversity INPUT", __func__);
2227                         dib7090_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
2228                         state->input_mode_mpeg = 0;
2229                         break;
2230         }
2231
2232         dib7000p_set_diversity_in(&state->demod, onoff);
2233         return 0;
2234 }
2235
2236 static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode)
2237 {
2238         struct dib7000p_state *state = fe->demodulator_priv;
2239
2240         u16 outreg, smo_mode, fifo_threshold;
2241         u8 prefer_mpeg_mux_use = 1;
2242         int ret = 0;
2243
2244         dib7090_host_bus_drive(state, 1);
2245
2246         fifo_threshold = 1792;
2247         smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
2248         outreg = dib7000p_read_word(state, 1286) & ~((1 << 10) | (0x7 << 6) | (1 << 1));
2249
2250         switch (mode) {
2251         case OUTMODE_HIGH_Z:
2252                 outreg = 0;
2253                 break;
2254
2255         case OUTMODE_MPEG2_SERIAL:
2256                 if (prefer_mpeg_mux_use) {
2257                         dprintk("setting output mode TS_SERIAL using Mpeg Mux");
2258                         dib7090_configMpegMux(state, 3, 1, 1);
2259                         dib7090_setHostBusMux(state, MPEG_ON_HOSTBUS);
2260                 } else {/* Use Smooth block */
2261                         dprintk("setting output mode TS_SERIAL using Smooth bloc");
2262                         dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
2263                         outreg |= (2<<6) | (0 << 1);
2264                 }
2265                 break;
2266
2267         case OUTMODE_MPEG2_PAR_GATED_CLK:
2268                 if (prefer_mpeg_mux_use) {
2269                         dprintk("setting output mode TS_PARALLEL_GATED using Mpeg Mux");
2270                         dib7090_configMpegMux(state, 2, 0, 0);
2271                         dib7090_setHostBusMux(state, MPEG_ON_HOSTBUS);
2272                 } else { /* Use Smooth block */
2273                         dprintk("setting output mode TS_PARALLEL_GATED using Smooth block");
2274                         dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
2275                         outreg |= (0<<6);
2276                 }
2277                 break;
2278
2279         case OUTMODE_MPEG2_PAR_CONT_CLK:        /* Using Smooth block only */
2280                 dprintk("setting output mode TS_PARALLEL_CONT using Smooth block");
2281                 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
2282                 outreg |= (1<<6);
2283                 break;
2284
2285         case OUTMODE_MPEG2_FIFO:        /* Using Smooth block because not supported by new Mpeg Mux bloc */
2286                 dprintk("setting output mode TS_FIFO using Smooth block");
2287                 dib7090_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
2288                 outreg |= (5<<6);
2289                 smo_mode |= (3 << 1);
2290                 fifo_threshold = 512;
2291                 break;
2292
2293         case OUTMODE_DIVERSITY:
2294                 dprintk("setting output mode MODE_DIVERSITY");
2295                 dib7090_setDibTxMux(state, DIV_ON_DIBTX);
2296                 dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
2297                 break;
2298
2299         case OUTMODE_ANALOG_ADC:
2300                 dprintk("setting output mode MODE_ANALOG_ADC");
2301                 dib7090_setDibTxMux(state, ADC_ON_DIBTX);
2302                 dib7090_setHostBusMux(state, DIBTX_ON_HOSTBUS);
2303                 break;
2304         }
2305         if (mode != OUTMODE_HIGH_Z)
2306                 outreg |= (1 << 10);
2307
2308         if (state->cfg.output_mpeg2_in_188_bytes)
2309                 smo_mode |= (1 << 5);
2310
2311         ret |= dib7000p_write_word(state, 235, smo_mode);
2312         ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
2313         ret |= dib7000p_write_word(state, 1286, outreg);
2314
2315         return ret;
2316 }
2317
2318 int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff)
2319 {
2320         struct dib7000p_state *state = fe->demodulator_priv;
2321         u16 en_cur_state;
2322
2323         dprintk("sleep dib7090: %d", onoff);
2324
2325         en_cur_state = dib7000p_read_word(state, 1922);
2326
2327         if (en_cur_state > 0xff)
2328                 state->tuner_enable = en_cur_state;
2329
2330         if (onoff)
2331                 en_cur_state &= 0x00ff;
2332         else {
2333                 if (state->tuner_enable != 0)
2334                         en_cur_state = state->tuner_enable;
2335         }
2336
2337         dib7000p_write_word(state, 1922, en_cur_state);
2338
2339         return 0;
2340 }
2341 EXPORT_SYMBOL(dib7090_tuner_sleep);
2342
2343 int dib7090_get_adc_power(struct dvb_frontend *fe)
2344 {
2345         return dib7000p_get_adc_power(fe);
2346 }
2347 EXPORT_SYMBOL(dib7090_get_adc_power);
2348
2349 int dib7090_slave_reset(struct dvb_frontend *fe)
2350 {
2351         struct dib7000p_state *state = fe->demodulator_priv;
2352         u16 reg;
2353
2354         reg = dib7000p_read_word(state, 1794);
2355         dib7000p_write_word(state, 1794, reg | (4 << 12));
2356
2357         dib7000p_write_word(state, 1032, 0xffff);
2358         return 0;
2359 }
2360 EXPORT_SYMBOL(dib7090_slave_reset);
2361
2362 static struct dvb_frontend_ops dib7000p_ops;
2363 struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg)
2364 {
2365         struct dvb_frontend *demod;
2366         struct dib7000p_state *st;
2367         st = kzalloc(sizeof(struct dib7000p_state), GFP_KERNEL);
2368         if (st == NULL)
2369                 return NULL;
2370
2371         memcpy(&st->cfg, cfg, sizeof(struct dib7000p_config));
2372         st->i2c_adap = i2c_adap;
2373         st->i2c_addr = i2c_addr;
2374         st->gpio_val = cfg->gpio_val;
2375         st->gpio_dir = cfg->gpio_dir;
2376
2377         /* Ensure the output mode remains at the previous default if it's
2378          * not specifically set by the caller.
2379          */
2380         if ((st->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
2381                 st->cfg.output_mode = OUTMODE_MPEG2_FIFO;
2382
2383         demod = &st->demod;
2384         demod->demodulator_priv = st;
2385         memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops));
2386         mutex_init(&st->i2c_buffer_lock);
2387
2388         dib7000p_write_word(st, 1287, 0x0003);  /* sram lead in, rdy */
2389
2390         if (dib7000p_identify(st) != 0)
2391                 goto error;
2392
2393         st->version = dib7000p_read_word(st, 897);
2394
2395         /* FIXME: make sure the dev.parent field is initialized, or else
2396            request_firmware() will hit an OOPS (this should be moved somewhere
2397            more common) */
2398         st->i2c_master.gated_tuner_i2c_adap.dev.parent = i2c_adap->dev.parent;
2399
2400         /* FIXME: make sure the dev.parent field is initialized, or else
2401            request_firmware() will hit an OOPS (this should be moved somewhere
2402            more common) */
2403         st->i2c_master.gated_tuner_i2c_adap.dev.parent = i2c_adap->dev.parent;
2404
2405         dibx000_init_i2c_master(&st->i2c_master, DIB7000P, st->i2c_adap, st->i2c_addr);
2406
2407         /* init 7090 tuner adapter */
2408         strncpy(st->dib7090_tuner_adap.name, "DiB7090 tuner interface", sizeof(st->dib7090_tuner_adap.name));
2409         st->dib7090_tuner_adap.algo = &dib7090_tuner_xfer_algo;
2410         st->dib7090_tuner_adap.algo_data = NULL;
2411         st->dib7090_tuner_adap.dev.parent = st->i2c_adap->dev.parent;
2412         i2c_set_adapdata(&st->dib7090_tuner_adap, st);
2413         i2c_add_adapter(&st->dib7090_tuner_adap);
2414
2415         dib7000p_demod_reset(st);
2416
2417         if (st->version == SOC7090) {
2418                 dib7090_set_output_mode(demod, st->cfg.output_mode);
2419                 dib7090_set_diversity_in(demod, 0);
2420         }
2421
2422         return demod;
2423
2424 error:
2425         kfree(st);
2426         return NULL;
2427 }
2428 EXPORT_SYMBOL(dib7000p_attach);
2429
2430 static struct dvb_frontend_ops dib7000p_ops = {
2431         .delsys = { SYS_DVBT },
2432         .info = {
2433                  .name = "DiBcom 7000PC",
2434                  .type = FE_OFDM,
2435                  .frequency_min = 44250000,
2436                  .frequency_max = 867250000,
2437                  .frequency_stepsize = 62500,
2438                  .caps = FE_CAN_INVERSION_AUTO |
2439                  FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2440                  FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2441                  FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
2442                  FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
2443                  },
2444
2445         .release = dib7000p_release,
2446
2447         .init = dib7000p_wakeup,
2448         .sleep = dib7000p_sleep,
2449
2450         .set_frontend = dib7000p_set_frontend,
2451         .get_tune_settings = dib7000p_fe_get_tune_settings,
2452         .get_frontend = dib7000p_get_frontend,
2453
2454         .read_status = dib7000p_read_status,
2455         .read_ber = dib7000p_read_ber,
2456         .read_signal_strength = dib7000p_read_signal_strength,
2457         .read_snr = dib7000p_read_snr,
2458         .read_ucblocks = dib7000p_read_unc_blocks,
2459 };
2460
2461 MODULE_AUTHOR("Olivier Grenie <ogrenie@dibcom.fr>");
2462 MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
2463 MODULE_DESCRIPTION("Driver for the DiBcom 7000PC COFDM demodulator");
2464 MODULE_LICENSE("GPL");