Pileus Git - ~andy/linux/blob - drivers/irqchip/irq-mmp.c

   1 /*
   2  *  linux/arch/arm/mach-mmp/irq.c
   3  *
   4  *  Generic IRQ handling, GPIO IRQ demultiplexing, etc.
   5  *  Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
   6  *
   7  *  Author:     Bin Yang <bin.yang@marvell.com>
   8  *              Haojian Zhuang <haojian.zhuang@gmail.com>
   9  *
  10  *  This program is free software; you can redistribute it and/or modify
  11  *  it under the terms of the GNU General Public License version 2 as
  12  *  published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/irq.h>
  18 #include <linux/irqdomain.h>
  19 #include <linux/io.h>
  20 #include <linux/ioport.h>
  21 #include <linux/of_address.h>
  22 #include <linux/of_irq.h>
  23
  24 #include <asm/exception.h>
  25 #include <asm/mach/irq.h>
  26
  27 #include "irqchip.h"
  28
  29 #define MAX_ICU_NR              16
  30
  31 #define PJ1_INT_SEL             0x10c
  32 #define PJ4_INT_SEL             0x104
  33
  34 /* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */
  35 #define SEL_INT_PENDING         (1 << 6)
  36 #define SEL_INT_NUM_MASK        0x3f
  37
  38 struct icu_chip_data {
  39         int                     nr_irqs;
  40         unsigned int            virq_base;
  41         unsigned int            cascade_irq;
  42         void __iomem            *reg_status;
  43         void __iomem            *reg_mask;
  44         unsigned int            conf_enable;
  45         unsigned int            conf_disable;
  46         unsigned int            conf_mask;
  47         unsigned int            clr_mfp_irq_base;
  48         unsigned int            clr_mfp_hwirq;
  49         struct irq_domain       *domain;
  50 };
  51
  52 struct mmp_intc_conf {
  53         unsigned int    conf_enable;
  54         unsigned int    conf_disable;
  55         unsigned int    conf_mask;
  56 };
  57
  58 static void __iomem *mmp_icu_base;
  59 static struct icu_chip_data icu_data[MAX_ICU_NR];
  60 static int max_icu_nr;
  61
  62 extern void mmp2_clear_pmic_int(void);
  63
  64 static void icu_mask_ack_irq(struct irq_data *d)
  65 {
  66         struct irq_domain *domain = d->domain;
  67         struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
  68         int hwirq;
  69         u32 r;
  70
  71         hwirq = d->irq - data->virq_base;
  72         if (data == &icu_data[0]) {
  73                 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
  74                 r &= ~data->conf_mask;
  75                 r |= data->conf_disable;
  76                 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
  77         } else {
  78 #ifdef CONFIG_CPU_MMP2
  79                 if ((data->virq_base == data->clr_mfp_irq_base)
  80                         && (hwirq == data->clr_mfp_hwirq))
  81                         mmp2_clear_pmic_int();
  82 #endif
  83                 r = readl_relaxed(data->reg_mask) | (1 << hwirq);
  84                 writel_relaxed(r, data->reg_mask);
  85         }
  86 }
  87
  88 static void icu_mask_irq(struct irq_data *d)
  89 {
  90         struct irq_domain *domain = d->domain;
  91         struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
  92         int hwirq;
  93         u32 r;
  94
  95         hwirq = d->irq - data->virq_base;
  96         if (data == &icu_data[0]) {
  97                 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
  98                 r &= ~data->conf_mask;
  99                 r |= data->conf_disable;
 100                 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
 101         } else {
 102                 r = readl_relaxed(data->reg_mask) | (1 << hwirq);
 103                 writel_relaxed(r, data->reg_mask);
 104         }
 105 }
 106
 107 static void icu_unmask_irq(struct irq_data *d)
 108 {
 109         struct irq_domain *domain = d->domain;
 110         struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
 111         int hwirq;
 112         u32 r;
 113
 114         hwirq = d->irq - data->virq_base;
 115         if (data == &icu_data[0]) {
 116                 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
 117                 r &= ~data->conf_mask;
 118                 r |= data->conf_enable;
 119                 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
 120         } else {
 121                 r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
 122                 writel_relaxed(r, data->reg_mask);
 123         }
 124 }
 125
 126 struct irq_chip icu_irq_chip = {
 127         .name           = "icu_irq",
 128         .irq_mask       = icu_mask_irq,
 129         .irq_mask_ack   = icu_mask_ack_irq,
 130         .irq_unmask     = icu_unmask_irq,
 131 };
 132
 133 static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
 134 {
 135         struct irq_domain *domain;
 136         struct icu_chip_data *data;
 137         int i;
 138         unsigned long mask, status, n;
 139
 140         for (i = 1; i < max_icu_nr; i++) {
 141                 if (irq == icu_data[i].cascade_irq) {
 142                         domain = icu_data[i].domain;
 143                         data = (struct icu_chip_data *)domain->host_data;
 144                         break;
 145                 }
 146         }
 147         if (i >= max_icu_nr) {
 148                 pr_err("Spurious irq %d in MMP INTC\n", irq);
 149                 return;
 150         }
 151
 152         mask = readl_relaxed(data->reg_mask);
 153         while (1) {
 154                 status = readl_relaxed(data->reg_status) & ~mask;
 155                 if (status == 0)
 156                         break;
 157                 for_each_set_bit(n, &status, BITS_PER_LONG) {
 158                         generic_handle_irq(icu_data[i].virq_base + n);
 159                 }
 160         }
 161 }
 162
 163 static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
 164                               irq_hw_number_t hw)
 165 {
 166         irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
 167         set_irq_flags(irq, IRQF_VALID);
 168         return 0;
 169 }
 170
 171 static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
 172                                 const u32 *intspec, unsigned int intsize,
 173                                 unsigned long *out_hwirq,
 174                                 unsigned int *out_type)
 175 {
 176         *out_hwirq = intspec[0];
 177         return 0;
 178 }
 179
 180 const struct irq_domain_ops mmp_irq_domain_ops = {
 181         .map            = mmp_irq_domain_map,
 182         .xlate          = mmp_irq_domain_xlate,
 183 };
 184
 185 static struct mmp_intc_conf mmp_conf = {
 186         .conf_enable    = 0x51,
 187         .conf_disable   = 0x0,
 188         .conf_mask      = 0x7f,
 189 };
 190
 191 static struct mmp_intc_conf mmp2_conf = {
 192         .conf_enable    = 0x20,
 193         .conf_disable   = 0x0,
 194         .conf_mask      = 0x7f,
 195 };
 196
 197 static asmlinkage void __exception_irq_entry
 198 mmp_handle_irq(struct pt_regs *regs)
 199 {
 200         int irq, hwirq;
 201
 202         hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL);
 203         if (!(hwirq & SEL_INT_PENDING))
 204                 return;
 205         hwirq &= SEL_INT_NUM_MASK;
 206         irq = irq_find_mapping(icu_data[0].domain, hwirq);
 207         handle_IRQ(irq, regs);
 208 }
 209
 210 static asmlinkage void __exception_irq_entry
 211 mmp2_handle_irq(struct pt_regs *regs)
 212 {
 213         int irq, hwirq;
 214
 215         hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL);
 216         if (!(hwirq & SEL_INT_PENDING))
 217                 return;
 218         hwirq &= SEL_INT_NUM_MASK;
 219         irq = irq_find_mapping(icu_data[0].domain, hwirq);
 220         handle_IRQ(irq, regs);
 221 }
 222
 223 /* MMP (ARMv5) */
 224 void __init icu_init_irq(void)
 225 {
 226         int irq;
 227
 228         max_icu_nr = 1;
 229         mmp_icu_base = ioremap(0xd4282000, 0x1000);
 230         icu_data[0].conf_enable = mmp_conf.conf_enable;
 231         icu_data[0].conf_disable = mmp_conf.conf_disable;
 232         icu_data[0].conf_mask = mmp_conf.conf_mask;
 233         icu_data[0].nr_irqs = 64;
 234         icu_data[0].virq_base = 0;
 235         icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
 236                                                    &irq_domain_simple_ops,
 237                                                    &icu_data[0]);
 238         for (irq = 0; irq < 64; irq++) {
 239                 icu_mask_irq(irq_get_irq_data(irq));
 240                 irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
 241                 set_irq_flags(irq, IRQF_VALID);
 242         }
 243         irq_set_default_host(icu_data[0].domain);
 244         set_handle_irq(mmp_handle_irq);
 245 }
 246
 247 /* MMP2 (ARMv7) */
 248 void __init mmp2_init_icu(void)
 249 {
 250         int irq, end;
 251
 252         max_icu_nr = 8;
 253         mmp_icu_base = ioremap(0xd4282000, 0x1000);
 254         icu_data[0].conf_enable = mmp2_conf.conf_enable;
 255         icu_data[0].conf_disable = mmp2_conf.conf_disable;
 256         icu_data[0].conf_mask = mmp2_conf.conf_mask;
 257         icu_data[0].nr_irqs = 64;
 258         icu_data[0].virq_base = 0;
 259         icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
 260                                                    &irq_domain_simple_ops,
 261                                                    &icu_data[0]);
 262         icu_data[1].reg_status = mmp_icu_base + 0x150;
 263         icu_data[1].reg_mask = mmp_icu_base + 0x168;
 264         icu_data[1].clr_mfp_irq_base = icu_data[0].virq_base +
 265                                 icu_data[0].nr_irqs;
 266         icu_data[1].clr_mfp_hwirq = 1;          /* offset to IRQ_MMP2_PMIC_BASE */
 267         icu_data[1].nr_irqs = 2;
 268         icu_data[1].cascade_irq = 4;
 269         icu_data[1].virq_base = icu_data[0].virq_base + icu_data[0].nr_irqs;
 270         icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
 271                                                    icu_data[1].virq_base, 0,
 272                                                    &irq_domain_simple_ops,
 273                                                    &icu_data[1]);
 274         icu_data[2].reg_status = mmp_icu_base + 0x154;
 275         icu_data[2].reg_mask = mmp_icu_base + 0x16c;
 276         icu_data[2].nr_irqs = 2;
 277         icu_data[2].cascade_irq = 5;
 278         icu_data[2].virq_base = icu_data[1].virq_base + icu_data[1].nr_irqs;
 279         icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
 280                                                    icu_data[2].virq_base, 0,
 281                                                    &irq_domain_simple_ops,
 282                                                    &icu_data[2]);
 283         icu_data[3].reg_status = mmp_icu_base + 0x180;
 284         icu_data[3].reg_mask = mmp_icu_base + 0x17c;
 285         icu_data[3].nr_irqs = 3;
 286         icu_data[3].cascade_irq = 9;
 287         icu_data[3].virq_base = icu_data[2].virq_base + icu_data[2].nr_irqs;
 288         icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
 289                                                    icu_data[3].virq_base, 0,
 290                                                    &irq_domain_simple_ops,
 291                                                    &icu_data[3]);
 292         icu_data[4].reg_status = mmp_icu_base + 0x158;
 293         icu_data[4].reg_mask = mmp_icu_base + 0x170;
 294         icu_data[4].nr_irqs = 5;
 295         icu_data[4].cascade_irq = 17;
 296         icu_data[4].virq_base = icu_data[3].virq_base + icu_data[3].nr_irqs;
 297         icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
 298                                                    icu_data[4].virq_base, 0,
 299                                                    &irq_domain_simple_ops,
 300                                                    &icu_data[4]);
 301         icu_data[5].reg_status = mmp_icu_base + 0x15c;
 302         icu_data[5].reg_mask = mmp_icu_base + 0x174;
 303         icu_data[5].nr_irqs = 15;
 304         icu_data[5].cascade_irq = 35;
 305         icu_data[5].virq_base = icu_data[4].virq_base + icu_data[4].nr_irqs;
 306         icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
 307                                                    icu_data[5].virq_base, 0,
 308                                                    &irq_domain_simple_ops,
 309                                                    &icu_data[5]);
 310         icu_data[6].reg_status = mmp_icu_base + 0x160;
 311         icu_data[6].reg_mask = mmp_icu_base + 0x178;
 312         icu_data[6].nr_irqs = 2;
 313         icu_data[6].cascade_irq = 51;
 314         icu_data[6].virq_base = icu_data[5].virq_base + icu_data[5].nr_irqs;
 315         icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
 316                                                    icu_data[6].virq_base, 0,
 317                                                    &irq_domain_simple_ops,
 318                                                    &icu_data[6]);
 319         icu_data[7].reg_status = mmp_icu_base + 0x188;
 320         icu_data[7].reg_mask = mmp_icu_base + 0x184;
 321         icu_data[7].nr_irqs = 2;
 322         icu_data[7].cascade_irq = 55;
 323         icu_data[7].virq_base = icu_data[6].virq_base + icu_data[6].nr_irqs;
 324         icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
 325                                                    icu_data[7].virq_base, 0,
 326                                                    &irq_domain_simple_ops,
 327                                                    &icu_data[7]);
 328         end = icu_data[7].virq_base + icu_data[7].nr_irqs;
 329         for (irq = 0; irq < end; irq++) {
 330                 icu_mask_irq(irq_get_irq_data(irq));
 331                 if (irq == icu_data[1].cascade_irq ||
 332                     irq == icu_data[2].cascade_irq ||
 333                     irq == icu_data[3].cascade_irq ||
 334                     irq == icu_data[4].cascade_irq ||
 335                     irq == icu_data[5].cascade_irq ||
 336                     irq == icu_data[6].cascade_irq ||
 337                     irq == icu_data[7].cascade_irq) {
 338                         irq_set_chip(irq, &icu_irq_chip);
 339                         irq_set_chained_handler(irq, icu_mux_irq_demux);
 340                 } else {
 341                         irq_set_chip_and_handler(irq, &icu_irq_chip,
 342                                                  handle_level_irq);
 343                 }
 344                 set_irq_flags(irq, IRQF_VALID);
 345         }
 346         irq_set_default_host(icu_data[0].domain);
 347         set_handle_irq(mmp2_handle_irq);
 348 }
 349
 350 #ifdef CONFIG_OF
 351 static int __init mmp_init_bases(struct device_node *node)
 352 {
 353         int ret, nr_irqs, irq, i = 0;
 354
 355         ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
 356         if (ret) {
 357                 pr_err("Not found mrvl,intc-nr-irqs property\n");
 358                 return ret;
 359         }
 360
 361         mmp_icu_base = of_iomap(node, 0);
 362         if (!mmp_icu_base) {
 363                 pr_err("Failed to get interrupt controller register\n");
 364                 return -ENOMEM;
 365         }
 366
 367         icu_data[0].virq_base = 0;
 368         icu_data[0].domain = irq_domain_add_linear(node, nr_irqs,
 369                                                    &mmp_irq_domain_ops,
 370                                                    &icu_data[0]);
 371         for (irq = 0; irq < nr_irqs; irq++) {
 372                 ret = irq_create_mapping(icu_data[0].domain, irq);
 373                 if (!ret) {
 374                         pr_err("Failed to mapping hwirq\n");
 375                         goto err;
 376                 }
 377                 if (!irq)
 378                         icu_data[0].virq_base = ret;
 379         }
 380         icu_data[0].nr_irqs = nr_irqs;
 381         return 0;
 382 err:
 383         if (icu_data[0].virq_base) {
 384                 for (i = 0; i < irq; i++)
 385                         irq_dispose_mapping(icu_data[0].virq_base + i);
 386         }
 387         irq_domain_remove(icu_data[0].domain);
 388         iounmap(mmp_icu_base);
 389         return -EINVAL;
 390 }
 391
 392 static int __init mmp_of_init(struct device_node *node,
 393                               struct device_node *parent)
 394 {
 395         int ret;
 396
 397         ret = mmp_init_bases(node);
 398         if (ret < 0)
 399                 return ret;
 400
 401         icu_data[0].conf_enable = mmp_conf.conf_enable;
 402         icu_data[0].conf_disable = mmp_conf.conf_disable;
 403         icu_data[0].conf_mask = mmp_conf.conf_mask;
 404         irq_set_default_host(icu_data[0].domain);
 405         set_handle_irq(mmp_handle_irq);
 406         max_icu_nr = 1;
 407         return 0;
 408 }
 409 IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init);
 410
 411 static int __init mmp2_of_init(struct device_node *node,
 412                                struct device_node *parent)
 413 {
 414         int ret;
 415
 416         ret = mmp_init_bases(node);
 417         if (ret < 0)
 418                 return ret;
 419
 420         icu_data[0].conf_enable = mmp2_conf.conf_enable;
 421         icu_data[0].conf_disable = mmp2_conf.conf_disable;
 422         icu_data[0].conf_mask = mmp2_conf.conf_mask;
 423         irq_set_default_host(icu_data[0].domain);
 424         set_handle_irq(mmp2_handle_irq);
 425         max_icu_nr = 1;
 426         return 0;
 427 }
 428 IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init);
 429
 430 static int __init mmp2_mux_of_init(struct device_node *node,
 431                                    struct device_node *parent)
 432 {
 433         struct resource res;
 434         int i, ret, irq, j = 0;
 435         u32 nr_irqs, mfp_irq;
 436
 437         if (!parent)
 438                 return -ENODEV;
 439
 440         i = max_icu_nr;
 441         ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
 442                                    &nr_irqs);
 443         if (ret) {
 444                 pr_err("Not found mrvl,intc-nr-irqs property\n");
 445                 return -EINVAL;
 446         }
 447         ret = of_address_to_resource(node, 0, &res);
 448         if (ret < 0) {
 449                 pr_err("Not found reg property\n");
 450                 return -EINVAL;
 451         }
 452         icu_data[i].reg_status = mmp_icu_base + res.start;
 453         ret = of_address_to_resource(node, 1, &res);
 454         if (ret < 0) {
 455                 pr_err("Not found reg property\n");
 456                 return -EINVAL;
 457         }
 458         icu_data[i].reg_mask = mmp_icu_base + res.start;
 459         icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
 460         if (!icu_data[i].cascade_irq)
 461                 return -EINVAL;
 462
 463         icu_data[i].virq_base = 0;
 464         icu_data[i].domain = irq_domain_add_linear(node, nr_irqs,
 465                                                    &mmp_irq_domain_ops,
 466                                                    &icu_data[i]);
 467         for (irq = 0; irq < nr_irqs; irq++) {
 468                 ret = irq_create_mapping(icu_data[i].domain, irq);
 469                 if (!ret) {
 470                         pr_err("Failed to mapping hwirq\n");
 471                         goto err;
 472                 }
 473                 if (!irq)
 474                         icu_data[i].virq_base = ret;
 475         }
 476         icu_data[i].nr_irqs = nr_irqs;
 477         if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
 478                                   &mfp_irq)) {
 479                 icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base;
 480                 icu_data[i].clr_mfp_hwirq = mfp_irq;
 481         }
 482         irq_set_chained_handler(icu_data[i].cascade_irq,
 483                                 icu_mux_irq_demux);
 484         max_icu_nr++;
 485         return 0;
 486 err:
 487         if (icu_data[i].virq_base) {
 488                 for (j = 0; j < irq; j++)
 489                         irq_dispose_mapping(icu_data[i].virq_base + j);
 490         }
 491         irq_domain_remove(icu_data[i].domain);
 492         return -EINVAL;
 493 }
 494 IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init);
 495 #endif