2 * omap iommu: tlb and pagetable primitives
4 * Copyright (C) 2008-2010 Nokia Corporation
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/err.h>
15 #include <linux/module.h>
16 #include <linux/slab.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/iommu.h>
22 #include <linux/mutex.h>
23 #include <linux/spinlock.h>
25 #include <asm/cacheflush.h>
27 #include <plat/iommu.h>
29 #include <plat/iopgtable.h>
31 #define for_each_iotlb_cr(obj, n, __i, cr) \
33 (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
36 /* bitmap of the page sizes currently supported */
37 #define OMAP_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
40 * struct omap_iommu_domain - omap iommu domain
41 * @pgtable: the page table
42 * @iommu_dev: an omap iommu device attached to this domain. only a single
43 * iommu device can be attached for now.
44 * @lock: domain lock, should be taken when attaching/detaching
46 struct omap_iommu_domain {
48 struct omap_iommu *iommu_dev;
52 /* accommodate the difference between omap1 and omap2/3 */
53 static const struct iommu_functions *arch_iommu;
55 static struct platform_driver omap_iommu_driver;
56 static struct kmem_cache *iopte_cachep;
59 * omap_install_iommu_arch - Install archtecure specific iommu functions
60 * @ops: a pointer to architecture specific iommu functions
62 * There are several kind of iommu algorithm(tlb, pagetable) among
63 * omap series. This interface installs such an iommu algorighm.
65 int omap_install_iommu_arch(const struct iommu_functions *ops)
73 EXPORT_SYMBOL_GPL(omap_install_iommu_arch);
76 * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions
77 * @ops: a pointer to architecture specific iommu functions
79 * This interface uninstalls the iommu algorighm installed previously.
81 void omap_uninstall_iommu_arch(const struct iommu_functions *ops)
83 if (arch_iommu != ops)
84 pr_err("%s: not your arch\n", __func__);
88 EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch);
91 * omap_iommu_save_ctx - Save registers for pm off-mode support
94 void omap_iommu_save_ctx(struct omap_iommu *obj)
96 arch_iommu->save_ctx(obj);
98 EXPORT_SYMBOL_GPL(omap_iommu_save_ctx);
101 * omap_iommu_restore_ctx - Restore registers for pm off-mode support
104 void omap_iommu_restore_ctx(struct omap_iommu *obj)
106 arch_iommu->restore_ctx(obj);
108 EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx);
111 * omap_iommu_arch_version - Return running iommu arch version
113 u32 omap_iommu_arch_version(void)
115 return arch_iommu->version;
117 EXPORT_SYMBOL_GPL(omap_iommu_arch_version);
119 static int iommu_enable(struct omap_iommu *obj)
129 clk_enable(obj->clk);
131 err = arch_iommu->enable(obj);
133 clk_disable(obj->clk);
137 static void iommu_disable(struct omap_iommu *obj)
142 clk_enable(obj->clk);
144 arch_iommu->disable(obj);
146 clk_disable(obj->clk);
152 void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
156 arch_iommu->cr_to_e(cr, e);
158 EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e);
160 static inline int iotlb_cr_valid(struct cr_regs *cr)
165 return arch_iommu->cr_valid(cr);
168 static inline struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj,
169 struct iotlb_entry *e)
174 return arch_iommu->alloc_cr(obj, e);
177 static u32 iotlb_cr_to_virt(struct cr_regs *cr)
179 return arch_iommu->cr_to_virt(cr);
182 static u32 get_iopte_attr(struct iotlb_entry *e)
184 return arch_iommu->get_pte_attr(e);
187 static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da)
189 return arch_iommu->fault_isr(obj, da);
192 static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l)
196 val = iommu_read_reg(obj, MMU_LOCK);
198 l->base = MMU_LOCK_BASE(val);
199 l->vict = MMU_LOCK_VICT(val);
203 static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l)
207 val = (l->base << MMU_LOCK_BASE_SHIFT);
208 val |= (l->vict << MMU_LOCK_VICT_SHIFT);
210 iommu_write_reg(obj, val, MMU_LOCK);
213 static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
215 arch_iommu->tlb_read_cr(obj, cr);
218 static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
220 arch_iommu->tlb_load_cr(obj, cr);
222 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
223 iommu_write_reg(obj, 1, MMU_LD_TLB);
227 * iotlb_dump_cr - Dump an iommu tlb entry into buf
229 * @cr: contents of cam and ram register
230 * @buf: output buffer
232 static inline ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr,
237 return arch_iommu->dump_cr(obj, cr, buf);
240 /* only used in iotlb iteration for-loop */
241 static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n)
246 iotlb_lock_get(obj, &l);
248 iotlb_lock_set(obj, &l);
249 iotlb_read_cr(obj, &cr);
255 * load_iotlb_entry - Set an iommu tlb entry
257 * @e: an iommu tlb entry info
259 #ifdef PREFETCH_IOTLB
260 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
266 if (!obj || !obj->nr_tlb_entries || !e)
269 clk_enable(obj->clk);
271 iotlb_lock_get(obj, &l);
272 if (l.base == obj->nr_tlb_entries) {
273 dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
281 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
282 if (!iotlb_cr_valid(&tmp))
285 if (i == obj->nr_tlb_entries) {
286 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
291 iotlb_lock_get(obj, &l);
294 iotlb_lock_set(obj, &l);
297 cr = iotlb_alloc_cr(obj, e);
299 clk_disable(obj->clk);
303 iotlb_load_cr(obj, cr);
308 /* increment victim for next tlb load */
309 if (++l.vict == obj->nr_tlb_entries)
311 iotlb_lock_set(obj, &l);
313 clk_disable(obj->clk);
317 #else /* !PREFETCH_IOTLB */
319 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
324 #endif /* !PREFETCH_IOTLB */
326 static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
328 return load_iotlb_entry(obj, e);
332 * flush_iotlb_page - Clear an iommu tlb entry
334 * @da: iommu device virtual address
336 * Clear an iommu tlb entry which includes 'da' address.
338 static void flush_iotlb_page(struct omap_iommu *obj, u32 da)
343 clk_enable(obj->clk);
345 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
349 if (!iotlb_cr_valid(&cr))
352 start = iotlb_cr_to_virt(&cr);
353 bytes = iopgsz_to_bytes(cr.cam & 3);
355 if ((start <= da) && (da < start + bytes)) {
356 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
357 __func__, start, da, bytes);
358 iotlb_load_cr(obj, &cr);
359 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
362 clk_disable(obj->clk);
364 if (i == obj->nr_tlb_entries)
365 dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
369 * flush_iotlb_all - Clear all iommu tlb entries
372 static void flush_iotlb_all(struct omap_iommu *obj)
376 clk_enable(obj->clk);
380 iotlb_lock_set(obj, &l);
382 iommu_write_reg(obj, 1, MMU_GFLUSH);
384 clk_disable(obj->clk);
387 #if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
389 ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes)
394 clk_enable(obj->clk);
396 bytes = arch_iommu->dump_ctx(obj, buf, bytes);
398 clk_disable(obj->clk);
402 EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx);
405 __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num)
408 struct iotlb_lock saved;
410 struct cr_regs *p = crs;
412 clk_enable(obj->clk);
413 iotlb_lock_get(obj, &saved);
415 for_each_iotlb_cr(obj, num, i, tmp) {
416 if (!iotlb_cr_valid(&tmp))
421 iotlb_lock_set(obj, &saved);
422 clk_disable(obj->clk);
428 * omap_dump_tlb_entries - dump cr arrays to given buffer
430 * @buf: output buffer
432 size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes)
438 num = bytes / sizeof(*cr);
439 num = min(obj->nr_tlb_entries, num);
441 cr = kcalloc(num, sizeof(*cr), GFP_KERNEL);
445 num = __dump_tlb_entries(obj, cr, num);
446 for (i = 0; i < num; i++)
447 p += iotlb_dump_cr(obj, cr + i, p);
452 EXPORT_SYMBOL_GPL(omap_dump_tlb_entries);
454 int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *))
456 return driver_for_each_device(&omap_iommu_driver.driver,
459 EXPORT_SYMBOL_GPL(omap_foreach_iommu_device);
461 #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */
464 * H/W pagetable operations
466 static void flush_iopgd_range(u32 *first, u32 *last)
468 /* FIXME: L2 cache should be taken care of if it exists */
470 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd"
472 first += L1_CACHE_BYTES / sizeof(*first);
473 } while (first <= last);
476 static void flush_iopte_range(u32 *first, u32 *last)
478 /* FIXME: L2 cache should be taken care of if it exists */
480 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte"
482 first += L1_CACHE_BYTES / sizeof(*first);
483 } while (first <= last);
486 static void iopte_free(u32 *iopte)
488 /* Note: freed iopte's must be clean ready for re-use */
489 kmem_cache_free(iopte_cachep, iopte);
492 static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da)
496 /* a table has already existed */
501 * do the allocation outside the page table lock
503 spin_unlock(&obj->page_table_lock);
504 iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
505 spin_lock(&obj->page_table_lock);
509 return ERR_PTR(-ENOMEM);
511 *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
512 flush_iopgd_range(iopgd, iopgd);
514 dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
516 /* We raced, free the reduniovant table */
521 iopte = iopte_offset(iopgd, da);
524 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
525 __func__, da, iopgd, *iopgd, iopte, *iopte);
530 static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
532 u32 *iopgd = iopgd_offset(obj, da);
534 if ((da | pa) & ~IOSECTION_MASK) {
535 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
536 __func__, da, pa, IOSECTION_SIZE);
540 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
541 flush_iopgd_range(iopgd, iopgd);
545 static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
547 u32 *iopgd = iopgd_offset(obj, da);
550 if ((da | pa) & ~IOSUPER_MASK) {
551 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
552 __func__, da, pa, IOSUPER_SIZE);
556 for (i = 0; i < 16; i++)
557 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
558 flush_iopgd_range(iopgd, iopgd + 15);
562 static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
564 u32 *iopgd = iopgd_offset(obj, da);
565 u32 *iopte = iopte_alloc(obj, iopgd, da);
568 return PTR_ERR(iopte);
570 *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
571 flush_iopte_range(iopte, iopte);
573 dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
574 __func__, da, pa, iopte, *iopte);
579 static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
581 u32 *iopgd = iopgd_offset(obj, da);
582 u32 *iopte = iopte_alloc(obj, iopgd, da);
585 if ((da | pa) & ~IOLARGE_MASK) {
586 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
587 __func__, da, pa, IOLARGE_SIZE);
592 return PTR_ERR(iopte);
594 for (i = 0; i < 16; i++)
595 *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
596 flush_iopte_range(iopte, iopte + 15);
601 iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e)
603 int (*fn)(struct omap_iommu *, u32, u32, u32);
611 case MMU_CAM_PGSZ_16M:
612 fn = iopgd_alloc_super;
614 case MMU_CAM_PGSZ_1M:
615 fn = iopgd_alloc_section;
617 case MMU_CAM_PGSZ_64K:
618 fn = iopte_alloc_large;
620 case MMU_CAM_PGSZ_4K:
621 fn = iopte_alloc_page;
629 prot = get_iopte_attr(e);
631 spin_lock(&obj->page_table_lock);
632 err = fn(obj, e->da, e->pa, prot);
633 spin_unlock(&obj->page_table_lock);
639 * omap_iopgtable_store_entry - Make an iommu pte entry
641 * @e: an iommu tlb entry info
643 int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e)
647 flush_iotlb_page(obj, e->da);
648 err = iopgtable_store_entry_core(obj, e);
650 prefetch_iotlb_entry(obj, e);
653 EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry);
656 * iopgtable_lookup_entry - Lookup an iommu pte entry
658 * @da: iommu device virtual address
659 * @ppgd: iommu pgd entry pointer to be returned
660 * @ppte: iommu pte entry pointer to be returned
663 iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
665 u32 *iopgd, *iopte = NULL;
667 iopgd = iopgd_offset(obj, da);
671 if (iopgd_is_table(*iopgd))
672 iopte = iopte_offset(iopgd, da);
678 static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da)
681 u32 *iopgd = iopgd_offset(obj, da);
687 if (iopgd_is_table(*iopgd)) {
689 u32 *iopte = iopte_offset(iopgd, da);
692 if (*iopte & IOPTE_LARGE) {
694 /* rewind to the 1st entry */
695 iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
698 memset(iopte, 0, nent * sizeof(*iopte));
699 flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
702 * do table walk to check if this table is necessary or not
704 iopte = iopte_offset(iopgd, 0);
705 for (i = 0; i < PTRS_PER_IOPTE; i++)
710 nent = 1; /* for the next L1 entry */
713 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
715 /* rewind to the 1st entry */
716 iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
720 memset(iopgd, 0, nent * sizeof(*iopgd));
721 flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
727 * iopgtable_clear_entry - Remove an iommu pte entry
729 * @da: iommu device virtual address
731 static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da)
735 spin_lock(&obj->page_table_lock);
737 bytes = iopgtable_clear_entry_core(obj, da);
738 flush_iotlb_page(obj, da);
740 spin_unlock(&obj->page_table_lock);
745 static void iopgtable_clear_entry_all(struct omap_iommu *obj)
749 spin_lock(&obj->page_table_lock);
751 for (i = 0; i < PTRS_PER_IOPGD; i++) {
755 da = i << IOPGD_SHIFT;
756 iopgd = iopgd_offset(obj, da);
761 if (iopgd_is_table(*iopgd))
762 iopte_free(iopte_offset(iopgd, 0));
765 flush_iopgd_range(iopgd, iopgd);
768 flush_iotlb_all(obj);
770 spin_unlock(&obj->page_table_lock);
774 * Device IOMMU generic operations
776 static irqreturn_t iommu_fault_handler(int irq, void *data)
780 struct omap_iommu *obj = data;
781 struct iommu_domain *domain = obj->domain;
786 clk_enable(obj->clk);
787 errs = iommu_report_fault(obj, &da);
788 clk_disable(obj->clk);
792 /* Fault callback or TLB/PTE Dynamic loading */
793 if (!report_iommu_fault(domain, obj->dev, da, 0))
798 iopgd = iopgd_offset(obj, da);
800 if (!iopgd_is_table(*iopgd)) {
801 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p "
802 "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd);
806 iopte = iopte_offset(iopgd, da);
808 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x "
809 "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd,
815 static int device_match_by_alias(struct device *dev, void *data)
817 struct omap_iommu *obj = to_iommu(dev);
818 const char *name = data;
820 pr_debug("%s: %s %s\n", __func__, obj->name, name);
822 return strcmp(obj->name, name) == 0;
826 * omap_find_iommu_device() - find an omap iommu device by name
827 * @name: name of the iommu device
829 * The generic iommu API requires the caller to provide the device
830 * he wishes to attach to a certain iommu domain.
832 * Drivers generally should not bother with this as it should just
833 * be taken care of by the DMA-API using dev_archdata.
835 * This function is provided as an interim solution until the latter
836 * materializes, and omap3isp is fully migrated to the DMA-API.
838 struct device *omap_find_iommu_device(const char *name)
840 return driver_find_device(&omap_iommu_driver.driver, NULL,
842 device_match_by_alias);
844 EXPORT_SYMBOL_GPL(omap_find_iommu_device);
847 * omap_iommu_attach() - attach iommu device to an iommu domain
848 * @dev: target omap iommu device
851 static struct omap_iommu *omap_iommu_attach(struct device *dev, u32 *iopgd)
854 struct omap_iommu *obj = to_iommu(dev);
856 spin_lock(&obj->iommu_lock);
858 /* an iommu device can only be attached once */
859 if (++obj->refcount > 1) {
860 dev_err(dev, "%s: already attached!\n", obj->name);
866 err = iommu_enable(obj);
869 flush_iotlb_all(obj);
871 if (!try_module_get(obj->owner))
874 spin_unlock(&obj->iommu_lock);
876 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
880 if (obj->refcount == 1)
884 spin_unlock(&obj->iommu_lock);
889 * omap_iommu_detach - release iommu device
892 static void omap_iommu_detach(struct omap_iommu *obj)
894 if (!obj || IS_ERR(obj))
897 spin_lock(&obj->iommu_lock);
899 if (--obj->refcount == 0)
902 module_put(obj->owner);
906 spin_unlock(&obj->iommu_lock);
908 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
912 * OMAP Device MMU(IOMMU) detection
914 static int __devinit omap_iommu_probe(struct platform_device *pdev)
918 struct omap_iommu *obj;
919 struct resource *res;
920 struct iommu_platform_data *pdata = pdev->dev.platform_data;
922 if (pdev->num_resources != 2)
925 obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
929 obj->clk = clk_get(&pdev->dev, pdata->clk_name);
930 if (IS_ERR(obj->clk))
933 obj->nr_tlb_entries = pdata->nr_tlb_entries;
934 obj->name = pdata->name;
935 obj->dev = &pdev->dev;
936 obj->ctx = (void *)obj + sizeof(*obj);
937 obj->da_start = pdata->da_start;
938 obj->da_end = pdata->da_end;
940 spin_lock_init(&obj->iommu_lock);
941 mutex_init(&obj->mmap_lock);
942 spin_lock_init(&obj->page_table_lock);
943 INIT_LIST_HEAD(&obj->mmap);
945 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
951 res = request_mem_region(res->start, resource_size(res),
952 dev_name(&pdev->dev));
958 obj->regbase = ioremap(res->start, resource_size(res));
964 irq = platform_get_irq(pdev, 0);
969 err = request_irq(irq, iommu_fault_handler, IRQF_SHARED,
970 dev_name(&pdev->dev), obj);
973 platform_set_drvdata(pdev, obj);
975 dev_info(&pdev->dev, "%s registered\n", obj->name);
979 iounmap(obj->regbase);
981 release_mem_region(res->start, resource_size(res));
989 static int __devexit omap_iommu_remove(struct platform_device *pdev)
992 struct resource *res;
993 struct omap_iommu *obj = platform_get_drvdata(pdev);
995 platform_set_drvdata(pdev, NULL);
997 iopgtable_clear_entry_all(obj);
999 irq = platform_get_irq(pdev, 0);
1001 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1002 release_mem_region(res->start, resource_size(res));
1003 iounmap(obj->regbase);
1006 dev_info(&pdev->dev, "%s removed\n", obj->name);
1011 static struct platform_driver omap_iommu_driver = {
1012 .probe = omap_iommu_probe,
1013 .remove = __devexit_p(omap_iommu_remove),
1015 .name = "omap-iommu",
1019 static void iopte_cachep_ctor(void *iopte)
1021 clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
1024 static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
1025 phys_addr_t pa, size_t bytes, int prot)
1027 struct omap_iommu_domain *omap_domain = domain->priv;
1028 struct omap_iommu *oiommu = omap_domain->iommu_dev;
1029 struct device *dev = oiommu->dev;
1030 struct iotlb_entry e;
1034 /* we only support mapping a single iommu page for now */
1035 omap_pgsz = bytes_to_iopgsz(bytes);
1036 if (omap_pgsz < 0) {
1037 dev_err(dev, "invalid size to map: %d\n", bytes);
1041 dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes);
1043 flags = omap_pgsz | prot;
1045 iotlb_init_entry(&e, da, pa, flags);
1047 ret = omap_iopgtable_store_entry(oiommu, &e);
1049 dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret);
1054 static size_t omap_iommu_unmap(struct iommu_domain *domain, unsigned long da,
1057 struct omap_iommu_domain *omap_domain = domain->priv;
1058 struct omap_iommu *oiommu = omap_domain->iommu_dev;
1059 struct device *dev = oiommu->dev;
1061 dev_dbg(dev, "unmapping da 0x%lx size %u\n", da, size);
1063 return iopgtable_clear_entry(oiommu, da);
1067 omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
1069 struct omap_iommu_domain *omap_domain = domain->priv;
1070 struct omap_iommu *oiommu;
1073 spin_lock(&omap_domain->lock);
1075 /* only a single device is supported per domain for now */
1076 if (omap_domain->iommu_dev) {
1077 dev_err(dev, "iommu domain is already attached\n");
1082 /* get a handle to and enable the omap iommu */
1083 oiommu = omap_iommu_attach(dev, omap_domain->pgtable);
1084 if (IS_ERR(oiommu)) {
1085 ret = PTR_ERR(oiommu);
1086 dev_err(dev, "can't get omap iommu: %d\n", ret);
1090 omap_domain->iommu_dev = oiommu;
1091 oiommu->domain = domain;
1094 spin_unlock(&omap_domain->lock);
1098 static void omap_iommu_detach_dev(struct iommu_domain *domain,
1101 struct omap_iommu_domain *omap_domain = domain->priv;
1102 struct omap_iommu *oiommu = to_iommu(dev);
1104 spin_lock(&omap_domain->lock);
1106 /* only a single device is supported per domain for now */
1107 if (omap_domain->iommu_dev != oiommu) {
1108 dev_err(dev, "invalid iommu device\n");
1112 iopgtable_clear_entry_all(oiommu);
1114 omap_iommu_detach(oiommu);
1116 omap_domain->iommu_dev = NULL;
1119 spin_unlock(&omap_domain->lock);
1122 static int omap_iommu_domain_init(struct iommu_domain *domain)
1124 struct omap_iommu_domain *omap_domain;
1126 omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL);
1128 pr_err("kzalloc failed\n");
1132 omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL);
1133 if (!omap_domain->pgtable) {
1134 pr_err("kzalloc failed\n");
1139 * should never fail, but please keep this around to ensure
1140 * we keep the hardware happy
1142 BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE));
1144 clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE);
1145 spin_lock_init(&omap_domain->lock);
1147 domain->priv = omap_domain;
1157 /* assume device was already detached */
1158 static void omap_iommu_domain_destroy(struct iommu_domain *domain)
1160 struct omap_iommu_domain *omap_domain = domain->priv;
1162 domain->priv = NULL;
1164 kfree(omap_domain->pgtable);
1168 static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain,
1171 struct omap_iommu_domain *omap_domain = domain->priv;
1172 struct omap_iommu *oiommu = omap_domain->iommu_dev;
1173 struct device *dev = oiommu->dev;
1175 phys_addr_t ret = 0;
1177 iopgtable_lookup_entry(oiommu, da, &pgd, &pte);
1180 if (iopte_is_small(*pte))
1181 ret = omap_iommu_translate(*pte, da, IOPTE_MASK);
1182 else if (iopte_is_large(*pte))
1183 ret = omap_iommu_translate(*pte, da, IOLARGE_MASK);
1185 dev_err(dev, "bogus pte 0x%x", *pte);
1187 if (iopgd_is_section(*pgd))
1188 ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK);
1189 else if (iopgd_is_super(*pgd))
1190 ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK);
1192 dev_err(dev, "bogus pgd 0x%x", *pgd);
1198 static int omap_iommu_domain_has_cap(struct iommu_domain *domain,
1204 static struct iommu_ops omap_iommu_ops = {
1205 .domain_init = omap_iommu_domain_init,
1206 .domain_destroy = omap_iommu_domain_destroy,
1207 .attach_dev = omap_iommu_attach_dev,
1208 .detach_dev = omap_iommu_detach_dev,
1209 .map = omap_iommu_map,
1210 .unmap = omap_iommu_unmap,
1211 .iova_to_phys = omap_iommu_iova_to_phys,
1212 .domain_has_cap = omap_iommu_domain_has_cap,
1213 .pgsize_bitmap = OMAP_IOMMU_PGSIZES,
1216 static int __init omap_iommu_init(void)
1218 struct kmem_cache *p;
1219 const unsigned long flags = SLAB_HWCACHE_ALIGN;
1220 size_t align = 1 << 10; /* L2 pagetable alignement */
1222 p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
1228 bus_set_iommu(&platform_bus_type, &omap_iommu_ops);
1230 return platform_driver_register(&omap_iommu_driver);
1232 module_init(omap_iommu_init);
1234 static void __exit omap_iommu_exit(void)
1236 kmem_cache_destroy(iopte_cachep);
1238 platform_driver_unregister(&omap_iommu_driver);
1240 module_exit(omap_iommu_exit);
1242 MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives");
1243 MODULE_ALIAS("platform:omap-iommu");
1244 MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
1245 MODULE_LICENSE("GPL v2");