2 * omap iommu: tlb and pagetable primitives
4 * Copyright (C) 2008-2010 Nokia Corporation
6 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>,
7 * Paul Mundt and Toshihiro Kobayashi
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/err.h>
15 #include <linux/module.h>
16 #include <linux/slab.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/clk.h>
20 #include <linux/platform_device.h>
21 #include <linux/iommu.h>
22 #include <linux/mutex.h>
23 #include <linux/spinlock.h>
25 #include <asm/cacheflush.h>
27 #include <plat/iommu.h>
29 #include <plat/iopgtable.h>
31 #define for_each_iotlb_cr(obj, n, __i, cr) \
33 (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
37 * struct omap_iommu_domain - omap iommu domain
38 * @pgtable: the page table
39 * @iommu_dev: an omap iommu device attached to this domain. only a single
40 * iommu device can be attached for now.
41 * @lock: domain lock, should be taken when attaching/detaching
43 struct omap_iommu_domain {
45 struct omap_iommu *iommu_dev;
49 /* accommodate the difference between omap1 and omap2/3 */
50 static const struct iommu_functions *arch_iommu;
52 static struct platform_driver omap_iommu_driver;
53 static struct kmem_cache *iopte_cachep;
56 * omap_install_iommu_arch - Install archtecure specific iommu functions
57 * @ops: a pointer to architecture specific iommu functions
59 * There are several kind of iommu algorithm(tlb, pagetable) among
60 * omap series. This interface installs such an iommu algorighm.
62 int omap_install_iommu_arch(const struct iommu_functions *ops)
70 EXPORT_SYMBOL_GPL(omap_install_iommu_arch);
73 * omap_uninstall_iommu_arch - Uninstall archtecure specific iommu functions
74 * @ops: a pointer to architecture specific iommu functions
76 * This interface uninstalls the iommu algorighm installed previously.
78 void omap_uninstall_iommu_arch(const struct iommu_functions *ops)
80 if (arch_iommu != ops)
81 pr_err("%s: not your arch\n", __func__);
85 EXPORT_SYMBOL_GPL(omap_uninstall_iommu_arch);
88 * omap_iommu_save_ctx - Save registers for pm off-mode support
91 void omap_iommu_save_ctx(struct device *dev)
93 struct omap_iommu *obj = dev_to_omap_iommu(dev);
95 arch_iommu->save_ctx(obj);
97 EXPORT_SYMBOL_GPL(omap_iommu_save_ctx);
100 * omap_iommu_restore_ctx - Restore registers for pm off-mode support
101 * @dev: client device
103 void omap_iommu_restore_ctx(struct device *dev)
105 struct omap_iommu *obj = dev_to_omap_iommu(dev);
107 arch_iommu->restore_ctx(obj);
109 EXPORT_SYMBOL_GPL(omap_iommu_restore_ctx);
112 * omap_iommu_arch_version - Return running iommu arch version
114 u32 omap_iommu_arch_version(void)
116 return arch_iommu->version;
118 EXPORT_SYMBOL_GPL(omap_iommu_arch_version);
120 static int iommu_enable(struct omap_iommu *obj)
130 clk_enable(obj->clk);
132 err = arch_iommu->enable(obj);
134 clk_disable(obj->clk);
138 static void iommu_disable(struct omap_iommu *obj)
143 clk_enable(obj->clk);
145 arch_iommu->disable(obj);
147 clk_disable(obj->clk);
153 void omap_iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e)
157 arch_iommu->cr_to_e(cr, e);
159 EXPORT_SYMBOL_GPL(omap_iotlb_cr_to_e);
161 static inline int iotlb_cr_valid(struct cr_regs *cr)
166 return arch_iommu->cr_valid(cr);
169 static inline struct cr_regs *iotlb_alloc_cr(struct omap_iommu *obj,
170 struct iotlb_entry *e)
175 return arch_iommu->alloc_cr(obj, e);
178 static u32 iotlb_cr_to_virt(struct cr_regs *cr)
180 return arch_iommu->cr_to_virt(cr);
183 static u32 get_iopte_attr(struct iotlb_entry *e)
185 return arch_iommu->get_pte_attr(e);
188 static u32 iommu_report_fault(struct omap_iommu *obj, u32 *da)
190 return arch_iommu->fault_isr(obj, da);
193 static void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l)
197 val = iommu_read_reg(obj, MMU_LOCK);
199 l->base = MMU_LOCK_BASE(val);
200 l->vict = MMU_LOCK_VICT(val);
204 static void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l)
208 val = (l->base << MMU_LOCK_BASE_SHIFT);
209 val |= (l->vict << MMU_LOCK_VICT_SHIFT);
211 iommu_write_reg(obj, val, MMU_LOCK);
214 static void iotlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)
216 arch_iommu->tlb_read_cr(obj, cr);
219 static void iotlb_load_cr(struct omap_iommu *obj, struct cr_regs *cr)
221 arch_iommu->tlb_load_cr(obj, cr);
223 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
224 iommu_write_reg(obj, 1, MMU_LD_TLB);
228 * iotlb_dump_cr - Dump an iommu tlb entry into buf
230 * @cr: contents of cam and ram register
231 * @buf: output buffer
233 static inline ssize_t iotlb_dump_cr(struct omap_iommu *obj, struct cr_regs *cr,
238 return arch_iommu->dump_cr(obj, cr, buf);
241 /* only used in iotlb iteration for-loop */
242 static struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n)
247 iotlb_lock_get(obj, &l);
249 iotlb_lock_set(obj, &l);
250 iotlb_read_cr(obj, &cr);
256 * load_iotlb_entry - Set an iommu tlb entry
258 * @e: an iommu tlb entry info
260 #ifdef PREFETCH_IOTLB
261 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
267 if (!obj || !obj->nr_tlb_entries || !e)
270 clk_enable(obj->clk);
272 iotlb_lock_get(obj, &l);
273 if (l.base == obj->nr_tlb_entries) {
274 dev_warn(obj->dev, "%s: preserve entries full\n", __func__);
282 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, tmp)
283 if (!iotlb_cr_valid(&tmp))
286 if (i == obj->nr_tlb_entries) {
287 dev_dbg(obj->dev, "%s: full: no entry\n", __func__);
292 iotlb_lock_get(obj, &l);
295 iotlb_lock_set(obj, &l);
298 cr = iotlb_alloc_cr(obj, e);
300 clk_disable(obj->clk);
304 iotlb_load_cr(obj, cr);
309 /* increment victim for next tlb load */
310 if (++l.vict == obj->nr_tlb_entries)
312 iotlb_lock_set(obj, &l);
314 clk_disable(obj->clk);
318 #else /* !PREFETCH_IOTLB */
320 static int load_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
325 #endif /* !PREFETCH_IOTLB */
327 static int prefetch_iotlb_entry(struct omap_iommu *obj, struct iotlb_entry *e)
329 return load_iotlb_entry(obj, e);
333 * flush_iotlb_page - Clear an iommu tlb entry
335 * @da: iommu device virtual address
337 * Clear an iommu tlb entry which includes 'da' address.
339 static void flush_iotlb_page(struct omap_iommu *obj, u32 da)
344 clk_enable(obj->clk);
346 for_each_iotlb_cr(obj, obj->nr_tlb_entries, i, cr) {
350 if (!iotlb_cr_valid(&cr))
353 start = iotlb_cr_to_virt(&cr);
354 bytes = iopgsz_to_bytes(cr.cam & 3);
356 if ((start <= da) && (da < start + bytes)) {
357 dev_dbg(obj->dev, "%s: %08x<=%08x(%x)\n",
358 __func__, start, da, bytes);
359 iotlb_load_cr(obj, &cr);
360 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
363 clk_disable(obj->clk);
365 if (i == obj->nr_tlb_entries)
366 dev_dbg(obj->dev, "%s: no page for %08x\n", __func__, da);
370 * flush_iotlb_all - Clear all iommu tlb entries
373 static void flush_iotlb_all(struct omap_iommu *obj)
377 clk_enable(obj->clk);
381 iotlb_lock_set(obj, &l);
383 iommu_write_reg(obj, 1, MMU_GFLUSH);
385 clk_disable(obj->clk);
388 #if defined(CONFIG_OMAP_IOMMU_DEBUG) || defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
390 ssize_t omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t bytes)
395 clk_enable(obj->clk);
397 bytes = arch_iommu->dump_ctx(obj, buf, bytes);
399 clk_disable(obj->clk);
403 EXPORT_SYMBOL_GPL(omap_iommu_dump_ctx);
406 __dump_tlb_entries(struct omap_iommu *obj, struct cr_regs *crs, int num)
409 struct iotlb_lock saved;
411 struct cr_regs *p = crs;
413 clk_enable(obj->clk);
414 iotlb_lock_get(obj, &saved);
416 for_each_iotlb_cr(obj, num, i, tmp) {
417 if (!iotlb_cr_valid(&tmp))
422 iotlb_lock_set(obj, &saved);
423 clk_disable(obj->clk);
429 * omap_dump_tlb_entries - dump cr arrays to given buffer
431 * @buf: output buffer
433 size_t omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t bytes)
439 num = bytes / sizeof(*cr);
440 num = min(obj->nr_tlb_entries, num);
442 cr = kcalloc(num, sizeof(*cr), GFP_KERNEL);
446 num = __dump_tlb_entries(obj, cr, num);
447 for (i = 0; i < num; i++)
448 p += iotlb_dump_cr(obj, cr + i, p);
453 EXPORT_SYMBOL_GPL(omap_dump_tlb_entries);
455 int omap_foreach_iommu_device(void *data, int (*fn)(struct device *, void *))
457 return driver_for_each_device(&omap_iommu_driver.driver,
460 EXPORT_SYMBOL_GPL(omap_foreach_iommu_device);
462 #endif /* CONFIG_OMAP_IOMMU_DEBUG_MODULE */
465 * H/W pagetable operations
467 static void flush_iopgd_range(u32 *first, u32 *last)
469 /* FIXME: L2 cache should be taken care of if it exists */
471 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd"
473 first += L1_CACHE_BYTES / sizeof(*first);
474 } while (first <= last);
477 static void flush_iopte_range(u32 *first, u32 *last)
479 /* FIXME: L2 cache should be taken care of if it exists */
481 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte"
483 first += L1_CACHE_BYTES / sizeof(*first);
484 } while (first <= last);
487 static void iopte_free(u32 *iopte)
489 /* Note: freed iopte's must be clean ready for re-use */
490 kmem_cache_free(iopte_cachep, iopte);
493 static u32 *iopte_alloc(struct omap_iommu *obj, u32 *iopgd, u32 da)
497 /* a table has already existed */
502 * do the allocation outside the page table lock
504 spin_unlock(&obj->page_table_lock);
505 iopte = kmem_cache_zalloc(iopte_cachep, GFP_KERNEL);
506 spin_lock(&obj->page_table_lock);
510 return ERR_PTR(-ENOMEM);
512 *iopgd = virt_to_phys(iopte) | IOPGD_TABLE;
513 flush_iopgd_range(iopgd, iopgd);
515 dev_vdbg(obj->dev, "%s: a new pte:%p\n", __func__, iopte);
517 /* We raced, free the reduniovant table */
522 iopte = iopte_offset(iopgd, da);
525 "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
526 __func__, da, iopgd, *iopgd, iopte, *iopte);
531 static int iopgd_alloc_section(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
533 u32 *iopgd = iopgd_offset(obj, da);
535 if ((da | pa) & ~IOSECTION_MASK) {
536 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
537 __func__, da, pa, IOSECTION_SIZE);
541 *iopgd = (pa & IOSECTION_MASK) | prot | IOPGD_SECTION;
542 flush_iopgd_range(iopgd, iopgd);
546 static int iopgd_alloc_super(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
548 u32 *iopgd = iopgd_offset(obj, da);
551 if ((da | pa) & ~IOSUPER_MASK) {
552 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
553 __func__, da, pa, IOSUPER_SIZE);
557 for (i = 0; i < 16; i++)
558 *(iopgd + i) = (pa & IOSUPER_MASK) | prot | IOPGD_SUPER;
559 flush_iopgd_range(iopgd, iopgd + 15);
563 static int iopte_alloc_page(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
565 u32 *iopgd = iopgd_offset(obj, da);
566 u32 *iopte = iopte_alloc(obj, iopgd, da);
569 return PTR_ERR(iopte);
571 *iopte = (pa & IOPAGE_MASK) | prot | IOPTE_SMALL;
572 flush_iopte_range(iopte, iopte);
574 dev_vdbg(obj->dev, "%s: da:%08x pa:%08x pte:%p *pte:%08x\n",
575 __func__, da, pa, iopte, *iopte);
580 static int iopte_alloc_large(struct omap_iommu *obj, u32 da, u32 pa, u32 prot)
582 u32 *iopgd = iopgd_offset(obj, da);
583 u32 *iopte = iopte_alloc(obj, iopgd, da);
586 if ((da | pa) & ~IOLARGE_MASK) {
587 dev_err(obj->dev, "%s: %08x:%08x should aligned on %08lx\n",
588 __func__, da, pa, IOLARGE_SIZE);
593 return PTR_ERR(iopte);
595 for (i = 0; i < 16; i++)
596 *(iopte + i) = (pa & IOLARGE_MASK) | prot | IOPTE_LARGE;
597 flush_iopte_range(iopte, iopte + 15);
602 iopgtable_store_entry_core(struct omap_iommu *obj, struct iotlb_entry *e)
604 int (*fn)(struct omap_iommu *, u32, u32, u32);
612 case MMU_CAM_PGSZ_16M:
613 fn = iopgd_alloc_super;
615 case MMU_CAM_PGSZ_1M:
616 fn = iopgd_alloc_section;
618 case MMU_CAM_PGSZ_64K:
619 fn = iopte_alloc_large;
621 case MMU_CAM_PGSZ_4K:
622 fn = iopte_alloc_page;
630 prot = get_iopte_attr(e);
632 spin_lock(&obj->page_table_lock);
633 err = fn(obj, e->da, e->pa, prot);
634 spin_unlock(&obj->page_table_lock);
640 * omap_iopgtable_store_entry - Make an iommu pte entry
642 * @e: an iommu tlb entry info
644 int omap_iopgtable_store_entry(struct omap_iommu *obj, struct iotlb_entry *e)
648 flush_iotlb_page(obj, e->da);
649 err = iopgtable_store_entry_core(obj, e);
651 prefetch_iotlb_entry(obj, e);
654 EXPORT_SYMBOL_GPL(omap_iopgtable_store_entry);
657 * iopgtable_lookup_entry - Lookup an iommu pte entry
659 * @da: iommu device virtual address
660 * @ppgd: iommu pgd entry pointer to be returned
661 * @ppte: iommu pte entry pointer to be returned
664 iopgtable_lookup_entry(struct omap_iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
666 u32 *iopgd, *iopte = NULL;
668 iopgd = iopgd_offset(obj, da);
672 if (iopgd_is_table(*iopgd))
673 iopte = iopte_offset(iopgd, da);
679 static size_t iopgtable_clear_entry_core(struct omap_iommu *obj, u32 da)
682 u32 *iopgd = iopgd_offset(obj, da);
688 if (iopgd_is_table(*iopgd)) {
690 u32 *iopte = iopte_offset(iopgd, da);
693 if (*iopte & IOPTE_LARGE) {
695 /* rewind to the 1st entry */
696 iopte = iopte_offset(iopgd, (da & IOLARGE_MASK));
699 memset(iopte, 0, nent * sizeof(*iopte));
700 flush_iopte_range(iopte, iopte + (nent - 1) * sizeof(*iopte));
703 * do table walk to check if this table is necessary or not
705 iopte = iopte_offset(iopgd, 0);
706 for (i = 0; i < PTRS_PER_IOPTE; i++)
711 nent = 1; /* for the next L1 entry */
714 if ((*iopgd & IOPGD_SUPER) == IOPGD_SUPER) {
716 /* rewind to the 1st entry */
717 iopgd = iopgd_offset(obj, (da & IOSUPER_MASK));
721 memset(iopgd, 0, nent * sizeof(*iopgd));
722 flush_iopgd_range(iopgd, iopgd + (nent - 1) * sizeof(*iopgd));
728 * iopgtable_clear_entry - Remove an iommu pte entry
730 * @da: iommu device virtual address
732 static size_t iopgtable_clear_entry(struct omap_iommu *obj, u32 da)
736 spin_lock(&obj->page_table_lock);
738 bytes = iopgtable_clear_entry_core(obj, da);
739 flush_iotlb_page(obj, da);
741 spin_unlock(&obj->page_table_lock);
746 static void iopgtable_clear_entry_all(struct omap_iommu *obj)
750 spin_lock(&obj->page_table_lock);
752 for (i = 0; i < PTRS_PER_IOPGD; i++) {
756 da = i << IOPGD_SHIFT;
757 iopgd = iopgd_offset(obj, da);
762 if (iopgd_is_table(*iopgd))
763 iopte_free(iopte_offset(iopgd, 0));
766 flush_iopgd_range(iopgd, iopgd);
769 flush_iotlb_all(obj);
771 spin_unlock(&obj->page_table_lock);
775 * Device IOMMU generic operations
777 static irqreturn_t iommu_fault_handler(int irq, void *data)
781 struct omap_iommu *obj = data;
782 struct iommu_domain *domain = obj->domain;
787 clk_enable(obj->clk);
788 errs = iommu_report_fault(obj, &da);
789 clk_disable(obj->clk);
793 /* Fault callback or TLB/PTE Dynamic loading */
794 if (!report_iommu_fault(domain, obj->dev, da, 0))
799 iopgd = iopgd_offset(obj, da);
801 if (!iopgd_is_table(*iopgd)) {
802 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p "
803 "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd);
807 iopte = iopte_offset(iopgd, da);
809 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x "
810 "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd,
816 static int device_match_by_alias(struct device *dev, void *data)
818 struct omap_iommu *obj = to_iommu(dev);
819 const char *name = data;
821 pr_debug("%s: %s %s\n", __func__, obj->name, name);
823 return strcmp(obj->name, name) == 0;
827 * omap_iommu_attach() - attach iommu device to an iommu domain
828 * @name: name of target omap iommu device
831 static struct omap_iommu *omap_iommu_attach(const char *name, u32 *iopgd)
835 struct omap_iommu *obj;
837 dev = driver_find_device(&omap_iommu_driver.driver, NULL,
839 device_match_by_alias);
845 spin_lock(&obj->iommu_lock);
847 /* an iommu device can only be attached once */
848 if (++obj->refcount > 1) {
849 dev_err(dev, "%s: already attached!\n", obj->name);
855 err = iommu_enable(obj);
858 flush_iotlb_all(obj);
860 if (!try_module_get(obj->owner))
863 spin_unlock(&obj->iommu_lock);
865 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
869 if (obj->refcount == 1)
873 spin_unlock(&obj->iommu_lock);
878 * omap_iommu_detach - release iommu device
881 static void omap_iommu_detach(struct omap_iommu *obj)
883 if (!obj || IS_ERR(obj))
886 spin_lock(&obj->iommu_lock);
888 if (--obj->refcount == 0)
891 module_put(obj->owner);
895 spin_unlock(&obj->iommu_lock);
897 dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
901 * OMAP Device MMU(IOMMU) detection
903 static int __devinit omap_iommu_probe(struct platform_device *pdev)
907 struct omap_iommu *obj;
908 struct resource *res;
909 struct iommu_platform_data *pdata = pdev->dev.platform_data;
911 if (pdev->num_resources != 2)
914 obj = kzalloc(sizeof(*obj) + MMU_REG_SIZE, GFP_KERNEL);
918 obj->clk = clk_get(&pdev->dev, pdata->clk_name);
919 if (IS_ERR(obj->clk))
922 obj->nr_tlb_entries = pdata->nr_tlb_entries;
923 obj->name = pdata->name;
924 obj->dev = &pdev->dev;
925 obj->ctx = (void *)obj + sizeof(*obj);
926 obj->da_start = pdata->da_start;
927 obj->da_end = pdata->da_end;
929 spin_lock_init(&obj->iommu_lock);
930 mutex_init(&obj->mmap_lock);
931 spin_lock_init(&obj->page_table_lock);
932 INIT_LIST_HEAD(&obj->mmap);
934 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
940 res = request_mem_region(res->start, resource_size(res),
941 dev_name(&pdev->dev));
947 obj->regbase = ioremap(res->start, resource_size(res));
953 irq = platform_get_irq(pdev, 0);
958 err = request_irq(irq, iommu_fault_handler, IRQF_SHARED,
959 dev_name(&pdev->dev), obj);
962 platform_set_drvdata(pdev, obj);
964 dev_info(&pdev->dev, "%s registered\n", obj->name);
968 iounmap(obj->regbase);
970 release_mem_region(res->start, resource_size(res));
978 static int __devexit omap_iommu_remove(struct platform_device *pdev)
981 struct resource *res;
982 struct omap_iommu *obj = platform_get_drvdata(pdev);
984 platform_set_drvdata(pdev, NULL);
986 iopgtable_clear_entry_all(obj);
988 irq = platform_get_irq(pdev, 0);
990 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
991 release_mem_region(res->start, resource_size(res));
992 iounmap(obj->regbase);
995 dev_info(&pdev->dev, "%s removed\n", obj->name);
1000 static struct platform_driver omap_iommu_driver = {
1001 .probe = omap_iommu_probe,
1002 .remove = __devexit_p(omap_iommu_remove),
1004 .name = "omap-iommu",
1008 static void iopte_cachep_ctor(void *iopte)
1010 clean_dcache_area(iopte, IOPTE_TABLE_SIZE);
1013 static int omap_iommu_map(struct iommu_domain *domain, unsigned long da,
1014 phys_addr_t pa, int order, int prot)
1016 struct omap_iommu_domain *omap_domain = domain->priv;
1017 struct omap_iommu *oiommu = omap_domain->iommu_dev;
1018 struct device *dev = oiommu->dev;
1019 size_t bytes = PAGE_SIZE << order;
1020 struct iotlb_entry e;
1024 /* we only support mapping a single iommu page for now */
1025 omap_pgsz = bytes_to_iopgsz(bytes);
1026 if (omap_pgsz < 0) {
1027 dev_err(dev, "invalid size to map: %d\n", bytes);
1031 dev_dbg(dev, "mapping da 0x%lx to pa 0x%x size 0x%x\n", da, pa, bytes);
1033 flags = omap_pgsz | prot;
1035 iotlb_init_entry(&e, da, pa, flags);
1037 ret = omap_iopgtable_store_entry(oiommu, &e);
1039 dev_err(dev, "omap_iopgtable_store_entry failed: %d\n", ret);
1044 static int omap_iommu_unmap(struct iommu_domain *domain, unsigned long da,
1047 struct omap_iommu_domain *omap_domain = domain->priv;
1048 struct omap_iommu *oiommu = omap_domain->iommu_dev;
1049 struct device *dev = oiommu->dev;
1052 dev_dbg(dev, "unmapping da 0x%lx order %d\n", da, order);
1054 unmap_size = iopgtable_clear_entry(oiommu, da);
1056 return unmap_size ? get_order(unmap_size) : -EINVAL;
1060 omap_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
1062 struct omap_iommu_domain *omap_domain = domain->priv;
1063 struct omap_iommu *oiommu;
1064 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1067 spin_lock(&omap_domain->lock);
1069 /* only a single device is supported per domain for now */
1070 if (omap_domain->iommu_dev) {
1071 dev_err(dev, "iommu domain is already attached\n");
1076 /* get a handle to and enable the omap iommu */
1077 oiommu = omap_iommu_attach(arch_data->name, omap_domain->pgtable);
1078 if (IS_ERR(oiommu)) {
1079 ret = PTR_ERR(oiommu);
1080 dev_err(dev, "can't get omap iommu: %d\n", ret);
1084 omap_domain->iommu_dev = arch_data->iommu_dev = oiommu;
1085 oiommu->domain = domain;
1088 spin_unlock(&omap_domain->lock);
1092 static void omap_iommu_detach_dev(struct iommu_domain *domain,
1095 struct omap_iommu_domain *omap_domain = domain->priv;
1096 struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
1097 struct omap_iommu *oiommu = dev_to_omap_iommu(dev);
1099 spin_lock(&omap_domain->lock);
1101 /* only a single device is supported per domain for now */
1102 if (omap_domain->iommu_dev != oiommu) {
1103 dev_err(dev, "invalid iommu device\n");
1107 iopgtable_clear_entry_all(oiommu);
1109 omap_iommu_detach(oiommu);
1111 omap_domain->iommu_dev = arch_data->iommu_dev = NULL;
1114 spin_unlock(&omap_domain->lock);
1117 static int omap_iommu_domain_init(struct iommu_domain *domain)
1119 struct omap_iommu_domain *omap_domain;
1121 omap_domain = kzalloc(sizeof(*omap_domain), GFP_KERNEL);
1123 pr_err("kzalloc failed\n");
1127 omap_domain->pgtable = kzalloc(IOPGD_TABLE_SIZE, GFP_KERNEL);
1128 if (!omap_domain->pgtable) {
1129 pr_err("kzalloc failed\n");
1134 * should never fail, but please keep this around to ensure
1135 * we keep the hardware happy
1137 BUG_ON(!IS_ALIGNED((long)omap_domain->pgtable, IOPGD_TABLE_SIZE));
1139 clean_dcache_area(omap_domain->pgtable, IOPGD_TABLE_SIZE);
1140 spin_lock_init(&omap_domain->lock);
1142 domain->priv = omap_domain;
1152 /* assume device was already detached */
1153 static void omap_iommu_domain_destroy(struct iommu_domain *domain)
1155 struct omap_iommu_domain *omap_domain = domain->priv;
1157 domain->priv = NULL;
1159 kfree(omap_domain->pgtable);
1163 static phys_addr_t omap_iommu_iova_to_phys(struct iommu_domain *domain,
1166 struct omap_iommu_domain *omap_domain = domain->priv;
1167 struct omap_iommu *oiommu = omap_domain->iommu_dev;
1168 struct device *dev = oiommu->dev;
1170 phys_addr_t ret = 0;
1172 iopgtable_lookup_entry(oiommu, da, &pgd, &pte);
1175 if (iopte_is_small(*pte))
1176 ret = omap_iommu_translate(*pte, da, IOPTE_MASK);
1177 else if (iopte_is_large(*pte))
1178 ret = omap_iommu_translate(*pte, da, IOLARGE_MASK);
1180 dev_err(dev, "bogus pte 0x%x, da 0x%lx", *pte, da);
1182 if (iopgd_is_section(*pgd))
1183 ret = omap_iommu_translate(*pgd, da, IOSECTION_MASK);
1184 else if (iopgd_is_super(*pgd))
1185 ret = omap_iommu_translate(*pgd, da, IOSUPER_MASK);
1187 dev_err(dev, "bogus pgd 0x%x, da 0x%lx", *pgd, da);
1193 static int omap_iommu_domain_has_cap(struct iommu_domain *domain,
1199 static struct iommu_ops omap_iommu_ops = {
1200 .domain_init = omap_iommu_domain_init,
1201 .domain_destroy = omap_iommu_domain_destroy,
1202 .attach_dev = omap_iommu_attach_dev,
1203 .detach_dev = omap_iommu_detach_dev,
1204 .map = omap_iommu_map,
1205 .unmap = omap_iommu_unmap,
1206 .iova_to_phys = omap_iommu_iova_to_phys,
1207 .domain_has_cap = omap_iommu_domain_has_cap,
1210 static int __init omap_iommu_init(void)
1212 struct kmem_cache *p;
1213 const unsigned long flags = SLAB_HWCACHE_ALIGN;
1214 size_t align = 1 << 10; /* L2 pagetable alignement */
1216 p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
1222 bus_set_iommu(&platform_bus_type, &omap_iommu_ops);
1224 return platform_driver_register(&omap_iommu_driver);
1226 module_init(omap_iommu_init);
1228 static void __exit omap_iommu_exit(void)
1230 kmem_cache_destroy(iopte_cachep);
1232 platform_driver_unregister(&omap_iommu_driver);
1234 module_exit(omap_iommu_exit);
1236 MODULE_DESCRIPTION("omap iommu: tlb and pagetable primitives");
1237 MODULE_ALIAS("platform:omap-iommu");
1238 MODULE_AUTHOR("Hiroshi DOYU, Paul Mundt and Toshihiro Kobayashi");
1239 MODULE_LICENSE("GPL v2");