2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
21 #define _ASM_X86_AMD_IOMMU_TYPES_H
23 #include <linux/types.h>
24 #include <linux/mutex.h>
25 #include <linux/list.h>
26 #include <linux/spinlock.h>
29 * Maximum number of IOMMUs supported
34 * some size calculation constants
36 #define DEV_TABLE_ENTRY_SIZE 32
37 #define ALIAS_TABLE_ENTRY_SIZE 2
38 #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
40 /* Length of the MMIO region for the AMD IOMMU */
41 #define MMIO_REGION_LENGTH 0x4000
43 /* Capability offsets used by the driver */
44 #define MMIO_CAP_HDR_OFFSET 0x00
45 #define MMIO_RANGE_OFFSET 0x0c
46 #define MMIO_MISC_OFFSET 0x10
48 /* Masks, shifts and macros to parse the device range capability */
49 #define MMIO_RANGE_LD_MASK 0xff000000
50 #define MMIO_RANGE_FD_MASK 0x00ff0000
51 #define MMIO_RANGE_BUS_MASK 0x0000ff00
52 #define MMIO_RANGE_LD_SHIFT 24
53 #define MMIO_RANGE_FD_SHIFT 16
54 #define MMIO_RANGE_BUS_SHIFT 8
55 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
56 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
57 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
58 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
60 /* Flag masks for the AMD IOMMU exclusion range */
61 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
62 #define MMIO_EXCL_ALLOW_MASK 0x02ULL
64 /* Used offsets into the MMIO space */
65 #define MMIO_DEV_TABLE_OFFSET 0x0000
66 #define MMIO_CMD_BUF_OFFSET 0x0008
67 #define MMIO_EVT_BUF_OFFSET 0x0010
68 #define MMIO_CONTROL_OFFSET 0x0018
69 #define MMIO_EXCL_BASE_OFFSET 0x0020
70 #define MMIO_EXCL_LIMIT_OFFSET 0x0028
71 #define MMIO_EXT_FEATURES 0x0030
72 #define MMIO_PPR_LOG_OFFSET 0x0038
73 #define MMIO_CMD_HEAD_OFFSET 0x2000
74 #define MMIO_CMD_TAIL_OFFSET 0x2008
75 #define MMIO_EVT_HEAD_OFFSET 0x2010
76 #define MMIO_EVT_TAIL_OFFSET 0x2018
77 #define MMIO_STATUS_OFFSET 0x2020
78 #define MMIO_PPR_HEAD_OFFSET 0x2030
79 #define MMIO_PPR_TAIL_OFFSET 0x2038
82 /* Extended Feature Bits */
83 #define FEATURE_PREFETCH (1ULL<<0)
84 #define FEATURE_PPR (1ULL<<1)
85 #define FEATURE_X2APIC (1ULL<<2)
86 #define FEATURE_NX (1ULL<<3)
87 #define FEATURE_GT (1ULL<<4)
88 #define FEATURE_IA (1ULL<<6)
89 #define FEATURE_GA (1ULL<<7)
90 #define FEATURE_HE (1ULL<<8)
91 #define FEATURE_PC (1ULL<<9)
93 #define FEATURE_PASID_SHIFT 32
94 #define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT)
96 #define FEATURE_GLXVAL_SHIFT 14
97 #define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT)
99 #define PASID_MASK 0x000fffff
101 /* MMIO status bits */
102 #define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2)
103 #define MMIO_STATUS_PPR_INT_MASK (1 << 6)
105 /* event logging constants */
106 #define EVENT_ENTRY_SIZE 0x10
107 #define EVENT_TYPE_SHIFT 28
108 #define EVENT_TYPE_MASK 0xf
109 #define EVENT_TYPE_ILL_DEV 0x1
110 #define EVENT_TYPE_IO_FAULT 0x2
111 #define EVENT_TYPE_DEV_TAB_ERR 0x3
112 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
113 #define EVENT_TYPE_ILL_CMD 0x5
114 #define EVENT_TYPE_CMD_HARD_ERR 0x6
115 #define EVENT_TYPE_IOTLB_INV_TO 0x7
116 #define EVENT_TYPE_INV_DEV_REQ 0x8
117 #define EVENT_DEVID_MASK 0xffff
118 #define EVENT_DEVID_SHIFT 0
119 #define EVENT_DOMID_MASK 0xffff
120 #define EVENT_DOMID_SHIFT 0
121 #define EVENT_FLAGS_MASK 0xfff
122 #define EVENT_FLAGS_SHIFT 0x10
124 /* feature control bits */
125 #define CONTROL_IOMMU_EN 0x00ULL
126 #define CONTROL_HT_TUN_EN 0x01ULL
127 #define CONTROL_EVT_LOG_EN 0x02ULL
128 #define CONTROL_EVT_INT_EN 0x03ULL
129 #define CONTROL_COMWAIT_EN 0x04ULL
130 #define CONTROL_PASSPW_EN 0x08ULL
131 #define CONTROL_RESPASSPW_EN 0x09ULL
132 #define CONTROL_COHERENT_EN 0x0aULL
133 #define CONTROL_ISOC_EN 0x0bULL
134 #define CONTROL_CMDBUF_EN 0x0cULL
135 #define CONTROL_PPFLOG_EN 0x0dULL
136 #define CONTROL_PPFINT_EN 0x0eULL
137 #define CONTROL_PPR_EN 0x0fULL
138 #define CONTROL_GT_EN 0x10ULL
140 /* command specific defines */
141 #define CMD_COMPL_WAIT 0x01
142 #define CMD_INV_DEV_ENTRY 0x02
143 #define CMD_INV_IOMMU_PAGES 0x03
144 #define CMD_INV_IOTLB_PAGES 0x04
145 #define CMD_INV_ALL 0x08
147 #define CMD_COMPL_WAIT_STORE_MASK 0x01
148 #define CMD_COMPL_WAIT_INT_MASK 0x02
149 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
150 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
152 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
154 /* macros and definitions for device table entries */
155 #define DEV_ENTRY_VALID 0x00
156 #define DEV_ENTRY_TRANSLATION 0x01
157 #define DEV_ENTRY_IR 0x3d
158 #define DEV_ENTRY_IW 0x3e
159 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
160 #define DEV_ENTRY_EX 0x67
161 #define DEV_ENTRY_SYSMGT1 0x68
162 #define DEV_ENTRY_SYSMGT2 0x69
163 #define DEV_ENTRY_INIT_PASS 0xb8
164 #define DEV_ENTRY_EINT_PASS 0xb9
165 #define DEV_ENTRY_NMI_PASS 0xba
166 #define DEV_ENTRY_LINT0_PASS 0xbe
167 #define DEV_ENTRY_LINT1_PASS 0xbf
168 #define DEV_ENTRY_MODE_MASK 0x07
169 #define DEV_ENTRY_MODE_SHIFT 0x09
171 /* constants to configure the command buffer */
172 #define CMD_BUFFER_SIZE 8192
173 #define CMD_BUFFER_UNINITIALIZED 1
174 #define CMD_BUFFER_ENTRIES 512
175 #define MMIO_CMD_SIZE_SHIFT 56
176 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
178 /* constants for event buffer handling */
179 #define EVT_BUFFER_SIZE 8192 /* 512 entries */
180 #define EVT_LEN_MASK (0x9ULL << 56)
182 /* Constants for PPR Log handling */
183 #define PPR_LOG_ENTRIES 512
184 #define PPR_LOG_SIZE_SHIFT 56
185 #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT)
186 #define PPR_ENTRY_SIZE 16
187 #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
189 #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
190 #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL)
191 #define PPR_DEVID(x) ((x) & 0xffffULL)
192 #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL)
193 #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL)
194 #define PPR_PASID2(x) (((x) >> 42) & 0xfULL)
195 #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x))
197 #define PPR_REQ_FAULT 0x01
199 #define PAGE_MODE_NONE 0x00
200 #define PAGE_MODE_1_LEVEL 0x01
201 #define PAGE_MODE_2_LEVEL 0x02
202 #define PAGE_MODE_3_LEVEL 0x03
203 #define PAGE_MODE_4_LEVEL 0x04
204 #define PAGE_MODE_5_LEVEL 0x05
205 #define PAGE_MODE_6_LEVEL 0x06
207 #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9))
208 #define PM_LEVEL_SIZE(x) (((x) < 6) ? \
209 ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
210 (0xffffffffffffffffULL))
211 #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
212 #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL)
213 #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \
214 IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
215 #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL)
218 #define PM_ADDR_MASK 0x000ffffffffff000ULL
219 #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \
220 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
221 #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr))
224 * Returns the page table level to use for a given page size
225 * Pagesize is expected to be a power-of-two
227 #define PAGE_SIZE_LEVEL(pagesize) \
228 ((__ffs(pagesize) - 12) / 9)
230 * Returns the number of ptes to use for a given page size
231 * Pagesize is expected to be a power-of-two
233 #define PAGE_SIZE_PTE_COUNT(pagesize) \
234 (1ULL << ((__ffs(pagesize) - 12) % 9))
237 * Aligns a given io-virtual address to a given page size
238 * Pagesize is expected to be a power-of-two
240 #define PAGE_SIZE_ALIGN(address, pagesize) \
241 ((address) & ~((pagesize) - 1))
243 * Creates an IOMMU PTE for an address an a given pagesize
244 * The PTE has no permission bits set
245 * Pagesize is expected to be a power-of-two larger than 4096
247 #define PAGE_SIZE_PTE(address, pagesize) \
248 (((address) | ((pagesize) - 1)) & \
249 (~(pagesize >> 1)) & PM_ADDR_MASK)
252 * Takes a PTE value with mode=0x07 and returns the page size it maps
254 #define PTE_PAGE_SIZE(pte) \
255 (1ULL << (1 + ffz(((pte) | 0xfffULL))))
257 #define IOMMU_PTE_P (1ULL << 0)
258 #define IOMMU_PTE_TV (1ULL << 1)
259 #define IOMMU_PTE_U (1ULL << 59)
260 #define IOMMU_PTE_FC (1ULL << 60)
261 #define IOMMU_PTE_IR (1ULL << 61)
262 #define IOMMU_PTE_IW (1ULL << 62)
264 #define DTE_FLAG_IOTLB (0x01UL << 32)
265 #define DTE_FLAG_GV (0x01ULL << 55)
266 #define DTE_GLX_SHIFT (56)
267 #define DTE_GLX_MASK (3)
269 #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL)
270 #define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL)
271 #define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0xfffffULL)
273 #define DTE_GCR3_INDEX_A 0
274 #define DTE_GCR3_INDEX_B 1
275 #define DTE_GCR3_INDEX_C 1
277 #define DTE_GCR3_SHIFT_A 58
278 #define DTE_GCR3_SHIFT_B 16
279 #define DTE_GCR3_SHIFT_C 43
282 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
283 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
284 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
285 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
287 #define IOMMU_PROT_MASK 0x03
288 #define IOMMU_PROT_IR 0x01
289 #define IOMMU_PROT_IW 0x02
291 /* IOMMU capabilities */
292 #define IOMMU_CAP_IOTLB 24
293 #define IOMMU_CAP_NPCACHE 26
294 #define IOMMU_CAP_EFR 27
296 #define MAX_DOMAIN_ID 65536
298 /* FIXME: move this macro to <linux/pci.h> */
299 #define PCI_BUS(x) (((x) >> 8) & 0xff)
301 /* Protection domain flags */
302 #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */
303 #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops
304 domain for an IOMMU */
305 #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page
307 #define PD_IOMMUV2_MASK (1UL << 3) /* domain has gcr3 table */
309 extern bool amd_iommu_dump;
310 #define DUMP_printk(format, arg...) \
312 if (amd_iommu_dump) \
313 printk(KERN_INFO "AMD-Vi: " format, ## arg); \
316 /* global flag if IOMMUs cache non-present entries */
317 extern bool amd_iommu_np_cache;
318 /* Only true if all IOMMUs support device IOTLBs */
319 extern bool amd_iommu_iotlb_sup;
322 * Make iterating over all IOMMUs easier
324 #define for_each_iommu(iommu) \
325 list_for_each_entry((iommu), &amd_iommu_list, list)
326 #define for_each_iommu_safe(iommu, next) \
327 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
329 #define APERTURE_RANGE_SHIFT 27 /* 128 MB */
330 #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT)
331 #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
332 #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */
333 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
334 #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL)
338 * This struct is used to pass information about
339 * incoming PPR faults around.
341 struct amd_iommu_fault {
342 u64 address; /* IO virtual address of the fault*/
343 u32 pasid; /* Address space identifier */
344 u16 device_id; /* Originating PCI device id */
345 u16 tag; /* PPR tag */
346 u16 flags; /* Fault flags */
350 #define PPR_FAULT_EXEC (1 << 1)
351 #define PPR_FAULT_READ (1 << 2)
352 #define PPR_FAULT_WRITE (1 << 5)
353 #define PPR_FAULT_USER (1 << 6)
354 #define PPR_FAULT_RSVD (1 << 7)
355 #define PPR_FAULT_GN (1 << 8)
358 * This structure contains generic data for IOMMU protection domains
359 * independent of their use.
361 struct protection_domain {
362 struct list_head list; /* for list of all protection domains */
363 struct list_head dev_list; /* List of all devices in this domain */
364 spinlock_t lock; /* mostly used to lock the page table*/
365 struct mutex api_lock; /* protect page tables in the iommu-api path */
366 u16 id; /* the domain id written to the device table */
367 int mode; /* paging mode (0-6 levels) */
368 u64 *pt_root; /* page table root pointer */
369 int glx; /* Number of levels for GCR3 table */
370 u64 *gcr3_tbl; /* Guest CR3 table */
371 unsigned long flags; /* flags to find out type of domain */
372 bool updated; /* complete domain flush required */
373 unsigned dev_cnt; /* devices assigned to this domain */
374 unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
375 void *priv; /* private data */
380 * This struct contains device specific data for the IOMMU
382 struct iommu_dev_data {
383 struct list_head list; /* For domain->dev_list */
384 struct list_head dev_data_list; /* For global dev_data_list */
385 struct iommu_dev_data *alias_data;/* The alias dev_data */
386 struct protection_domain *domain; /* Domain the device is bound to */
387 atomic_t bind; /* Domain attach reverent count */
388 u16 devid; /* PCI Device ID */
389 bool iommu_v2; /* Device can make use of IOMMUv2 */
390 bool passthrough; /* Default for device is pt_domain */
394 } ats; /* ATS state */
398 * For dynamic growth the aperture size is split into ranges of 128MB of
399 * DMA address space each. This struct represents one such range.
401 struct aperture_range {
403 /* address allocation bitmap */
404 unsigned long *bitmap;
407 * Array of PTE pages for the aperture. In this array we save all the
408 * leaf pages of the domain page table used for the aperture. This way
409 * we don't need to walk the page table to find a specific PTE. We can
410 * just calculate its address in constant time.
414 unsigned long offset;
418 * Data container for a dma_ops specific protection domain
420 struct dma_ops_domain {
421 struct list_head list;
423 /* generic protection domain information */
424 struct protection_domain domain;
426 /* size of the aperture for the mappings */
427 unsigned long aperture_size;
429 /* address we start to search for free addresses */
430 unsigned long next_address;
432 /* address space relevant data */
433 struct aperture_range *aperture[APERTURE_MAX_RANGES];
435 /* This will be set to true when TLB needs to be flushed */
439 * if this is a preallocated domain, keep the device for which it was
440 * preallocated in this variable
446 * Structure where we save information about one hardware AMD IOMMU in the
450 struct list_head list;
452 /* Index within the IOMMU array */
455 /* locks the accesses to the hardware */
458 /* Pointer to PCI device of this IOMMU */
461 /* physical address of MMIO space */
463 /* virtual address of MMIO space */
466 /* capabilities of that IOMMU read from ACPI */
469 /* flags read from acpi table */
472 /* Extended features */
479 * Capability pointer. There could be more than one IOMMU per PCI
480 * device function if there are more than one AMD IOMMU capability
485 /* pci domain of this IOMMU */
488 /* first device this IOMMU handles. read from PCI */
490 /* last device this IOMMU handles. read from PCI */
493 /* start of exclusion range of that IOMMU */
495 /* length of exclusion range of that IOMMU */
496 u64 exclusion_length;
498 /* command buffer virtual address */
500 /* size of command buffer */
503 /* size of event buffer */
505 /* event buffer virtual address */
507 /* MSI number for event interrupt */
510 /* Base of the PPR log, if present */
513 /* true if interrupts for this IOMMU are already enabled */
516 /* if one, we need to send a completion wait command */
519 /* default dma_ops domain for that IOMMU */
520 struct dma_ops_domain *default_dom;
523 * We can't rely on the BIOS to restore all values on reinit, so we
532 * Each iommu has 6 l1s, each of which is documented as having 0x12
535 u32 stored_l1[6][0x12];
537 /* The l2 indirect registers */
542 * List with all IOMMUs in the system. This list is not locked because it is
543 * only written and read at driver initialization or suspend time
545 extern struct list_head amd_iommu_list;
548 * Array with pointers to each IOMMU struct
549 * The indices are referenced in the protection domains
551 extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
553 /* Number of IOMMUs present in the system */
554 extern int amd_iommus_present;
557 * Declarations for the global list of all protection domains
559 extern spinlock_t amd_iommu_pd_lock;
560 extern struct list_head amd_iommu_pd_list;
563 * Structure defining one entry in the device table
565 struct dev_table_entry {
570 * One entry for unity mappings parsed out of the ACPI table.
572 struct unity_map_entry {
573 struct list_head list;
575 /* starting device id this entry is used for (including) */
577 /* end device id this entry is used for (including) */
580 /* start address to unity map (including) */
582 /* end address to unity map (including) */
585 /* required protection */
590 * List of all unity mappings. It is not locked because as runtime it is only
591 * read. It is created at ACPI table parsing time.
593 extern struct list_head amd_iommu_unity_map;
596 * Data structures for device handling
600 * Device table used by hardware. Read and write accesses by software are
601 * locked with the amd_iommu_pd_table lock.
603 extern struct dev_table_entry *amd_iommu_dev_table;
606 * Alias table to find requestor ids to device ids. Not locked because only
609 extern u16 *amd_iommu_alias_table;
612 * Reverse lookup table to find the IOMMU which translates a specific device.
614 extern struct amd_iommu **amd_iommu_rlookup_table;
616 /* size of the dma_ops aperture as power of 2 */
617 extern unsigned amd_iommu_aperture_order;
619 /* largest PCI device id we expect translation requests for */
620 extern u16 amd_iommu_last_bdf;
622 /* allocation bitmap for domain ids */
623 extern unsigned long *amd_iommu_pd_alloc_bitmap;
626 * If true, the addresses will be flushed on unmap time, not when
629 extern bool amd_iommu_unmap_flush;
631 /* Smallest number of PASIDs supported by any IOMMU in the system */
632 extern u32 amd_iommu_max_pasids;
634 extern bool amd_iommu_v2_present;
636 extern bool amd_iommu_force_isolation;
638 /* Max levels of glxval supported */
639 extern int amd_iommu_max_glx_val;
641 /* takes bus and device/function and returns the device id
642 * FIXME: should that be in generic PCI code? */
643 static inline u16 calc_devid(u8 bus, u8 devfn)
645 return (((u16)bus) << 8) | devfn;
648 #ifdef CONFIG_AMD_IOMMU_STATS
650 struct __iommu_counter {
656 #define DECLARE_STATS_COUNTER(nm) \
657 static struct __iommu_counter nm = { \
661 #define INC_STATS_COUNTER(name) name.value += 1
662 #define ADD_STATS_COUNTER(name, x) name.value += (x)
663 #define SUB_STATS_COUNTER(name, x) name.value -= (x)
665 #else /* CONFIG_AMD_IOMMU_STATS */
667 #define DECLARE_STATS_COUNTER(name)
668 #define INC_STATS_COUNTER(name)
669 #define ADD_STATS_COUNTER(name, x)
670 #define SUB_STATS_COUNTER(name, x)
672 #endif /* CONFIG_AMD_IOMMU_STATS */
674 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */