2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/slab.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <linux/amd-iommu.h>
28 #include <linux/export.h>
29 #include <acpi/acpi.h>
30 #include <asm/pci-direct.h>
31 #include <asm/iommu.h>
33 #include <asm/x86_init.h>
34 #include <asm/iommu_table.h>
35 #include <asm/io_apic.h>
36 #include <asm/irq_remapping.h>
38 #include "amd_iommu_proto.h"
39 #include "amd_iommu_types.h"
40 #include "irq_remapping.h"
43 * definitions for the ACPI scanning code
45 #define IVRS_HEADER_LENGTH 48
47 #define ACPI_IVHD_TYPE 0x10
48 #define ACPI_IVMD_TYPE_ALL 0x20
49 #define ACPI_IVMD_TYPE 0x21
50 #define ACPI_IVMD_TYPE_RANGE 0x22
52 #define IVHD_DEV_ALL 0x01
53 #define IVHD_DEV_SELECT 0x02
54 #define IVHD_DEV_SELECT_RANGE_START 0x03
55 #define IVHD_DEV_RANGE_END 0x04
56 #define IVHD_DEV_ALIAS 0x42
57 #define IVHD_DEV_ALIAS_RANGE 0x43
58 #define IVHD_DEV_EXT_SELECT 0x46
59 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
60 #define IVHD_DEV_SPECIAL 0x48
62 #define IVHD_SPECIAL_IOAPIC 1
63 #define IVHD_SPECIAL_HPET 2
65 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
66 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
67 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
68 #define IVHD_FLAG_ISOC_EN_MASK 0x08
70 #define IVMD_FLAG_EXCL_RANGE 0x08
71 #define IVMD_FLAG_UNITY_MAP 0x01
73 #define ACPI_DEVFLAG_INITPASS 0x01
74 #define ACPI_DEVFLAG_EXTINT 0x02
75 #define ACPI_DEVFLAG_NMI 0x04
76 #define ACPI_DEVFLAG_SYSMGT1 0x10
77 #define ACPI_DEVFLAG_SYSMGT2 0x20
78 #define ACPI_DEVFLAG_LINT0 0x40
79 #define ACPI_DEVFLAG_LINT1 0x80
80 #define ACPI_DEVFLAG_ATSDIS 0x10000000
83 * ACPI table definitions
85 * These data structures are laid over the table to parse the important values
90 * structure describing one IOMMU in the ACPI table. Typically followed by one
91 * or more ivhd_entrys.
103 } __attribute__((packed));
106 * A device entry describing which devices a specific IOMMU translates and
107 * which requestor ids they use.
114 } __attribute__((packed));
117 * An AMD IOMMU memory definition structure. It defines things like exclusion
118 * ranges for devices and regions that should be unity mapped.
129 } __attribute__((packed));
132 bool amd_iommu_irq_remap __read_mostly;
134 static bool amd_iommu_detected;
135 static bool __initdata amd_iommu_disabled;
137 u16 amd_iommu_last_bdf; /* largest PCI device id we have
139 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
141 u32 amd_iommu_unmap_flush; /* if true, flush on every unmap */
143 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
146 /* Array to assign indices to IOMMUs*/
147 struct amd_iommu *amd_iommus[MAX_IOMMUS];
148 int amd_iommus_present;
150 /* IOMMUs have a non-present cache? */
151 bool amd_iommu_np_cache __read_mostly;
152 bool amd_iommu_iotlb_sup __read_mostly = true;
154 u32 amd_iommu_max_pasids __read_mostly = ~0;
156 bool amd_iommu_v2_present __read_mostly;
158 bool amd_iommu_force_isolation __read_mostly;
161 * List of protection domains - used during resume
163 LIST_HEAD(amd_iommu_pd_list);
164 spinlock_t amd_iommu_pd_lock;
167 * Pointer to the device table which is shared by all AMD IOMMUs
168 * it is indexed by the PCI device id or the HT unit id and contains
169 * information about the domain the device belongs to as well as the
170 * page table root pointer.
172 struct dev_table_entry *amd_iommu_dev_table;
175 * The alias table is a driver specific data structure which contains the
176 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
177 * More than one device can share the same requestor id.
179 u16 *amd_iommu_alias_table;
182 * The rlookup table is used to find the IOMMU which is responsible
183 * for a specific device. It is also indexed by the PCI device id.
185 struct amd_iommu **amd_iommu_rlookup_table;
188 * This table is used to find the irq remapping table for a given device id
191 struct irq_remap_table **irq_lookup_table;
194 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
195 * to know which ones are already in use.
197 unsigned long *amd_iommu_pd_alloc_bitmap;
199 static u32 dev_table_size; /* size of the device table */
200 static u32 alias_table_size; /* size of the alias table */
201 static u32 rlookup_table_size; /* size if the rlookup table */
203 enum iommu_init_state {
216 /* Early ioapic and hpet maps from kernel command line */
217 #define EARLY_MAP_SIZE 4
218 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
219 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
220 static int __initdata early_ioapic_map_size;
221 static int __initdata early_hpet_map_size;
223 static enum iommu_init_state init_state = IOMMU_START_STATE;
225 static int amd_iommu_enable_interrupts(void);
226 static int __init iommu_go_to_state(enum iommu_init_state state);
228 static inline void update_last_devid(u16 devid)
230 if (devid > amd_iommu_last_bdf)
231 amd_iommu_last_bdf = devid;
234 static inline unsigned long tbl_size(int entry_size)
236 unsigned shift = PAGE_SHIFT +
237 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
242 /* Access to l1 and l2 indexed register spaces */
244 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
248 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
249 pci_read_config_dword(iommu->dev, 0xfc, &val);
253 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
255 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
256 pci_write_config_dword(iommu->dev, 0xfc, val);
257 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
260 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
264 pci_write_config_dword(iommu->dev, 0xf0, address);
265 pci_read_config_dword(iommu->dev, 0xf4, &val);
269 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
271 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
272 pci_write_config_dword(iommu->dev, 0xf4, val);
275 /****************************************************************************
277 * AMD IOMMU MMIO register space handling functions
279 * These functions are used to program the IOMMU device registers in
280 * MMIO space required for that driver.
282 ****************************************************************************/
285 * This function set the exclusion range in the IOMMU. DMA accesses to the
286 * exclusion range are passed through untranslated
288 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
290 u64 start = iommu->exclusion_start & PAGE_MASK;
291 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
294 if (!iommu->exclusion_start)
297 entry = start | MMIO_EXCL_ENABLE_MASK;
298 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
299 &entry, sizeof(entry));
302 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
303 &entry, sizeof(entry));
306 /* Programs the physical address of the device table into the IOMMU hardware */
307 static void iommu_set_device_table(struct amd_iommu *iommu)
311 BUG_ON(iommu->mmio_base == NULL);
313 entry = virt_to_phys(amd_iommu_dev_table);
314 entry |= (dev_table_size >> 12) - 1;
315 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
316 &entry, sizeof(entry));
319 /* Generic functions to enable/disable certain features of the IOMMU. */
320 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
324 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
326 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
329 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
333 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
335 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
338 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
342 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
343 ctrl &= ~CTRL_INV_TO_MASK;
344 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
345 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
348 /* Function to enable the hardware */
349 static void iommu_enable(struct amd_iommu *iommu)
351 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
354 static void iommu_disable(struct amd_iommu *iommu)
356 /* Disable command buffer */
357 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
359 /* Disable event logging and event interrupts */
360 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
361 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
363 /* Disable IOMMU hardware itself */
364 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
368 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
369 * the system has one.
371 static u8 __iomem * __init iommu_map_mmio_space(u64 address)
373 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) {
374 pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
376 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
380 return (u8 __iomem *)ioremap_nocache(address, MMIO_REGION_LENGTH);
383 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
385 if (iommu->mmio_base)
386 iounmap(iommu->mmio_base);
387 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
390 /****************************************************************************
392 * The functions below belong to the first pass of AMD IOMMU ACPI table
393 * parsing. In this pass we try to find out the highest device id this
394 * code has to handle. Upon this information the size of the shared data
395 * structures is determined later.
397 ****************************************************************************/
400 * This function calculates the length of a given IVHD entry
402 static inline int ivhd_entry_length(u8 *ivhd)
404 return 0x04 << (*ivhd >> 6);
408 * This function reads the last device id the IOMMU has to handle from the PCI
409 * capability header for this IOMMU
411 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
415 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
416 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
422 * After reading the highest device id from the IOMMU PCI capability header
423 * this function looks if there is a higher device id defined in the ACPI table
425 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
427 u8 *p = (void *)h, *end = (void *)h;
428 struct ivhd_entry *dev;
433 find_last_devid_on_pci(PCI_BUS(h->devid),
439 dev = (struct ivhd_entry *)p;
441 case IVHD_DEV_SELECT:
442 case IVHD_DEV_RANGE_END:
444 case IVHD_DEV_EXT_SELECT:
445 /* all the above subfield types refer to device ids */
446 update_last_devid(dev->devid);
451 p += ivhd_entry_length(p);
460 * Iterate over all IVHD entries in the ACPI table and find the highest device
461 * id which we need to handle. This is the first of three functions which parse
462 * the ACPI table. So we check the checksum here.
464 static int __init find_last_devid_acpi(struct acpi_table_header *table)
467 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
468 struct ivhd_header *h;
471 * Validate checksum here so we don't need to do it when
472 * we actually parse the table
474 for (i = 0; i < table->length; ++i)
477 /* ACPI table corrupt */
480 p += IVRS_HEADER_LENGTH;
482 end += table->length;
484 h = (struct ivhd_header *)p;
487 find_last_devid_from_ivhd(h);
499 /****************************************************************************
501 * The following functions belong to the code path which parses the ACPI table
502 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
503 * data structures, initialize the device/alias/rlookup table and also
504 * basically initialize the hardware.
506 ****************************************************************************/
509 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
510 * write commands to that buffer later and the IOMMU will execute them
513 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
515 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
516 get_order(CMD_BUFFER_SIZE));
521 iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
527 * This function resets the command buffer if the IOMMU stopped fetching
530 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
532 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
534 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
535 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
537 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
541 * This function writes the command buffer address to the hardware and
544 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
548 BUG_ON(iommu->cmd_buf == NULL);
550 entry = (u64)virt_to_phys(iommu->cmd_buf);
551 entry |= MMIO_CMD_SIZE_512;
553 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
554 &entry, sizeof(entry));
556 amd_iommu_reset_cmd_buffer(iommu);
557 iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
560 static void __init free_command_buffer(struct amd_iommu *iommu)
562 free_pages((unsigned long)iommu->cmd_buf,
563 get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
566 /* allocates the memory where the IOMMU will log its events to */
567 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
569 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
570 get_order(EVT_BUFFER_SIZE));
572 if (iommu->evt_buf == NULL)
575 iommu->evt_buf_size = EVT_BUFFER_SIZE;
577 return iommu->evt_buf;
580 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
584 BUG_ON(iommu->evt_buf == NULL);
586 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
588 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
589 &entry, sizeof(entry));
591 /* set head and tail to zero manually */
592 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
593 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
595 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
598 static void __init free_event_buffer(struct amd_iommu *iommu)
600 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
603 /* allocates the memory where the IOMMU will log its events to */
604 static u8 * __init alloc_ppr_log(struct amd_iommu *iommu)
606 iommu->ppr_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
607 get_order(PPR_LOG_SIZE));
609 if (iommu->ppr_log == NULL)
612 return iommu->ppr_log;
615 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
619 if (iommu->ppr_log == NULL)
622 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
624 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
625 &entry, sizeof(entry));
627 /* set head and tail to zero manually */
628 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
629 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
631 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
632 iommu_feature_enable(iommu, CONTROL_PPR_EN);
635 static void __init free_ppr_log(struct amd_iommu *iommu)
637 if (iommu->ppr_log == NULL)
640 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
643 static void iommu_enable_gt(struct amd_iommu *iommu)
645 if (!iommu_feature(iommu, FEATURE_GT))
648 iommu_feature_enable(iommu, CONTROL_GT_EN);
651 /* sets a specific bit in the device table entry. */
652 static void set_dev_entry_bit(u16 devid, u8 bit)
654 int i = (bit >> 6) & 0x03;
655 int _bit = bit & 0x3f;
657 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
660 static int get_dev_entry_bit(u16 devid, u8 bit)
662 int i = (bit >> 6) & 0x03;
663 int _bit = bit & 0x3f;
665 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
669 void amd_iommu_apply_erratum_63(u16 devid)
673 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
674 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
677 set_dev_entry_bit(devid, DEV_ENTRY_IW);
680 /* Writes the specific IOMMU for a device into the rlookup table */
681 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
683 amd_iommu_rlookup_table[devid] = iommu;
687 * This function takes the device specific flags read from the ACPI
688 * table and sets up the device table entry with that information
690 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
691 u16 devid, u32 flags, u32 ext_flags)
693 if (flags & ACPI_DEVFLAG_INITPASS)
694 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
695 if (flags & ACPI_DEVFLAG_EXTINT)
696 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
697 if (flags & ACPI_DEVFLAG_NMI)
698 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
699 if (flags & ACPI_DEVFLAG_SYSMGT1)
700 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
701 if (flags & ACPI_DEVFLAG_SYSMGT2)
702 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
703 if (flags & ACPI_DEVFLAG_LINT0)
704 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
705 if (flags & ACPI_DEVFLAG_LINT1)
706 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
708 amd_iommu_apply_erratum_63(devid);
710 set_iommu_for_device(iommu, devid);
713 static int __init add_special_device(u8 type, u8 id, u16 devid, bool cmd_line)
715 struct devid_map *entry;
716 struct list_head *list;
718 if (type == IVHD_SPECIAL_IOAPIC)
720 else if (type == IVHD_SPECIAL_HPET)
725 list_for_each_entry(entry, list, list) {
726 if (!(entry->id == id && entry->cmd_line))
729 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
730 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
735 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
740 entry->devid = devid;
741 entry->cmd_line = cmd_line;
743 list_add_tail(&entry->list, list);
748 static int __init add_early_maps(void)
752 for (i = 0; i < early_ioapic_map_size; ++i) {
753 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
754 early_ioapic_map[i].id,
755 early_ioapic_map[i].devid,
756 early_ioapic_map[i].cmd_line);
761 for (i = 0; i < early_hpet_map_size; ++i) {
762 ret = add_special_device(IVHD_SPECIAL_HPET,
763 early_hpet_map[i].id,
764 early_hpet_map[i].devid,
765 early_hpet_map[i].cmd_line);
774 * Reads the device exclusion range from ACPI and initializes the IOMMU with
777 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
779 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
781 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
786 * We only can configure exclusion ranges per IOMMU, not
787 * per device. But we can enable the exclusion range per
788 * device. This is done here
790 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
791 iommu->exclusion_start = m->range_start;
792 iommu->exclusion_length = m->range_length;
797 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
798 * initializes the hardware and our data structures with it.
800 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
801 struct ivhd_header *h)
804 u8 *end = p, flags = 0;
805 u16 devid = 0, devid_start = 0, devid_to = 0;
806 u32 dev_i, ext_flags = 0;
808 struct ivhd_entry *e;
812 ret = add_early_maps();
817 * First save the recommended feature enable bits from ACPI
819 iommu->acpi_flags = h->flags;
822 * Done. Now parse the device entries
824 p += sizeof(struct ivhd_header);
829 e = (struct ivhd_entry *)p;
833 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
834 " last device %02x:%02x.%x flags: %02x\n",
835 PCI_BUS(iommu->first_device),
836 PCI_SLOT(iommu->first_device),
837 PCI_FUNC(iommu->first_device),
838 PCI_BUS(iommu->last_device),
839 PCI_SLOT(iommu->last_device),
840 PCI_FUNC(iommu->last_device),
843 for (dev_i = iommu->first_device;
844 dev_i <= iommu->last_device; ++dev_i)
845 set_dev_entry_from_acpi(iommu, dev_i,
848 case IVHD_DEV_SELECT:
850 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
858 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
860 case IVHD_DEV_SELECT_RANGE_START:
862 DUMP_printk(" DEV_SELECT_RANGE_START\t "
863 "devid: %02x:%02x.%x flags: %02x\n",
869 devid_start = e->devid;
876 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
877 "flags: %02x devid_to: %02x:%02x.%x\n",
882 PCI_BUS(e->ext >> 8),
883 PCI_SLOT(e->ext >> 8),
884 PCI_FUNC(e->ext >> 8));
887 devid_to = e->ext >> 8;
888 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
889 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
890 amd_iommu_alias_table[devid] = devid_to;
892 case IVHD_DEV_ALIAS_RANGE:
894 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
895 "devid: %02x:%02x.%x flags: %02x "
896 "devid_to: %02x:%02x.%x\n",
901 PCI_BUS(e->ext >> 8),
902 PCI_SLOT(e->ext >> 8),
903 PCI_FUNC(e->ext >> 8));
905 devid_start = e->devid;
907 devid_to = e->ext >> 8;
911 case IVHD_DEV_EXT_SELECT:
913 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
914 "flags: %02x ext: %08x\n",
921 set_dev_entry_from_acpi(iommu, devid, e->flags,
924 case IVHD_DEV_EXT_SELECT_RANGE:
926 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
927 "%02x:%02x.%x flags: %02x ext: %08x\n",
933 devid_start = e->devid;
938 case IVHD_DEV_RANGE_END:
940 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
946 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
948 amd_iommu_alias_table[dev_i] = devid_to;
949 set_dev_entry_from_acpi(iommu,
950 devid_to, flags, ext_flags);
952 set_dev_entry_from_acpi(iommu, dev_i,
956 case IVHD_DEV_SPECIAL: {
962 handle = e->ext & 0xff;
963 devid = (e->ext >> 8) & 0xffff;
964 type = (e->ext >> 24) & 0xff;
966 if (type == IVHD_SPECIAL_IOAPIC)
968 else if (type == IVHD_SPECIAL_HPET)
973 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
979 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
980 ret = add_special_device(type, handle, devid, false);
989 p += ivhd_entry_length(p);
995 /* Initializes the device->iommu mapping for the driver */
996 static int __init init_iommu_devices(struct amd_iommu *iommu)
1000 for (i = iommu->first_device; i <= iommu->last_device; ++i)
1001 set_iommu_for_device(iommu, i);
1006 static void __init free_iommu_one(struct amd_iommu *iommu)
1008 free_command_buffer(iommu);
1009 free_event_buffer(iommu);
1010 free_ppr_log(iommu);
1011 iommu_unmap_mmio_space(iommu);
1014 static void __init free_iommu_all(void)
1016 struct amd_iommu *iommu, *next;
1018 for_each_iommu_safe(iommu, next) {
1019 list_del(&iommu->list);
1020 free_iommu_one(iommu);
1026 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1028 * BIOS should disable L2B micellaneous clock gating by setting
1029 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1031 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1035 if ((boot_cpu_data.x86 != 0x15) ||
1036 (boot_cpu_data.x86_model < 0x10) ||
1037 (boot_cpu_data.x86_model > 0x1f))
1040 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1041 pci_read_config_dword(iommu->dev, 0xf4, &value);
1046 /* Select NB indirect register 0x90 and enable writing */
1047 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1049 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1050 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1051 dev_name(&iommu->dev->dev));
1053 /* Clear the enable writing bit */
1054 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1058 * This function clues the initialization function for one IOMMU
1059 * together and also allocates the command buffer and programs the
1060 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1062 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1066 spin_lock_init(&iommu->lock);
1068 /* Add IOMMU to internal data structures */
1069 list_add_tail(&iommu->list, &amd_iommu_list);
1070 iommu->index = amd_iommus_present++;
1072 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1073 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1077 /* Index is fine - add IOMMU to the array */
1078 amd_iommus[iommu->index] = iommu;
1081 * Copy data from ACPI table entry to the iommu struct
1083 iommu->devid = h->devid;
1084 iommu->cap_ptr = h->cap_ptr;
1085 iommu->pci_seg = h->pci_seg;
1086 iommu->mmio_phys = h->mmio_phys;
1087 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
1088 if (!iommu->mmio_base)
1091 iommu->cmd_buf = alloc_command_buffer(iommu);
1092 if (!iommu->cmd_buf)
1095 iommu->evt_buf = alloc_event_buffer(iommu);
1096 if (!iommu->evt_buf)
1099 iommu->int_enabled = false;
1101 ret = init_iommu_from_acpi(iommu, h);
1106 * Make sure IOMMU is not considered to translate itself. The IVRS
1107 * table tells us so, but this is a lie!
1109 amd_iommu_rlookup_table[iommu->devid] = NULL;
1111 init_iommu_devices(iommu);
1117 * Iterates over all IOMMU entries in the ACPI table, allocates the
1118 * IOMMU structure and initializes it with init_iommu_one()
1120 static int __init init_iommu_all(struct acpi_table_header *table)
1122 u8 *p = (u8 *)table, *end = (u8 *)table;
1123 struct ivhd_header *h;
1124 struct amd_iommu *iommu;
1127 end += table->length;
1128 p += IVRS_HEADER_LENGTH;
1131 h = (struct ivhd_header *)p;
1133 case ACPI_IVHD_TYPE:
1135 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1136 "seg: %d flags: %01x info %04x\n",
1137 PCI_BUS(h->devid), PCI_SLOT(h->devid),
1138 PCI_FUNC(h->devid), h->cap_ptr,
1139 h->pci_seg, h->flags, h->info);
1140 DUMP_printk(" mmio-addr: %016llx\n",
1143 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1147 ret = init_iommu_one(iommu, h);
1162 static int iommu_init_pci(struct amd_iommu *iommu)
1164 int cap_ptr = iommu->cap_ptr;
1165 u32 range, misc, low, high;
1167 iommu->dev = pci_get_bus_and_slot(PCI_BUS(iommu->devid),
1168 iommu->devid & 0xff);
1172 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1174 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1176 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1179 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
1180 MMIO_GET_FD(range));
1181 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
1182 MMIO_GET_LD(range));
1184 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1185 amd_iommu_iotlb_sup = false;
1187 /* read extended feature bits */
1188 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1189 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1191 iommu->features = ((u64)high << 32) | low;
1193 if (iommu_feature(iommu, FEATURE_GT)) {
1198 shift = iommu->features & FEATURE_PASID_MASK;
1199 shift >>= FEATURE_PASID_SHIFT;
1200 pasids = (1 << shift);
1202 amd_iommu_max_pasids = min(amd_iommu_max_pasids, pasids);
1204 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1205 glxval >>= FEATURE_GLXVAL_SHIFT;
1207 if (amd_iommu_max_glx_val == -1)
1208 amd_iommu_max_glx_val = glxval;
1210 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1213 if (iommu_feature(iommu, FEATURE_GT) &&
1214 iommu_feature(iommu, FEATURE_PPR)) {
1215 iommu->is_iommu_v2 = true;
1216 amd_iommu_v2_present = true;
1219 if (iommu_feature(iommu, FEATURE_PPR)) {
1220 iommu->ppr_log = alloc_ppr_log(iommu);
1221 if (!iommu->ppr_log)
1225 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1226 amd_iommu_np_cache = true;
1228 if (is_rd890_iommu(iommu->dev)) {
1231 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1235 * Some rd890 systems may not be fully reconfigured by the
1236 * BIOS, so it's necessary for us to store this information so
1237 * it can be reprogrammed on resume
1239 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1240 &iommu->stored_addr_lo);
1241 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1242 &iommu->stored_addr_hi);
1244 /* Low bit locks writes to configuration space */
1245 iommu->stored_addr_lo &= ~1;
1247 for (i = 0; i < 6; i++)
1248 for (j = 0; j < 0x12; j++)
1249 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1251 for (i = 0; i < 0x83; i++)
1252 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1255 amd_iommu_erratum_746_workaround(iommu);
1257 return pci_enable_device(iommu->dev);
1260 static void print_iommu_info(void)
1262 static const char * const feat_str[] = {
1263 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1264 "IA", "GA", "HE", "PC"
1266 struct amd_iommu *iommu;
1268 for_each_iommu(iommu) {
1271 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1272 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1274 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1275 pr_info("AMD-Vi: Extended features: ");
1276 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1277 if (iommu_feature(iommu, (1ULL << i)))
1278 pr_cont(" %s", feat_str[i]);
1283 if (irq_remapping_enabled)
1284 pr_info("AMD-Vi: Interrupt remapping enabled\n");
1287 static int __init amd_iommu_init_pci(void)
1289 struct amd_iommu *iommu;
1292 for_each_iommu(iommu) {
1293 ret = iommu_init_pci(iommu);
1298 ret = amd_iommu_init_devices();
1305 /****************************************************************************
1307 * The following functions initialize the MSI interrupts for all IOMMUs
1308 * in the system. It's a bit challenging because there could be multiple
1309 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1312 ****************************************************************************/
1314 static int iommu_setup_msi(struct amd_iommu *iommu)
1318 r = pci_enable_msi(iommu->dev);
1322 r = request_threaded_irq(iommu->dev->irq,
1323 amd_iommu_int_handler,
1324 amd_iommu_int_thread,
1329 pci_disable_msi(iommu->dev);
1333 iommu->int_enabled = true;
1338 static int iommu_init_msi(struct amd_iommu *iommu)
1342 if (iommu->int_enabled)
1345 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
1346 ret = iommu_setup_msi(iommu);
1354 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1356 if (iommu->ppr_log != NULL)
1357 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1362 /****************************************************************************
1364 * The next functions belong to the third pass of parsing the ACPI
1365 * table. In this last pass the memory mapping requirements are
1366 * gathered (like exclusion and unity mapping ranges).
1368 ****************************************************************************/
1370 static void __init free_unity_maps(void)
1372 struct unity_map_entry *entry, *next;
1374 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1375 list_del(&entry->list);
1380 /* called when we find an exclusion range definition in ACPI */
1381 static int __init init_exclusion_range(struct ivmd_header *m)
1386 case ACPI_IVMD_TYPE:
1387 set_device_exclusion_range(m->devid, m);
1389 case ACPI_IVMD_TYPE_ALL:
1390 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1391 set_device_exclusion_range(i, m);
1393 case ACPI_IVMD_TYPE_RANGE:
1394 for (i = m->devid; i <= m->aux; ++i)
1395 set_device_exclusion_range(i, m);
1404 /* called for unity map ACPI definition */
1405 static int __init init_unity_map_range(struct ivmd_header *m)
1407 struct unity_map_entry *e = NULL;
1410 e = kzalloc(sizeof(*e), GFP_KERNEL);
1418 case ACPI_IVMD_TYPE:
1419 s = "IVMD_TYPEi\t\t\t";
1420 e->devid_start = e->devid_end = m->devid;
1422 case ACPI_IVMD_TYPE_ALL:
1423 s = "IVMD_TYPE_ALL\t\t";
1425 e->devid_end = amd_iommu_last_bdf;
1427 case ACPI_IVMD_TYPE_RANGE:
1428 s = "IVMD_TYPE_RANGE\t\t";
1429 e->devid_start = m->devid;
1430 e->devid_end = m->aux;
1433 e->address_start = PAGE_ALIGN(m->range_start);
1434 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1435 e->prot = m->flags >> 1;
1437 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1438 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1439 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1440 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1441 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1442 e->address_start, e->address_end, m->flags);
1444 list_add_tail(&e->list, &amd_iommu_unity_map);
1449 /* iterates over all memory definitions we find in the ACPI table */
1450 static int __init init_memory_definitions(struct acpi_table_header *table)
1452 u8 *p = (u8 *)table, *end = (u8 *)table;
1453 struct ivmd_header *m;
1455 end += table->length;
1456 p += IVRS_HEADER_LENGTH;
1459 m = (struct ivmd_header *)p;
1460 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1461 init_exclusion_range(m);
1462 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1463 init_unity_map_range(m);
1472 * Init the device table to not allow DMA access for devices and
1473 * suppress all page faults
1475 static void init_device_table_dma(void)
1479 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1480 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1481 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1485 static void __init uninit_device_table_dma(void)
1489 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1490 amd_iommu_dev_table[devid].data[0] = 0ULL;
1491 amd_iommu_dev_table[devid].data[1] = 0ULL;
1495 static void init_device_table(void)
1499 if (!amd_iommu_irq_remap)
1502 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1503 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1506 static void iommu_init_flags(struct amd_iommu *iommu)
1508 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1509 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1510 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1512 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1513 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1514 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1516 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1517 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1518 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1520 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1521 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1522 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1525 * make IOMMU memory accesses cache coherent
1527 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1529 /* Set IOTLB invalidation timeout to 1s */
1530 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1533 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1536 u32 ioc_feature_control;
1537 struct pci_dev *pdev = iommu->root_pdev;
1539 /* RD890 BIOSes may not have completely reconfigured the iommu */
1540 if (!is_rd890_iommu(iommu->dev) || !pdev)
1544 * First, we need to ensure that the iommu is enabled. This is
1545 * controlled by a register in the northbridge
1548 /* Select Northbridge indirect register 0x75 and enable writing */
1549 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1550 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1552 /* Enable the iommu */
1553 if (!(ioc_feature_control & 0x1))
1554 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1556 /* Restore the iommu BAR */
1557 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1558 iommu->stored_addr_lo);
1559 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1560 iommu->stored_addr_hi);
1562 /* Restore the l1 indirect regs for each of the 6 l1s */
1563 for (i = 0; i < 6; i++)
1564 for (j = 0; j < 0x12; j++)
1565 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1567 /* Restore the l2 indirect regs */
1568 for (i = 0; i < 0x83; i++)
1569 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1571 /* Lock PCI setup registers */
1572 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1573 iommu->stored_addr_lo | 1);
1577 * This function finally enables all IOMMUs found in the system after
1578 * they have been initialized
1580 static void early_enable_iommus(void)
1582 struct amd_iommu *iommu;
1584 for_each_iommu(iommu) {
1585 iommu_disable(iommu);
1586 iommu_init_flags(iommu);
1587 iommu_set_device_table(iommu);
1588 iommu_enable_command_buffer(iommu);
1589 iommu_enable_event_buffer(iommu);
1590 iommu_set_exclusion_range(iommu);
1591 iommu_enable(iommu);
1592 iommu_flush_all_caches(iommu);
1596 static void enable_iommus_v2(void)
1598 struct amd_iommu *iommu;
1600 for_each_iommu(iommu) {
1601 iommu_enable_ppr_log(iommu);
1602 iommu_enable_gt(iommu);
1606 static void enable_iommus(void)
1608 early_enable_iommus();
1613 static void disable_iommus(void)
1615 struct amd_iommu *iommu;
1617 for_each_iommu(iommu)
1618 iommu_disable(iommu);
1622 * Suspend/Resume support
1623 * disable suspend until real resume implemented
1626 static void amd_iommu_resume(void)
1628 struct amd_iommu *iommu;
1630 for_each_iommu(iommu)
1631 iommu_apply_resume_quirks(iommu);
1633 /* re-load the hardware */
1636 amd_iommu_enable_interrupts();
1639 static int amd_iommu_suspend(void)
1641 /* disable IOMMUs to go out of the way for BIOS */
1647 static struct syscore_ops amd_iommu_syscore_ops = {
1648 .suspend = amd_iommu_suspend,
1649 .resume = amd_iommu_resume,
1652 static void __init free_on_init_error(void)
1654 free_pages((unsigned long)irq_lookup_table,
1655 get_order(rlookup_table_size));
1657 if (amd_iommu_irq_cache) {
1658 kmem_cache_destroy(amd_iommu_irq_cache);
1659 amd_iommu_irq_cache = NULL;
1663 free_pages((unsigned long)amd_iommu_rlookup_table,
1664 get_order(rlookup_table_size));
1666 free_pages((unsigned long)amd_iommu_alias_table,
1667 get_order(alias_table_size));
1669 free_pages((unsigned long)amd_iommu_dev_table,
1670 get_order(dev_table_size));
1674 #ifdef CONFIG_GART_IOMMU
1676 * We failed to initialize the AMD IOMMU - try fallback to GART
1684 /* SB IOAPIC is always on this device in AMD systems */
1685 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
1687 static bool __init check_ioapic_information(void)
1689 bool ret, has_sb_ioapic;
1692 has_sb_ioapic = false;
1695 for (idx = 0; idx < nr_ioapics; idx++) {
1696 int devid, id = mpc_ioapic_id(idx);
1698 devid = get_ioapic_devid(id);
1700 pr_err(FW_BUG "AMD-Vi: IOAPIC[%d] not in IVRS table\n", id);
1702 } else if (devid == IOAPIC_SB_DEVID) {
1703 has_sb_ioapic = true;
1708 if (!has_sb_ioapic) {
1710 * We expect the SB IOAPIC to be listed in the IVRS
1711 * table. The system timer is connected to the SB IOAPIC
1712 * and if we don't have it in the list the system will
1713 * panic at boot time. This situation usually happens
1714 * when the BIOS is buggy and provides us the wrong
1715 * device id for the IOAPIC in the system.
1717 pr_err(FW_BUG "AMD-Vi: No southbridge IOAPIC found in IVRS table\n");
1721 pr_err("AMD-Vi: Disabling interrupt remapping due to BIOS Bug(s)\n");
1726 static void __init free_dma_resources(void)
1728 amd_iommu_uninit_devices();
1730 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1731 get_order(MAX_DOMAIN_ID/8));
1737 * This is the hardware init function for AMD IOMMU in the system.
1738 * This function is called either from amd_iommu_init or from the interrupt
1739 * remapping setup code.
1741 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1744 * 1 pass) Find the highest PCI device id the driver has to handle.
1745 * Upon this information the size of the data structures is
1746 * determined that needs to be allocated.
1748 * 2 pass) Initialize the data structures just allocated with the
1749 * information in the ACPI table about available AMD IOMMUs
1750 * in the system. It also maps the PCI devices in the
1751 * system to specific IOMMUs
1753 * 3 pass) After the basic data structures are allocated and
1754 * initialized we update them with information about memory
1755 * remapping requirements parsed out of the ACPI table in
1758 * After everything is set up the IOMMUs are enabled and the necessary
1759 * hotplug and suspend notifiers are registered.
1761 static int __init early_amd_iommu_init(void)
1763 struct acpi_table_header *ivrs_base;
1764 acpi_size ivrs_size;
1768 if (!amd_iommu_detected)
1771 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1772 if (status == AE_NOT_FOUND)
1774 else if (ACPI_FAILURE(status)) {
1775 const char *err = acpi_format_exception(status);
1776 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1781 * First parse ACPI tables to find the largest Bus/Dev/Func
1782 * we need to handle. Upon this information the shared data
1783 * structures for the IOMMUs in the system will be allocated
1785 ret = find_last_devid_acpi(ivrs_base);
1789 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1790 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1791 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1793 /* Device table - directly used by all IOMMUs */
1795 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1796 get_order(dev_table_size));
1797 if (amd_iommu_dev_table == NULL)
1801 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1802 * IOMMU see for that device
1804 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1805 get_order(alias_table_size));
1806 if (amd_iommu_alias_table == NULL)
1809 /* IOMMU rlookup table - find the IOMMU for a specific device */
1810 amd_iommu_rlookup_table = (void *)__get_free_pages(
1811 GFP_KERNEL | __GFP_ZERO,
1812 get_order(rlookup_table_size));
1813 if (amd_iommu_rlookup_table == NULL)
1816 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1817 GFP_KERNEL | __GFP_ZERO,
1818 get_order(MAX_DOMAIN_ID/8));
1819 if (amd_iommu_pd_alloc_bitmap == NULL)
1823 * let all alias entries point to itself
1825 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1826 amd_iommu_alias_table[i] = i;
1829 * never allocate domain 0 because its used as the non-allocated and
1830 * error value placeholder
1832 amd_iommu_pd_alloc_bitmap[0] = 1;
1834 spin_lock_init(&amd_iommu_pd_lock);
1837 * now the data structures are allocated and basically initialized
1838 * start the real acpi table scan
1840 ret = init_iommu_all(ivrs_base);
1844 if (amd_iommu_irq_remap)
1845 amd_iommu_irq_remap = check_ioapic_information();
1847 if (amd_iommu_irq_remap) {
1849 * Interrupt remapping enabled, create kmem_cache for the
1852 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
1853 MAX_IRQS_PER_TABLE * sizeof(u32),
1854 IRQ_TABLE_ALIGNMENT,
1856 if (!amd_iommu_irq_cache)
1859 irq_lookup_table = (void *)__get_free_pages(
1860 GFP_KERNEL | __GFP_ZERO,
1861 get_order(rlookup_table_size));
1862 if (!irq_lookup_table)
1866 ret = init_memory_definitions(ivrs_base);
1870 /* init the device table */
1871 init_device_table();
1874 /* Don't leak any ACPI memory */
1875 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1881 static int amd_iommu_enable_interrupts(void)
1883 struct amd_iommu *iommu;
1886 for_each_iommu(iommu) {
1887 ret = iommu_init_msi(iommu);
1896 static bool detect_ivrs(void)
1898 struct acpi_table_header *ivrs_base;
1899 acpi_size ivrs_size;
1902 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
1903 if (status == AE_NOT_FOUND)
1905 else if (ACPI_FAILURE(status)) {
1906 const char *err = acpi_format_exception(status);
1907 pr_err("AMD-Vi: IVRS table error: %s\n", err);
1911 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
1913 /* Make sure ACS will be enabled during PCI probe */
1916 if (!disable_irq_remap)
1917 amd_iommu_irq_remap = true;
1922 static int amd_iommu_init_dma(void)
1924 struct amd_iommu *iommu;
1927 if (iommu_pass_through)
1928 ret = amd_iommu_init_passthrough();
1930 ret = amd_iommu_init_dma_ops();
1935 init_device_table_dma();
1937 for_each_iommu(iommu)
1938 iommu_flush_all_caches(iommu);
1940 amd_iommu_init_api();
1942 amd_iommu_init_notifier();
1947 /****************************************************************************
1949 * AMD IOMMU Initialization State Machine
1951 ****************************************************************************/
1953 static int __init state_next(void)
1957 switch (init_state) {
1958 case IOMMU_START_STATE:
1959 if (!detect_ivrs()) {
1960 init_state = IOMMU_NOT_FOUND;
1963 init_state = IOMMU_IVRS_DETECTED;
1966 case IOMMU_IVRS_DETECTED:
1967 ret = early_amd_iommu_init();
1968 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
1970 case IOMMU_ACPI_FINISHED:
1971 early_enable_iommus();
1972 register_syscore_ops(&amd_iommu_syscore_ops);
1973 x86_platform.iommu_shutdown = disable_iommus;
1974 init_state = IOMMU_ENABLED;
1977 ret = amd_iommu_init_pci();
1978 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
1981 case IOMMU_PCI_INIT:
1982 ret = amd_iommu_enable_interrupts();
1983 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
1985 case IOMMU_INTERRUPTS_EN:
1986 ret = amd_iommu_init_dma();
1987 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
1990 init_state = IOMMU_INITIALIZED;
1992 case IOMMU_INITIALIZED:
1995 case IOMMU_NOT_FOUND:
1996 case IOMMU_INIT_ERROR:
1997 /* Error states => do nothing */
2008 static int __init iommu_go_to_state(enum iommu_init_state state)
2012 while (init_state != state) {
2014 if (init_state == IOMMU_NOT_FOUND ||
2015 init_state == IOMMU_INIT_ERROR)
2022 #ifdef CONFIG_IRQ_REMAP
2023 int __init amd_iommu_prepare(void)
2025 return iommu_go_to_state(IOMMU_ACPI_FINISHED);
2028 int __init amd_iommu_supported(void)
2030 return amd_iommu_irq_remap ? 1 : 0;
2033 int __init amd_iommu_enable(void)
2037 ret = iommu_go_to_state(IOMMU_ENABLED);
2041 irq_remapping_enabled = 1;
2046 void amd_iommu_disable(void)
2048 amd_iommu_suspend();
2051 int amd_iommu_reenable(int mode)
2058 int __init amd_iommu_enable_faulting(void)
2060 /* We enable MSI later when PCI is initialized */
2066 * This is the core init function for AMD IOMMU hardware in the system.
2067 * This function is called from the generic x86 DMA layer initialization
2070 static int __init amd_iommu_init(void)
2074 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2076 free_dma_resources();
2077 if (!irq_remapping_enabled) {
2079 free_on_init_error();
2081 struct amd_iommu *iommu;
2083 uninit_device_table_dma();
2084 for_each_iommu(iommu)
2085 iommu_flush_all_caches(iommu);
2092 /****************************************************************************
2094 * Early detect code. This code runs at IOMMU detection time in the DMA
2095 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2098 ****************************************************************************/
2099 int __init amd_iommu_detect(void)
2103 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2106 if (amd_iommu_disabled)
2109 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2113 amd_iommu_detected = true;
2115 x86_init.iommu.iommu_init = amd_iommu_init;
2120 /****************************************************************************
2122 * Parsing functions for the AMD IOMMU specific kernel command line
2125 ****************************************************************************/
2127 static int __init parse_amd_iommu_dump(char *str)
2129 amd_iommu_dump = true;
2134 static int __init parse_amd_iommu_options(char *str)
2136 for (; *str; ++str) {
2137 if (strncmp(str, "fullflush", 9) == 0)
2138 amd_iommu_unmap_flush = true;
2139 if (strncmp(str, "off", 3) == 0)
2140 amd_iommu_disabled = true;
2141 if (strncmp(str, "force_isolation", 15) == 0)
2142 amd_iommu_force_isolation = true;
2148 static int __init parse_ivrs_ioapic(char *str)
2150 unsigned int bus, dev, fn;
2154 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2157 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2161 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2162 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2167 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2169 i = early_ioapic_map_size++;
2170 early_ioapic_map[i].id = id;
2171 early_ioapic_map[i].devid = devid;
2172 early_ioapic_map[i].cmd_line = true;
2177 static int __init parse_ivrs_hpet(char *str)
2179 unsigned int bus, dev, fn;
2183 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2186 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2190 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2191 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2196 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2198 i = early_hpet_map_size++;
2199 early_hpet_map[i].id = id;
2200 early_hpet_map[i].devid = devid;
2201 early_hpet_map[i].cmd_line = true;
2206 __setup("amd_iommu_dump", parse_amd_iommu_dump);
2207 __setup("amd_iommu=", parse_amd_iommu_options);
2208 __setup("ivrs_ioapic", parse_ivrs_ioapic);
2209 __setup("ivrs_hpet", parse_ivrs_hpet);
2211 IOMMU_INIT_FINISH(amd_iommu_detect,
2212 gart_iommu_hole_init,
2216 bool amd_iommu_v2_supported(void)
2218 return amd_iommu_v2_present;
2220 EXPORT_SYMBOL(amd_iommu_v2_supported);