2 * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
4 * Copyright (c) 2005, 2006 PathScale, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <rdma/ib_mad.h>
36 #include <rdma/ib_user_verbs.h>
38 #include <linux/utsname.h>
39 #include <linux/rculist.h>
41 #include <linux/random.h>
44 #include "qib_common.h"
46 static unsigned int ib_qib_qp_table_size = 256;
47 module_param_named(qp_table_size, ib_qib_qp_table_size, uint, S_IRUGO);
48 MODULE_PARM_DESC(qp_table_size, "QP table size");
50 unsigned int ib_qib_lkey_table_size = 16;
51 module_param_named(lkey_table_size, ib_qib_lkey_table_size, uint,
53 MODULE_PARM_DESC(lkey_table_size,
54 "LKEY table size in bits (2^n, 1 <= n <= 23)");
56 static unsigned int ib_qib_max_pds = 0xFFFF;
57 module_param_named(max_pds, ib_qib_max_pds, uint, S_IRUGO);
58 MODULE_PARM_DESC(max_pds,
59 "Maximum number of protection domains to support");
61 static unsigned int ib_qib_max_ahs = 0xFFFF;
62 module_param_named(max_ahs, ib_qib_max_ahs, uint, S_IRUGO);
63 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
65 unsigned int ib_qib_max_cqes = 0x2FFFF;
66 module_param_named(max_cqes, ib_qib_max_cqes, uint, S_IRUGO);
67 MODULE_PARM_DESC(max_cqes,
68 "Maximum number of completion queue entries to support");
70 unsigned int ib_qib_max_cqs = 0x1FFFF;
71 module_param_named(max_cqs, ib_qib_max_cqs, uint, S_IRUGO);
72 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
74 unsigned int ib_qib_max_qp_wrs = 0x3FFF;
75 module_param_named(max_qp_wrs, ib_qib_max_qp_wrs, uint, S_IRUGO);
76 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
78 unsigned int ib_qib_max_qps = 16384;
79 module_param_named(max_qps, ib_qib_max_qps, uint, S_IRUGO);
80 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
82 unsigned int ib_qib_max_sges = 0x60;
83 module_param_named(max_sges, ib_qib_max_sges, uint, S_IRUGO);
84 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
86 unsigned int ib_qib_max_mcast_grps = 16384;
87 module_param_named(max_mcast_grps, ib_qib_max_mcast_grps, uint, S_IRUGO);
88 MODULE_PARM_DESC(max_mcast_grps,
89 "Maximum number of multicast groups to support");
91 unsigned int ib_qib_max_mcast_qp_attached = 16;
92 module_param_named(max_mcast_qp_attached, ib_qib_max_mcast_qp_attached,
94 MODULE_PARM_DESC(max_mcast_qp_attached,
95 "Maximum number of attached QPs to support");
97 unsigned int ib_qib_max_srqs = 1024;
98 module_param_named(max_srqs, ib_qib_max_srqs, uint, S_IRUGO);
99 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
101 unsigned int ib_qib_max_srq_sges = 128;
102 module_param_named(max_srq_sges, ib_qib_max_srq_sges, uint, S_IRUGO);
103 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
105 unsigned int ib_qib_max_srq_wrs = 0x1FFFF;
106 module_param_named(max_srq_wrs, ib_qib_max_srq_wrs, uint, S_IRUGO);
107 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
109 static unsigned int ib_qib_disable_sma;
110 module_param_named(disable_sma, ib_qib_disable_sma, uint, S_IWUSR | S_IRUGO);
111 MODULE_PARM_DESC(disable_sma, "Disable the SMA");
114 * Note that it is OK to post send work requests in the SQE and ERR
115 * states; qib_do_send() will process them and generate error
116 * completions as per IB 1.2 C10-96.
118 const int ib_qib_state_ops[IB_QPS_ERR + 1] = {
120 [IB_QPS_INIT] = QIB_POST_RECV_OK,
121 [IB_QPS_RTR] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK,
122 [IB_QPS_RTS] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK |
123 QIB_POST_SEND_OK | QIB_PROCESS_SEND_OK |
124 QIB_PROCESS_NEXT_SEND_OK,
125 [IB_QPS_SQD] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK |
126 QIB_POST_SEND_OK | QIB_PROCESS_SEND_OK,
127 [IB_QPS_SQE] = QIB_POST_RECV_OK | QIB_PROCESS_RECV_OK |
128 QIB_POST_SEND_OK | QIB_FLUSH_SEND,
129 [IB_QPS_ERR] = QIB_POST_RECV_OK | QIB_FLUSH_RECV |
130 QIB_POST_SEND_OK | QIB_FLUSH_SEND,
133 struct qib_ucontext {
134 struct ib_ucontext ibucontext;
137 static inline struct qib_ucontext *to_iucontext(struct ib_ucontext
140 return container_of(ibucontext, struct qib_ucontext, ibucontext);
144 * Translate ib_wr_opcode into ib_wc_opcode.
146 const enum ib_wc_opcode ib_qib_wc_opcode[] = {
147 [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
148 [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
149 [IB_WR_SEND] = IB_WC_SEND,
150 [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
151 [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
152 [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
153 [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD
159 __be64 ib_qib_sys_image_guid;
162 * qib_copy_sge - copy data to SGE memory
164 * @data: the data to copy
165 * @length: the length of the data
167 void qib_copy_sge(struct qib_sge_state *ss, void *data, u32 length, int release)
169 struct qib_sge *sge = &ss->sge;
172 u32 len = sge->length;
176 if (len > sge->sge_length)
177 len = sge->sge_length;
179 memcpy(sge->vaddr, data, len);
182 sge->sge_length -= len;
183 if (sge->sge_length == 0) {
185 atomic_dec(&sge->mr->refcount);
187 *sge = *ss->sg_list++;
188 } else if (sge->length == 0 && sge->mr->lkey) {
189 if (++sge->n >= QIB_SEGSZ) {
190 if (++sge->m >= sge->mr->mapsz)
195 sge->mr->map[sge->m]->segs[sge->n].vaddr;
197 sge->mr->map[sge->m]->segs[sge->n].length;
205 * qib_skip_sge - skip over SGE memory - XXX almost dup of prev func
207 * @length: the number of bytes to skip
209 void qib_skip_sge(struct qib_sge_state *ss, u32 length, int release)
211 struct qib_sge *sge = &ss->sge;
214 u32 len = sge->length;
218 if (len > sge->sge_length)
219 len = sge->sge_length;
223 sge->sge_length -= len;
224 if (sge->sge_length == 0) {
226 atomic_dec(&sge->mr->refcount);
228 *sge = *ss->sg_list++;
229 } else if (sge->length == 0 && sge->mr->lkey) {
230 if (++sge->n >= QIB_SEGSZ) {
231 if (++sge->m >= sge->mr->mapsz)
236 sge->mr->map[sge->m]->segs[sge->n].vaddr;
238 sge->mr->map[sge->m]->segs[sge->n].length;
245 * Count the number of DMA descriptors needed to send length bytes of data.
246 * Don't modify the qib_sge_state to get the count.
247 * Return zero if any of the segments is not aligned.
249 static u32 qib_count_sge(struct qib_sge_state *ss, u32 length)
251 struct qib_sge *sg_list = ss->sg_list;
252 struct qib_sge sge = ss->sge;
253 u8 num_sge = ss->num_sge;
254 u32 ndesc = 1; /* count the header */
257 u32 len = sge.length;
261 if (len > sge.sge_length)
262 len = sge.sge_length;
264 if (((long) sge.vaddr & (sizeof(u32) - 1)) ||
265 (len != length && (len & (sizeof(u32) - 1)))) {
272 sge.sge_length -= len;
273 if (sge.sge_length == 0) {
276 } else if (sge.length == 0 && sge.mr->lkey) {
277 if (++sge.n >= QIB_SEGSZ) {
278 if (++sge.m >= sge.mr->mapsz)
283 sge.mr->map[sge.m]->segs[sge.n].vaddr;
285 sge.mr->map[sge.m]->segs[sge.n].length;
293 * Copy from the SGEs to the data buffer.
295 static void qib_copy_from_sge(void *data, struct qib_sge_state *ss, u32 length)
297 struct qib_sge *sge = &ss->sge;
300 u32 len = sge->length;
304 if (len > sge->sge_length)
305 len = sge->sge_length;
307 memcpy(data, sge->vaddr, len);
310 sge->sge_length -= len;
311 if (sge->sge_length == 0) {
313 *sge = *ss->sg_list++;
314 } else if (sge->length == 0 && sge->mr->lkey) {
315 if (++sge->n >= QIB_SEGSZ) {
316 if (++sge->m >= sge->mr->mapsz)
321 sge->mr->map[sge->m]->segs[sge->n].vaddr;
323 sge->mr->map[sge->m]->segs[sge->n].length;
331 * qib_post_one_send - post one RC, UC, or UD send work request
332 * @qp: the QP to post on
333 * @wr: the work request to send
335 static int qib_post_one_send(struct qib_qp *qp, struct ib_send_wr *wr)
337 struct qib_swqe *wqe;
344 struct qib_lkey_table *rkt;
347 spin_lock_irqsave(&qp->s_lock, flags);
349 /* Check that state is OK to post send. */
350 if (unlikely(!(ib_qib_state_ops[qp->state] & QIB_POST_SEND_OK)))
353 /* IB spec says that num_sge == 0 is OK. */
354 if (wr->num_sge > qp->s_max_sge)
358 * Don't allow RDMA reads or atomic operations on UC or
359 * undefined operations.
360 * Make sure buffer is large enough to hold the result for atomics.
362 if (wr->opcode == IB_WR_FAST_REG_MR) {
363 if (qib_fast_reg_mr(qp, wr))
365 } else if (qp->ibqp.qp_type == IB_QPT_UC) {
366 if ((unsigned) wr->opcode >= IB_WR_RDMA_READ)
368 } else if (qp->ibqp.qp_type != IB_QPT_RC) {
369 /* Check IB_QPT_SMI, IB_QPT_GSI, IB_QPT_UD opcode */
370 if (wr->opcode != IB_WR_SEND &&
371 wr->opcode != IB_WR_SEND_WITH_IMM)
373 /* Check UD destination address PD */
374 if (qp->ibqp.pd != wr->wr.ud.ah->pd)
376 } else if ((unsigned) wr->opcode > IB_WR_ATOMIC_FETCH_AND_ADD)
378 else if (wr->opcode >= IB_WR_ATOMIC_CMP_AND_SWP &&
380 wr->sg_list[0].length < sizeof(u64) ||
381 wr->sg_list[0].addr & (sizeof(u64) - 1)))
383 else if (wr->opcode >= IB_WR_RDMA_READ && !qp->s_max_rd_atomic)
386 next = qp->s_head + 1;
387 if (next >= qp->s_size)
389 if (next == qp->s_last) {
394 rkt = &to_idev(qp->ibqp.device)->lk_table;
395 pd = to_ipd(qp->ibqp.pd);
396 wqe = get_swqe_ptr(qp, qp->s_head);
401 acc = wr->opcode >= IB_WR_RDMA_READ ?
402 IB_ACCESS_LOCAL_WRITE : 0;
403 for (i = 0; i < wr->num_sge; i++) {
404 u32 length = wr->sg_list[i].length;
409 ok = qib_lkey_ok(rkt, pd, &wqe->sg_list[j],
410 &wr->sg_list[i], acc);
412 goto bail_inval_free;
413 wqe->length += length;
418 if (qp->ibqp.qp_type == IB_QPT_UC ||
419 qp->ibqp.qp_type == IB_QPT_RC) {
420 if (wqe->length > 0x80000000U)
421 goto bail_inval_free;
422 } else if (wqe->length > (dd_from_ibdev(qp->ibqp.device)->pport +
423 qp->port_num - 1)->ibmtu)
424 goto bail_inval_free;
426 atomic_inc(&to_iah(wr->wr.ud.ah)->refcount);
427 wqe->ssn = qp->s_ssn++;
435 struct qib_sge *sge = &wqe->sg_list[--j];
437 atomic_dec(&sge->mr->refcount);
442 spin_unlock_irqrestore(&qp->s_lock, flags);
447 * qib_post_send - post a send on a QP
448 * @ibqp: the QP to post the send on
449 * @wr: the list of work requests to post
450 * @bad_wr: the first bad WR is put here
452 * This may be called from interrupt context.
454 static int qib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
455 struct ib_send_wr **bad_wr)
457 struct qib_qp *qp = to_iqp(ibqp);
460 for (; wr; wr = wr->next) {
461 err = qib_post_one_send(qp, wr);
468 /* Try to do the send work in the caller's context. */
469 qib_do_send(&qp->s_work);
476 * qib_post_receive - post a receive on a QP
477 * @ibqp: the QP to post the receive on
478 * @wr: the WR to post
479 * @bad_wr: the first bad WR is put here
481 * This may be called from interrupt context.
483 static int qib_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
484 struct ib_recv_wr **bad_wr)
486 struct qib_qp *qp = to_iqp(ibqp);
487 struct qib_rwq *wq = qp->r_rq.wq;
491 /* Check that state is OK to post receive. */
492 if (!(ib_qib_state_ops[qp->state] & QIB_POST_RECV_OK) || !wq) {
498 for (; wr; wr = wr->next) {
499 struct qib_rwqe *wqe;
503 if ((unsigned) wr->num_sge > qp->r_rq.max_sge) {
509 spin_lock_irqsave(&qp->r_rq.lock, flags);
511 if (next >= qp->r_rq.size)
513 if (next == wq->tail) {
514 spin_unlock_irqrestore(&qp->r_rq.lock, flags);
520 wqe = get_rwqe_ptr(&qp->r_rq, wq->head);
521 wqe->wr_id = wr->wr_id;
522 wqe->num_sge = wr->num_sge;
523 for (i = 0; i < wr->num_sge; i++)
524 wqe->sg_list[i] = wr->sg_list[i];
525 /* Make sure queue entry is written before the head index. */
528 spin_unlock_irqrestore(&qp->r_rq.lock, flags);
537 * qib_qp_rcv - processing an incoming packet on a QP
538 * @rcd: the context pointer
539 * @hdr: the packet header
540 * @has_grh: true if the packet has a GRH
541 * @data: the packet data
542 * @tlen: the packet length
543 * @qp: the QP the packet came on
545 * This is called from qib_ib_rcv() to process an incoming packet
547 * Called at interrupt level.
549 static void qib_qp_rcv(struct qib_ctxtdata *rcd, struct qib_ib_header *hdr,
550 int has_grh, void *data, u32 tlen, struct qib_qp *qp)
552 struct qib_ibport *ibp = &rcd->ppd->ibport_data;
554 spin_lock(&qp->r_lock);
556 /* Check for valid receive state. */
557 if (!(ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK)) {
562 switch (qp->ibqp.qp_type) {
565 if (ib_qib_disable_sma)
569 qib_ud_rcv(ibp, hdr, has_grh, data, tlen, qp);
573 qib_rc_rcv(rcd, hdr, has_grh, data, tlen, qp);
577 qib_uc_rcv(ibp, hdr, has_grh, data, tlen, qp);
585 spin_unlock(&qp->r_lock);
589 * qib_ib_rcv - process an incoming packet
590 * @rcd: the context pointer
591 * @rhdr: the header of the packet
592 * @data: the packet payload
593 * @tlen: the packet length
595 * This is called from qib_kreceive() to process an incoming packet at
596 * interrupt level. Tlen is the length of the header + data + CRC in bytes.
598 void qib_ib_rcv(struct qib_ctxtdata *rcd, void *rhdr, void *data, u32 tlen)
600 struct qib_pportdata *ppd = rcd->ppd;
601 struct qib_ibport *ibp = &ppd->ibport_data;
602 struct qib_ib_header *hdr = rhdr;
603 struct qib_other_headers *ohdr;
610 /* 24 == LRH+BTH+CRC */
611 if (unlikely(tlen < 24))
614 /* Check for a valid destination LID (see ch. 7.11.1). */
615 lid = be16_to_cpu(hdr->lrh[1]);
616 if (lid < QIB_MULTICAST_LID_BASE) {
617 lid &= ~((1 << ppd->lmc) - 1);
618 if (unlikely(lid != ppd->lid))
623 lnh = be16_to_cpu(hdr->lrh[0]) & 3;
624 if (lnh == QIB_LRH_BTH)
626 else if (lnh == QIB_LRH_GRH) {
629 ohdr = &hdr->u.l.oth;
630 if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR)
632 vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow);
633 if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
638 opcode = be32_to_cpu(ohdr->bth[0]) >> 24;
639 ibp->opstats[opcode & 0x7f].n_bytes += tlen;
640 ibp->opstats[opcode & 0x7f].n_packets++;
642 /* Get the destination QP number. */
643 qp_num = be32_to_cpu(ohdr->bth[1]) & QIB_QPN_MASK;
644 if (qp_num == QIB_MULTICAST_QPN) {
645 struct qib_mcast *mcast;
646 struct qib_mcast_qp *p;
648 if (lnh != QIB_LRH_GRH)
650 mcast = qib_mcast_find(ibp, &hdr->u.l.grh.dgid);
653 ibp->n_multicast_rcv++;
654 list_for_each_entry_rcu(p, &mcast->qp_list, list)
655 qib_qp_rcv(rcd, hdr, 1, data, tlen, p->qp);
657 * Notify qib_multicast_detach() if it is waiting for us
660 if (atomic_dec_return(&mcast->refcount) <= 1)
661 wake_up(&mcast->wait);
663 if (rcd->lookaside_qp) {
664 if (rcd->lookaside_qpn != qp_num) {
665 if (atomic_dec_and_test(
666 &rcd->lookaside_qp->refcount))
668 &rcd->lookaside_qp->wait);
669 rcd->lookaside_qp = NULL;
672 if (!rcd->lookaside_qp) {
673 qp = qib_lookup_qpn(ibp, qp_num);
676 rcd->lookaside_qp = qp;
677 rcd->lookaside_qpn = qp_num;
679 qp = rcd->lookaside_qp;
680 ibp->n_unicast_rcv++;
681 qib_qp_rcv(rcd, hdr, lnh == QIB_LRH_GRH, data, tlen, qp);
690 * This is called from a timer to check for QPs
691 * which need kernel memory in order to send a packet.
693 static void mem_timer(unsigned long data)
695 struct qib_ibdev *dev = (struct qib_ibdev *) data;
696 struct list_head *list = &dev->memwait;
697 struct qib_qp *qp = NULL;
700 spin_lock_irqsave(&dev->pending_lock, flags);
701 if (!list_empty(list)) {
702 qp = list_entry(list->next, struct qib_qp, iowait);
703 list_del_init(&qp->iowait);
704 atomic_inc(&qp->refcount);
705 if (!list_empty(list))
706 mod_timer(&dev->mem_timer, jiffies + 1);
708 spin_unlock_irqrestore(&dev->pending_lock, flags);
711 spin_lock_irqsave(&qp->s_lock, flags);
712 if (qp->s_flags & QIB_S_WAIT_KMEM) {
713 qp->s_flags &= ~QIB_S_WAIT_KMEM;
714 qib_schedule_send(qp);
716 spin_unlock_irqrestore(&qp->s_lock, flags);
717 if (atomic_dec_and_test(&qp->refcount))
722 static void update_sge(struct qib_sge_state *ss, u32 length)
724 struct qib_sge *sge = &ss->sge;
726 sge->vaddr += length;
727 sge->length -= length;
728 sge->sge_length -= length;
729 if (sge->sge_length == 0) {
731 *sge = *ss->sg_list++;
732 } else if (sge->length == 0 && sge->mr->lkey) {
733 if (++sge->n >= QIB_SEGSZ) {
734 if (++sge->m >= sge->mr->mapsz)
738 sge->vaddr = sge->mr->map[sge->m]->segs[sge->n].vaddr;
739 sge->length = sge->mr->map[sge->m]->segs[sge->n].length;
743 #ifdef __LITTLE_ENDIAN
744 static inline u32 get_upper_bits(u32 data, u32 shift)
746 return data >> shift;
749 static inline u32 set_upper_bits(u32 data, u32 shift)
751 return data << shift;
754 static inline u32 clear_upper_bytes(u32 data, u32 n, u32 off)
756 data <<= ((sizeof(u32) - n) * BITS_PER_BYTE);
757 data >>= ((sizeof(u32) - n - off) * BITS_PER_BYTE);
761 static inline u32 get_upper_bits(u32 data, u32 shift)
763 return data << shift;
766 static inline u32 set_upper_bits(u32 data, u32 shift)
768 return data >> shift;
771 static inline u32 clear_upper_bytes(u32 data, u32 n, u32 off)
773 data >>= ((sizeof(u32) - n) * BITS_PER_BYTE);
774 data <<= ((sizeof(u32) - n - off) * BITS_PER_BYTE);
779 static void copy_io(u32 __iomem *piobuf, struct qib_sge_state *ss,
780 u32 length, unsigned flush_wc)
787 u32 len = ss->sge.length;
792 if (len > ss->sge.sge_length)
793 len = ss->sge.sge_length;
795 /* If the source address is not aligned, try to align it. */
796 off = (unsigned long)ss->sge.vaddr & (sizeof(u32) - 1);
798 u32 *addr = (u32 *)((unsigned long)ss->sge.vaddr &
800 u32 v = get_upper_bits(*addr, off * BITS_PER_BYTE);
803 y = sizeof(u32) - off;
806 if (len + extra >= sizeof(u32)) {
807 data |= set_upper_bits(v, extra *
809 len = sizeof(u32) - extra;
814 __raw_writel(data, piobuf);
819 /* Clear unused upper bytes */
820 data |= clear_upper_bytes(v, len, extra);
828 /* Source address is aligned. */
829 u32 *addr = (u32 *) ss->sge.vaddr;
830 int shift = extra * BITS_PER_BYTE;
831 int ushift = 32 - shift;
834 while (l >= sizeof(u32)) {
837 data |= set_upper_bits(v, shift);
838 __raw_writel(data, piobuf);
839 data = get_upper_bits(v, ushift);
845 * We still have 'extra' number of bytes leftover.
850 if (l + extra >= sizeof(u32)) {
851 data |= set_upper_bits(v, shift);
852 len -= l + extra - sizeof(u32);
857 __raw_writel(data, piobuf);
862 /* Clear unused upper bytes */
863 data |= clear_upper_bytes(v, l, extra);
870 } else if (len == length) {
874 } else if (len == length) {
878 * Need to round up for the last dword in the
882 qib_pio_copy(piobuf, ss->sge.vaddr, w - 1);
884 last = ((u32 *) ss->sge.vaddr)[w - 1];
889 qib_pio_copy(piobuf, ss->sge.vaddr, w);
892 extra = len & (sizeof(u32) - 1);
894 u32 v = ((u32 *) ss->sge.vaddr)[w];
896 /* Clear unused upper bytes */
897 data = clear_upper_bytes(v, extra, 0);
903 /* Update address before sending packet. */
904 update_sge(ss, length);
906 /* must flush early everything before trigger word */
908 __raw_writel(last, piobuf);
909 /* be sure trigger word is written */
912 __raw_writel(last, piobuf);
915 static struct qib_verbs_txreq *get_txreq(struct qib_ibdev *dev,
916 struct qib_qp *qp, int *retp)
918 struct qib_verbs_txreq *tx;
921 spin_lock_irqsave(&qp->s_lock, flags);
922 spin_lock(&dev->pending_lock);
924 if (!list_empty(&dev->txreq_free)) {
925 struct list_head *l = dev->txreq_free.next;
928 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
931 if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK &&
932 list_empty(&qp->iowait)) {
934 qp->s_flags |= QIB_S_WAIT_TX;
935 list_add_tail(&qp->iowait, &dev->txwait);
938 qp->s_flags &= ~QIB_S_BUSY;
942 spin_unlock(&dev->pending_lock);
943 spin_unlock_irqrestore(&qp->s_lock, flags);
948 void qib_put_txreq(struct qib_verbs_txreq *tx)
950 struct qib_ibdev *dev;
955 dev = to_idev(qp->ibqp.device);
957 if (atomic_dec_and_test(&qp->refcount))
960 atomic_dec(&tx->mr->refcount);
963 if (tx->txreq.flags & QIB_SDMA_TXREQ_F_FREEBUF) {
964 tx->txreq.flags &= ~QIB_SDMA_TXREQ_F_FREEBUF;
965 dma_unmap_single(&dd_from_dev(dev)->pcidev->dev,
966 tx->txreq.addr, tx->hdr_dwords << 2,
968 kfree(tx->align_buf);
971 spin_lock_irqsave(&dev->pending_lock, flags);
973 /* Put struct back on free list */
974 list_add(&tx->txreq.list, &dev->txreq_free);
976 if (!list_empty(&dev->txwait)) {
977 /* Wake up first QP wanting a free struct */
978 qp = list_entry(dev->txwait.next, struct qib_qp, iowait);
979 list_del_init(&qp->iowait);
980 atomic_inc(&qp->refcount);
981 spin_unlock_irqrestore(&dev->pending_lock, flags);
983 spin_lock_irqsave(&qp->s_lock, flags);
984 if (qp->s_flags & QIB_S_WAIT_TX) {
985 qp->s_flags &= ~QIB_S_WAIT_TX;
986 qib_schedule_send(qp);
988 spin_unlock_irqrestore(&qp->s_lock, flags);
990 if (atomic_dec_and_test(&qp->refcount))
993 spin_unlock_irqrestore(&dev->pending_lock, flags);
997 * This is called when there are send DMA descriptors that might be
1000 * This is called with ppd->sdma_lock held.
1002 void qib_verbs_sdma_desc_avail(struct qib_pportdata *ppd, unsigned avail)
1004 struct qib_qp *qp, *nqp;
1005 struct qib_qp *qps[20];
1006 struct qib_ibdev *dev;
1010 dev = &ppd->dd->verbs_dev;
1011 spin_lock(&dev->pending_lock);
1013 /* Search wait list for first QP wanting DMA descriptors. */
1014 list_for_each_entry_safe(qp, nqp, &dev->dmawait, iowait) {
1015 if (qp->port_num != ppd->port)
1017 if (n == ARRAY_SIZE(qps))
1019 if (qp->s_tx->txreq.sg_count > avail)
1021 avail -= qp->s_tx->txreq.sg_count;
1022 list_del_init(&qp->iowait);
1023 atomic_inc(&qp->refcount);
1027 spin_unlock(&dev->pending_lock);
1029 for (i = 0; i < n; i++) {
1031 spin_lock(&qp->s_lock);
1032 if (qp->s_flags & QIB_S_WAIT_DMA_DESC) {
1033 qp->s_flags &= ~QIB_S_WAIT_DMA_DESC;
1034 qib_schedule_send(qp);
1036 spin_unlock(&qp->s_lock);
1037 if (atomic_dec_and_test(&qp->refcount))
1043 * This is called with ppd->sdma_lock held.
1045 static void sdma_complete(struct qib_sdma_txreq *cookie, int status)
1047 struct qib_verbs_txreq *tx =
1048 container_of(cookie, struct qib_verbs_txreq, txreq);
1049 struct qib_qp *qp = tx->qp;
1051 spin_lock(&qp->s_lock);
1053 qib_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
1054 else if (qp->ibqp.qp_type == IB_QPT_RC) {
1055 struct qib_ib_header *hdr;
1057 if (tx->txreq.flags & QIB_SDMA_TXREQ_F_FREEBUF)
1058 hdr = &tx->align_buf->hdr;
1060 struct qib_ibdev *dev = to_idev(qp->ibqp.device);
1062 hdr = &dev->pio_hdrs[tx->hdr_inx].hdr;
1064 qib_rc_send_complete(qp, hdr);
1066 if (atomic_dec_and_test(&qp->s_dma_busy)) {
1067 if (qp->state == IB_QPS_RESET)
1068 wake_up(&qp->wait_dma);
1069 else if (qp->s_flags & QIB_S_WAIT_DMA) {
1070 qp->s_flags &= ~QIB_S_WAIT_DMA;
1071 qib_schedule_send(qp);
1074 spin_unlock(&qp->s_lock);
1079 static int wait_kmem(struct qib_ibdev *dev, struct qib_qp *qp)
1081 unsigned long flags;
1084 spin_lock_irqsave(&qp->s_lock, flags);
1085 if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK) {
1086 spin_lock(&dev->pending_lock);
1087 if (list_empty(&qp->iowait)) {
1088 if (list_empty(&dev->memwait))
1089 mod_timer(&dev->mem_timer, jiffies + 1);
1090 qp->s_flags |= QIB_S_WAIT_KMEM;
1091 list_add_tail(&qp->iowait, &dev->memwait);
1093 spin_unlock(&dev->pending_lock);
1094 qp->s_flags &= ~QIB_S_BUSY;
1097 spin_unlock_irqrestore(&qp->s_lock, flags);
1102 static int qib_verbs_send_dma(struct qib_qp *qp, struct qib_ib_header *hdr,
1103 u32 hdrwords, struct qib_sge_state *ss, u32 len,
1104 u32 plen, u32 dwords)
1106 struct qib_ibdev *dev = to_idev(qp->ibqp.device);
1107 struct qib_devdata *dd = dd_from_dev(dev);
1108 struct qib_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
1109 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1110 struct qib_verbs_txreq *tx;
1111 struct qib_pio_header *phdr;
1119 /* resend previously constructed packet */
1120 ret = qib_sdma_verbs_send(ppd, tx->ss, tx->dwords, tx);
1124 tx = get_txreq(dev, qp, &ret);
1128 control = dd->f_setpbc_control(ppd, plen, qp->s_srate,
1129 be16_to_cpu(hdr->lrh[0]) >> 12);
1131 atomic_inc(&qp->refcount);
1132 tx->wqe = qp->s_wqe;
1133 tx->mr = qp->s_rdma_mr;
1135 qp->s_rdma_mr = NULL;
1136 tx->txreq.callback = sdma_complete;
1137 if (dd->flags & QIB_HAS_SDMA_TIMEOUT)
1138 tx->txreq.flags = QIB_SDMA_TXREQ_F_HEADTOHOST;
1140 tx->txreq.flags = QIB_SDMA_TXREQ_F_INTREQ;
1141 if (plen + 1 > dd->piosize2kmax_dwords)
1142 tx->txreq.flags |= QIB_SDMA_TXREQ_F_USELARGEBUF;
1146 * Don't try to DMA if it takes more descriptors than
1149 ndesc = qib_count_sge(ss, len);
1150 if (ndesc >= ppd->sdma_descq_cnt)
1155 phdr = &dev->pio_hdrs[tx->hdr_inx];
1156 phdr->pbc[0] = cpu_to_le32(plen);
1157 phdr->pbc[1] = cpu_to_le32(control);
1158 memcpy(&phdr->hdr, hdr, hdrwords << 2);
1159 tx->txreq.flags |= QIB_SDMA_TXREQ_F_FREEDESC;
1160 tx->txreq.sg_count = ndesc;
1161 tx->txreq.addr = dev->pio_hdrs_phys +
1162 tx->hdr_inx * sizeof(struct qib_pio_header);
1163 tx->hdr_dwords = hdrwords + 2; /* add PBC length */
1164 ret = qib_sdma_verbs_send(ppd, ss, dwords, tx);
1168 /* Allocate a buffer and copy the header and payload to it. */
1169 tx->hdr_dwords = plen + 1;
1170 phdr = kmalloc(tx->hdr_dwords << 2, GFP_ATOMIC);
1173 phdr->pbc[0] = cpu_to_le32(plen);
1174 phdr->pbc[1] = cpu_to_le32(control);
1175 memcpy(&phdr->hdr, hdr, hdrwords << 2);
1176 qib_copy_from_sge((u32 *) &phdr->hdr + hdrwords, ss, len);
1178 tx->txreq.addr = dma_map_single(&dd->pcidev->dev, phdr,
1179 tx->hdr_dwords << 2, DMA_TO_DEVICE);
1180 if (dma_mapping_error(&dd->pcidev->dev, tx->txreq.addr))
1182 tx->align_buf = phdr;
1183 tx->txreq.flags |= QIB_SDMA_TXREQ_F_FREEBUF;
1184 tx->txreq.sg_count = 1;
1185 ret = qib_sdma_verbs_send(ppd, NULL, 0, tx);
1192 ret = wait_kmem(dev, qp);
1200 * If we are now in the error state, return zero to flush the
1201 * send work request.
1203 static int no_bufs_available(struct qib_qp *qp)
1205 struct qib_ibdev *dev = to_idev(qp->ibqp.device);
1206 struct qib_devdata *dd;
1207 unsigned long flags;
1211 * Note that as soon as want_buffer() is called and
1212 * possibly before it returns, qib_ib_piobufavail()
1213 * could be called. Therefore, put QP on the I/O wait list before
1214 * enabling the PIO avail interrupt.
1216 spin_lock_irqsave(&qp->s_lock, flags);
1217 if (ib_qib_state_ops[qp->state] & QIB_PROCESS_RECV_OK) {
1218 spin_lock(&dev->pending_lock);
1219 if (list_empty(&qp->iowait)) {
1221 qp->s_flags |= QIB_S_WAIT_PIO;
1222 list_add_tail(&qp->iowait, &dev->piowait);
1223 dd = dd_from_dev(dev);
1224 dd->f_wantpiobuf_intr(dd, 1);
1226 spin_unlock(&dev->pending_lock);
1227 qp->s_flags &= ~QIB_S_BUSY;
1230 spin_unlock_irqrestore(&qp->s_lock, flags);
1234 static int qib_verbs_send_pio(struct qib_qp *qp, struct qib_ib_header *ibhdr,
1235 u32 hdrwords, struct qib_sge_state *ss, u32 len,
1236 u32 plen, u32 dwords)
1238 struct qib_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1239 struct qib_pportdata *ppd = dd->pport + qp->port_num - 1;
1240 u32 *hdr = (u32 *) ibhdr;
1241 u32 __iomem *piobuf_orig;
1242 u32 __iomem *piobuf;
1244 unsigned long flags;
1249 control = dd->f_setpbc_control(ppd, plen, qp->s_srate,
1250 be16_to_cpu(ibhdr->lrh[0]) >> 12);
1251 pbc = ((u64) control << 32) | plen;
1252 piobuf = dd->f_getsendbuf(ppd, pbc, &pbufn);
1253 if (unlikely(piobuf == NULL))
1254 return no_bufs_available(qp);
1258 * We have to flush after the PBC for correctness on some cpus
1259 * or WC buffer can be written out of order.
1261 writeq(pbc, piobuf);
1262 piobuf_orig = piobuf;
1265 flush_wc = dd->flags & QIB_PIO_FLUSH_WC;
1268 * If there is just the header portion, must flush before
1269 * writing last word of header for correctness, and after
1270 * the last header word (trigger word).
1274 qib_pio_copy(piobuf, hdr, hdrwords - 1);
1276 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords - 1);
1279 qib_pio_copy(piobuf, hdr, hdrwords);
1285 qib_pio_copy(piobuf, hdr, hdrwords);
1288 /* The common case is aligned and contained in one segment. */
1289 if (likely(ss->num_sge == 1 && len <= ss->sge.length &&
1290 !((unsigned long)ss->sge.vaddr & (sizeof(u32) - 1)))) {
1291 u32 *addr = (u32 *) ss->sge.vaddr;
1293 /* Update address before sending packet. */
1294 update_sge(ss, len);
1296 qib_pio_copy(piobuf, addr, dwords - 1);
1297 /* must flush early everything before trigger word */
1299 __raw_writel(addr[dwords - 1], piobuf + dwords - 1);
1300 /* be sure trigger word is written */
1303 qib_pio_copy(piobuf, addr, dwords);
1306 copy_io(piobuf, ss, len, flush_wc);
1308 if (dd->flags & QIB_USE_SPCL_TRIG) {
1309 u32 spcl_off = (pbufn >= dd->piobcnt2k) ? 2047 : 1023;
1311 __raw_writel(0xaebecede, piobuf_orig + spcl_off);
1313 qib_sendbuf_done(dd, pbufn);
1314 if (qp->s_rdma_mr) {
1315 atomic_dec(&qp->s_rdma_mr->refcount);
1316 qp->s_rdma_mr = NULL;
1319 spin_lock_irqsave(&qp->s_lock, flags);
1320 qib_send_complete(qp, qp->s_wqe, IB_WC_SUCCESS);
1321 spin_unlock_irqrestore(&qp->s_lock, flags);
1322 } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1323 spin_lock_irqsave(&qp->s_lock, flags);
1324 qib_rc_send_complete(qp, ibhdr);
1325 spin_unlock_irqrestore(&qp->s_lock, flags);
1331 * qib_verbs_send - send a packet
1332 * @qp: the QP to send on
1333 * @hdr: the packet header
1334 * @hdrwords: the number of 32-bit words in the header
1335 * @ss: the SGE to send
1336 * @len: the length of the packet in bytes
1338 * Return zero if packet is sent or queued OK.
1339 * Return non-zero and clear qp->s_flags QIB_S_BUSY otherwise.
1341 int qib_verbs_send(struct qib_qp *qp, struct qib_ib_header *hdr,
1342 u32 hdrwords, struct qib_sge_state *ss, u32 len)
1344 struct qib_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1347 u32 dwords = (len + 3) >> 2;
1350 * Calculate the send buffer trigger address.
1351 * The +1 counts for the pbc control dword following the pbc length.
1353 plen = hdrwords + dwords + 1;
1356 * VL15 packets (IB_QPT_SMI) will always use PIO, so we
1357 * can defer SDMA restart until link goes ACTIVE without
1358 * worrying about just how we got there.
1360 if (qp->ibqp.qp_type == IB_QPT_SMI ||
1361 !(dd->flags & QIB_HAS_SEND_DMA))
1362 ret = qib_verbs_send_pio(qp, hdr, hdrwords, ss, len,
1365 ret = qib_verbs_send_dma(qp, hdr, hdrwords, ss, len,
1371 int qib_snapshot_counters(struct qib_pportdata *ppd, u64 *swords,
1372 u64 *rwords, u64 *spkts, u64 *rpkts,
1376 struct qib_devdata *dd = ppd->dd;
1378 if (!(dd->flags & QIB_PRESENT)) {
1379 /* no hardware, freeze, etc. */
1383 *swords = dd->f_portcntr(ppd, QIBPORTCNTR_WORDSEND);
1384 *rwords = dd->f_portcntr(ppd, QIBPORTCNTR_WORDRCV);
1385 *spkts = dd->f_portcntr(ppd, QIBPORTCNTR_PKTSEND);
1386 *rpkts = dd->f_portcntr(ppd, QIBPORTCNTR_PKTRCV);
1387 *xmit_wait = dd->f_portcntr(ppd, QIBPORTCNTR_SENDSTALL);
1396 * qib_get_counters - get various chip counters
1397 * @dd: the qlogic_ib device
1398 * @cntrs: counters are placed here
1400 * Return the counters needed by recv_pma_get_portcounters().
1402 int qib_get_counters(struct qib_pportdata *ppd,
1403 struct qib_verbs_counters *cntrs)
1407 if (!(ppd->dd->flags & QIB_PRESENT)) {
1408 /* no hardware, freeze, etc. */
1412 cntrs->symbol_error_counter =
1413 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBSYMBOLERR);
1414 cntrs->link_error_recovery_counter =
1415 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBLINKERRRECOV);
1417 * The link downed counter counts when the other side downs the
1418 * connection. We add in the number of times we downed the link
1419 * due to local link integrity errors to compensate.
1421 cntrs->link_downed_counter =
1422 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBLINKDOWN);
1423 cntrs->port_rcv_errors =
1424 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXDROPPKT) +
1425 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RCVOVFL) +
1426 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERR_RLEN) +
1427 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_INVALIDRLEN) +
1428 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRLINK) +
1429 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRICRC) +
1430 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRVCRC) +
1431 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRLPCRC) +
1432 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_BADFORMAT);
1433 cntrs->port_rcv_errors +=
1434 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXLOCALPHYERR);
1435 cntrs->port_rcv_errors +=
1436 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXVLERR);
1437 cntrs->port_rcv_remphys_errors =
1438 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RCVEBP);
1439 cntrs->port_xmit_discards =
1440 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_UNSUPVL);
1441 cntrs->port_xmit_data = ppd->dd->f_portcntr(ppd,
1442 QIBPORTCNTR_WORDSEND);
1443 cntrs->port_rcv_data = ppd->dd->f_portcntr(ppd,
1444 QIBPORTCNTR_WORDRCV);
1445 cntrs->port_xmit_packets = ppd->dd->f_portcntr(ppd,
1446 QIBPORTCNTR_PKTSEND);
1447 cntrs->port_rcv_packets = ppd->dd->f_portcntr(ppd,
1448 QIBPORTCNTR_PKTRCV);
1449 cntrs->local_link_integrity_errors =
1450 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_LLI);
1451 cntrs->excessive_buffer_overrun_errors =
1452 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_EXCESSBUFOVFL);
1453 cntrs->vl15_dropped =
1454 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_VL15PKTDROP);
1463 * qib_ib_piobufavail - callback when a PIO buffer is available
1464 * @dd: the device pointer
1466 * This is called from qib_intr() at interrupt level when a PIO buffer is
1467 * available after qib_verbs_send() returned an error that no buffers were
1468 * available. Disable the interrupt if there are no more QPs waiting.
1470 void qib_ib_piobufavail(struct qib_devdata *dd)
1472 struct qib_ibdev *dev = &dd->verbs_dev;
1473 struct list_head *list;
1474 struct qib_qp *qps[5];
1476 unsigned long flags;
1479 list = &dev->piowait;
1483 * Note: checking that the piowait list is empty and clearing
1484 * the buffer available interrupt needs to be atomic or we
1485 * could end up with QPs on the wait list with the interrupt
1488 spin_lock_irqsave(&dev->pending_lock, flags);
1489 while (!list_empty(list)) {
1490 if (n == ARRAY_SIZE(qps))
1492 qp = list_entry(list->next, struct qib_qp, iowait);
1493 list_del_init(&qp->iowait);
1494 atomic_inc(&qp->refcount);
1497 dd->f_wantpiobuf_intr(dd, 0);
1499 spin_unlock_irqrestore(&dev->pending_lock, flags);
1501 for (i = 0; i < n; i++) {
1504 spin_lock_irqsave(&qp->s_lock, flags);
1505 if (qp->s_flags & QIB_S_WAIT_PIO) {
1506 qp->s_flags &= ~QIB_S_WAIT_PIO;
1507 qib_schedule_send(qp);
1509 spin_unlock_irqrestore(&qp->s_lock, flags);
1511 /* Notify qib_destroy_qp() if it is waiting. */
1512 if (atomic_dec_and_test(&qp->refcount))
1517 static int qib_query_device(struct ib_device *ibdev,
1518 struct ib_device_attr *props)
1520 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1521 struct qib_ibdev *dev = to_idev(ibdev);
1523 memset(props, 0, sizeof(*props));
1525 props->device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1526 IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1527 IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1528 IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE;
1529 props->page_size_cap = PAGE_SIZE;
1531 QIB_SRC_OUI_1 << 16 | QIB_SRC_OUI_2 << 8 | QIB_SRC_OUI_3;
1532 props->vendor_part_id = dd->deviceid;
1533 props->hw_ver = dd->minrev;
1534 props->sys_image_guid = ib_qib_sys_image_guid;
1535 props->max_mr_size = ~0ULL;
1536 props->max_qp = ib_qib_max_qps;
1537 props->max_qp_wr = ib_qib_max_qp_wrs;
1538 props->max_sge = ib_qib_max_sges;
1539 props->max_cq = ib_qib_max_cqs;
1540 props->max_ah = ib_qib_max_ahs;
1541 props->max_cqe = ib_qib_max_cqes;
1542 props->max_mr = dev->lk_table.max;
1543 props->max_fmr = dev->lk_table.max;
1544 props->max_map_per_fmr = 32767;
1545 props->max_pd = ib_qib_max_pds;
1546 props->max_qp_rd_atom = QIB_MAX_RDMA_ATOMIC;
1547 props->max_qp_init_rd_atom = 255;
1548 /* props->max_res_rd_atom */
1549 props->max_srq = ib_qib_max_srqs;
1550 props->max_srq_wr = ib_qib_max_srq_wrs;
1551 props->max_srq_sge = ib_qib_max_srq_sges;
1552 /* props->local_ca_ack_delay */
1553 props->atomic_cap = IB_ATOMIC_GLOB;
1554 props->max_pkeys = qib_get_npkeys(dd);
1555 props->max_mcast_grp = ib_qib_max_mcast_grps;
1556 props->max_mcast_qp_attach = ib_qib_max_mcast_qp_attached;
1557 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
1558 props->max_mcast_grp;
1563 static int qib_query_port(struct ib_device *ibdev, u8 port,
1564 struct ib_port_attr *props)
1566 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1567 struct qib_ibport *ibp = to_iport(ibdev, port);
1568 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1572 memset(props, 0, sizeof(*props));
1573 props->lid = lid ? lid : be16_to_cpu(IB_LID_PERMISSIVE);
1574 props->lmc = ppd->lmc;
1575 props->sm_lid = ibp->sm_lid;
1576 props->sm_sl = ibp->sm_sl;
1577 props->state = dd->f_iblink_state(ppd->lastibcstat);
1578 props->phys_state = dd->f_ibphys_portstate(ppd->lastibcstat);
1579 props->port_cap_flags = ibp->port_cap_flags;
1580 props->gid_tbl_len = QIB_GUIDS_PER_PORT;
1581 props->max_msg_sz = 0x80000000;
1582 props->pkey_tbl_len = qib_get_npkeys(dd);
1583 props->bad_pkey_cntr = ibp->pkey_violations;
1584 props->qkey_viol_cntr = ibp->qkey_violations;
1585 props->active_width = ppd->link_width_active;
1586 /* See rate_show() */
1587 props->active_speed = ppd->link_speed_active;
1588 props->max_vl_num = qib_num_vls(ppd->vls_supported);
1589 props->init_type_reply = 0;
1591 props->max_mtu = qib_ibmtu ? qib_ibmtu : IB_MTU_4096;
1592 switch (ppd->ibmtu) {
1611 props->active_mtu = mtu;
1612 props->subnet_timeout = ibp->subnet_timeout;
1617 static int qib_modify_device(struct ib_device *device,
1618 int device_modify_mask,
1619 struct ib_device_modify *device_modify)
1621 struct qib_devdata *dd = dd_from_ibdev(device);
1625 if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1626 IB_DEVICE_MODIFY_NODE_DESC)) {
1631 if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1632 memcpy(device->node_desc, device_modify->node_desc, 64);
1633 for (i = 0; i < dd->num_pports; i++) {
1634 struct qib_ibport *ibp = &dd->pport[i].ibport_data;
1636 qib_node_desc_chg(ibp);
1640 if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1641 ib_qib_sys_image_guid =
1642 cpu_to_be64(device_modify->sys_image_guid);
1643 for (i = 0; i < dd->num_pports; i++) {
1644 struct qib_ibport *ibp = &dd->pport[i].ibport_data;
1646 qib_sys_guid_chg(ibp);
1656 static int qib_modify_port(struct ib_device *ibdev, u8 port,
1657 int port_modify_mask, struct ib_port_modify *props)
1659 struct qib_ibport *ibp = to_iport(ibdev, port);
1660 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1662 ibp->port_cap_flags |= props->set_port_cap_mask;
1663 ibp->port_cap_flags &= ~props->clr_port_cap_mask;
1664 if (props->set_port_cap_mask || props->clr_port_cap_mask)
1665 qib_cap_mask_chg(ibp);
1666 if (port_modify_mask & IB_PORT_SHUTDOWN)
1667 qib_set_linkstate(ppd, QIB_IB_LINKDOWN);
1668 if (port_modify_mask & IB_PORT_RESET_QKEY_CNTR)
1669 ibp->qkey_violations = 0;
1673 static int qib_query_gid(struct ib_device *ibdev, u8 port,
1674 int index, union ib_gid *gid)
1676 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1679 if (!port || port > dd->num_pports)
1682 struct qib_ibport *ibp = to_iport(ibdev, port);
1683 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1685 gid->global.subnet_prefix = ibp->gid_prefix;
1687 gid->global.interface_id = ppd->guid;
1688 else if (index < QIB_GUIDS_PER_PORT)
1689 gid->global.interface_id = ibp->guids[index - 1];
1697 static struct ib_pd *qib_alloc_pd(struct ib_device *ibdev,
1698 struct ib_ucontext *context,
1699 struct ib_udata *udata)
1701 struct qib_ibdev *dev = to_idev(ibdev);
1706 * This is actually totally arbitrary. Some correctness tests
1707 * assume there's a maximum number of PDs that can be allocated.
1708 * We don't actually have this limit, but we fail the test if
1709 * we allow allocations of more than we report for this value.
1712 pd = kmalloc(sizeof *pd, GFP_KERNEL);
1714 ret = ERR_PTR(-ENOMEM);
1718 spin_lock(&dev->n_pds_lock);
1719 if (dev->n_pds_allocated == ib_qib_max_pds) {
1720 spin_unlock(&dev->n_pds_lock);
1722 ret = ERR_PTR(-ENOMEM);
1726 dev->n_pds_allocated++;
1727 spin_unlock(&dev->n_pds_lock);
1729 /* ib_alloc_pd() will initialize pd->ibpd. */
1730 pd->user = udata != NULL;
1738 static int qib_dealloc_pd(struct ib_pd *ibpd)
1740 struct qib_pd *pd = to_ipd(ibpd);
1741 struct qib_ibdev *dev = to_idev(ibpd->device);
1743 spin_lock(&dev->n_pds_lock);
1744 dev->n_pds_allocated--;
1745 spin_unlock(&dev->n_pds_lock);
1752 int qib_check_ah(struct ib_device *ibdev, struct ib_ah_attr *ah_attr)
1754 /* A multicast address requires a GRH (see ch. 8.4.1). */
1755 if (ah_attr->dlid >= QIB_MULTICAST_LID_BASE &&
1756 ah_attr->dlid != QIB_PERMISSIVE_LID &&
1757 !(ah_attr->ah_flags & IB_AH_GRH))
1759 if ((ah_attr->ah_flags & IB_AH_GRH) &&
1760 ah_attr->grh.sgid_index >= QIB_GUIDS_PER_PORT)
1762 if (ah_attr->dlid == 0)
1764 if (ah_attr->port_num < 1 ||
1765 ah_attr->port_num > ibdev->phys_port_cnt)
1767 if (ah_attr->static_rate != IB_RATE_PORT_CURRENT &&
1768 ib_rate_to_mult(ah_attr->static_rate) < 0)
1770 if (ah_attr->sl > 15)
1778 * qib_create_ah - create an address handle
1779 * @pd: the protection domain
1780 * @ah_attr: the attributes of the AH
1782 * This may be called from interrupt context.
1784 static struct ib_ah *qib_create_ah(struct ib_pd *pd,
1785 struct ib_ah_attr *ah_attr)
1789 struct qib_ibdev *dev = to_idev(pd->device);
1790 unsigned long flags;
1792 if (qib_check_ah(pd->device, ah_attr)) {
1793 ret = ERR_PTR(-EINVAL);
1797 ah = kmalloc(sizeof *ah, GFP_ATOMIC);
1799 ret = ERR_PTR(-ENOMEM);
1803 spin_lock_irqsave(&dev->n_ahs_lock, flags);
1804 if (dev->n_ahs_allocated == ib_qib_max_ahs) {
1805 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1807 ret = ERR_PTR(-ENOMEM);
1811 dev->n_ahs_allocated++;
1812 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1814 /* ib_create_ah() will initialize ah->ibah. */
1815 ah->attr = *ah_attr;
1816 atomic_set(&ah->refcount, 0);
1825 * qib_destroy_ah - destroy an address handle
1826 * @ibah: the AH to destroy
1828 * This may be called from interrupt context.
1830 static int qib_destroy_ah(struct ib_ah *ibah)
1832 struct qib_ibdev *dev = to_idev(ibah->device);
1833 struct qib_ah *ah = to_iah(ibah);
1834 unsigned long flags;
1836 if (atomic_read(&ah->refcount) != 0)
1839 spin_lock_irqsave(&dev->n_ahs_lock, flags);
1840 dev->n_ahs_allocated--;
1841 spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
1848 static int qib_modify_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1850 struct qib_ah *ah = to_iah(ibah);
1852 if (qib_check_ah(ibah->device, ah_attr))
1855 ah->attr = *ah_attr;
1860 static int qib_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
1862 struct qib_ah *ah = to_iah(ibah);
1864 *ah_attr = ah->attr;
1870 * qib_get_npkeys - return the size of the PKEY table for context 0
1871 * @dd: the qlogic_ib device
1873 unsigned qib_get_npkeys(struct qib_devdata *dd)
1875 return ARRAY_SIZE(dd->rcd[0]->pkeys);
1879 * Return the indexed PKEY from the port PKEY table.
1880 * No need to validate rcd[ctxt]; the port is setup if we are here.
1882 unsigned qib_get_pkey(struct qib_ibport *ibp, unsigned index)
1884 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1885 struct qib_devdata *dd = ppd->dd;
1886 unsigned ctxt = ppd->hw_pidx;
1889 /* dd->rcd null if mini_init or some init failures */
1890 if (!dd->rcd || index >= ARRAY_SIZE(dd->rcd[ctxt]->pkeys))
1893 ret = dd->rcd[ctxt]->pkeys[index];
1898 static int qib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1901 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1904 if (index >= qib_get_npkeys(dd)) {
1909 *pkey = qib_get_pkey(to_iport(ibdev, port), index);
1917 * qib_alloc_ucontext - allocate a ucontest
1918 * @ibdev: the infiniband device
1919 * @udata: not used by the QLogic_IB driver
1922 static struct ib_ucontext *qib_alloc_ucontext(struct ib_device *ibdev,
1923 struct ib_udata *udata)
1925 struct qib_ucontext *context;
1926 struct ib_ucontext *ret;
1928 context = kmalloc(sizeof *context, GFP_KERNEL);
1930 ret = ERR_PTR(-ENOMEM);
1934 ret = &context->ibucontext;
1940 static int qib_dealloc_ucontext(struct ib_ucontext *context)
1942 kfree(to_iucontext(context));
1946 static void init_ibport(struct qib_pportdata *ppd)
1948 struct qib_verbs_counters cntrs;
1949 struct qib_ibport *ibp = &ppd->ibport_data;
1951 spin_lock_init(&ibp->lock);
1952 /* Set the prefix to the default value (see ch. 4.1.1) */
1953 ibp->gid_prefix = IB_DEFAULT_GID_PREFIX;
1954 ibp->sm_lid = be16_to_cpu(IB_LID_PERMISSIVE);
1955 ibp->port_cap_flags = IB_PORT_SYS_IMAGE_GUID_SUP |
1956 IB_PORT_CLIENT_REG_SUP | IB_PORT_SL_MAP_SUP |
1957 IB_PORT_TRAP_SUP | IB_PORT_AUTO_MIGR_SUP |
1958 IB_PORT_DR_NOTICE_SUP | IB_PORT_CAP_MASK_NOTICE_SUP |
1959 IB_PORT_OTHER_LOCAL_CHANGES_SUP;
1960 if (ppd->dd->flags & QIB_HAS_LINK_LATENCY)
1961 ibp->port_cap_flags |= IB_PORT_LINK_LATENCY_SUP;
1962 ibp->pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
1963 ibp->pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
1964 ibp->pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
1965 ibp->pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
1966 ibp->pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
1968 /* Snapshot current HW counters to "clear" them. */
1969 qib_get_counters(ppd, &cntrs);
1970 ibp->z_symbol_error_counter = cntrs.symbol_error_counter;
1971 ibp->z_link_error_recovery_counter =
1972 cntrs.link_error_recovery_counter;
1973 ibp->z_link_downed_counter = cntrs.link_downed_counter;
1974 ibp->z_port_rcv_errors = cntrs.port_rcv_errors;
1975 ibp->z_port_rcv_remphys_errors = cntrs.port_rcv_remphys_errors;
1976 ibp->z_port_xmit_discards = cntrs.port_xmit_discards;
1977 ibp->z_port_xmit_data = cntrs.port_xmit_data;
1978 ibp->z_port_rcv_data = cntrs.port_rcv_data;
1979 ibp->z_port_xmit_packets = cntrs.port_xmit_packets;
1980 ibp->z_port_rcv_packets = cntrs.port_rcv_packets;
1981 ibp->z_local_link_integrity_errors =
1982 cntrs.local_link_integrity_errors;
1983 ibp->z_excessive_buffer_overrun_errors =
1984 cntrs.excessive_buffer_overrun_errors;
1985 ibp->z_vl15_dropped = cntrs.vl15_dropped;
1986 RCU_INIT_POINTER(ibp->qp0, NULL);
1987 RCU_INIT_POINTER(ibp->qp1, NULL);
1991 * qib_register_ib_device - register our device with the infiniband core
1992 * @dd: the device data structure
1993 * Return the allocated qib_ibdev pointer or NULL on error.
1995 int qib_register_ib_device(struct qib_devdata *dd)
1997 struct qib_ibdev *dev = &dd->verbs_dev;
1998 struct ib_device *ibdev = &dev->ibdev;
1999 struct qib_pportdata *ppd = dd->pport;
2000 unsigned i, lk_tab_size;
2003 dev->qp_table_size = ib_qib_qp_table_size;
2004 get_random_bytes(&dev->qp_rnd, sizeof(dev->qp_rnd));
2005 dev->qp_table = kmalloc(dev->qp_table_size * sizeof *dev->qp_table,
2007 if (!dev->qp_table) {
2011 for (i = 0; i < dev->qp_table_size; i++)
2012 RCU_INIT_POINTER(dev->qp_table[i], NULL);
2014 for (i = 0; i < dd->num_pports; i++)
2015 init_ibport(ppd + i);
2017 /* Only need to initialize non-zero fields. */
2018 spin_lock_init(&dev->qpt_lock);
2019 spin_lock_init(&dev->n_pds_lock);
2020 spin_lock_init(&dev->n_ahs_lock);
2021 spin_lock_init(&dev->n_cqs_lock);
2022 spin_lock_init(&dev->n_qps_lock);
2023 spin_lock_init(&dev->n_srqs_lock);
2024 spin_lock_init(&dev->n_mcast_grps_lock);
2025 init_timer(&dev->mem_timer);
2026 dev->mem_timer.function = mem_timer;
2027 dev->mem_timer.data = (unsigned long) dev;
2029 qib_init_qpn_table(dd, &dev->qpn_table);
2032 * The top ib_qib_lkey_table_size bits are used to index the
2033 * table. The lower 8 bits can be owned by the user (copied from
2034 * the LKEY). The remaining bits act as a generation number or tag.
2036 spin_lock_init(&dev->lk_table.lock);
2037 dev->lk_table.max = 1 << ib_qib_lkey_table_size;
2038 lk_tab_size = dev->lk_table.max * sizeof(*dev->lk_table.table);
2039 dev->lk_table.table = (struct qib_mregion **)
2040 __get_free_pages(GFP_KERNEL, get_order(lk_tab_size));
2041 if (dev->lk_table.table == NULL) {
2045 memset(dev->lk_table.table, 0, lk_tab_size);
2046 INIT_LIST_HEAD(&dev->pending_mmaps);
2047 spin_lock_init(&dev->pending_lock);
2048 dev->mmap_offset = PAGE_SIZE;
2049 spin_lock_init(&dev->mmap_offset_lock);
2050 INIT_LIST_HEAD(&dev->piowait);
2051 INIT_LIST_HEAD(&dev->dmawait);
2052 INIT_LIST_HEAD(&dev->txwait);
2053 INIT_LIST_HEAD(&dev->memwait);
2054 INIT_LIST_HEAD(&dev->txreq_free);
2056 if (ppd->sdma_descq_cnt) {
2057 dev->pio_hdrs = dma_alloc_coherent(&dd->pcidev->dev,
2058 ppd->sdma_descq_cnt *
2059 sizeof(struct qib_pio_header),
2060 &dev->pio_hdrs_phys,
2062 if (!dev->pio_hdrs) {
2068 for (i = 0; i < ppd->sdma_descq_cnt; i++) {
2069 struct qib_verbs_txreq *tx;
2071 tx = kzalloc(sizeof *tx, GFP_KERNEL);
2077 list_add(&tx->txreq.list, &dev->txreq_free);
2081 * The system image GUID is supposed to be the same for all
2082 * IB HCAs in a single system but since there can be other
2083 * device types in the system, we can't be sure this is unique.
2085 if (!ib_qib_sys_image_guid)
2086 ib_qib_sys_image_guid = ppd->guid;
2088 strlcpy(ibdev->name, "qib%d", IB_DEVICE_NAME_MAX);
2089 ibdev->owner = THIS_MODULE;
2090 ibdev->node_guid = ppd->guid;
2091 ibdev->uverbs_abi_ver = QIB_UVERBS_ABI_VERSION;
2092 ibdev->uverbs_cmd_mask =
2093 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2094 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2095 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2096 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2097 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2098 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
2099 (1ull << IB_USER_VERBS_CMD_MODIFY_AH) |
2100 (1ull << IB_USER_VERBS_CMD_QUERY_AH) |
2101 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
2102 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2103 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2104 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2105 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2106 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2107 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2108 (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
2109 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
2110 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2111 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2112 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2113 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2114 (1ull << IB_USER_VERBS_CMD_POST_SEND) |
2115 (1ull << IB_USER_VERBS_CMD_POST_RECV) |
2116 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2117 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2118 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2119 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2120 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2121 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2122 (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV);
2123 ibdev->node_type = RDMA_NODE_IB_CA;
2124 ibdev->phys_port_cnt = dd->num_pports;
2125 ibdev->num_comp_vectors = 1;
2126 ibdev->dma_device = &dd->pcidev->dev;
2127 ibdev->query_device = qib_query_device;
2128 ibdev->modify_device = qib_modify_device;
2129 ibdev->query_port = qib_query_port;
2130 ibdev->modify_port = qib_modify_port;
2131 ibdev->query_pkey = qib_query_pkey;
2132 ibdev->query_gid = qib_query_gid;
2133 ibdev->alloc_ucontext = qib_alloc_ucontext;
2134 ibdev->dealloc_ucontext = qib_dealloc_ucontext;
2135 ibdev->alloc_pd = qib_alloc_pd;
2136 ibdev->dealloc_pd = qib_dealloc_pd;
2137 ibdev->create_ah = qib_create_ah;
2138 ibdev->destroy_ah = qib_destroy_ah;
2139 ibdev->modify_ah = qib_modify_ah;
2140 ibdev->query_ah = qib_query_ah;
2141 ibdev->create_srq = qib_create_srq;
2142 ibdev->modify_srq = qib_modify_srq;
2143 ibdev->query_srq = qib_query_srq;
2144 ibdev->destroy_srq = qib_destroy_srq;
2145 ibdev->create_qp = qib_create_qp;
2146 ibdev->modify_qp = qib_modify_qp;
2147 ibdev->query_qp = qib_query_qp;
2148 ibdev->destroy_qp = qib_destroy_qp;
2149 ibdev->post_send = qib_post_send;
2150 ibdev->post_recv = qib_post_receive;
2151 ibdev->post_srq_recv = qib_post_srq_receive;
2152 ibdev->create_cq = qib_create_cq;
2153 ibdev->destroy_cq = qib_destroy_cq;
2154 ibdev->resize_cq = qib_resize_cq;
2155 ibdev->poll_cq = qib_poll_cq;
2156 ibdev->req_notify_cq = qib_req_notify_cq;
2157 ibdev->get_dma_mr = qib_get_dma_mr;
2158 ibdev->reg_phys_mr = qib_reg_phys_mr;
2159 ibdev->reg_user_mr = qib_reg_user_mr;
2160 ibdev->dereg_mr = qib_dereg_mr;
2161 ibdev->alloc_fast_reg_mr = qib_alloc_fast_reg_mr;
2162 ibdev->alloc_fast_reg_page_list = qib_alloc_fast_reg_page_list;
2163 ibdev->free_fast_reg_page_list = qib_free_fast_reg_page_list;
2164 ibdev->alloc_fmr = qib_alloc_fmr;
2165 ibdev->map_phys_fmr = qib_map_phys_fmr;
2166 ibdev->unmap_fmr = qib_unmap_fmr;
2167 ibdev->dealloc_fmr = qib_dealloc_fmr;
2168 ibdev->attach_mcast = qib_multicast_attach;
2169 ibdev->detach_mcast = qib_multicast_detach;
2170 ibdev->process_mad = qib_process_mad;
2171 ibdev->mmap = qib_mmap;
2172 ibdev->dma_ops = &qib_dma_mapping_ops;
2174 snprintf(ibdev->node_desc, sizeof(ibdev->node_desc),
2175 QIB_IDSTR " %s", init_utsname()->nodename);
2177 ret = ib_register_device(ibdev, qib_create_port_files);
2181 ret = qib_create_agents(dev);
2185 if (qib_verbs_register_sysfs(dd))
2191 qib_free_agents(dev);
2193 ib_unregister_device(ibdev);
2196 while (!list_empty(&dev->txreq_free)) {
2197 struct list_head *l = dev->txreq_free.next;
2198 struct qib_verbs_txreq *tx;
2201 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
2204 if (ppd->sdma_descq_cnt)
2205 dma_free_coherent(&dd->pcidev->dev,
2206 ppd->sdma_descq_cnt *
2207 sizeof(struct qib_pio_header),
2208 dev->pio_hdrs, dev->pio_hdrs_phys);
2210 free_pages((unsigned long) dev->lk_table.table, get_order(lk_tab_size));
2212 kfree(dev->qp_table);
2214 qib_dev_err(dd, "cannot register verbs: %d!\n", -ret);
2219 void qib_unregister_ib_device(struct qib_devdata *dd)
2221 struct qib_ibdev *dev = &dd->verbs_dev;
2222 struct ib_device *ibdev = &dev->ibdev;
2224 unsigned lk_tab_size;
2226 qib_verbs_unregister_sysfs(dd);
2228 qib_free_agents(dev);
2230 ib_unregister_device(ibdev);
2232 if (!list_empty(&dev->piowait))
2233 qib_dev_err(dd, "piowait list not empty!\n");
2234 if (!list_empty(&dev->dmawait))
2235 qib_dev_err(dd, "dmawait list not empty!\n");
2236 if (!list_empty(&dev->txwait))
2237 qib_dev_err(dd, "txwait list not empty!\n");
2238 if (!list_empty(&dev->memwait))
2239 qib_dev_err(dd, "memwait list not empty!\n");
2241 qib_dev_err(dd, "DMA MR not NULL!\n");
2243 qps_inuse = qib_free_all_qps(dd);
2245 qib_dev_err(dd, "QP memory leak! %u still in use\n",
2248 del_timer_sync(&dev->mem_timer);
2249 qib_free_qpn_table(&dev->qpn_table);
2250 while (!list_empty(&dev->txreq_free)) {
2251 struct list_head *l = dev->txreq_free.next;
2252 struct qib_verbs_txreq *tx;
2255 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
2258 if (dd->pport->sdma_descq_cnt)
2259 dma_free_coherent(&dd->pcidev->dev,
2260 dd->pport->sdma_descq_cnt *
2261 sizeof(struct qib_pio_header),
2262 dev->pio_hdrs, dev->pio_hdrs_phys);
2263 lk_tab_size = dev->lk_table.max * sizeof(*dev->lk_table.table);
2264 free_pages((unsigned long) dev->lk_table.table,
2265 get_order(lk_tab_size));
2266 kfree(dev->qp_table);