2 * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/sched.h>
35 #include <linux/spinlock.h>
36 #include <linux/idr.h>
37 #include <linux/pci.h>
39 #include <linux/delay.h>
40 #include <linux/netdevice.h>
41 #include <linux/vmalloc.h>
42 #include <linux/bitmap.h>
43 #include <linux/slab.h>
45 #include "ipath_kernel.h"
46 #include "ipath_verbs.h"
48 static void ipath_update_pio_bufs(struct ipath_devdata *);
50 const char *ipath_get_unit_name(int unit)
52 static char iname[16];
53 snprintf(iname, sizeof iname, "infinipath%u", unit);
57 #define DRIVER_LOAD_MSG "QLogic " IPATH_DRV_NAME " loaded: "
58 #define PFX IPATH_DRV_NAME ": "
61 * The size has to be longer than this string, so we can append
62 * board/chip information to it in the init code.
64 const char ib_ipath_version[] = IPATH_IDSTR "\n";
66 static struct idr unit_table;
67 DEFINE_SPINLOCK(ipath_devs_lock);
68 LIST_HEAD(ipath_dev_list);
70 wait_queue_head_t ipath_state_wait;
72 unsigned ipath_debug = __IPATH_INFO;
74 module_param_named(debug, ipath_debug, uint, S_IWUSR | S_IRUGO);
75 MODULE_PARM_DESC(debug, "mask for debug prints");
76 EXPORT_SYMBOL_GPL(ipath_debug);
78 unsigned ipath_mtu4096 = 1; /* max 4KB IB mtu by default, if supported */
79 module_param_named(mtu4096, ipath_mtu4096, uint, S_IRUGO);
80 MODULE_PARM_DESC(mtu4096, "enable MTU of 4096 bytes, if supported");
82 static unsigned ipath_hol_timeout_ms = 13000;
83 module_param_named(hol_timeout_ms, ipath_hol_timeout_ms, uint, S_IRUGO);
84 MODULE_PARM_DESC(hol_timeout_ms,
85 "duration of user app suspension after link failure");
87 unsigned ipath_linkrecovery = 1;
88 module_param_named(linkrecovery, ipath_linkrecovery, uint, S_IWUSR | S_IRUGO);
89 MODULE_PARM_DESC(linkrecovery, "enable workaround for link recovery issue");
91 MODULE_LICENSE("GPL");
92 MODULE_AUTHOR("QLogic <support@qlogic.com>");
93 MODULE_DESCRIPTION("QLogic InfiniPath driver");
96 * Table to translate the LINKTRAININGSTATE portion of
97 * IBCStatus to a human-readable form.
99 const char *ipath_ibcstatus_str[] = {
106 "LState6", /* unused */
107 "LState7", /* unused */
113 "CfgTxRevLane", /* unused before IBA7220 */
116 /* below were added for IBA7220 */
120 "CfgWaitCfgEnhanced",
125 "LTState18", "LTState19", "LTState1A", "LTState1B",
126 "LTState1C", "LTState1D", "LTState1E", "LTState1F"
129 static void __devexit ipath_remove_one(struct pci_dev *);
130 static int __devinit ipath_init_one(struct pci_dev *,
131 const struct pci_device_id *);
133 /* Only needed for registration, nothing else needs this info */
134 #define PCI_VENDOR_ID_PATHSCALE 0x1fc1
135 #define PCI_DEVICE_ID_INFINIPATH_HT 0xd
137 /* Number of seconds before our card status check... */
138 #define STATUS_TIMEOUT 60
140 static const struct pci_device_id ipath_pci_tbl[] = {
141 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_INFINIPATH_HT) },
145 MODULE_DEVICE_TABLE(pci, ipath_pci_tbl);
147 static struct pci_driver ipath_driver = {
148 .name = IPATH_DRV_NAME,
149 .probe = ipath_init_one,
150 .remove = __devexit_p(ipath_remove_one),
151 .id_table = ipath_pci_tbl,
153 .groups = ipath_driver_attr_groups,
157 static inline void read_bars(struct ipath_devdata *dd, struct pci_dev *dev,
158 u32 *bar0, u32 *bar1)
162 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
164 ipath_dev_err(dd, "failed to read bar0 before enable: "
167 ret = pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, bar1);
169 ipath_dev_err(dd, "failed to read bar1 before enable: "
172 ipath_dbg("Read bar0 %x bar1 %x\n", *bar0, *bar1);
175 static void ipath_free_devdata(struct pci_dev *pdev,
176 struct ipath_devdata *dd)
180 pci_set_drvdata(pdev, NULL);
182 if (dd->ipath_unit != -1) {
183 spin_lock_irqsave(&ipath_devs_lock, flags);
184 idr_remove(&unit_table, dd->ipath_unit);
185 list_del(&dd->ipath_list);
186 spin_unlock_irqrestore(&ipath_devs_lock, flags);
191 static struct ipath_devdata *ipath_alloc_devdata(struct pci_dev *pdev)
194 struct ipath_devdata *dd;
197 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
198 dd = ERR_PTR(-ENOMEM);
202 dd = vmalloc(sizeof(*dd));
204 dd = ERR_PTR(-ENOMEM);
207 memset(dd, 0, sizeof(*dd));
210 spin_lock_irqsave(&ipath_devs_lock, flags);
212 ret = idr_get_new(&unit_table, dd, &dd->ipath_unit);
214 printk(KERN_ERR IPATH_DRV_NAME
215 ": Could not allocate unit ID: error %d\n", -ret);
216 ipath_free_devdata(pdev, dd);
222 pci_set_drvdata(pdev, dd);
224 list_add(&dd->ipath_list, &ipath_dev_list);
227 spin_unlock_irqrestore(&ipath_devs_lock, flags);
233 static inline struct ipath_devdata *__ipath_lookup(int unit)
235 return idr_find(&unit_table, unit);
238 struct ipath_devdata *ipath_lookup(int unit)
240 struct ipath_devdata *dd;
243 spin_lock_irqsave(&ipath_devs_lock, flags);
244 dd = __ipath_lookup(unit);
245 spin_unlock_irqrestore(&ipath_devs_lock, flags);
250 int ipath_count_units(int *npresentp, int *nupp, int *maxportsp)
252 int nunits, npresent, nup;
253 struct ipath_devdata *dd;
257 nunits = npresent = nup = maxports = 0;
259 spin_lock_irqsave(&ipath_devs_lock, flags);
261 list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
263 if ((dd->ipath_flags & IPATH_PRESENT) && dd->ipath_kregbase)
266 !(dd->ipath_flags & (IPATH_DISABLED | IPATH_LINKDOWN
269 if (dd->ipath_cfgports > maxports)
270 maxports = dd->ipath_cfgports;
273 spin_unlock_irqrestore(&ipath_devs_lock, flags);
276 *npresentp = npresent;
280 *maxportsp = maxports;
286 * These next two routines are placeholders in case we don't have per-arch
287 * code for controlling write combining. If explicit control of write
288 * combining is not available, performance will probably be awful.
291 int __attribute__((weak)) ipath_enable_wc(struct ipath_devdata *dd)
296 void __attribute__((weak)) ipath_disable_wc(struct ipath_devdata *dd)
301 * Perform a PIO buffer bandwidth write test, to verify proper system
302 * configuration. Even when all the setup calls work, occasionally
303 * BIOS or other issues can prevent write combining from working, or
304 * can cause other bandwidth problems to the chip.
306 * This test simply writes the same buffer over and over again, and
307 * measures close to the peak bandwidth to the chip (not testing
308 * data bandwidth to the wire). On chips that use an address-based
309 * trigger to send packets to the wire, this is easy. On chips that
310 * use a count to trigger, we want to make sure that the packet doesn't
311 * go out on the wire, or trigger flow control checks.
313 static void ipath_verify_pioperf(struct ipath_devdata *dd)
315 u32 pbnum, cnt, lcnt;
320 piobuf = ipath_getpiobuf(dd, 0, &pbnum);
322 dev_info(&dd->pcidev->dev,
323 "No PIObufs for checking perf, skipping\n");
328 * Enough to give us a reasonable test, less than piobuf size, and
329 * likely multiple of store buffer length.
335 dev_info(&dd->pcidev->dev,
336 "Couldn't get memory for checking PIO perf,"
341 preempt_disable(); /* we want reasonably accurate elapsed time */
342 msecs = 1 + jiffies_to_msecs(jiffies);
343 for (lcnt = 0; lcnt < 10000U; lcnt++) {
344 /* wait until we cross msec boundary */
345 if (jiffies_to_msecs(jiffies) >= msecs)
350 ipath_disable_armlaunch(dd);
353 * length 0, no dwords actually sent, and mark as VL15
354 * on chips where that may matter (due to IB flowcontrol)
356 if ((dd->ipath_flags & IPATH_HAS_PBC_CNT))
357 writeq(1UL << 63, piobuf);
363 * this is only roughly accurate, since even with preempt we
364 * still take interrupts that could take a while. Running for
365 * >= 5 msec seems to get us "close enough" to accurate values
367 msecs = jiffies_to_msecs(jiffies);
368 for (emsecs = lcnt = 0; emsecs <= 5UL; lcnt++) {
369 __iowrite32_copy(piobuf + 64, addr, cnt >> 2);
370 emsecs = jiffies_to_msecs(jiffies) - msecs;
373 /* 1 GiB/sec, slightly over IB SDR line rate */
374 if (lcnt < (emsecs * 1024U))
376 "Performance problem: bandwidth to PIO buffers is "
378 lcnt / (u32) emsecs);
380 ipath_dbg("PIO buffer bandwidth %u MiB/sec is OK\n",
381 lcnt / (u32) emsecs);
388 /* disarm piobuf, so it's available again */
389 ipath_disarm_piobufs(dd, pbnum, 1);
390 ipath_enable_armlaunch(dd);
393 static void cleanup_device(struct ipath_devdata *dd);
395 static int __devinit ipath_init_one(struct pci_dev *pdev,
396 const struct pci_device_id *ent)
399 struct ipath_devdata *dd;
400 unsigned long long addr;
401 u32 bar0 = 0, bar1 = 0;
404 dd = ipath_alloc_devdata(pdev);
407 printk(KERN_ERR IPATH_DRV_NAME
408 ": Could not allocate devdata: error %d\n", -ret);
412 ipath_cdbg(VERBOSE, "initializing unit #%u\n", dd->ipath_unit);
414 ret = pci_enable_device(pdev);
416 /* This can happen iff:
418 * We did a chip reset, and then failed to reprogram the
419 * BAR, or the chip reset due to an internal error. We then
420 * unloaded the driver and reloaded it.
422 * Both reset cases set the BAR back to initial state. For
423 * the latter case, the AER sticky error bit at offset 0x718
424 * should be set, but the Linux kernel doesn't yet know
425 * about that, it appears. If the original BAR was retained
426 * in the kernel data structures, this may be OK.
428 ipath_dev_err(dd, "enable unit %d failed: error %d\n",
429 dd->ipath_unit, -ret);
432 addr = pci_resource_start(pdev, 0);
433 len = pci_resource_len(pdev, 0);
434 ipath_cdbg(VERBOSE, "regbase (0) %llx len %d irq %d, vend %x/%x "
435 "driver_data %lx\n", addr, len, pdev->irq, ent->vendor,
436 ent->device, ent->driver_data);
438 read_bars(dd, pdev, &bar0, &bar1);
440 if (!bar1 && !(bar0 & ~0xf)) {
442 dev_info(&pdev->dev, "BAR is 0 (probable RESET), "
443 "rewriting as %llx\n", addr);
444 ret = pci_write_config_dword(
445 pdev, PCI_BASE_ADDRESS_0, addr);
447 ipath_dev_err(dd, "rewrite of BAR0 "
448 "failed: err %d\n", -ret);
451 ret = pci_write_config_dword(
452 pdev, PCI_BASE_ADDRESS_1, addr >> 32);
454 ipath_dev_err(dd, "rewrite of BAR1 "
455 "failed: err %d\n", -ret);
459 ipath_dev_err(dd, "BAR is 0 (probable RESET), "
460 "not usable until reboot\n");
466 ret = pci_request_regions(pdev, IPATH_DRV_NAME);
468 dev_info(&pdev->dev, "pci_request_regions unit %u fails: "
469 "err %d\n", dd->ipath_unit, -ret);
473 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
476 * if the 64 bit setup fails, try 32 bit. Some systems
477 * do not setup 64 bit maps on systems with 2GB or less
480 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
483 "Unable to set DMA mask for unit %u: %d\n",
484 dd->ipath_unit, ret);
488 ipath_dbg("No 64bit DMA mask, used 32 bit mask\n");
489 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
492 "Unable to set DMA consistent mask "
494 dd->ipath_unit, ret);
499 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
502 "Unable to set DMA consistent mask "
504 dd->ipath_unit, ret);
507 pci_set_master(pdev);
510 * Save BARs to rewrite after device reset. Save all 64 bits of
513 dd->ipath_pcibar0 = addr;
514 dd->ipath_pcibar1 = addr >> 32;
515 dd->ipath_deviceid = ent->device; /* save for later use */
516 dd->ipath_vendorid = ent->vendor;
518 /* setup the chip-specific functions, as early as possible. */
519 switch (ent->device) {
520 case PCI_DEVICE_ID_INFINIPATH_HT:
521 ipath_init_iba6110_funcs(dd);
525 ipath_dev_err(dd, "Found unknown QLogic deviceid 0x%x, "
526 "failing\n", ent->device);
530 for (j = 0; j < 6; j++) {
531 if (!pdev->resource[j].start)
533 ipath_cdbg(VERBOSE, "BAR %d %pR, len %llx\n",
534 j, &pdev->resource[j],
535 (unsigned long long)pci_resource_len(pdev, j));
539 ipath_dev_err(dd, "No valid address in BAR 0!\n");
544 ret = pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
546 ipath_dev_err(dd, "Failed to read PCI revision ID unit "
547 "%u: err %d\n", dd->ipath_unit, -ret);
548 goto bail_regions; /* shouldn't ever happen */
550 dd->ipath_pcirev = rev;
552 #if defined(__powerpc__)
553 /* There isn't a generic way to specify writethrough mappings */
554 dd->ipath_kregbase = __ioremap(addr, len,
555 (_PAGE_NO_CACHE|_PAGE_WRITETHRU));
557 dd->ipath_kregbase = ioremap_nocache(addr, len);
560 if (!dd->ipath_kregbase) {
561 ipath_dbg("Unable to map io addr %llx to kvirt, failing\n",
566 dd->ipath_kregend = (u64 __iomem *)
567 ((void __iomem *)dd->ipath_kregbase + len);
568 dd->ipath_physaddr = addr; /* used for io_remap, etc. */
570 ipath_cdbg(VERBOSE, "mapped io addr %llx to kregbase %p\n",
571 addr, dd->ipath_kregbase);
573 if (dd->ipath_f_bus(dd, pdev))
574 ipath_dev_err(dd, "Failed to setup config space; "
575 "continuing anyway\n");
578 * set up our interrupt handler; IRQF_SHARED probably not needed,
579 * since MSI interrupts shouldn't be shared but won't hurt for now.
580 * check 0 irq after we return from chip-specific bus setup, since
581 * that can affect this due to setup
584 ipath_dev_err(dd, "irq is 0, BIOS error? Interrupts won't "
587 ret = request_irq(dd->ipath_irq, ipath_intr, IRQF_SHARED,
590 ipath_dev_err(dd, "Couldn't setup irq handler, "
591 "irq=%d: %d\n", dd->ipath_irq, ret);
596 ret = ipath_init_chip(dd, 0); /* do the chip-specific init */
600 ret = ipath_enable_wc(dd);
603 ipath_dev_err(dd, "Write combining not enabled "
604 "(err %d): performance may be poor\n",
609 ipath_verify_pioperf(dd);
611 ipath_device_create_group(&pdev->dev, dd);
612 ipathfs_add_device(dd);
615 ipath_register_ib_device(dd);
623 dd->ipath_f_free_irq(dd);
625 if (dd->ipath_f_cleanup)
626 dd->ipath_f_cleanup(dd);
629 iounmap((volatile void __iomem *) dd->ipath_kregbase);
632 pci_release_regions(pdev);
635 pci_disable_device(pdev);
638 ipath_free_devdata(pdev, dd);
644 static void cleanup_device(struct ipath_devdata *dd)
647 struct ipath_portdata **tmp;
650 if (*dd->ipath_statusp & IPATH_STATUS_CHIP_PRESENT) {
651 /* can't do anything more with chip; needs re-init */
652 *dd->ipath_statusp &= ~IPATH_STATUS_CHIP_PRESENT;
653 if (dd->ipath_kregbase) {
655 * if we haven't already cleaned up before these are
656 * to ensure any register reads/writes "fail" until
659 dd->ipath_kregbase = NULL;
660 dd->ipath_uregbase = 0;
661 dd->ipath_sregbase = 0;
662 dd->ipath_cregbase = 0;
663 dd->ipath_kregsize = 0;
665 ipath_disable_wc(dd);
668 if (dd->ipath_spectriggerhit)
669 dev_info(&dd->pcidev->dev, "%lu special trigger hits\n",
670 dd->ipath_spectriggerhit);
672 if (dd->ipath_pioavailregs_dma) {
673 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
674 (void *) dd->ipath_pioavailregs_dma,
675 dd->ipath_pioavailregs_phys);
676 dd->ipath_pioavailregs_dma = NULL;
678 if (dd->ipath_dummy_hdrq) {
679 dma_free_coherent(&dd->pcidev->dev,
680 dd->ipath_pd[0]->port_rcvhdrq_size,
681 dd->ipath_dummy_hdrq, dd->ipath_dummy_hdrq_phys);
682 dd->ipath_dummy_hdrq = NULL;
685 if (dd->ipath_pageshadow) {
686 struct page **tmpp = dd->ipath_pageshadow;
687 dma_addr_t *tmpd = dd->ipath_physshadow;
690 ipath_cdbg(VERBOSE, "Unlocking any expTID pages still "
692 for (port = 0; port < dd->ipath_cfgports; port++) {
693 int port_tidbase = port * dd->ipath_rcvtidcnt;
694 int maxtid = port_tidbase + dd->ipath_rcvtidcnt;
695 for (i = port_tidbase; i < maxtid; i++) {
698 pci_unmap_page(dd->pcidev, tmpd[i],
699 PAGE_SIZE, PCI_DMA_FROMDEVICE);
700 ipath_release_user_pages(&tmpp[i], 1);
706 ipath_stats.sps_pageunlocks += cnt;
707 ipath_cdbg(VERBOSE, "There were still %u expTID "
708 "entries locked\n", cnt);
710 if (ipath_stats.sps_pagelocks ||
711 ipath_stats.sps_pageunlocks)
712 ipath_cdbg(VERBOSE, "%llu pages locked, %llu "
713 "unlocked via ipath_m{un}lock\n",
715 ipath_stats.sps_pagelocks,
717 ipath_stats.sps_pageunlocks);
719 ipath_cdbg(VERBOSE, "Free shadow page tid array at %p\n",
720 dd->ipath_pageshadow);
721 tmpp = dd->ipath_pageshadow;
722 dd->ipath_pageshadow = NULL;
725 dd->ipath_egrtidbase = NULL;
729 * free any resources still in use (usually just kernel ports)
730 * at unload; we do for portcnt, because that's what we allocate.
731 * We acquire lock to be really paranoid that ipath_pd isn't being
732 * accessed from some interrupt-related code (that should not happen,
733 * but best to be sure).
735 spin_lock_irqsave(&dd->ipath_uctxt_lock, flags);
738 spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags);
739 for (port = 0; port < dd->ipath_portcnt; port++) {
740 struct ipath_portdata *pd = tmp[port];
741 tmp[port] = NULL; /* debugging paranoia */
742 ipath_free_pddata(dd, pd);
747 static void __devexit ipath_remove_one(struct pci_dev *pdev)
749 struct ipath_devdata *dd = pci_get_drvdata(pdev);
751 ipath_cdbg(VERBOSE, "removing, pdev=%p, dd=%p\n", pdev, dd);
754 * disable the IB link early, to be sure no new packets arrive, which
755 * complicates the shutdown process
757 ipath_shutdown_device(dd);
759 flush_scheduled_work();
762 ipath_unregister_ib_device(dd->verbs_dev);
764 ipath_diag_remove(dd);
765 ipath_user_remove(dd);
766 ipathfs_remove_device(dd);
767 ipath_device_remove_group(&pdev->dev, dd);
769 ipath_cdbg(VERBOSE, "Releasing pci memory regions, dd %p, "
770 "unit %u\n", dd, (u32) dd->ipath_unit);
775 * turn off rcv, send, and interrupts for all ports, all drivers
776 * should also hard reset the chip here?
777 * free up port 0 (kernel) rcvhdr, egr bufs, and eventually tid bufs
778 * for all versions of the driver, if they were allocated
781 ipath_cdbg(VERBOSE, "unit %u free irq %d\n",
782 dd->ipath_unit, dd->ipath_irq);
783 dd->ipath_f_free_irq(dd);
785 ipath_dbg("irq is 0, not doing free_irq "
786 "for unit %u\n", dd->ipath_unit);
788 * we check for NULL here, because it's outside
789 * the kregbase check, and we need to call it
790 * after the free_irq. Thus it's possible that
791 * the function pointers were never initialized.
793 if (dd->ipath_f_cleanup)
794 /* clean up chip-specific stuff */
795 dd->ipath_f_cleanup(dd);
797 ipath_cdbg(VERBOSE, "Unmapping kregbase %p\n", dd->ipath_kregbase);
798 iounmap((volatile void __iomem *) dd->ipath_kregbase);
799 pci_release_regions(pdev);
800 ipath_cdbg(VERBOSE, "calling pci_disable_device\n");
801 pci_disable_device(pdev);
803 ipath_free_devdata(pdev, dd);
806 /* general driver use */
807 DEFINE_MUTEX(ipath_mutex);
809 static DEFINE_SPINLOCK(ipath_pioavail_lock);
812 * ipath_disarm_piobufs - cancel a range of PIO buffers
813 * @dd: the infinipath device
814 * @first: the first PIO buffer to cancel
815 * @cnt: the number of PIO buffers to cancel
817 * cancel a range of PIO buffers, used when they might be armed, but
818 * not triggered. Used at init to ensure buffer state, and also user
819 * process close, in case it died while writing to a PIO buffer
822 void ipath_disarm_piobufs(struct ipath_devdata *dd, unsigned first,
825 unsigned i, last = first + cnt;
828 ipath_cdbg(PKT, "disarm %u PIObufs first=%u\n", cnt, first);
829 for (i = first; i < last; i++) {
830 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
832 * The disarm-related bits are write-only, so it
833 * is ok to OR them in with our copy of sendctrl
834 * while we hold the lock.
836 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
837 dd->ipath_sendctrl | INFINIPATH_S_DISARM |
838 (i << INFINIPATH_S_DISARMPIOBUF_SHIFT));
839 /* can't disarm bufs back-to-back per iba7220 spec */
840 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
841 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
843 /* on some older chips, update may not happen after cancel */
844 ipath_force_pio_avail_update(dd);
848 * ipath_wait_linkstate - wait for an IB link state change to occur
849 * @dd: the infinipath device
850 * @state: the state to wait for
851 * @msecs: the number of milliseconds to wait
853 * wait up to msecs milliseconds for IB link state change to occur for
854 * now, take the easy polling route. Currently used only by
855 * ipath_set_linkstate. Returns 0 if state reached, otherwise
856 * -ETIMEDOUT state can have multiple states set, for any of several
859 int ipath_wait_linkstate(struct ipath_devdata *dd, u32 state, int msecs)
861 dd->ipath_state_wanted = state;
862 wait_event_interruptible_timeout(ipath_state_wait,
863 (dd->ipath_flags & state),
864 msecs_to_jiffies(msecs));
865 dd->ipath_state_wanted = 0;
867 if (!(dd->ipath_flags & state)) {
869 ipath_cdbg(VERBOSE, "Didn't reach linkstate %s within %u"
871 /* test INIT ahead of DOWN, both can be set */
872 (state & IPATH_LINKINIT) ? "INIT" :
873 ((state & IPATH_LINKDOWN) ? "DOWN" :
874 ((state & IPATH_LINKARMED) ? "ARM" : "ACTIVE")),
876 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
877 ipath_cdbg(VERBOSE, "ibcc=%llx ibcstatus=%llx (%s)\n",
878 (unsigned long long) ipath_read_kreg64(
879 dd, dd->ipath_kregs->kr_ibcctrl),
880 (unsigned long long) val,
881 ipath_ibcstatus_str[val & dd->ibcs_lts_mask]);
883 return (dd->ipath_flags & state) ? 0 : -ETIMEDOUT;
886 static void decode_sdma_errs(struct ipath_devdata *dd, ipath_err_t err,
887 char *buf, size_t blen)
889 static const struct {
893 { INFINIPATH_E_SDMAGENMISMATCH, "SDmaGenMismatch" },
894 { INFINIPATH_E_SDMAOUTOFBOUND, "SDmaOutOfBound" },
895 { INFINIPATH_E_SDMATAILOUTOFBOUND, "SDmaTailOutOfBound" },
896 { INFINIPATH_E_SDMABASE, "SDmaBase" },
897 { INFINIPATH_E_SDMA1STDESC, "SDma1stDesc" },
898 { INFINIPATH_E_SDMARPYTAG, "SDmaRpyTag" },
899 { INFINIPATH_E_SDMADWEN, "SDmaDwEn" },
900 { INFINIPATH_E_SDMAMISSINGDW, "SDmaMissingDw" },
901 { INFINIPATH_E_SDMAUNEXPDATA, "SDmaUnexpData" },
902 { INFINIPATH_E_SDMADESCADDRMISALIGN, "SDmaDescAddrMisalign" },
903 { INFINIPATH_E_SENDBUFMISUSE, "SendBufMisuse" },
904 { INFINIPATH_E_SDMADISABLED, "SDmaDisabled" },
910 for (i = 0; i < ARRAY_SIZE(errs); i++) {
911 expected = (errs[i].err != INFINIPATH_E_SDMADISABLED) ? 0 :
912 test_bit(IPATH_SDMA_ABORTING, &dd->ipath_sdma_status);
913 if ((err & errs[i].err) && !expected)
914 bidx += snprintf(buf + bidx, blen - bidx,
920 * Decode the error status into strings, deciding whether to always
921 * print * it or not depending on "normal packet errors" vs everything
922 * else. Return 1 if "real" errors, otherwise 0 if only packet
923 * errors, so caller can decide what to print with the string.
925 int ipath_decode_err(struct ipath_devdata *dd, char *buf, size_t blen,
930 if (err & INFINIPATH_E_PKTERRS) {
931 if (!(err & ~INFINIPATH_E_PKTERRS))
932 iserr = 0; // if only packet errors.
933 if (ipath_debug & __IPATH_ERRPKTDBG) {
934 if (err & INFINIPATH_E_REBP)
935 strlcat(buf, "EBP ", blen);
936 if (err & INFINIPATH_E_RVCRC)
937 strlcat(buf, "VCRC ", blen);
938 if (err & INFINIPATH_E_RICRC) {
939 strlcat(buf, "CRC ", blen);
940 // clear for check below, so only once
941 err &= INFINIPATH_E_RICRC;
943 if (err & INFINIPATH_E_RSHORTPKTLEN)
944 strlcat(buf, "rshortpktlen ", blen);
945 if (err & INFINIPATH_E_SDROPPEDDATAPKT)
946 strlcat(buf, "sdroppeddatapkt ", blen);
947 if (err & INFINIPATH_E_SPKTLEN)
948 strlcat(buf, "spktlen ", blen);
950 if ((err & INFINIPATH_E_RICRC) &&
951 !(err&(INFINIPATH_E_RVCRC|INFINIPATH_E_REBP)))
952 strlcat(buf, "CRC ", blen);
956 if (err & INFINIPATH_E_RHDRLEN)
957 strlcat(buf, "rhdrlen ", blen);
958 if (err & INFINIPATH_E_RBADTID)
959 strlcat(buf, "rbadtid ", blen);
960 if (err & INFINIPATH_E_RBADVERSION)
961 strlcat(buf, "rbadversion ", blen);
962 if (err & INFINIPATH_E_RHDR)
963 strlcat(buf, "rhdr ", blen);
964 if (err & INFINIPATH_E_SENDSPECIALTRIGGER)
965 strlcat(buf, "sendspecialtrigger ", blen);
966 if (err & INFINIPATH_E_RLONGPKTLEN)
967 strlcat(buf, "rlongpktlen ", blen);
968 if (err & INFINIPATH_E_RMAXPKTLEN)
969 strlcat(buf, "rmaxpktlen ", blen);
970 if (err & INFINIPATH_E_RMINPKTLEN)
971 strlcat(buf, "rminpktlen ", blen);
972 if (err & INFINIPATH_E_SMINPKTLEN)
973 strlcat(buf, "sminpktlen ", blen);
974 if (err & INFINIPATH_E_RFORMATERR)
975 strlcat(buf, "rformaterr ", blen);
976 if (err & INFINIPATH_E_RUNSUPVL)
977 strlcat(buf, "runsupvl ", blen);
978 if (err & INFINIPATH_E_RUNEXPCHAR)
979 strlcat(buf, "runexpchar ", blen);
980 if (err & INFINIPATH_E_RIBFLOW)
981 strlcat(buf, "ribflow ", blen);
982 if (err & INFINIPATH_E_SUNDERRUN)
983 strlcat(buf, "sunderrun ", blen);
984 if (err & INFINIPATH_E_SPIOARMLAUNCH)
985 strlcat(buf, "spioarmlaunch ", blen);
986 if (err & INFINIPATH_E_SUNEXPERRPKTNUM)
987 strlcat(buf, "sunexperrpktnum ", blen);
988 if (err & INFINIPATH_E_SDROPPEDSMPPKT)
989 strlcat(buf, "sdroppedsmppkt ", blen);
990 if (err & INFINIPATH_E_SMAXPKTLEN)
991 strlcat(buf, "smaxpktlen ", blen);
992 if (err & INFINIPATH_E_SUNSUPVL)
993 strlcat(buf, "sunsupVL ", blen);
994 if (err & INFINIPATH_E_INVALIDADDR)
995 strlcat(buf, "invalidaddr ", blen);
996 if (err & INFINIPATH_E_RRCVEGRFULL)
997 strlcat(buf, "rcvegrfull ", blen);
998 if (err & INFINIPATH_E_RRCVHDRFULL)
999 strlcat(buf, "rcvhdrfull ", blen);
1000 if (err & INFINIPATH_E_IBSTATUSCHANGED)
1001 strlcat(buf, "ibcstatuschg ", blen);
1002 if (err & INFINIPATH_E_RIBLOSTLINK)
1003 strlcat(buf, "riblostlink ", blen);
1004 if (err & INFINIPATH_E_HARDWARE)
1005 strlcat(buf, "hardware ", blen);
1006 if (err & INFINIPATH_E_RESET)
1007 strlcat(buf, "reset ", blen);
1008 if (err & INFINIPATH_E_SDMAERRS)
1009 decode_sdma_errs(dd, err, buf, blen);
1010 if (err & INFINIPATH_E_INVALIDEEPCMD)
1011 strlcat(buf, "invalideepromcmd ", blen);
1017 * get_rhf_errstring - decode RHF errors
1018 * @err: the err number
1019 * @msg: the output buffer
1020 * @len: the length of the output buffer
1022 * only used one place now, may want more later
1024 static void get_rhf_errstring(u32 err, char *msg, size_t len)
1026 /* if no errors, and so don't need to check what's first */
1029 if (err & INFINIPATH_RHF_H_ICRCERR)
1030 strlcat(msg, "icrcerr ", len);
1031 if (err & INFINIPATH_RHF_H_VCRCERR)
1032 strlcat(msg, "vcrcerr ", len);
1033 if (err & INFINIPATH_RHF_H_PARITYERR)
1034 strlcat(msg, "parityerr ", len);
1035 if (err & INFINIPATH_RHF_H_LENERR)
1036 strlcat(msg, "lenerr ", len);
1037 if (err & INFINIPATH_RHF_H_MTUERR)
1038 strlcat(msg, "mtuerr ", len);
1039 if (err & INFINIPATH_RHF_H_IHDRERR)
1040 /* infinipath hdr checksum error */
1041 strlcat(msg, "ipathhdrerr ", len);
1042 if (err & INFINIPATH_RHF_H_TIDERR)
1043 strlcat(msg, "tiderr ", len);
1044 if (err & INFINIPATH_RHF_H_MKERR)
1045 /* bad port, offset, etc. */
1046 strlcat(msg, "invalid ipathhdr ", len);
1047 if (err & INFINIPATH_RHF_H_IBERR)
1048 strlcat(msg, "iberr ", len);
1049 if (err & INFINIPATH_RHF_L_SWA)
1050 strlcat(msg, "swA ", len);
1051 if (err & INFINIPATH_RHF_L_SWB)
1052 strlcat(msg, "swB ", len);
1056 * ipath_get_egrbuf - get an eager buffer
1057 * @dd: the infinipath device
1058 * @bufnum: the eager buffer to get
1060 * must only be called if ipath_pd[port] is known to be allocated
1062 static inline void *ipath_get_egrbuf(struct ipath_devdata *dd, u32 bufnum)
1064 return dd->ipath_port0_skbinfo ?
1065 (void *) dd->ipath_port0_skbinfo[bufnum].skb->data : NULL;
1069 * ipath_alloc_skb - allocate an skb and buffer with possible constraints
1070 * @dd: the infinipath device
1071 * @gfp_mask: the sk_buff SFP mask
1073 struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd,
1076 struct sk_buff *skb;
1080 * Only fully supported way to handle this is to allocate lots
1081 * extra, align as needed, and then do skb_reserve(). That wastes
1082 * a lot of memory... I'll have to hack this into infinipath_copy
1087 * We need 2 extra bytes for ipath_ether data sent in the
1088 * key header. In order to keep everything dword aligned,
1089 * we'll reserve 4 bytes.
1091 len = dd->ipath_ibmaxlen + 4;
1093 if (dd->ipath_flags & IPATH_4BYTE_TID) {
1094 /* We need a 2KB multiple alignment, and there is no way
1095 * to do it except to allocate extra and then skb_reserve
1096 * enough to bring it up to the right alignment.
1101 skb = __dev_alloc_skb(len, gfp_mask);
1103 ipath_dev_err(dd, "Failed to allocate skbuff, length %u\n",
1108 skb_reserve(skb, 4);
1110 if (dd->ipath_flags & IPATH_4BYTE_TID) {
1111 u32 una = (unsigned long)skb->data & 2047;
1113 skb_reserve(skb, 2048 - una);
1120 static void ipath_rcv_hdrerr(struct ipath_devdata *dd,
1125 struct ipath_message_header *hdr)
1129 get_rhf_errstring(eflags, emsg, sizeof emsg);
1130 ipath_cdbg(PKT, "RHFerrs %x hdrqtail=%x typ=%u "
1131 "tlen=%x opcode=%x egridx=%x: %s\n",
1133 ipath_hdrget_rcv_type(rhf_addr),
1134 ipath_hdrget_length_in_bytes(rhf_addr),
1135 be32_to_cpu(hdr->bth[0]) >> 24,
1138 /* Count local link integrity errors. */
1139 if (eflags & (INFINIPATH_RHF_H_ICRCERR | INFINIPATH_RHF_H_VCRCERR)) {
1140 u8 n = (dd->ipath_ibcctrl >>
1141 INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT) &
1142 INFINIPATH_IBCC_PHYERRTHRESHOLD_MASK;
1144 if (++dd->ipath_lli_counter > n) {
1145 dd->ipath_lli_counter = 0;
1146 dd->ipath_lli_errors++;
1152 * ipath_kreceive - receive a packet
1153 * @pd: the infinipath port
1155 * called from interrupt handler for errors or receive interrupt
1157 void ipath_kreceive(struct ipath_portdata *pd)
1159 struct ipath_devdata *dd = pd->port_dd;
1162 const u32 rsize = dd->ipath_rcvhdrentsize; /* words */
1163 const u32 maxcnt = dd->ipath_rcvhdrcnt * rsize; /* words */
1164 u32 etail = -1, l, hdrqtail;
1165 struct ipath_message_header *hdr;
1166 u32 eflags, i, etype, tlen, pkttot = 0, updegr = 0, reloop = 0;
1167 static u64 totcalls; /* stats, may eventually remove */
1171 rhf_addr = (__le32 *) pd->port_rcvhdrq + l + dd->ipath_rhf_offset;
1172 if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
1173 u32 seq = ipath_hdrget_seq(rhf_addr);
1175 if (seq != pd->port_seq_cnt)
1179 hdrqtail = ipath_get_rcvhdrtail(pd);
1186 for (last = 0, i = 1; !last; i += !last) {
1187 hdr = dd->ipath_f_get_msgheader(dd, rhf_addr);
1188 eflags = ipath_hdrget_err_flags(rhf_addr);
1189 etype = ipath_hdrget_rcv_type(rhf_addr);
1191 tlen = ipath_hdrget_length_in_bytes(rhf_addr);
1193 if ((dd->ipath_flags & IPATH_NODMA_RTAIL) ?
1194 ipath_hdrget_use_egr_buf(rhf_addr) :
1195 (etype != RCVHQ_RCV_TYPE_EXPECTED)) {
1197 * It turns out that the chip uses an eager buffer
1198 * for all non-expected packets, whether it "needs"
1199 * one or not. So always get the index, but don't
1200 * set ebuf (so we try to copy data) unless the
1201 * length requires it.
1203 etail = ipath_hdrget_index(rhf_addr);
1205 if (tlen > sizeof(*hdr) ||
1206 etype == RCVHQ_RCV_TYPE_NON_KD)
1207 ebuf = ipath_get_egrbuf(dd, etail);
1211 * both tiderr and ipathhdrerr are set for all plain IB
1212 * packets; only ipathhdrerr should be set.
1215 if (etype != RCVHQ_RCV_TYPE_NON_KD &&
1216 etype != RCVHQ_RCV_TYPE_ERROR &&
1217 ipath_hdrget_ipath_ver(hdr->iph.ver_port_tid_offset) !=
1219 ipath_cdbg(PKT, "Bad InfiniPath protocol version "
1222 if (unlikely(eflags))
1223 ipath_rcv_hdrerr(dd, eflags, l, etail, rhf_addr, hdr);
1224 else if (etype == RCVHQ_RCV_TYPE_NON_KD) {
1225 ipath_ib_rcv(dd->verbs_dev, (u32 *)hdr, ebuf, tlen);
1226 if (dd->ipath_lli_counter)
1227 dd->ipath_lli_counter--;
1228 } else if (etype == RCVHQ_RCV_TYPE_EAGER) {
1229 u8 opcode = be32_to_cpu(hdr->bth[0]) >> 24;
1230 u32 qp = be32_to_cpu(hdr->bth[1]) & 0xffffff;
1231 ipath_cdbg(PKT, "typ %x, opcode %x (eager, "
1232 "qp=%x), len %x; ignored\n",
1233 etype, opcode, qp, tlen);
1235 else if (etype == RCVHQ_RCV_TYPE_EXPECTED)
1236 ipath_dbg("Bug: Expected TID, opcode %x; ignored\n",
1237 be32_to_cpu(hdr->bth[0]) >> 24);
1240 * error packet, type of error unknown.
1241 * Probably type 3, but we don't know, so don't
1242 * even try to print the opcode, etc.
1243 * Usually caused by a "bad packet", that has no
1244 * BTH, when the LRH says it should.
1246 ipath_cdbg(ERRPKT, "Error Pkt, but no eflags! egrbuf"
1247 " %x, len %x hdrq+%x rhf: %Lx\n",
1248 etail, tlen, l, (unsigned long long)
1249 le64_to_cpu(*(__le64 *) rhf_addr));
1250 if (ipath_debug & __IPATH_ERRPKTDBG) {
1251 u32 j, *d, dw = rsize-2;
1252 if (rsize > (tlen>>2))
1255 printk(KERN_DEBUG "EPkt rcvhdr(%x dw):\n",
1257 for (j = 0; j < dw; j++)
1258 printk(KERN_DEBUG "%8x%s", d[j],
1259 (j%8) == 7 ? "\n" : " ");
1260 printk(KERN_DEBUG ".\n");
1266 rhf_addr = (__le32 *) pd->port_rcvhdrq +
1267 l + dd->ipath_rhf_offset;
1268 if (dd->ipath_flags & IPATH_NODMA_RTAIL) {
1269 u32 seq = ipath_hdrget_seq(rhf_addr);
1271 if (++pd->port_seq_cnt > 13)
1272 pd->port_seq_cnt = 1;
1273 if (seq != pd->port_seq_cnt)
1275 } else if (l == hdrqtail)
1278 * update head regs on last packet, and every 16 packets.
1279 * Reduce bus traffic, while still trying to prevent
1280 * rcvhdrq overflows, for when the queue is nearly full
1282 if (last || !(i & 0xf)) {
1285 /* request IBA6120 and 7220 interrupt only on last */
1287 lval |= dd->ipath_rhdrhead_intr_off;
1288 ipath_write_ureg(dd, ur_rcvhdrhead, lval,
1291 ipath_write_ureg(dd, ur_rcvegrindexhead,
1292 etail, pd->port_port);
1298 if (!dd->ipath_rhdrhead_intr_off && !reloop &&
1299 !(dd->ipath_flags & IPATH_NODMA_RTAIL)) {
1300 /* IBA6110 workaround; we can have a race clearing chip
1301 * interrupt with another interrupt about to be delivered,
1302 * and can clear it before it is delivered on the GPIO
1303 * workaround. By doing the extra check here for the
1304 * in-memory tail register updating while we were doing
1305 * earlier packets, we "almost" guarantee we have covered
1308 u32 hqtail = ipath_get_rcvhdrtail(pd);
1309 if (hqtail != hdrqtail) {
1311 reloop = 1; /* loop 1 extra time at most */
1320 if (pkttot > ipath_stats.sps_maxpkts_call)
1321 ipath_stats.sps_maxpkts_call = pkttot;
1322 ipath_stats.sps_port0pkts += pkttot;
1323 ipath_stats.sps_avgpkts_call =
1324 ipath_stats.sps_port0pkts / ++totcalls;
1330 * ipath_update_pio_bufs - update shadow copy of the PIO availability map
1331 * @dd: the infinipath device
1333 * called whenever our local copy indicates we have run out of send buffers
1334 * NOTE: This can be called from interrupt context by some code
1335 * and from non-interrupt context by ipath_getpiobuf().
1338 static void ipath_update_pio_bufs(struct ipath_devdata *dd)
1340 unsigned long flags;
1342 const unsigned piobregs = (unsigned)dd->ipath_pioavregs;
1344 /* If the generation (check) bits have changed, then we update the
1345 * busy bit for the corresponding PIO buffer. This algorithm will
1346 * modify positions to the value they already have in some cases
1347 * (i.e., no change), but it's faster than changing only the bits
1348 * that have changed.
1350 * We would like to do this atomicly, to avoid spinlocks in the
1351 * critical send path, but that's not really possible, given the
1352 * type of changes, and that this routine could be called on
1353 * multiple cpu's simultaneously, so we lock in this routine only,
1354 * to avoid conflicting updates; all we change is the shadow, and
1355 * it's a single 64 bit memory location, so by definition the update
1356 * is atomic in terms of what other cpu's can see in testing the
1357 * bits. The spin_lock overhead isn't too bad, since it only
1358 * happens when all buffers are in use, so only cpu overhead, not
1359 * latency or bandwidth is affected.
1361 if (!dd->ipath_pioavailregs_dma) {
1362 ipath_dbg("Update shadow pioavail, but regs_dma NULL!\n");
1365 if (ipath_debug & __IPATH_VERBDBG) {
1366 /* only if packet debug and verbose */
1367 volatile __le64 *dma = dd->ipath_pioavailregs_dma;
1368 unsigned long *shadow = dd->ipath_pioavailshadow;
1370 ipath_cdbg(PKT, "Refill avail, dma0=%llx shad0=%lx, "
1371 "d1=%llx s1=%lx, d2=%llx s2=%lx, d3=%llx "
1373 (unsigned long long) le64_to_cpu(dma[0]),
1375 (unsigned long long) le64_to_cpu(dma[1]),
1377 (unsigned long long) le64_to_cpu(dma[2]),
1379 (unsigned long long) le64_to_cpu(dma[3]),
1383 PKT, "2nd group, dma4=%llx shad4=%lx, "
1384 "d5=%llx s5=%lx, d6=%llx s6=%lx, "
1386 (unsigned long long) le64_to_cpu(dma[4]),
1388 (unsigned long long) le64_to_cpu(dma[5]),
1390 (unsigned long long) le64_to_cpu(dma[6]),
1392 (unsigned long long) le64_to_cpu(dma[7]),
1395 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1396 for (i = 0; i < piobregs; i++) {
1397 u64 pchbusy, pchg, piov, pnew;
1399 * Chip Errata: bug 6641; even and odd qwords>3 are swapped
1401 if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS))
1402 piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i ^ 1]);
1404 piov = le64_to_cpu(dd->ipath_pioavailregs_dma[i]);
1405 pchg = dd->ipath_pioavailkernel[i] &
1406 ~(dd->ipath_pioavailshadow[i] ^ piov);
1407 pchbusy = pchg << INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT;
1408 if (pchg && (pchbusy & dd->ipath_pioavailshadow[i])) {
1409 pnew = dd->ipath_pioavailshadow[i] & ~pchbusy;
1410 pnew |= piov & pchbusy;
1411 dd->ipath_pioavailshadow[i] = pnew;
1414 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1418 * used to force update of pioavailshadow if we can't get a pio buffer.
1419 * Needed primarily due to exitting freeze mode after recovering
1420 * from errors. Done lazily, because it's safer (known to not
1421 * be writing pio buffers).
1423 static void ipath_reset_availshadow(struct ipath_devdata *dd)
1426 unsigned long flags;
1428 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1429 for (i = 0; i < dd->ipath_pioavregs; i++) {
1431 /* deal with 6110 chip bug on high register #s */
1432 im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ?
1434 val = le64_to_cpu(dd->ipath_pioavailregs_dma[im]);
1436 * busy out the buffers not in the kernel avail list,
1437 * without changing the generation bits.
1439 oldval = dd->ipath_pioavailshadow[i];
1440 dd->ipath_pioavailshadow[i] = val |
1441 ((~dd->ipath_pioavailkernel[i] <<
1442 INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT) &
1443 0xaaaaaaaaaaaaaaaaULL); /* All BUSY bits in qword */
1444 if (oldval != dd->ipath_pioavailshadow[i])
1445 ipath_dbg("shadow[%d] was %Lx, now %lx\n",
1446 i, (unsigned long long) oldval,
1447 dd->ipath_pioavailshadow[i]);
1449 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1453 * ipath_setrcvhdrsize - set the receive header size
1454 * @dd: the infinipath device
1455 * @rhdrsize: the receive header size
1457 * called from user init code, and also layered driver init
1459 int ipath_setrcvhdrsize(struct ipath_devdata *dd, unsigned rhdrsize)
1463 if (dd->ipath_flags & IPATH_RCVHDRSZ_SET) {
1464 if (dd->ipath_rcvhdrsize != rhdrsize) {
1465 dev_info(&dd->pcidev->dev,
1466 "Error: can't set protocol header "
1467 "size %u, already %u\n",
1468 rhdrsize, dd->ipath_rcvhdrsize);
1471 ipath_cdbg(VERBOSE, "Reuse same protocol header "
1472 "size %u\n", dd->ipath_rcvhdrsize);
1473 } else if (rhdrsize > (dd->ipath_rcvhdrentsize -
1474 (sizeof(u64) / sizeof(u32)))) {
1475 ipath_dbg("Error: can't set protocol header size %u "
1476 "(> max %u)\n", rhdrsize,
1477 dd->ipath_rcvhdrentsize -
1478 (u32) (sizeof(u64) / sizeof(u32)));
1481 dd->ipath_flags |= IPATH_RCVHDRSZ_SET;
1482 dd->ipath_rcvhdrsize = rhdrsize;
1483 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
1484 dd->ipath_rcvhdrsize);
1485 ipath_cdbg(VERBOSE, "Set protocol header size to %u\n",
1486 dd->ipath_rcvhdrsize);
1492 * debugging code and stats updates if no pio buffers available.
1494 static noinline void no_pio_bufs(struct ipath_devdata *dd)
1496 unsigned long *shadow = dd->ipath_pioavailshadow;
1497 __le64 *dma = (__le64 *)dd->ipath_pioavailregs_dma;
1499 dd->ipath_upd_pio_shadow = 1;
1502 * not atomic, but if we lose a stat count in a while, that's OK
1504 ipath_stats.sps_nopiobufs++;
1505 if (!(++dd->ipath_consec_nopiobuf % 100000)) {
1506 ipath_force_pio_avail_update(dd); /* at start */
1507 ipath_dbg("%u tries no piobufavail ts%lx; dmacopy: "
1508 "%llx %llx %llx %llx\n"
1509 "ipath shadow: %lx %lx %lx %lx\n",
1510 dd->ipath_consec_nopiobuf,
1511 (unsigned long)get_cycles(),
1512 (unsigned long long) le64_to_cpu(dma[0]),
1513 (unsigned long long) le64_to_cpu(dma[1]),
1514 (unsigned long long) le64_to_cpu(dma[2]),
1515 (unsigned long long) le64_to_cpu(dma[3]),
1516 shadow[0], shadow[1], shadow[2], shadow[3]);
1518 * 4 buffers per byte, 4 registers above, cover rest
1521 if ((dd->ipath_piobcnt2k + dd->ipath_piobcnt4k) >
1522 (sizeof(shadow[0]) * 4 * 4))
1523 ipath_dbg("2nd group: dmacopy: "
1524 "%llx %llx %llx %llx\n"
1525 "ipath shadow: %lx %lx %lx %lx\n",
1526 (unsigned long long)le64_to_cpu(dma[4]),
1527 (unsigned long long)le64_to_cpu(dma[5]),
1528 (unsigned long long)le64_to_cpu(dma[6]),
1529 (unsigned long long)le64_to_cpu(dma[7]),
1530 shadow[4], shadow[5], shadow[6], shadow[7]);
1532 /* at end, so update likely happened */
1533 ipath_reset_availshadow(dd);
1538 * common code for normal driver pio buffer allocation, and reserved
1541 * do appropriate marking as busy, etc.
1542 * returns buffer number if one found (>=0), negative number is error.
1544 static u32 __iomem *ipath_getpiobuf_range(struct ipath_devdata *dd,
1545 u32 *pbufnum, u32 first, u32 last, u32 firsti)
1547 int i, j, updated = 0;
1549 unsigned long flags;
1550 unsigned long *shadow = dd->ipath_pioavailshadow;
1553 piobcnt = last - first;
1554 if (dd->ipath_upd_pio_shadow) {
1556 * Minor optimization. If we had no buffers on last call,
1557 * start out by doing the update; continue and do scan even
1558 * if no buffers were updated, to be paranoid
1560 ipath_update_pio_bufs(dd);
1567 * while test_and_set_bit() is atomic, we do that and then the
1568 * change_bit(), and the pair is not. See if this is the cause
1569 * of the remaining armlaunch errors.
1571 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1572 for (j = 0; j < piobcnt; j++, i++) {
1575 if (__test_and_set_bit((2 * i) + 1, shadow))
1577 /* flip generation bit */
1578 __change_bit(2 * i, shadow);
1581 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1586 * first time through; shadow exhausted, but may be
1587 * buffers available, try an update and then rescan.
1589 ipath_update_pio_bufs(dd);
1593 } else if (updated == 1 && piobcnt <=
1594 ((dd->ipath_sendctrl
1595 >> INFINIPATH_S_UPDTHRESH_SHIFT) &
1596 INFINIPATH_S_UPDTHRESH_MASK)) {
1598 * for chips supporting and using the update
1599 * threshold we need to force an update of the
1600 * in-memory copy if the count is less than the
1601 * thershold, then check one more time.
1603 ipath_force_pio_avail_update(dd);
1604 ipath_update_pio_bufs(dd);
1613 if (i < dd->ipath_piobcnt2k)
1614 buf = (u32 __iomem *) (dd->ipath_pio2kbase +
1615 i * dd->ipath_palign);
1617 buf = (u32 __iomem *)
1618 (dd->ipath_pio4kbase +
1619 (i - dd->ipath_piobcnt2k) * dd->ipath_4kalign);
1628 * ipath_getpiobuf - find an available pio buffer
1629 * @dd: the infinipath device
1630 * @plen: the size of the PIO buffer needed in 32-bit words
1631 * @pbufnum: the buffer number is placed here
1633 u32 __iomem *ipath_getpiobuf(struct ipath_devdata *dd, u32 plen, u32 *pbufnum)
1639 if (plen + 1 >= IPATH_SMALLBUF_DWORDS) {
1640 first = dd->ipath_piobcnt2k;
1641 lasti = dd->ipath_lastpioindexl;
1644 lasti = dd->ipath_lastpioindex;
1646 nbufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
1647 buf = ipath_getpiobuf_range(dd, &pnum, first, nbufs, lasti);
1651 * Set next starting place. It's just an optimization,
1652 * it doesn't matter who wins on this, so no locking
1654 if (plen + 1 >= IPATH_SMALLBUF_DWORDS)
1655 dd->ipath_lastpioindexl = pnum + 1;
1657 dd->ipath_lastpioindex = pnum + 1;
1658 if (dd->ipath_upd_pio_shadow)
1659 dd->ipath_upd_pio_shadow = 0;
1660 if (dd->ipath_consec_nopiobuf)
1661 dd->ipath_consec_nopiobuf = 0;
1662 ipath_cdbg(VERBOSE, "Return piobuf%u %uk @ %p\n",
1663 pnum, (pnum < dd->ipath_piobcnt2k) ? 2 : 4, buf);
1672 * ipath_chg_pioavailkernel - change which send buffers are available for kernel
1673 * @dd: the infinipath device
1674 * @start: the starting send buffer number
1675 * @len: the number of send buffers
1676 * @avail: true if the buffers are available for kernel use, false otherwise
1678 void ipath_chg_pioavailkernel(struct ipath_devdata *dd, unsigned start,
1679 unsigned len, int avail)
1681 unsigned long flags;
1682 unsigned end, cnt = 0;
1684 /* There are two bits per send buffer (busy and generation) */
1686 end = start + len * 2;
1688 spin_lock_irqsave(&ipath_pioavail_lock, flags);
1689 /* Set or clear the busy bit in the shadow. */
1690 while (start < end) {
1695 * the BUSY bit will never be set, because we disarm
1696 * the user buffers before we hand them back to the
1697 * kernel. We do have to make sure the generation
1698 * bit is set correctly in shadow, since it could
1699 * have changed many times while allocated to user.
1700 * We can't use the bitmap functions on the full
1701 * dma array because it is always little-endian, so
1702 * we have to flip to host-order first.
1703 * BITS_PER_LONG is slightly wrong, since it's
1704 * always 64 bits per register in chip...
1705 * We only work on 64 bit kernels, so that's OK.
1707 /* deal with 6110 chip bug on high register #s */
1708 i = start / BITS_PER_LONG;
1709 im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ?
1711 __clear_bit(INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT
1712 + start, dd->ipath_pioavailshadow);
1713 dma = (unsigned long) le64_to_cpu(
1714 dd->ipath_pioavailregs_dma[im]);
1715 if (test_bit((INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT
1716 + start) % BITS_PER_LONG, &dma))
1717 __set_bit(INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT
1718 + start, dd->ipath_pioavailshadow);
1720 __clear_bit(INFINIPATH_SENDPIOAVAIL_CHECK_SHIFT
1721 + start, dd->ipath_pioavailshadow);
1722 __set_bit(start, dd->ipath_pioavailkernel);
1724 __set_bit(start + INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT,
1725 dd->ipath_pioavailshadow);
1726 __clear_bit(start, dd->ipath_pioavailkernel);
1731 if (dd->ipath_pioupd_thresh) {
1732 end = 2 * (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k);
1733 cnt = bitmap_weight(dd->ipath_pioavailkernel, end);
1735 spin_unlock_irqrestore(&ipath_pioavail_lock, flags);
1738 * When moving buffers from kernel to user, if number assigned to
1739 * the user is less than the pio update threshold, and threshold
1740 * is supported (cnt was computed > 0), drop the update threshold
1741 * so we update at least once per allocated number of buffers.
1742 * In any case, if the kernel buffers are less than the threshold,
1743 * drop the threshold. We don't bother increasing it, having once
1744 * decreased it, since it would typically just cycle back and forth.
1745 * If we don't decrease below buffers in use, we can wait a long
1746 * time for an update, until some other context uses PIO buffers.
1748 if (!avail && len < cnt)
1750 if (cnt < dd->ipath_pioupd_thresh) {
1751 dd->ipath_pioupd_thresh = cnt;
1752 ipath_dbg("Decreased pio update threshold to %u\n",
1753 dd->ipath_pioupd_thresh);
1754 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1755 dd->ipath_sendctrl &= ~(INFINIPATH_S_UPDTHRESH_MASK
1756 << INFINIPATH_S_UPDTHRESH_SHIFT);
1757 dd->ipath_sendctrl |= dd->ipath_pioupd_thresh
1758 << INFINIPATH_S_UPDTHRESH_SHIFT;
1759 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1760 dd->ipath_sendctrl);
1761 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1766 * ipath_create_rcvhdrq - create a receive header queue
1767 * @dd: the infinipath device
1768 * @pd: the port data
1770 * this must be contiguous memory (from an i/o perspective), and must be
1771 * DMA'able (which means for some systems, it will go through an IOMMU,
1772 * or be forced into a low address range).
1774 int ipath_create_rcvhdrq(struct ipath_devdata *dd,
1775 struct ipath_portdata *pd)
1779 if (!pd->port_rcvhdrq) {
1780 dma_addr_t phys_hdrqtail;
1781 gfp_t gfp_flags = GFP_USER | __GFP_COMP;
1782 int amt = ALIGN(dd->ipath_rcvhdrcnt * dd->ipath_rcvhdrentsize *
1783 sizeof(u32), PAGE_SIZE);
1785 pd->port_rcvhdrq = dma_alloc_coherent(
1786 &dd->pcidev->dev, amt, &pd->port_rcvhdrq_phys,
1789 if (!pd->port_rcvhdrq) {
1790 ipath_dev_err(dd, "attempt to allocate %d bytes "
1791 "for port %u rcvhdrq failed\n",
1792 amt, pd->port_port);
1797 if (!(dd->ipath_flags & IPATH_NODMA_RTAIL)) {
1798 pd->port_rcvhdrtail_kvaddr = dma_alloc_coherent(
1799 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail,
1801 if (!pd->port_rcvhdrtail_kvaddr) {
1802 ipath_dev_err(dd, "attempt to allocate 1 page "
1803 "for port %u rcvhdrqtailaddr "
1804 "failed\n", pd->port_port);
1806 dma_free_coherent(&dd->pcidev->dev, amt,
1808 pd->port_rcvhdrq_phys);
1809 pd->port_rcvhdrq = NULL;
1812 pd->port_rcvhdrqtailaddr_phys = phys_hdrqtail;
1813 ipath_cdbg(VERBOSE, "port %d hdrtailaddr, %llx "
1814 "physical\n", pd->port_port,
1815 (unsigned long long) phys_hdrqtail);
1818 pd->port_rcvhdrq_size = amt;
1820 ipath_cdbg(VERBOSE, "%d pages at %p (phys %lx) size=%lu "
1821 "for port %u rcvhdr Q\n",
1822 amt >> PAGE_SHIFT, pd->port_rcvhdrq,
1823 (unsigned long) pd->port_rcvhdrq_phys,
1824 (unsigned long) pd->port_rcvhdrq_size,
1828 ipath_cdbg(VERBOSE, "reuse port %d rcvhdrq @%p %llx phys; "
1829 "hdrtailaddr@%p %llx physical\n",
1830 pd->port_port, pd->port_rcvhdrq,
1831 (unsigned long long) pd->port_rcvhdrq_phys,
1832 pd->port_rcvhdrtail_kvaddr, (unsigned long long)
1833 pd->port_rcvhdrqtailaddr_phys);
1835 /* clear for security and sanity on each use */
1836 memset(pd->port_rcvhdrq, 0, pd->port_rcvhdrq_size);
1837 if (pd->port_rcvhdrtail_kvaddr)
1838 memset(pd->port_rcvhdrtail_kvaddr, 0, PAGE_SIZE);
1841 * tell chip each time we init it, even if we are re-using previous
1842 * memory (we zero the register at process close)
1844 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdrtailaddr,
1845 pd->port_port, pd->port_rcvhdrqtailaddr_phys);
1846 ipath_write_kreg_port(dd, dd->ipath_kregs->kr_rcvhdraddr,
1847 pd->port_port, pd->port_rcvhdrq_phys);
1855 * Flush all sends that might be in the ready to send state, as well as any
1856 * that are in the process of being sent. Used whenever we need to be
1857 * sure the send side is idle. Cleans up all buffer state by canceling
1858 * all pio buffers, and issuing an abort, which cleans up anything in the
1859 * launch fifo. The cancel is superfluous on some chip versions, but
1860 * it's safer to always do it.
1861 * PIOAvail bits are updated by the chip as if normal send had happened.
1863 void ipath_cancel_sends(struct ipath_devdata *dd, int restore_sendctrl)
1865 unsigned long flags;
1867 if (dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) {
1868 ipath_cdbg(VERBOSE, "Ignore while in autonegotiation\n");
1872 * If we have SDMA, and it's not disabled, we have to kick off the
1873 * abort state machine, provided we aren't already aborting.
1874 * If we are in the process of aborting SDMA (!DISABLED, but ABORTING),
1875 * we skip the rest of this routine. It is already "in progress"
1877 if (dd->ipath_flags & IPATH_HAS_SEND_DMA) {
1879 unsigned long *statp = &dd->ipath_sdma_status;
1881 spin_lock_irqsave(&dd->ipath_sdma_lock, flags);
1883 test_and_set_bit(IPATH_SDMA_ABORTING, statp)
1884 && !test_bit(IPATH_SDMA_DISABLED, statp);
1885 spin_unlock_irqrestore(&dd->ipath_sdma_lock, flags);
1890 ipath_dbg("Cancelling all in-progress send buffers\n");
1892 /* skip armlaunch errs for a while */
1893 dd->ipath_lastcancel = jiffies + HZ / 2;
1896 * The abort bit is auto-clearing. We also don't want pioavail
1897 * update happening during this, and we don't want any other
1898 * sends going out, so turn those off for the duration. We read
1899 * the scratch register to be sure that cancels and the abort
1900 * have taken effect in the chip. Otherwise two parts are same
1901 * as ipath_force_pio_avail_update()
1903 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1904 dd->ipath_sendctrl &= ~(INFINIPATH_S_PIOBUFAVAILUPD
1905 | INFINIPATH_S_PIOENABLE);
1906 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1907 dd->ipath_sendctrl | INFINIPATH_S_ABORT);
1908 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1909 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1911 /* disarm all send buffers */
1912 ipath_disarm_piobufs(dd, 0,
1913 dd->ipath_piobcnt2k + dd->ipath_piobcnt4k);
1915 if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
1916 set_bit(IPATH_SDMA_DISARMED, &dd->ipath_sdma_status);
1918 if (restore_sendctrl) {
1919 /* else done by caller later if needed */
1920 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1921 dd->ipath_sendctrl |= INFINIPATH_S_PIOBUFAVAILUPD |
1922 INFINIPATH_S_PIOENABLE;
1923 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1924 dd->ipath_sendctrl);
1925 /* and again, be sure all have hit the chip */
1926 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1927 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1930 if ((dd->ipath_flags & IPATH_HAS_SEND_DMA) &&
1931 !test_bit(IPATH_SDMA_DISABLED, &dd->ipath_sdma_status) &&
1932 test_bit(IPATH_SDMA_RUNNING, &dd->ipath_sdma_status)) {
1933 spin_lock_irqsave(&dd->ipath_sdma_lock, flags);
1934 /* only wait so long for intr */
1935 dd->ipath_sdma_abort_intr_timeout = jiffies + HZ;
1936 dd->ipath_sdma_reset_wait = 200;
1937 if (!test_bit(IPATH_SDMA_SHUTDOWN, &dd->ipath_sdma_status))
1938 tasklet_hi_schedule(&dd->ipath_sdma_abort_task);
1939 spin_unlock_irqrestore(&dd->ipath_sdma_lock, flags);
1945 * Force an update of in-memory copy of the pioavail registers, when
1946 * needed for any of a variety of reasons. We read the scratch register
1947 * to make it highly likely that the update will have happened by the
1948 * time we return. If already off (as in cancel_sends above), this
1949 * routine is a nop, on the assumption that the caller will "do the
1952 void ipath_force_pio_avail_update(struct ipath_devdata *dd)
1954 unsigned long flags;
1956 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1957 if (dd->ipath_sendctrl & INFINIPATH_S_PIOBUFAVAILUPD) {
1958 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1959 dd->ipath_sendctrl & ~INFINIPATH_S_PIOBUFAVAILUPD);
1960 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1961 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1962 dd->ipath_sendctrl);
1963 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1965 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1968 static void ipath_set_ib_lstate(struct ipath_devdata *dd, int linkcmd,
1972 static const char *what[4] = {
1974 [INFINIPATH_IBCC_LINKCMD_DOWN] = "DOWN",
1975 [INFINIPATH_IBCC_LINKCMD_ARMED] = "ARMED",
1976 [INFINIPATH_IBCC_LINKCMD_ACTIVE] = "ACTIVE"
1979 if (linitcmd == INFINIPATH_IBCC_LINKINITCMD_DISABLE) {
1981 * If we are told to disable, note that so link-recovery
1982 * code does not attempt to bring us back up.
1985 dd->ipath_flags |= IPATH_IB_LINK_DISABLED;
1987 } else if (linitcmd) {
1989 * Any other linkinitcmd will lead to LINKDOWN and then
1990 * to INIT (if all is well), so clear flag to let
1991 * link-recovery code attempt to bring us back up.
1994 dd->ipath_flags &= ~IPATH_IB_LINK_DISABLED;
1998 mod_wd = (linkcmd << dd->ibcc_lc_shift) |
1999 (linitcmd << INFINIPATH_IBCC_LINKINITCMD_SHIFT);
2001 "Moving unit %u to %s (initcmd=0x%x), current ltstate is %s\n",
2002 dd->ipath_unit, what[linkcmd], linitcmd,
2003 ipath_ibcstatus_str[ipath_ib_linktrstate(dd,
2004 ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus))]);
2006 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2007 dd->ipath_ibcctrl | mod_wd);
2008 /* read from chip so write is flushed */
2009 (void) ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
2012 int ipath_set_linkstate(struct ipath_devdata *dd, u8 newstate)
2018 case IPATH_IB_LINKDOWN_ONLY:
2019 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN, 0);
2024 case IPATH_IB_LINKDOWN:
2025 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
2026 INFINIPATH_IBCC_LINKINITCMD_POLL);
2031 case IPATH_IB_LINKDOWN_SLEEP:
2032 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
2033 INFINIPATH_IBCC_LINKINITCMD_SLEEP);
2038 case IPATH_IB_LINKDOWN_DISABLE:
2039 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_DOWN,
2040 INFINIPATH_IBCC_LINKINITCMD_DISABLE);
2045 case IPATH_IB_LINKARM:
2046 if (dd->ipath_flags & IPATH_LINKARMED) {
2050 if (!(dd->ipath_flags &
2051 (IPATH_LINKINIT | IPATH_LINKACTIVE))) {
2055 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ARMED, 0);
2058 * Since the port can transition to ACTIVE by receiving
2059 * a non VL 15 packet, wait for either state.
2061 lstate = IPATH_LINKARMED | IPATH_LINKACTIVE;
2064 case IPATH_IB_LINKACTIVE:
2065 if (dd->ipath_flags & IPATH_LINKACTIVE) {
2069 if (!(dd->ipath_flags & IPATH_LINKARMED)) {
2073 ipath_set_ib_lstate(dd, INFINIPATH_IBCC_LINKCMD_ACTIVE, 0);
2074 lstate = IPATH_LINKACTIVE;
2077 case IPATH_IB_LINK_LOOPBACK:
2078 dev_info(&dd->pcidev->dev, "Enabling IB local loopback\n");
2079 dd->ipath_ibcctrl |= INFINIPATH_IBCC_LOOPBACK;
2080 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2083 /* turn heartbeat off, as it causes loopback to fail */
2084 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2085 IPATH_IB_HRTBT_OFF);
2090 case IPATH_IB_LINK_EXTERNAL:
2091 dev_info(&dd->pcidev->dev,
2092 "Disabling IB local loopback (normal)\n");
2093 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2095 dd->ipath_ibcctrl &= ~INFINIPATH_IBCC_LOOPBACK;
2096 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2103 * Heartbeat can be explicitly enabled by the user via
2104 * "hrtbt_enable" "file", and if disabled, trying to enable here
2105 * will have no effect. Implicit changes (heartbeat off when
2106 * loopback on, and vice versa) are included to ease testing.
2108 case IPATH_IB_LINK_HRTBT:
2109 ret = dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2113 case IPATH_IB_LINK_NO_HRTBT:
2114 ret = dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_HRTBT,
2115 IPATH_IB_HRTBT_OFF);
2119 ipath_dbg("Invalid linkstate 0x%x requested\n", newstate);
2123 ret = ipath_wait_linkstate(dd, lstate, 2000);
2130 * ipath_set_mtu - set the MTU
2131 * @dd: the infinipath device
2134 * we can handle "any" incoming size, the issue here is whether we
2135 * need to restrict our outgoing size. For now, we don't do any
2136 * sanity checking on this, and we don't deal with what happens to
2137 * programs that are already running when the size changes.
2138 * NOTE: changing the MTU will usually cause the IBC to go back to
2139 * link INIT state...
2141 int ipath_set_mtu(struct ipath_devdata *dd, u16 arg)
2148 * mtu is IB data payload max. It's the largest power of 2 less
2149 * than piosize (or even larger, since it only really controls the
2150 * largest we can receive; we can send the max of the mtu and
2151 * piosize). We check that it's one of the valid IB sizes.
2153 if (arg != 256 && arg != 512 && arg != 1024 && arg != 2048 &&
2154 (arg != 4096 || !ipath_mtu4096)) {
2155 ipath_dbg("Trying to set invalid mtu %u, failing\n", arg);
2159 if (dd->ipath_ibmtu == arg) {
2160 ret = 0; /* same as current */
2164 piosize = dd->ipath_ibmaxlen;
2165 dd->ipath_ibmtu = arg;
2167 if (arg >= (piosize - IPATH_PIO_MAXIBHDR)) {
2168 /* Only if it's not the initial value (or reset to it) */
2169 if (piosize != dd->ipath_init_ibmaxlen) {
2170 if (arg > piosize && arg <= dd->ipath_init_ibmaxlen)
2171 piosize = dd->ipath_init_ibmaxlen;
2172 dd->ipath_ibmaxlen = piosize;
2175 } else if ((arg + IPATH_PIO_MAXIBHDR) != dd->ipath_ibmaxlen) {
2176 piosize = arg + IPATH_PIO_MAXIBHDR;
2177 ipath_cdbg(VERBOSE, "ibmaxlen was 0x%x, setting to 0x%x "
2178 "(mtu 0x%x)\n", dd->ipath_ibmaxlen, piosize,
2180 dd->ipath_ibmaxlen = piosize;
2185 u64 ibc = dd->ipath_ibcctrl, ibdw;
2187 * update our housekeeping variables, and set IBC max
2188 * size, same as init code; max IBC is max we allow in
2189 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
2191 dd->ipath_ibmaxlen = piosize - 2 * sizeof(u32);
2192 ibdw = (dd->ipath_ibmaxlen >> 2) + 1;
2193 ibc &= ~(INFINIPATH_IBCC_MAXPKTLEN_MASK <<
2194 dd->ibcc_mpl_shift);
2195 ibc |= ibdw << dd->ibcc_mpl_shift;
2196 dd->ipath_ibcctrl = ibc;
2197 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl,
2199 dd->ipath_f_tidtemplate(dd);
2208 int ipath_set_lid(struct ipath_devdata *dd, u32 lid, u8 lmc)
2210 dd->ipath_lid = lid;
2211 dd->ipath_lmc = lmc;
2213 dd->ipath_f_set_ib_cfg(dd, IPATH_IB_CFG_LIDLMC, lid |
2214 (~((1U << lmc) - 1)) << 16);
2216 dev_info(&dd->pcidev->dev, "We got a lid: 0x%x\n", lid);
2223 * ipath_write_kreg_port - write a device's per-port 64-bit kernel register
2224 * @dd: the infinipath device
2225 * @regno: the register number to write
2226 * @port: the port containing the register
2227 * @value: the value to write
2229 * Registers that vary with the chip implementation constants (port)
2232 void ipath_write_kreg_port(const struct ipath_devdata *dd, ipath_kreg regno,
2233 unsigned port, u64 value)
2237 if (port < dd->ipath_portcnt &&
2238 (regno == dd->ipath_kregs->kr_rcvhdraddr ||
2239 regno == dd->ipath_kregs->kr_rcvhdrtailaddr))
2240 where = regno + port;
2244 ipath_write_kreg(dd, where, value);
2248 * Following deal with the "obviously simple" task of overriding the state
2249 * of the LEDS, which normally indicate link physical and logical status.
2250 * The complications arise in dealing with different hardware mappings
2251 * and the board-dependent routine being called from interrupts.
2252 * and then there's the requirement to _flash_ them.
2254 #define LED_OVER_FREQ_SHIFT 8
2255 #define LED_OVER_FREQ_MASK (0xFF<<LED_OVER_FREQ_SHIFT)
2256 /* Below is "non-zero" to force override, but both actual LEDs are off */
2257 #define LED_OVER_BOTH_OFF (8)
2259 static void ipath_run_led_override(unsigned long opaque)
2261 struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
2264 u64 lstate, ltstate, val;
2266 if (!(dd->ipath_flags & IPATH_INITTED))
2269 pidx = dd->ipath_led_override_phase++ & 1;
2270 dd->ipath_led_override = dd->ipath_led_override_vals[pidx];
2271 timeoff = dd->ipath_led_override_timeoff;
2274 * below potentially restores the LED values per current status,
2275 * should also possibly setup the traffic-blink register,
2276 * but leave that to per-chip functions.
2278 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
2279 ltstate = ipath_ib_linktrstate(dd, val);
2280 lstate = ipath_ib_linkstate(dd, val);
2282 dd->ipath_f_setextled(dd, lstate, ltstate);
2283 mod_timer(&dd->ipath_led_override_timer, jiffies + timeoff);
2286 void ipath_set_led_override(struct ipath_devdata *dd, unsigned int val)
2290 if (!(dd->ipath_flags & IPATH_INITTED))
2293 /* First check if we are blinking. If not, use 1HZ polling */
2295 freq = (val & LED_OVER_FREQ_MASK) >> LED_OVER_FREQ_SHIFT;
2298 /* For blink, set each phase from one nybble of val */
2299 dd->ipath_led_override_vals[0] = val & 0xF;
2300 dd->ipath_led_override_vals[1] = (val >> 4) & 0xF;
2301 timeoff = (HZ << 4)/freq;
2303 /* Non-blink set both phases the same. */
2304 dd->ipath_led_override_vals[0] = val & 0xF;
2305 dd->ipath_led_override_vals[1] = val & 0xF;
2307 dd->ipath_led_override_timeoff = timeoff;
2310 * If the timer has not already been started, do so. Use a "quick"
2311 * timeout so the function will be called soon, to look at our request.
2313 if (atomic_inc_return(&dd->ipath_led_override_timer_active) == 1) {
2314 /* Need to start timer */
2315 init_timer(&dd->ipath_led_override_timer);
2316 dd->ipath_led_override_timer.function =
2317 ipath_run_led_override;
2318 dd->ipath_led_override_timer.data = (unsigned long) dd;
2319 dd->ipath_led_override_timer.expires = jiffies + 1;
2320 add_timer(&dd->ipath_led_override_timer);
2322 atomic_dec(&dd->ipath_led_override_timer_active);
2326 * ipath_shutdown_device - shut down a device
2327 * @dd: the infinipath device
2329 * This is called to make the device quiet when we are about to
2330 * unload the driver, and also when the device is administratively
2331 * disabled. It does not free any data structures.
2332 * Everything it does has to be setup again by ipath_init_chip(dd,1)
2334 void ipath_shutdown_device(struct ipath_devdata *dd)
2336 unsigned long flags;
2338 ipath_dbg("Shutting down the device\n");
2340 ipath_hol_up(dd); /* make sure user processes aren't suspended */
2342 dd->ipath_flags |= IPATH_LINKUNK;
2343 dd->ipath_flags &= ~(IPATH_INITTED | IPATH_LINKDOWN |
2344 IPATH_LINKINIT | IPATH_LINKARMED |
2346 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_CONF |
2347 IPATH_STATUS_IB_READY);
2349 /* mask interrupts, but not errors */
2350 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
2352 dd->ipath_rcvctrl = 0;
2353 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
2356 if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
2360 * gracefully stop all sends allowing any in progress to trickle out
2363 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
2364 dd->ipath_sendctrl = 0;
2365 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
2367 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
2368 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
2371 * enough for anything that's going to trickle out to have actually
2376 dd->ipath_f_setextled(dd, 0, 0); /* make sure LEDs are off */
2378 ipath_set_ib_lstate(dd, 0, INFINIPATH_IBCC_LINKINITCMD_DISABLE);
2379 ipath_cancel_sends(dd, 0);
2382 * we are shutting down, so tell components that care. We don't do
2383 * this on just a link state change, much like ethernet, a cable
2384 * unplug, etc. doesn't change driver state
2386 signal_ib_event(dd, IB_EVENT_PORT_ERR);
2389 dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
2390 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
2391 dd->ipath_control | INFINIPATH_C_FREEZEMODE);
2394 * clear SerdesEnable and turn the leds off; do this here because
2395 * we are unloading, so don't count on interrupts to move along
2396 * Turn the LEDs off explictly for the same reason.
2398 dd->ipath_f_quiet_serdes(dd);
2400 /* stop all the timers that might still be running */
2401 del_timer_sync(&dd->ipath_hol_timer);
2402 if (dd->ipath_stats_timer_active) {
2403 del_timer_sync(&dd->ipath_stats_timer);
2404 dd->ipath_stats_timer_active = 0;
2406 if (dd->ipath_intrchk_timer.data) {
2407 del_timer_sync(&dd->ipath_intrchk_timer);
2408 dd->ipath_intrchk_timer.data = 0;
2410 if (atomic_read(&dd->ipath_led_override_timer_active)) {
2411 del_timer_sync(&dd->ipath_led_override_timer);
2412 atomic_set(&dd->ipath_led_override_timer_active, 0);
2416 * clear all interrupts and errors, so that the next time the driver
2417 * is loaded or device is enabled, we know that whatever is set
2418 * happened while we were unloaded
2420 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
2421 ~0ULL & ~INFINIPATH_HWE_MEMBISTFAILED);
2422 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
2423 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
2425 ipath_cdbg(VERBOSE, "Flush time and errors to EEPROM\n");
2426 ipath_update_eeprom_log(dd);
2430 * ipath_free_pddata - free a port's allocated data
2431 * @dd: the infinipath device
2432 * @pd: the portdata structure
2434 * free up any allocated data for a port
2435 * This should not touch anything that would affect a simultaneous
2436 * re-allocation of port data, because it is called after ipath_mutex
2437 * is released (and can be called from reinit as well).
2438 * It should never change any chip state, or global driver state.
2439 * (The only exception to global state is freeing the port0 port0_skbs.)
2441 void ipath_free_pddata(struct ipath_devdata *dd, struct ipath_portdata *pd)
2446 if (pd->port_rcvhdrq) {
2447 ipath_cdbg(VERBOSE, "free closed port %d rcvhdrq @ %p "
2448 "(size=%lu)\n", pd->port_port, pd->port_rcvhdrq,
2449 (unsigned long) pd->port_rcvhdrq_size);
2450 dma_free_coherent(&dd->pcidev->dev, pd->port_rcvhdrq_size,
2451 pd->port_rcvhdrq, pd->port_rcvhdrq_phys);
2452 pd->port_rcvhdrq = NULL;
2453 if (pd->port_rcvhdrtail_kvaddr) {
2454 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
2455 pd->port_rcvhdrtail_kvaddr,
2456 pd->port_rcvhdrqtailaddr_phys);
2457 pd->port_rcvhdrtail_kvaddr = NULL;
2460 if (pd->port_port && pd->port_rcvegrbuf) {
2463 for (e = 0; e < pd->port_rcvegrbuf_chunks; e++) {
2464 void *base = pd->port_rcvegrbuf[e];
2465 size_t size = pd->port_rcvegrbuf_size;
2467 ipath_cdbg(VERBOSE, "egrbuf free(%p, %lu), "
2468 "chunk %u/%u\n", base,
2469 (unsigned long) size,
2470 e, pd->port_rcvegrbuf_chunks);
2471 dma_free_coherent(&dd->pcidev->dev, size,
2472 base, pd->port_rcvegrbuf_phys[e]);
2474 kfree(pd->port_rcvegrbuf);
2475 pd->port_rcvegrbuf = NULL;
2476 kfree(pd->port_rcvegrbuf_phys);
2477 pd->port_rcvegrbuf_phys = NULL;
2478 pd->port_rcvegrbuf_chunks = 0;
2479 } else if (pd->port_port == 0 && dd->ipath_port0_skbinfo) {
2481 struct ipath_skbinfo *skbinfo = dd->ipath_port0_skbinfo;
2483 dd->ipath_port0_skbinfo = NULL;
2484 ipath_cdbg(VERBOSE, "free closed port %d "
2485 "ipath_port0_skbinfo @ %p\n", pd->port_port,
2487 for (e = 0; e < dd->ipath_p0_rcvegrcnt; e++)
2488 if (skbinfo[e].skb) {
2489 pci_unmap_single(dd->pcidev, skbinfo[e].phys,
2491 PCI_DMA_FROMDEVICE);
2492 dev_kfree_skb(skbinfo[e].skb);
2496 kfree(pd->port_tid_pg_list);
2497 vfree(pd->subport_uregbase);
2498 vfree(pd->subport_rcvegrbuf);
2499 vfree(pd->subport_rcvhdr_base);
2503 static int __init infinipath_init(void)
2507 if (ipath_debug & __IPATH_DBG)
2508 printk(KERN_INFO DRIVER_LOAD_MSG "%s", ib_ipath_version);
2511 * These must be called before the driver is registered with
2512 * the PCI subsystem.
2514 idr_init(&unit_table);
2515 if (!idr_pre_get(&unit_table, GFP_KERNEL)) {
2516 printk(KERN_ERR IPATH_DRV_NAME ": idr_pre_get() failed\n");
2521 ret = pci_register_driver(&ipath_driver);
2523 printk(KERN_ERR IPATH_DRV_NAME
2524 ": Unable to register driver: error %d\n", -ret);
2528 ret = ipath_init_ipathfs();
2530 printk(KERN_ERR IPATH_DRV_NAME ": Unable to create "
2531 "ipathfs: error %d\n", -ret);
2538 pci_unregister_driver(&ipath_driver);
2541 idr_destroy(&unit_table);
2547 static void __exit infinipath_cleanup(void)
2549 ipath_exit_ipathfs();
2551 ipath_cdbg(VERBOSE, "Unregistering pci driver\n");
2552 pci_unregister_driver(&ipath_driver);
2554 idr_destroy(&unit_table);
2558 * ipath_reset_device - reset the chip if possible
2559 * @unit: the device to reset
2561 * Whether or not reset is successful, we attempt to re-initialize the chip
2562 * (that is, much like a driver unload/reload). We clear the INITTED flag
2563 * so that the various entry points will fail until we reinitialize. For
2564 * now, we only allow this if no user ports are open that use chip resources
2566 int ipath_reset_device(int unit)
2569 struct ipath_devdata *dd = ipath_lookup(unit);
2570 unsigned long flags;
2577 if (atomic_read(&dd->ipath_led_override_timer_active)) {
2578 /* Need to stop LED timer, _then_ shut off LEDs */
2579 del_timer_sync(&dd->ipath_led_override_timer);
2580 atomic_set(&dd->ipath_led_override_timer_active, 0);
2583 /* Shut off LEDs after we are sure timer is not running */
2584 dd->ipath_led_override = LED_OVER_BOTH_OFF;
2585 dd->ipath_f_setextled(dd, 0, 0);
2587 dev_info(&dd->pcidev->dev, "Reset on unit %u requested\n", unit);
2589 if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT)) {
2590 dev_info(&dd->pcidev->dev, "Invalid unit number %u or "
2591 "not initialized or not present\n", unit);
2596 spin_lock_irqsave(&dd->ipath_uctxt_lock, flags);
2598 for (i = 1; i < dd->ipath_cfgports; i++) {
2599 if (!dd->ipath_pd[i] || !dd->ipath_pd[i]->port_cnt)
2601 spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags);
2602 ipath_dbg("unit %u port %d is in use "
2603 "(PID %u cmd %s), can't reset\n",
2605 pid_nr(dd->ipath_pd[i]->port_pid),
2606 dd->ipath_pd[i]->port_comm);
2610 spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags);
2612 if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
2615 dd->ipath_flags &= ~IPATH_INITTED;
2616 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
2617 ret = dd->ipath_f_reset(dd);
2619 ipath_dbg("Reinitializing unit %u after reset attempt\n",
2621 ret = ipath_init_chip(dd, 1);
2625 ipath_dev_err(dd, "Reinitialize unit %u after "
2626 "reset failed with %d\n", unit, ret);
2628 dev_info(&dd->pcidev->dev, "Reinitialized unit %u after "
2629 "resetting\n", unit);
2636 * send a signal to all the processes that have the driver open
2637 * through the normal interfaces (i.e., everything other than diags
2638 * interface). Returns number of signalled processes.
2640 static int ipath_signal_procs(struct ipath_devdata *dd, int sig)
2642 int i, sub, any = 0;
2644 unsigned long flags;
2649 spin_lock_irqsave(&dd->ipath_uctxt_lock, flags);
2650 for (i = 1; i < dd->ipath_cfgports; i++) {
2651 if (!dd->ipath_pd[i] || !dd->ipath_pd[i]->port_cnt)
2653 pid = dd->ipath_pd[i]->port_pid;
2657 dev_info(&dd->pcidev->dev, "context %d in use "
2658 "(PID %u), sending signal %d\n",
2659 i, pid_nr(pid), sig);
2660 kill_pid(pid, sig, 1);
2662 for (sub = 0; sub < INFINIPATH_MAX_SUBPORT; sub++) {
2663 pid = dd->ipath_pd[i]->port_subpid[sub];
2666 dev_info(&dd->pcidev->dev, "sub-context "
2667 "%d:%d in use (PID %u), sending "
2668 "signal %d\n", i, sub, pid_nr(pid), sig);
2669 kill_pid(pid, sig, 1);
2673 spin_unlock_irqrestore(&dd->ipath_uctxt_lock, flags);
2677 static void ipath_hol_signal_down(struct ipath_devdata *dd)
2679 if (ipath_signal_procs(dd, SIGSTOP))
2680 ipath_dbg("Stopped some processes\n");
2681 ipath_cancel_sends(dd, 1);
2685 static void ipath_hol_signal_up(struct ipath_devdata *dd)
2687 if (ipath_signal_procs(dd, SIGCONT))
2688 ipath_dbg("Continued some processes\n");
2692 * link is down, stop any users processes, and flush pending sends
2693 * to prevent HoL blocking, then start the HoL timer that
2694 * periodically continues, then stop procs, so they can detect
2695 * link down if they want, and do something about it.
2696 * Timer may already be running, so use mod_timer, not add_timer.
2698 void ipath_hol_down(struct ipath_devdata *dd)
2700 dd->ipath_hol_state = IPATH_HOL_DOWN;
2701 ipath_hol_signal_down(dd);
2702 dd->ipath_hol_next = IPATH_HOL_DOWNCONT;
2703 dd->ipath_hol_timer.expires = jiffies +
2704 msecs_to_jiffies(ipath_hol_timeout_ms);
2705 mod_timer(&dd->ipath_hol_timer, dd->ipath_hol_timer.expires);
2709 * link is up, continue any user processes, and ensure timer
2710 * is a nop, if running. Let timer keep running, if set; it
2711 * will nop when it sees the link is up
2713 void ipath_hol_up(struct ipath_devdata *dd)
2715 ipath_hol_signal_up(dd);
2716 dd->ipath_hol_state = IPATH_HOL_UP;
2720 * toggle the running/not running state of user proceses
2721 * to prevent HoL blocking on chip resources, but still allow
2722 * user processes to do link down special case handling.
2723 * Should only be called via the timer
2725 void ipath_hol_event(unsigned long opaque)
2727 struct ipath_devdata *dd = (struct ipath_devdata *)opaque;
2729 if (dd->ipath_hol_next == IPATH_HOL_DOWNSTOP
2730 && dd->ipath_hol_state != IPATH_HOL_UP) {
2731 dd->ipath_hol_next = IPATH_HOL_DOWNCONT;
2732 ipath_dbg("Stopping processes\n");
2733 ipath_hol_signal_down(dd);
2734 } else { /* may do "extra" if also in ipath_hol_up() */
2735 dd->ipath_hol_next = IPATH_HOL_DOWNSTOP;
2736 ipath_dbg("Continuing processes\n");
2737 ipath_hol_signal_up(dd);
2739 if (dd->ipath_hol_state == IPATH_HOL_UP)
2740 ipath_dbg("link's up, don't resched timer\n");
2742 dd->ipath_hol_timer.expires = jiffies +
2743 msecs_to_jiffies(ipath_hol_timeout_ms);
2744 mod_timer(&dd->ipath_hol_timer,
2745 dd->ipath_hol_timer.expires);
2749 int ipath_set_rx_pol_inv(struct ipath_devdata *dd, u8 new_pol_inv)
2753 if (new_pol_inv > INFINIPATH_XGXS_RX_POL_MASK)
2755 if (dd->ipath_rx_pol_inv != new_pol_inv) {
2756 dd->ipath_rx_pol_inv = new_pol_inv;
2757 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
2758 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
2759 INFINIPATH_XGXS_RX_POL_SHIFT);
2760 val |= ((u64)dd->ipath_rx_pol_inv) <<
2761 INFINIPATH_XGXS_RX_POL_SHIFT;
2762 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
2768 * Disable and enable the armlaunch error. Used for PIO bandwidth testing on
2769 * the 7220, which is count-based, rather than trigger-based. Safe for the
2770 * driver check, since it's at init. Not completely safe when used for
2771 * user-mode checking, since some error checking can be lost, but not
2772 * particularly risky, and only has problematic side-effects in the face of
2773 * very buggy user code. There is no reference counting, but that's also
2774 * fine, given the intended use.
2776 void ipath_enable_armlaunch(struct ipath_devdata *dd)
2778 dd->ipath_lasterror &= ~INFINIPATH_E_SPIOARMLAUNCH;
2779 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
2780 INFINIPATH_E_SPIOARMLAUNCH);
2781 dd->ipath_errormask |= INFINIPATH_E_SPIOARMLAUNCH;
2782 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
2783 dd->ipath_errormask);
2786 void ipath_disable_armlaunch(struct ipath_devdata *dd)
2788 /* so don't re-enable if already set */
2789 dd->ipath_maskederrs &= ~INFINIPATH_E_SPIOARMLAUNCH;
2790 dd->ipath_errormask &= ~INFINIPATH_E_SPIOARMLAUNCH;
2791 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
2792 dd->ipath_errormask);
2795 module_init(infinipath_init);
2796 module_exit(infinipath_cleanup);