2 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2003 Red Hat
4 * Copyright (C) 2007-2008 MontaVista Software, Inc.
5 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
7 * May be copied or modified under the terms of the GNU General Public License
9 * Documentation for CMD680:
10 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
12 * Documentation for SiI 3112:
13 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
15 * Errata and other documentation only available under NDA.
19 * If you are using Marvell SATA-IDE adapters with Maxtor drives
20 * ensure the system is set up for ATA100/UDMA5, not UDMA6.
22 * If you are using WD drives with SATA bridges you must set the
23 * drive to "Single". "Master" will hang.
25 * If you have strange problems with nVidia chipset systems please
26 * see the SI support documentation and update your system BIOS
29 * The Dell DRAC4 has some interesting features including effectively hot
30 * unplugging/replugging the virtual CD interface when the DRAC is reset.
31 * This often causes drivers/ide/siimage to panic but is ok with the rather
32 * smarter code in libata.
38 #include <linux/types.h>
39 #include <linux/module.h>
40 #include <linux/pci.h>
41 #include <linux/ide.h>
42 #include <linux/init.h>
45 #define DRV_NAME "siimage"
48 * pdev_is_sata - check if device is SATA
49 * @pdev: PCI device to check
51 * Returns true if this is a SATA controller
54 static int pdev_is_sata(struct pci_dev *pdev)
56 #ifdef CONFIG_BLK_DEV_IDE_SATA
57 switch (pdev->device) {
58 case PCI_DEVICE_ID_SII_3112:
59 case PCI_DEVICE_ID_SII_1210SA:
61 case PCI_DEVICE_ID_SII_680:
70 * is_sata - check if hwif is SATA
71 * @hwif: interface to check
73 * Returns true if this is a SATA controller
76 static inline int is_sata(ide_hwif_t *hwif)
78 return pdev_is_sata(to_pci_dev(hwif->dev));
82 * siimage_selreg - return register base
86 * Turn a config register offset into the right address in either
87 * PCI space or MMIO space to access the control register in question
88 * Thankfully this is a configuration operation, so isn't performance
92 static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
94 unsigned long base = (unsigned long)hwif->hwif_data;
97 if (hwif->host_flags & IDE_HFLAG_MMIO)
98 base += hwif->channel << 6;
100 base += hwif->channel << 4;
105 * siimage_seldev - return register base
109 * Turn a config register offset into the right address in either
110 * PCI space or MMIO space to access the control register in question
111 * including accounting for the unit shift.
114 static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
116 ide_hwif_t *hwif = drive->hwif;
117 unsigned long base = (unsigned long)hwif->hwif_data;
118 u8 unit = drive->dn & 1;
121 if (hwif->host_flags & IDE_HFLAG_MMIO)
122 base += hwif->channel << 6;
124 base += hwif->channel << 4;
125 base |= unit << unit;
129 static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr)
131 struct ide_host *host = pci_get_drvdata(dev);
135 tmp = readb((void __iomem *)addr);
137 pci_read_config_byte(dev, addr, &tmp);
142 static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr)
144 struct ide_host *host = pci_get_drvdata(dev);
148 tmp = readw((void __iomem *)addr);
150 pci_read_config_word(dev, addr, &tmp);
155 static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr)
157 struct ide_host *host = pci_get_drvdata(dev);
160 writeb(val, (void __iomem *)addr);
162 pci_write_config_byte(dev, addr, val);
165 static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr)
167 struct ide_host *host = pci_get_drvdata(dev);
170 writew(val, (void __iomem *)addr);
172 pci_write_config_word(dev, addr, val);
175 static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr)
177 struct ide_host *host = pci_get_drvdata(dev);
180 writel(val, (void __iomem *)addr);
182 pci_write_config_dword(dev, addr, val);
186 * sil_udma_filter - compute UDMA mask
189 * Compute the available UDMA speeds for the device on the interface.
191 * For the CMD680 this depends on the clocking mode (scsc), for the
192 * SI3112 SATA controller life is a bit simpler.
195 static u8 sil_pata_udma_filter(ide_drive_t *drive)
197 ide_hwif_t *hwif = drive->hwif;
198 struct pci_dev *dev = to_pci_dev(hwif->dev);
199 unsigned long base = (unsigned long)hwif->hwif_data;
202 base += (hwif->host_flags & IDE_HFLAG_MMIO) ? 0x4A : 0x8A;
204 scsc = sil_ioread8(dev, base);
206 switch (scsc & 0x30) {
210 case 0x20: /* 2xPCI */
216 default: /* Disabled ? */
223 static u8 sil_sata_udma_filter(ide_drive_t *drive)
225 char *m = (char *)&drive->id[ATA_ID_PROD];
227 return strstr(m, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6;
231 * sil_set_pio_mode - set host controller for PIO mode
233 * @pio: PIO mode number
235 * Load the timing settings for this device mode into the
239 static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
241 static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
242 static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
244 ide_hwif_t *hwif = drive->hwif;
245 struct pci_dev *dev = to_pci_dev(hwif->dev);
246 ide_drive_t *pair = ide_get_pair_dev(drive);
249 unsigned long addr = siimage_seldev(drive, 0x04);
250 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
251 unsigned long base = (unsigned long)hwif->hwif_data;
253 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
254 u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
255 : (mmio ? 0xB4 : 0x80);
257 u8 unit = drive->dn & 1;
259 /* trim *taskfile* PIO to the slowest of the master/slave */
261 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
263 if (pair_pio < tf_pio)
267 /* cheat for now and use the docs */
268 speedp = data_speed[pio];
269 speedt = tf_speed[tf_pio];
271 sil_iowrite16(dev, speedp, addr);
272 sil_iowrite16(dev, speedt, tfaddr);
274 /* now set up IORDY */
275 speedp = sil_ioread16(dev, tfaddr - 2);
278 mode = sil_ioread8(dev, base + addr_mask);
279 mode &= ~(unit ? 0x30 : 0x03);
281 if (ide_pio_need_iordy(drive, pio)) {
283 mode |= unit ? 0x10 : 0x01;
286 sil_iowrite16(dev, speedp, tfaddr - 2);
287 sil_iowrite8(dev, mode, base + addr_mask);
291 * sil_set_dma_mode - set host controller for DMA mode
295 * Tune the SiI chipset for the desired DMA mode.
298 static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed)
300 static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
301 static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
302 static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
304 ide_hwif_t *hwif = drive->hwif;
305 struct pci_dev *dev = to_pci_dev(hwif->dev);
306 unsigned long base = (unsigned long)hwif->hwif_data;
307 u16 ultra = 0, multi = 0;
308 u8 mode = 0, unit = drive->dn & 1;
309 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
310 u8 scsc = 0, addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
311 : (mmio ? 0xB4 : 0x80);
312 unsigned long ma = siimage_seldev(drive, 0x08);
313 unsigned long ua = siimage_seldev(drive, 0x0C);
315 scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A));
316 mode = sil_ioread8 (dev, base + addr_mask);
317 multi = sil_ioread16(dev, ma);
318 ultra = sil_ioread16(dev, ua);
320 mode &= ~(unit ? 0x30 : 0x03);
322 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
324 scsc = is_sata(hwif) ? 1 : scsc;
326 if (speed >= XFER_UDMA_0) {
328 ultra |= scsc ? ultra6[speed - XFER_UDMA_0] :
329 ultra5[speed - XFER_UDMA_0];
330 mode |= unit ? 0x30 : 0x03;
332 multi = dma[speed - XFER_MW_DMA_0];
333 mode |= unit ? 0x20 : 0x02;
336 sil_iowrite8 (dev, mode, base + addr_mask);
337 sil_iowrite16(dev, multi, ma);
338 sil_iowrite16(dev, ultra, ua);
342 * siimage_mmio_dma_test_irq - check we caused an IRQ
343 * @drive: drive we are testing
345 * Check if we caused an IDE DMA interrupt. We may also have caused
346 * SATA status interrupts, if so we clean them up and continue.
349 static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
351 ide_hwif_t *hwif = drive->hwif;
352 void __iomem *sata_error_addr
353 = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET];
355 if (sata_error_addr) {
356 unsigned long base = (unsigned long)hwif->hwif_data;
357 u32 ext_stat = readl((void __iomem *)(base + 0x10));
360 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
361 u32 sata_error = readl(sata_error_addr);
363 writel(sata_error, sata_error_addr);
364 watchdog = (sata_error & 0x00680000) ? 1 : 0;
365 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
366 "watchdog = %d, %s\n",
367 drive->name, sata_error, watchdog, __func__);
369 watchdog = (ext_stat & 0x8000) ? 1 : 0;
372 if (!(ext_stat & 0x0404) && !watchdog)
376 /* return 1 if INTR asserted */
377 if (readb((void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)) & 4)
383 static int siimage_dma_test_irq(ide_drive_t *drive)
385 if (drive->hwif->host_flags & IDE_HFLAG_MMIO)
386 return siimage_mmio_dma_test_irq(drive);
388 return ide_dma_test_irq(drive);
392 * sil_sata_reset_poll - wait for SATA reset
393 * @drive: drive we are resetting
395 * Poll the SATA phy and see whether it has come back from the dead
399 static int sil_sata_reset_poll(ide_drive_t *drive)
401 ide_hwif_t *hwif = drive->hwif;
402 void __iomem *sata_status_addr
403 = (void __iomem *)hwif->sata_scr[SATA_STATUS_OFFSET];
405 if (sata_status_addr) {
406 /* SATA Status is available only when in MMIO mode */
407 u32 sata_stat = readl(sata_status_addr);
409 if ((sata_stat & 0x03) != 0x03) {
410 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
411 hwif->name, sata_stat);
420 * sil_sata_pre_reset - reset hook
421 * @drive: IDE device being reset
423 * For the SATA devices we need to handle recalibration/geometry
427 static void sil_sata_pre_reset(ide_drive_t *drive)
429 if (drive->media == ide_disk) {
430 drive->special_flags &=
431 ~(IDE_SFLAG_SET_GEOMETRY | IDE_SFLAG_RECALIBRATE);
436 * init_chipset_siimage - set up an SI device
439 * Perform the initial PCI set up for this device. Attempt to switch
440 * to 133 MHz clocking if the system isn't already set up to do it.
443 static int init_chipset_siimage(struct pci_dev *dev)
445 struct ide_host *host = pci_get_drvdata(dev);
446 void __iomem *ioaddr = host->host_priv;
447 unsigned long base, scsc_addr;
448 u8 rev = dev->revision, tmp;
450 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
455 base = (unsigned long)ioaddr;
457 if (ioaddr && pdev_is_sata(dev)) {
460 /* make sure IDE0/1 interrupts are not masked */
461 irq_mask = (1 << 22) | (1 << 23);
462 tmp32 = readl(ioaddr + 0x48);
463 if (tmp32 & irq_mask) {
465 writel(tmp32, ioaddr + 0x48);
466 readl(ioaddr + 0x48); /* flush */
468 writel(0, ioaddr + 0x148);
469 writel(0, ioaddr + 0x1C8);
472 sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
473 sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
475 scsc_addr = base ? (base + 0x4A) : 0x8A;
476 tmp = sil_ioread8(dev, scsc_addr);
478 switch (tmp & 0x30) {
480 /* On 100 MHz clocking, try and switch to 133 MHz */
481 sil_iowrite8(dev, tmp | 0x10, scsc_addr);
484 /* Clocking is disabled, attempt to force 133MHz clocking. */
485 sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
487 /* On 133Mhz clocking. */
490 /* On PCIx2 clocking. */
494 tmp = sil_ioread8(dev, scsc_addr);
496 sil_iowrite8 (dev, 0x72, base + 0xA1);
497 sil_iowrite16(dev, 0x328A, base + 0xA2);
498 sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
499 sil_iowrite32(dev, 0x43924392, base + 0xA8);
500 sil_iowrite32(dev, 0x40094009, base + 0xAC);
501 sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1);
502 sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2);
503 sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
504 sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
505 sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
507 if (base && pdev_is_sata(dev)) {
508 writel(0xFFFF0000, ioaddr + 0x108);
509 writel(0xFFFF0000, ioaddr + 0x188);
510 writel(0x00680000, ioaddr + 0x148);
511 writel(0x00680000, ioaddr + 0x1C8);
514 /* report the clocking mode of the controller */
515 if (!pdev_is_sata(dev)) {
516 static const char *clk_str[] =
517 { "== 100", "== 133", "== 2X PCI", "DISABLED!" };
520 printk(KERN_INFO DRV_NAME " %s: BASE CLOCK %s\n",
521 pci_name(dev), clk_str[tmp & 3]);
528 * init_mmio_iops_siimage - set up the iops for MMIO
529 * @hwif: interface to set up
531 * The basic setup here is fairly simple, we can use standard MMIO
532 * operations. However we do have to set the taskfile register offsets
533 * by hand as there isn't a standard defined layout for them this time.
535 * The hardware supports buffered taskfiles and also some rather nice
536 * extended PRD tables. For better SI3112 support use the libata driver
539 static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
541 struct pci_dev *dev = to_pci_dev(hwif->dev);
542 struct ide_host *host = pci_get_drvdata(dev);
543 void *addr = host->host_priv;
544 u8 ch = hwif->channel;
545 struct ide_io_ports *io_ports = &hwif->io_ports;
549 * Fill in the basic hwif bits
551 hwif->host_flags |= IDE_HFLAG_MMIO;
553 hwif->hwif_data = addr;
556 * Now set up the hw. We have to do this ourselves as the
557 * MMIO layout isn't the same as the standard port based I/O.
559 memset(io_ports, 0, sizeof(*io_ports));
561 base = (unsigned long)addr;
568 * The buffered task file doesn't have status/control, so we
569 * can't currently use it sanely since we want to use LBA48 mode.
571 io_ports->data_addr = base;
572 io_ports->error_addr = base + 1;
573 io_ports->nsect_addr = base + 2;
574 io_ports->lbal_addr = base + 3;
575 io_ports->lbam_addr = base + 4;
576 io_ports->lbah_addr = base + 5;
577 io_ports->device_addr = base + 6;
578 io_ports->status_addr = base + 7;
579 io_ports->ctl_addr = base + 10;
581 if (pdev_is_sata(dev)) {
582 base = (unsigned long)addr;
585 hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
586 hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
587 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
590 hwif->irq = dev->irq;
592 hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
595 static int is_dev_seagate_sata(ide_drive_t *drive)
597 const char *s = (const char *)&drive->id[ATA_ID_PROD];
598 unsigned len = strnlen(s, ATA_ID_PROD_LEN);
600 if ((len > 4) && (!memcmp(s, "ST", 2)))
601 if ((!memcmp(s + len - 2, "AS", 2)) ||
602 (!memcmp(s + len - 3, "ASL", 3))) {
603 printk(KERN_INFO "%s: applying pessimistic Seagate "
604 "errata fix\n", drive->name);
612 * sil_quirkproc - post probe fixups
615 * Called after drive probe we use this to decide whether the
616 * Seagate fixup must be applied. This used to be in init_iops but
617 * that can occur before we know what drives are present.
620 static void sil_quirkproc(ide_drive_t *drive)
622 ide_hwif_t *hwif = drive->hwif;
624 /* Try and rise the rqsize */
625 if (!is_sata(hwif) || !is_dev_seagate_sata(drive))
630 * init_iops_siimage - set up iops
631 * @hwif: interface to set up
633 * Do the basic setup for the SIIMAGE hardware interface
634 * and then do the MMIO setup if we can. This is the first
635 * look in we get for setting up the hwif so that we
636 * can get the iops right before using them.
639 static void __devinit init_iops_siimage(ide_hwif_t *hwif)
641 struct pci_dev *dev = to_pci_dev(hwif->dev);
642 struct ide_host *host = pci_get_drvdata(dev);
644 hwif->hwif_data = NULL;
646 /* Pessimal until we finish probing */
650 init_mmio_iops_siimage(hwif);
654 * sil_cable_detect - cable detection
655 * @hwif: interface to check
657 * Check for the presence of an ATA66 capable cable on the interface.
660 static u8 sil_cable_detect(ide_hwif_t *hwif)
662 struct pci_dev *dev = to_pci_dev(hwif->dev);
663 unsigned long addr = siimage_selreg(hwif, 0);
664 u8 ata66 = sil_ioread8(dev, addr);
666 return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
669 static const struct ide_port_ops sil_pata_port_ops = {
670 .set_pio_mode = sil_set_pio_mode,
671 .set_dma_mode = sil_set_dma_mode,
672 .quirkproc = sil_quirkproc,
673 .udma_filter = sil_pata_udma_filter,
674 .cable_detect = sil_cable_detect,
677 static const struct ide_port_ops sil_sata_port_ops = {
678 .set_pio_mode = sil_set_pio_mode,
679 .set_dma_mode = sil_set_dma_mode,
680 .reset_poll = sil_sata_reset_poll,
681 .pre_reset = sil_sata_pre_reset,
682 .quirkproc = sil_quirkproc,
683 .udma_filter = sil_sata_udma_filter,
684 .cable_detect = sil_cable_detect,
687 static const struct ide_dma_ops sil_dma_ops = {
688 .dma_host_set = ide_dma_host_set,
689 .dma_setup = ide_dma_setup,
690 .dma_start = ide_dma_start,
691 .dma_end = ide_dma_end,
692 .dma_test_irq = siimage_dma_test_irq,
693 .dma_timer_expiry = ide_dma_sff_timer_expiry,
694 .dma_lost_irq = ide_dma_lost_irq,
695 .dma_sff_read_status = ide_dma_sff_read_status,
698 #define DECLARE_SII_DEV(p_ops) \
701 .init_chipset = init_chipset_siimage, \
702 .init_iops = init_iops_siimage, \
704 .dma_ops = &sil_dma_ops, \
705 .pio_mask = ATA_PIO4, \
706 .mwdma_mask = ATA_MWDMA2, \
707 .udma_mask = ATA_UDMA6, \
710 static const struct ide_port_info siimage_chipsets[] __devinitdata = {
711 /* 0: SiI680 */ DECLARE_SII_DEV(&sil_pata_port_ops),
712 /* 1: SiI3112 */ DECLARE_SII_DEV(&sil_sata_port_ops)
716 * siimage_init_one - PCI layer discovery entry
718 * @id: ident table entry
720 * Called by the PCI code when it finds an SiI680 or SiI3112 controller.
721 * We then use the IDE PCI generic helper to do most of the work.
724 static int __devinit siimage_init_one(struct pci_dev *dev,
725 const struct pci_device_id *id)
727 void __iomem *ioaddr = NULL;
728 resource_size_t bar5 = pci_resource_start(dev, 5);
729 unsigned long barsize = pci_resource_len(dev, 5);
731 struct ide_port_info d;
732 u8 idx = id->driver_data;
735 d = siimage_chipsets[idx];
738 static int first = 1;
741 printk(KERN_INFO DRV_NAME ": For full SATA support you "
742 "should use the libata sata_sil module.\n");
746 d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
749 rc = pci_enable_device(dev);
753 pci_read_config_byte(dev, 0x8A, &BA5_EN);
754 if ((BA5_EN & 0x01) || bar5) {
756 * Drop back to PIO if we can't map the MMIO. Some systems
757 * seem to get terminally confused in the PCI spaces.
759 if (!request_mem_region(bar5, barsize, d.name)) {
760 printk(KERN_WARNING DRV_NAME " %s: MMIO ports not "
761 "available\n", pci_name(dev));
763 ioaddr = pci_ioremap_bar(dev, 5);
765 release_mem_region(bar5, barsize);
769 rc = ide_pci_init_one(dev, &d, ioaddr);
773 release_mem_region(bar5, barsize);
775 pci_disable_device(dev);
781 static void __devexit siimage_remove(struct pci_dev *dev)
783 struct ide_host *host = pci_get_drvdata(dev);
784 void __iomem *ioaddr = host->host_priv;
789 resource_size_t bar5 = pci_resource_start(dev, 5);
790 unsigned long barsize = pci_resource_len(dev, 5);
793 release_mem_region(bar5, barsize);
796 pci_disable_device(dev);
799 static const struct pci_device_id siimage_pci_tbl[] = {
800 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 },
801 #ifdef CONFIG_BLK_DEV_IDE_SATA
802 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 },
803 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 1 },
807 MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
809 static struct pci_driver siimage_pci_driver = {
811 .id_table = siimage_pci_tbl,
812 .probe = siimage_init_one,
813 .remove = __devexit_p(siimage_remove),
814 .suspend = ide_pci_suspend,
815 .resume = ide_pci_resume,
818 static int __init siimage_ide_init(void)
820 return ide_pci_register_driver(&siimage_pci_driver);
823 static void __exit siimage_ide_exit(void)
825 pci_unregister_driver(&siimage_pci_driver);
828 module_init(siimage_ide_init);
829 module_exit(siimage_ide_exit);
831 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
832 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
833 MODULE_LICENSE("GPL");