Pileus Git - ~andy/linux/blob - drivers/ide/au1xxx-ide.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
   4  *
   5  * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
   6  *
   7  * This program is free software; you can redistribute it and/or modify it under
   8  * the terms of the GNU General Public License as published by the Free Software
   9  * Foundation; either version 2 of the License, or (at your option) any later
  10  * version.
  11  *
  12  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  13  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
  14  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
  15  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  16  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  17  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  18  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  19  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  21  * POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  * You should have received a copy of the GNU General Public License along with
  24  * this program; if not, write to the Free Software Foundation, Inc.,
  25  * 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
  28  *       Interface and Linux Device Driver" Application Note.
  29  */
  30 #include <linux/types.h>
  31 #include <linux/module.h>
  32 #include <linux/kernel.h>
  33 #include <linux/delay.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/init.h>
  36 #include <linux/ide.h>
  37 #include <linux/scatterlist.h>
  38
  39 #include <asm/mach-au1x00/au1xxx.h>
  40 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  41 #include <asm/mach-au1x00/au1xxx_ide.h>
  42
  43 #define DRV_NAME        "au1200-ide"
  44 #define DRV_AUTHOR      "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
  45
  46 /* enable the burstmode in the dbdma */
  47 #define IDE_AU1XXX_BURSTMODE    1
  48
  49 static _auide_hwif auide_hwif;
  50
  51 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
  52
  53 void auide_insw(unsigned long port, void *addr, u32 count)
  54 {
  55         _auide_hwif *ahwif = &auide_hwif;
  56         chan_tab_t *ctp;
  57         au1x_ddma_desc_t *dp;
  58
  59         if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
  60                            DDMA_FLAGS_NOIE)) {
  61                 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
  62                 return;
  63         }
  64         ctp = *((chan_tab_t **)ahwif->rx_chan);
  65         dp = ctp->cur_ptr;
  66         while (dp->dscr_cmd0 & DSCR_CMD0_V)
  67                 ;
  68         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
  69 }
  70
  71 void auide_outsw(unsigned long port, void *addr, u32 count)
  72 {
  73         _auide_hwif *ahwif = &auide_hwif;
  74         chan_tab_t *ctp;
  75         au1x_ddma_desc_t *dp;
  76
  77         if(!put_source_flags(ahwif->tx_chan, (void*)addr,
  78                              count << 1, DDMA_FLAGS_NOIE)) {
  79                 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
  80                 return;
  81         }
  82         ctp = *((chan_tab_t **)ahwif->tx_chan);
  83         dp = ctp->cur_ptr;
  84         while (dp->dscr_cmd0 & DSCR_CMD0_V)
  85                 ;
  86         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
  87 }
  88
  89 static void au1xxx_input_data(ide_drive_t *drive, struct request *rq,
  90                               void *buf, unsigned int len)
  91 {
  92         auide_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
  93 }
  94
  95 static void au1xxx_output_data(ide_drive_t *drive, struct request *rq,
  96                                void *buf, unsigned int len)
  97 {
  98         auide_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
  99 }
 100 #endif
 101
 102 static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
 103 {
 104         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
 105
 106         /* set pio mode! */
 107         switch(pio) {
 108         case 0:
 109                 mem_sttime = SBC_IDE_TIMING(PIO0);
 110
 111                 /* set configuration for RCS2# */
 112                 mem_stcfg |= TS_MASK;
 113                 mem_stcfg &= ~TCSOE_MASK;
 114                 mem_stcfg &= ~TOECS_MASK;
 115                 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
 116                 break;
 117
 118         case 1:
 119                 mem_sttime = SBC_IDE_TIMING(PIO1);
 120
 121                 /* set configuration for RCS2# */
 122                 mem_stcfg |= TS_MASK;
 123                 mem_stcfg &= ~TCSOE_MASK;
 124                 mem_stcfg &= ~TOECS_MASK;
 125                 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
 126                 break;
 127
 128         case 2:
 129                 mem_sttime = SBC_IDE_TIMING(PIO2);
 130
 131                 /* set configuration for RCS2# */
 132                 mem_stcfg &= ~TS_MASK;
 133                 mem_stcfg &= ~TCSOE_MASK;
 134                 mem_stcfg &= ~TOECS_MASK;
 135                 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
 136                 break;
 137
 138         case 3:
 139                 mem_sttime = SBC_IDE_TIMING(PIO3);
 140
 141                 /* set configuration for RCS2# */
 142                 mem_stcfg &= ~TS_MASK;
 143                 mem_stcfg &= ~TCSOE_MASK;
 144                 mem_stcfg &= ~TOECS_MASK;
 145                 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
 146
 147                 break;
 148
 149         case 4:
 150                 mem_sttime = SBC_IDE_TIMING(PIO4);
 151
 152                 /* set configuration for RCS2# */
 153                 mem_stcfg &= ~TS_MASK;
 154                 mem_stcfg &= ~TCSOE_MASK;
 155                 mem_stcfg &= ~TOECS_MASK;
 156                 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
 157                 break;
 158         }
 159
 160         au_writel(mem_sttime,MEM_STTIME2);
 161         au_writel(mem_stcfg,MEM_STCFG2);
 162 }
 163
 164 static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
 165 {
 166         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
 167
 168         switch(speed) {
 169 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 170         case XFER_MW_DMA_2:
 171                 mem_sttime = SBC_IDE_TIMING(MDMA2);
 172
 173                 /* set configuration for RCS2# */
 174                 mem_stcfg &= ~TS_MASK;
 175                 mem_stcfg &= ~TCSOE_MASK;
 176                 mem_stcfg &= ~TOECS_MASK;
 177                 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
 178
 179                 break;
 180         case XFER_MW_DMA_1:
 181                 mem_sttime = SBC_IDE_TIMING(MDMA1);
 182
 183                 /* set configuration for RCS2# */
 184                 mem_stcfg &= ~TS_MASK;
 185                 mem_stcfg &= ~TCSOE_MASK;
 186                 mem_stcfg &= ~TOECS_MASK;
 187                 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
 188
 189                 break;
 190         case XFER_MW_DMA_0:
 191                 mem_sttime = SBC_IDE_TIMING(MDMA0);
 192
 193                 /* set configuration for RCS2# */
 194                 mem_stcfg |= TS_MASK;
 195                 mem_stcfg &= ~TCSOE_MASK;
 196                 mem_stcfg &= ~TOECS_MASK;
 197                 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
 198
 199                 break;
 200 #endif
 201         }
 202
 203         au_writel(mem_sttime,MEM_STTIME2);
 204         au_writel(mem_stcfg,MEM_STCFG2);
 205 }
 206
 207 /*
 208  * Multi-Word DMA + DbDMA functions
 209  */
 210
 211 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 212 static int auide_build_dmatable(ide_drive_t *drive)
 213 {
 214         int i, iswrite, count = 0;
 215         ide_hwif_t *hwif = drive->hwif;
 216         struct request *rq = hwif->rq;
 217         _auide_hwif *ahwif = &auide_hwif;
 218         struct scatterlist *sg;
 219
 220         iswrite = (rq_data_dir(rq) == WRITE);
 221         /* Save for interrupt context */
 222         ahwif->drive = drive;
 223
 224         hwif->sg_nents = i = ide_build_sglist(drive, rq);
 225
 226         if (!i)
 227                 return 0;
 228
 229         /* fill the descriptors */
 230         sg = hwif->sg_table;
 231         while (i && sg_dma_len(sg)) {
 232                 u32 cur_addr;
 233                 u32 cur_len;
 234
 235                 cur_addr = sg_dma_address(sg);
 236                 cur_len = sg_dma_len(sg);
 237
 238                 while (cur_len) {
 239                         u32 flags = DDMA_FLAGS_NOIE;
 240                         unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
 241
 242                         if (++count >= PRD_ENTRIES) {
 243                                 printk(KERN_WARNING "%s: DMA table too small\n",
 244                                        drive->name);
 245                                 goto use_pio_instead;
 246                         }
 247
 248                         /* Lets enable intr for the last descriptor only */
 249                         if (1==i)
 250                                 flags = DDMA_FLAGS_IE;
 251                         else
 252                                 flags = DDMA_FLAGS_NOIE;
 253
 254                         if (iswrite) {
 255                                 if(!put_source_flags(ahwif->tx_chan,
 256                                                      (void*) sg_virt(sg),
 257                                                      tc, flags)) {
 258                                         printk(KERN_ERR "%s failed %d\n",
 259                                                __func__, __LINE__);
 260                                 }
 261                         } else
 262                         {
 263                                 if(!put_dest_flags(ahwif->rx_chan,
 264                                                    (void*) sg_virt(sg),
 265                                                    tc, flags)) {
 266                                         printk(KERN_ERR "%s failed %d\n",
 267                                                __func__, __LINE__);
 268                                 }
 269                         }
 270
 271                         cur_addr += tc;
 272                         cur_len -= tc;
 273                 }
 274                 sg = sg_next(sg);
 275                 i--;
 276         }
 277
 278         if (count)
 279                 return 1;
 280
 281  use_pio_instead:
 282         ide_destroy_dmatable(drive);
 283
 284         return 0; /* revert to PIO for this request */
 285 }
 286
 287 static int auide_dma_end(ide_drive_t *drive)
 288 {
 289         ide_destroy_dmatable(drive);
 290
 291         return 0;
 292 }
 293
 294 static void auide_dma_start(ide_drive_t *drive )
 295 {
 296 }
 297
 298
 299 static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
 300 {
 301         /* issue cmd to drive */
 302         ide_execute_command(drive, command, &ide_dma_intr,
 303                             (2*WAIT_CMD), NULL);
 304 }
 305
 306 static int auide_dma_setup(ide_drive_t *drive)
 307 {
 308         struct request *rq = drive->hwif->rq;
 309
 310         if (!auide_build_dmatable(drive)) {
 311                 ide_map_sg(drive, rq);
 312                 return 1;
 313         }
 314
 315         drive->waiting_for_dma = 1;
 316         return 0;
 317 }
 318
 319 static int auide_dma_test_irq(ide_drive_t *drive)
 320 {
 321         /* If dbdma didn't execute the STOP command yet, the
 322          * active bit is still set
 323          */
 324         drive->waiting_for_dma++;
 325         if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
 326                 printk(KERN_WARNING "%s: timeout waiting for ddma to \
 327                                      complete\n", drive->name);
 328                 return 1;
 329         }
 330         udelay(10);
 331         return 0;
 332 }
 333
 334 static void auide_dma_host_set(ide_drive_t *drive, int on)
 335 {
 336 }
 337
 338 static void auide_ddma_tx_callback(int irq, void *param)
 339 {
 340         _auide_hwif *ahwif = (_auide_hwif*)param;
 341         ahwif->drive->waiting_for_dma = 0;
 342 }
 343
 344 static void auide_ddma_rx_callback(int irq, void *param)
 345 {
 346         _auide_hwif *ahwif = (_auide_hwif*)param;
 347         ahwif->drive->waiting_for_dma = 0;
 348 }
 349
 350 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
 351
 352 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
 353 {
 354         dev->dev_id          = dev_id;
 355         dev->dev_physaddr    = (u32)IDE_PHYS_ADDR;
 356         dev->dev_intlevel    = 0;
 357         dev->dev_intpolarity = 0;
 358         dev->dev_tsize       = tsize;
 359         dev->dev_devwidth    = devwidth;
 360         dev->dev_flags       = flags;
 361 }
 362
 363 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 364 static const struct ide_dma_ops au1xxx_dma_ops = {
 365         .dma_host_set           = auide_dma_host_set,
 366         .dma_setup              = auide_dma_setup,
 367         .dma_exec_cmd           = auide_dma_exec_cmd,
 368         .dma_start              = auide_dma_start,
 369         .dma_end                = auide_dma_end,
 370         .dma_test_irq           = auide_dma_test_irq,
 371         .dma_lost_irq           = ide_dma_lost_irq,
 372         .dma_timeout            = ide_dma_timeout,
 373 };
 374
 375 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
 376 {
 377         _auide_hwif *auide = &auide_hwif;
 378         dbdev_tab_t source_dev_tab, target_dev_tab;
 379         u32 dev_id, tsize, devwidth, flags;
 380
 381         dev_id   = IDE_DDMA_REQ;
 382
 383         tsize    =  8; /*  1 */
 384         devwidth = 32; /* 16 */
 385
 386 #ifdef IDE_AU1XXX_BURSTMODE
 387         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
 388 #else
 389         flags = DEV_FLAGS_SYNC;
 390 #endif
 391
 392         /* setup dev_tab for tx channel */
 393         auide_init_dbdma_dev( &source_dev_tab,
 394                               dev_id,
 395                               tsize, devwidth, DEV_FLAGS_OUT | flags);
 396         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 397
 398         auide_init_dbdma_dev( &source_dev_tab,
 399                               dev_id,
 400                               tsize, devwidth, DEV_FLAGS_IN | flags);
 401         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 402
 403         /* We also need to add a target device for the DMA */
 404         auide_init_dbdma_dev( &target_dev_tab,
 405                               (u32)DSCR_CMD0_ALWAYS,
 406                               tsize, devwidth, DEV_FLAGS_ANYUSE);
 407         auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
 408
 409         /* Get a channel for TX */
 410         auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
 411                                                  auide->tx_dev_id,
 412                                                  auide_ddma_tx_callback,
 413                                                  (void*)auide);
 414
 415         /* Get a channel for RX */
 416         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
 417                                                  auide->target_dev_id,
 418                                                  auide_ddma_rx_callback,
 419                                                  (void*)auide);
 420
 421         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
 422                                                              NUM_DESCRIPTORS);
 423         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
 424                                                              NUM_DESCRIPTORS);
 425
 426         /* FIXME: check return value */
 427         (void)ide_allocate_dma_engine(hwif);
 428
 429         au1xxx_dbdma_start( auide->tx_chan );
 430         au1xxx_dbdma_start( auide->rx_chan );
 431
 432         return 0;
 433 }
 434 #else
 435 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
 436 {
 437         _auide_hwif *auide = &auide_hwif;
 438         dbdev_tab_t source_dev_tab;
 439         int flags;
 440
 441 #ifdef IDE_AU1XXX_BURSTMODE
 442         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
 443 #else
 444         flags = DEV_FLAGS_SYNC;
 445 #endif
 446
 447         /* setup dev_tab for tx channel */
 448         auide_init_dbdma_dev( &source_dev_tab,
 449                               (u32)DSCR_CMD0_ALWAYS,
 450                               8, 32, DEV_FLAGS_OUT | flags);
 451         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 452
 453         auide_init_dbdma_dev( &source_dev_tab,
 454                               (u32)DSCR_CMD0_ALWAYS,
 455                               8, 32, DEV_FLAGS_IN | flags);
 456         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 457
 458         /* Get a channel for TX */
 459         auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
 460                                                  auide->tx_dev_id,
 461                                                  NULL,
 462                                                  (void*)auide);
 463
 464         /* Get a channel for RX */
 465         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
 466                                                  DSCR_CMD0_ALWAYS,
 467                                                  NULL,
 468                                                  (void*)auide);
 469
 470         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
 471                                                              NUM_DESCRIPTORS);
 472         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
 473                                                              NUM_DESCRIPTORS);
 474
 475         au1xxx_dbdma_start( auide->tx_chan );
 476         au1xxx_dbdma_start( auide->rx_chan );
 477
 478         return 0;
 479 }
 480 #endif
 481
 482 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
 483 {
 484         int i;
 485         unsigned long *ata_regs = hw->io_ports_array;
 486
 487         /* FIXME? */
 488         for (i = 0; i < 8; i++)
 489                 *ata_regs++ = ahwif->regbase + (i << IDE_REG_SHIFT);
 490
 491         /* set the Alternative Status register */
 492         *ata_regs = ahwif->regbase + (14 << IDE_REG_SHIFT);
 493 }
 494
 495 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
 496 static const struct ide_tp_ops au1xxx_tp_ops = {
 497         .exec_command           = ide_exec_command,
 498         .read_status            = ide_read_status,
 499         .read_altstatus         = ide_read_altstatus,
 500
 501         .set_irq                = ide_set_irq,
 502
 503         .tf_load                = ide_tf_load,
 504         .tf_read                = ide_tf_read,
 505
 506         .input_data             = au1xxx_input_data,
 507         .output_data            = au1xxx_output_data,
 508 };
 509 #endif
 510
 511 static const struct ide_port_ops au1xxx_port_ops = {
 512         .set_pio_mode           = au1xxx_set_pio_mode,
 513         .set_dma_mode           = auide_set_dma_mode,
 514 };
 515
 516 static const struct ide_port_info au1xxx_port_info = {
 517         .init_dma               = auide_ddma_init,
 518 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
 519         .tp_ops                 = &au1xxx_tp_ops,
 520 #endif
 521         .port_ops               = &au1xxx_port_ops,
 522 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 523         .dma_ops                = &au1xxx_dma_ops,
 524 #endif
 525         .host_flags             = IDE_HFLAG_POST_SET_MODE |
 526                                   IDE_HFLAG_NO_IO_32BIT |
 527                                   IDE_HFLAG_UNMASK_IRQS,
 528         .pio_mask               = ATA_PIO4,
 529 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 530         .mwdma_mask             = ATA_MWDMA2,
 531 #endif
 532 };
 533
 534 static int au_ide_probe(struct platform_device *dev)
 535 {
 536         _auide_hwif *ahwif = &auide_hwif;
 537         struct resource *res;
 538         struct ide_host *host;
 539         int ret = 0;
 540         hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
 541
 542 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
 543         char *mode = "MWDMA2";
 544 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
 545         char *mode = "PIO+DDMA(offload)";
 546 #endif
 547
 548         memset(&auide_hwif, 0, sizeof(_auide_hwif));
 549         ahwif->irq = platform_get_irq(dev, 0);
 550
 551         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 552
 553         if (res == NULL) {
 554                 pr_debug("%s %d: no base address\n", DRV_NAME, dev->id);
 555                 ret = -ENODEV;
 556                 goto out;
 557         }
 558         if (ahwif->irq < 0) {
 559                 pr_debug("%s %d: no IRQ\n", DRV_NAME, dev->id);
 560                 ret = -ENODEV;
 561                 goto out;
 562         }
 563
 564         if (!request_mem_region(res->start, res->end - res->start + 1,
 565                                 dev->name)) {
 566                 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
 567                 ret =  -EBUSY;
 568                 goto out;
 569         }
 570
 571         ahwif->regbase = (u32)ioremap(res->start, res->end - res->start + 1);
 572         if (ahwif->regbase == 0) {
 573                 ret = -ENOMEM;
 574                 goto out;
 575         }
 576
 577         memset(&hw, 0, sizeof(hw));
 578         auide_setup_ports(&hw, ahwif);
 579         hw.irq = ahwif->irq;
 580         hw.dev = &dev->dev;
 581         hw.chipset = ide_au1xxx;
 582
 583         ret = ide_host_add(&au1xxx_port_info, hws, &host);
 584         if (ret)
 585                 goto out;
 586
 587         auide_hwif.hwif = host->ports[0];
 588
 589         platform_set_drvdata(dev, host);
 590
 591         printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
 592
 593  out:
 594         return ret;
 595 }
 596
 597 static int au_ide_remove(struct platform_device *dev)
 598 {
 599         struct resource *res;
 600         struct ide_host *host = platform_get_drvdata(dev);
 601         _auide_hwif *ahwif = &auide_hwif;
 602
 603         ide_host_remove(host);
 604
 605         iounmap((void *)ahwif->regbase);
 606
 607         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 608         release_mem_region(res->start, res->end - res->start + 1);
 609
 610         return 0;
 611 }
 612
 613 static struct platform_driver au1200_ide_driver = {
 614         .driver = {
 615                 .name           = "au1200-ide",
 616                 .owner          = THIS_MODULE,
 617         },
 618         .probe          = au_ide_probe,
 619         .remove         = au_ide_remove,
 620 };
 621
 622 static int __init au_ide_init(void)
 623 {
 624         return platform_driver_register(&au1200_ide_driver);
 625 }
 626
 627 static void __exit au_ide_exit(void)
 628 {
 629         platform_driver_unregister(&au1200_ide_driver);
 630 }
 631
 632 MODULE_LICENSE("GPL");
 633 MODULE_DESCRIPTION("AU1200 IDE driver");
 634
 635 module_init(au_ide_init);
 636 module_exit(au_ide_exit);