Pileus Git - ~andy/linux/blob - drivers/i2c/busses/i2c-tegra.c

   1 /*
   2  * drivers/i2c/busses/i2c-tegra.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Colin Cross <ccross@android.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/err.h>
  23 #include <linux/i2c.h>
  24 #include <linux/io.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/of_device.h>
  29 #include <linux/module.h>
  30 #include <linux/clk/tegra.h>
  31
  32 #include <asm/unaligned.h>
  33
  34 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
  35 #define BYTES_PER_FIFO_WORD 4
  36
  37 #define I2C_CNFG                                0x000
  38 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
  39 #define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
  40 #define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
  41 #define I2C_STATUS                              0x01C
  42 #define I2C_SL_CNFG                             0x020
  43 #define I2C_SL_CNFG_NACK                        (1<<1)
  44 #define I2C_SL_CNFG_NEWSL                       (1<<2)
  45 #define I2C_SL_ADDR1                            0x02c
  46 #define I2C_SL_ADDR2                            0x030
  47 #define I2C_TX_FIFO                             0x050
  48 #define I2C_RX_FIFO                             0x054
  49 #define I2C_PACKET_TRANSFER_STATUS              0x058
  50 #define I2C_FIFO_CONTROL                        0x05c
  51 #define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
  52 #define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
  53 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
  54 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
  55 #define I2C_FIFO_STATUS                         0x060
  56 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
  57 #define I2C_FIFO_STATUS_TX_SHIFT                4
  58 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
  59 #define I2C_FIFO_STATUS_RX_SHIFT                0
  60 #define I2C_INT_MASK                            0x064
  61 #define I2C_INT_STATUS                          0x068
  62 #define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
  63 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
  64 #define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
  65 #define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
  66 #define I2C_INT_NO_ACK                          (1<<3)
  67 #define I2C_INT_ARBITRATION_LOST                (1<<2)
  68 #define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
  69 #define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
  70 #define I2C_CLK_DIVISOR                         0x06c
  71 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT     16
  72 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE        8
  73
  74 #define DVC_CTRL_REG1                           0x000
  75 #define DVC_CTRL_REG1_INTR_EN                   (1<<10)
  76 #define DVC_CTRL_REG2                           0x004
  77 #define DVC_CTRL_REG3                           0x008
  78 #define DVC_CTRL_REG3_SW_PROG                   (1<<26)
  79 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          (1<<30)
  80 #define DVC_STATUS                              0x00c
  81 #define DVC_STATUS_I2C_DONE_INTR                (1<<30)
  82
  83 #define I2C_ERR_NONE                            0x00
  84 #define I2C_ERR_NO_ACK                          0x01
  85 #define I2C_ERR_ARBITRATION_LOST                0x02
  86 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
  87
  88 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
  89 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
  90 #define PACKET_HEADER0_CONT_ID_SHIFT            12
  91 #define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
  92
  93 #define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
  94 #define I2C_HEADER_CONT_ON_NAK                  (1<<21)
  95 #define I2C_HEADER_SEND_START_BYTE              (1<<20)
  96 #define I2C_HEADER_READ                         (1<<19)
  97 #define I2C_HEADER_10BIT_ADDR                   (1<<18)
  98 #define I2C_HEADER_IE_ENABLE                    (1<<17)
  99 #define I2C_HEADER_REPEAT_START                 (1<<16)
 100 #define I2C_HEADER_CONTINUE_XFER                (1<<15)
 101 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
 102 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
 103 /*
 104  * msg_end_type: The bus control which need to be send at end of transfer.
 105  * @MSG_END_STOP: Send stop pulse at end of transfer.
 106  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
 107  * @MSG_END_CONTINUE: The following on message is coming and so do not send
 108  *              stop or repeat start.
 109  */
 110 enum msg_end_type {
 111         MSG_END_STOP,
 112         MSG_END_REPEAT_START,
 113         MSG_END_CONTINUE,
 114 };
 115
 116 /**
 117  * struct tegra_i2c_hw_feature : Different HW support on Tegra
 118  * @has_continue_xfer_support: Continue transfer supports.
 119  * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
 120  *              complete interrupt per packet basis.
 121  * @has_single_clk_source: The i2c controller has single clock source. Tegra30
 122  *              and earlier Socs has two clock sources i.e. div-clk and
 123  *              fast-clk.
 124  * @clk_divisor_hs_mode: Clock divisor in HS mode.
 125  * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
 126  *              applicable if there is no fast clock source i.e. single clock
 127  *              source.
 128  */
 129
 130 struct tegra_i2c_hw_feature {
 131         bool has_continue_xfer_support;
 132         bool has_per_pkt_xfer_complete_irq;
 133         bool has_single_clk_source;
 134         int clk_divisor_hs_mode;
 135         int clk_divisor_std_fast_mode;
 136 };
 137
 138 /**
 139  * struct tegra_i2c_dev - per device i2c context
 140  * @dev: device reference for power management
 141  * @hw: Tegra i2c hw feature.
 142  * @adapter: core i2c layer adapter information
 143  * @div_clk: clock reference for div clock of i2c controller.
 144  * @fast_clk: clock reference for fast clock of i2c controller.
 145  * @base: ioremapped registers cookie
 146  * @cont_id: i2c controller id, used for for packet header
 147  * @irq: irq number of transfer complete interrupt
 148  * @is_dvc: identifies the DVC i2c controller, has a different register layout
 149  * @msg_complete: transfer completion notifier
 150  * @msg_err: error code for completed message
 151  * @msg_buf: pointer to current message data
 152  * @msg_buf_remaining: size of unsent data in the message buffer
 153  * @msg_read: identifies read transfers
 154  * @bus_clk_rate: current i2c bus clock rate
 155  * @is_suspended: prevents i2c controller accesses after suspend is called
 156  */
 157 struct tegra_i2c_dev {
 158         struct device *dev;
 159         const struct tegra_i2c_hw_feature *hw;
 160         struct i2c_adapter adapter;
 161         struct clk *div_clk;
 162         struct clk *fast_clk;
 163         void __iomem *base;
 164         int cont_id;
 165         int irq;
 166         bool irq_disabled;
 167         int is_dvc;
 168         struct completion msg_complete;
 169         int msg_err;
 170         u8 *msg_buf;
 171         size_t msg_buf_remaining;
 172         int msg_read;
 173         u32 bus_clk_rate;
 174         bool is_suspended;
 175 };
 176
 177 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
 178 {
 179         writel(val, i2c_dev->base + reg);
 180 }
 181
 182 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 183 {
 184         return readl(i2c_dev->base + reg);
 185 }
 186
 187 /*
 188  * i2c_writel and i2c_readl will offset the register if necessary to talk
 189  * to the I2C block inside the DVC block
 190  */
 191 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 192         unsigned long reg)
 193 {
 194         if (i2c_dev->is_dvc)
 195                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 196         return reg;
 197 }
 198
 199 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 200         unsigned long reg)
 201 {
 202         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 203
 204         /* Read back register to make sure that register writes completed */
 205         if (reg != I2C_TX_FIFO)
 206                 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 207 }
 208
 209 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 210 {
 211         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 212 }
 213
 214 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 215         unsigned long reg, int len)
 216 {
 217         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 218 }
 219
 220 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 221         unsigned long reg, int len)
 222 {
 223         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 224 }
 225
 226 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 227 {
 228         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 229         int_mask &= ~mask;
 230         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 231 }
 232
 233 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 234 {
 235         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 236         int_mask |= mask;
 237         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 238 }
 239
 240 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 241 {
 242         unsigned long timeout = jiffies + HZ;
 243         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
 244         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
 245         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 246
 247         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
 248                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
 249                 if (time_after(jiffies, timeout)) {
 250                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 251                         return -ETIMEDOUT;
 252                 }
 253                 msleep(1);
 254         }
 255         return 0;
 256 }
 257
 258 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 259 {
 260         u32 val;
 261         int rx_fifo_avail;
 262         u8 *buf = i2c_dev->msg_buf;
 263         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 264         int words_to_transfer;
 265
 266         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 267         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
 268                 I2C_FIFO_STATUS_RX_SHIFT;
 269
 270         /* Rounds down to not include partial word at the end of buf */
 271         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 272         if (words_to_transfer > rx_fifo_avail)
 273                 words_to_transfer = rx_fifo_avail;
 274
 275         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 276
 277         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 278         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 279         rx_fifo_avail -= words_to_transfer;
 280
 281         /*
 282          * If there is a partial word at the end of buf, handle it manually to
 283          * prevent overwriting past the end of buf
 284          */
 285         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 286                 BUG_ON(buf_remaining > 3);
 287                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 288                 memcpy(buf, &val, buf_remaining);
 289                 buf_remaining = 0;
 290                 rx_fifo_avail--;
 291         }
 292
 293         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
 294         i2c_dev->msg_buf_remaining = buf_remaining;
 295         i2c_dev->msg_buf = buf;
 296         return 0;
 297 }
 298
 299 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 300 {
 301         u32 val;
 302         int tx_fifo_avail;
 303         u8 *buf = i2c_dev->msg_buf;
 304         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 305         int words_to_transfer;
 306
 307         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 308         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
 309                 I2C_FIFO_STATUS_TX_SHIFT;
 310
 311         /* Rounds down to not include partial word at the end of buf */
 312         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 313
 314         /* It's very common to have < 4 bytes, so optimize that case. */
 315         if (words_to_transfer) {
 316                 if (words_to_transfer > tx_fifo_avail)
 317                         words_to_transfer = tx_fifo_avail;
 318
 319                 /*
 320                  * Update state before writing to FIFO.  If this casues us
 321                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
 322                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
 323                  * not maskable).  We need to make sure that the isr sees
 324                  * buf_remaining as 0 and doesn't call us back re-entrantly.
 325                  */
 326                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 327                 tx_fifo_avail -= words_to_transfer;
 328                 i2c_dev->msg_buf_remaining = buf_remaining;
 329                 i2c_dev->msg_buf = buf +
 330                         words_to_transfer * BYTES_PER_FIFO_WORD;
 331                 barrier();
 332
 333                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 334
 335                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 336         }
 337
 338         /*
 339          * If there is a partial word at the end of buf, handle it manually to
 340          * prevent reading past the end of buf, which could cross a page
 341          * boundary and fault.
 342          */
 343         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 344                 BUG_ON(buf_remaining > 3);
 345                 memcpy(&val, buf, buf_remaining);
 346
 347                 /* Again update before writing to FIFO to make sure isr sees. */
 348                 i2c_dev->msg_buf_remaining = 0;
 349                 i2c_dev->msg_buf = NULL;
 350                 barrier();
 351
 352                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 353         }
 354
 355         return 0;
 356 }
 357
 358 /*
 359  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 360  * block.  This block is identical to the rest of the I2C blocks, except that
 361  * it only supports master mode, it has registers moved around, and it needs
 362  * some extra init to get it into I2C mode.  The register moves are handled
 363  * by i2c_readl and i2c_writel
 364  */
 365 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 366 {
 367         u32 val = 0;
 368         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 369         val |= DVC_CTRL_REG3_SW_PROG;
 370         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 371         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 372
 373         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 374         val |= DVC_CTRL_REG1_INTR_EN;
 375         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 376 }
 377
 378 static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev)
 379 {
 380         int ret;
 381         if (!i2c_dev->hw->has_single_clk_source) {
 382                 ret = clk_prepare_enable(i2c_dev->fast_clk);
 383                 if (ret < 0) {
 384                         dev_err(i2c_dev->dev,
 385                                 "Enabling fast clk failed, err %d\n", ret);
 386                         return ret;
 387                 }
 388         }
 389         ret = clk_prepare_enable(i2c_dev->div_clk);
 390         if (ret < 0) {
 391                 dev_err(i2c_dev->dev,
 392                         "Enabling div clk failed, err %d\n", ret);
 393                 clk_disable_unprepare(i2c_dev->fast_clk);
 394         }
 395         return ret;
 396 }
 397
 398 static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev)
 399 {
 400         clk_disable_unprepare(i2c_dev->div_clk);
 401         if (!i2c_dev->hw->has_single_clk_source)
 402                 clk_disable_unprepare(i2c_dev->fast_clk);
 403 }
 404
 405 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 406 {
 407         u32 val;
 408         int err = 0;
 409         int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
 410         u32 clk_divisor;
 411
 412         err = tegra_i2c_clock_enable(i2c_dev);
 413         if (err < 0) {
 414                 dev_err(i2c_dev->dev, "Clock enable failed %d\n", err);
 415                 return err;
 416         }
 417
 418         tegra_periph_reset_assert(i2c_dev->div_clk);
 419         udelay(2);
 420         tegra_periph_reset_deassert(i2c_dev->div_clk);
 421
 422         if (i2c_dev->is_dvc)
 423                 tegra_dvc_init(i2c_dev);
 424
 425         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 426                 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 427         i2c_writel(i2c_dev, val, I2C_CNFG);
 428         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 429
 430         clk_multiplier *= (i2c_dev->hw->clk_divisor_std_fast_mode + 1);
 431         clk_set_rate(i2c_dev->div_clk, i2c_dev->bus_clk_rate * clk_multiplier);
 432
 433         /* Make sure clock divisor programmed correctly */
 434         clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
 435         clk_divisor |= i2c_dev->hw->clk_divisor_std_fast_mode <<
 436                                         I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
 437         i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
 438
 439         if (!i2c_dev->is_dvc) {
 440                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 441                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 442                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 443                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 444                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 445
 446         }
 447
 448         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
 449                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
 450         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 451
 452         if (tegra_i2c_flush_fifos(i2c_dev))
 453                 err = -ETIMEDOUT;
 454
 455         tegra_i2c_clock_disable(i2c_dev);
 456
 457         if (i2c_dev->irq_disabled) {
 458                 i2c_dev->irq_disabled = 0;
 459                 enable_irq(i2c_dev->irq);
 460         }
 461
 462         return err;
 463 }
 464
 465 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 466 {
 467         u32 status;
 468         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 469         struct tegra_i2c_dev *i2c_dev = dev_id;
 470
 471         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 472
 473         if (status == 0) {
 474                 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
 475                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 476                          i2c_readl(i2c_dev, I2C_STATUS),
 477                          i2c_readl(i2c_dev, I2C_CNFG));
 478                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 479
 480                 if (!i2c_dev->irq_disabled) {
 481                         disable_irq_nosync(i2c_dev->irq);
 482                         i2c_dev->irq_disabled = 1;
 483                 }
 484                 goto err;
 485         }
 486
 487         if (unlikely(status & status_err)) {
 488                 if (status & I2C_INT_NO_ACK)
 489                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 490                 if (status & I2C_INT_ARBITRATION_LOST)
 491                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 492                 goto err;
 493         }
 494
 495         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 496                 if (i2c_dev->msg_buf_remaining)
 497                         tegra_i2c_empty_rx_fifo(i2c_dev);
 498                 else
 499                         BUG();
 500         }
 501
 502         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 503                 if (i2c_dev->msg_buf_remaining)
 504                         tegra_i2c_fill_tx_fifo(i2c_dev);
 505                 else
 506                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
 507         }
 508
 509         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 510         if (i2c_dev->is_dvc)
 511                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 512
 513         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 514                 BUG_ON(i2c_dev->msg_buf_remaining);
 515                 complete(&i2c_dev->msg_complete);
 516         }
 517         return IRQ_HANDLED;
 518 err:
 519         /* An error occurred, mask all interrupts */
 520         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 521                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 522                 I2C_INT_RX_FIFO_DATA_REQ);
 523         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 524         if (i2c_dev->is_dvc)
 525                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 526
 527         complete(&i2c_dev->msg_complete);
 528         return IRQ_HANDLED;
 529 }
 530
 531 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
 532         struct i2c_msg *msg, enum msg_end_type end_state)
 533 {
 534         u32 packet_header;
 535         u32 int_mask;
 536         int ret;
 537
 538         tegra_i2c_flush_fifos(i2c_dev);
 539
 540         if (msg->len == 0)
 541                 return -EINVAL;
 542
 543         i2c_dev->msg_buf = msg->buf;
 544         i2c_dev->msg_buf_remaining = msg->len;
 545         i2c_dev->msg_err = I2C_ERR_NONE;
 546         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
 547         INIT_COMPLETION(i2c_dev->msg_complete);
 548
 549         packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 550                         PACKET_HEADER0_PROTOCOL_I2C |
 551                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 552                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 553         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 554
 555         packet_header = msg->len - 1;
 556         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 557
 558         packet_header = I2C_HEADER_IE_ENABLE;
 559         if (end_state == MSG_END_CONTINUE)
 560                 packet_header |= I2C_HEADER_CONTINUE_XFER;
 561         else if (end_state == MSG_END_REPEAT_START)
 562                 packet_header |= I2C_HEADER_REPEAT_START;
 563         if (msg->flags & I2C_M_TEN) {
 564                 packet_header |= msg->addr;
 565                 packet_header |= I2C_HEADER_10BIT_ADDR;
 566         } else {
 567                 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
 568         }
 569         if (msg->flags & I2C_M_IGNORE_NAK)
 570                 packet_header |= I2C_HEADER_CONT_ON_NAK;
 571         if (msg->flags & I2C_M_RD)
 572                 packet_header |= I2C_HEADER_READ;
 573         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 574
 575         if (!(msg->flags & I2C_M_RD))
 576                 tegra_i2c_fill_tx_fifo(i2c_dev);
 577
 578         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 579         if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
 580                 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
 581         if (msg->flags & I2C_M_RD)
 582                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
 583         else if (i2c_dev->msg_buf_remaining)
 584                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
 585         tegra_i2c_unmask_irq(i2c_dev, int_mask);
 586         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
 587                 i2c_readl(i2c_dev, I2C_INT_MASK));
 588
 589         ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
 590         tegra_i2c_mask_irq(i2c_dev, int_mask);
 591
 592         if (ret == 0) {
 593                 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
 594
 595                 tegra_i2c_init(i2c_dev);
 596                 return -ETIMEDOUT;
 597         }
 598
 599         dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
 600                 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
 601
 602         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
 603                 return 0;
 604
 605         /*
 606          * NACK interrupt is generated before the I2C controller generates the
 607          * STOP condition on the bus. So wait for 2 clock periods before resetting
 608          * the controller so that STOP condition has been delivered properly.
 609          */
 610         if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
 611                 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
 612
 613         tegra_i2c_init(i2c_dev);
 614         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
 615                 if (msg->flags & I2C_M_IGNORE_NAK)
 616                         return 0;
 617                 return -EREMOTEIO;
 618         }
 619
 620         return -EIO;
 621 }
 622
 623 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 624         int num)
 625 {
 626         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 627         int i;
 628         int ret = 0;
 629
 630         if (i2c_dev->is_suspended)
 631                 return -EBUSY;
 632
 633         ret = tegra_i2c_clock_enable(i2c_dev);
 634         if (ret < 0) {
 635                 dev_err(i2c_dev->dev, "Clock enable failed %d\n", ret);
 636                 return ret;
 637         }
 638
 639         for (i = 0; i < num; i++) {
 640                 enum msg_end_type end_type = MSG_END_STOP;
 641                 if (i < (num - 1)) {
 642                         if (msgs[i + 1].flags & I2C_M_NOSTART)
 643                                 end_type = MSG_END_CONTINUE;
 644                         else
 645                                 end_type = MSG_END_REPEAT_START;
 646                 }
 647                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
 648                 if (ret)
 649                         break;
 650         }
 651         tegra_i2c_clock_disable(i2c_dev);
 652         return ret ?: i;
 653 }
 654
 655 static u32 tegra_i2c_func(struct i2c_adapter *adap)
 656 {
 657         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 658         u32 ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
 659                                 I2C_FUNC_PROTOCOL_MANGLING;
 660
 661         if (i2c_dev->hw->has_continue_xfer_support)
 662                 ret |= I2C_FUNC_NOSTART;
 663         return ret;
 664 }
 665
 666 static const struct i2c_algorithm tegra_i2c_algo = {
 667         .master_xfer    = tegra_i2c_xfer,
 668         .functionality  = tegra_i2c_func,
 669 };
 670
 671 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
 672         .has_continue_xfer_support = false,
 673         .has_per_pkt_xfer_complete_irq = false,
 674         .has_single_clk_source = false,
 675         .clk_divisor_hs_mode = 3,
 676         .clk_divisor_std_fast_mode = 0,
 677 };
 678
 679 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
 680         .has_continue_xfer_support = true,
 681         .has_per_pkt_xfer_complete_irq = false,
 682         .has_single_clk_source = false,
 683         .clk_divisor_hs_mode = 3,
 684         .clk_divisor_std_fast_mode = 0,
 685 };
 686
 687 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
 688         .has_continue_xfer_support = true,
 689         .has_per_pkt_xfer_complete_irq = true,
 690         .has_single_clk_source = true,
 691         .clk_divisor_hs_mode = 1,
 692         .clk_divisor_std_fast_mode = 0x19,
 693 };
 694
 695 /* Match table for of_platform binding */
 696 static const struct of_device_id tegra_i2c_of_match[] = {
 697         { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
 698         { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
 699         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
 700         { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
 701         {},
 702 };
 703 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
 704
 705 static int tegra_i2c_probe(struct platform_device *pdev)
 706 {
 707         struct tegra_i2c_dev *i2c_dev;
 708         struct resource *res;
 709         struct clk *div_clk;
 710         struct clk *fast_clk;
 711         void __iomem *base;
 712         int irq;
 713         int ret = 0;
 714
 715         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 716         base = devm_ioremap_resource(&pdev->dev, res);
 717         if (IS_ERR(base))
 718                 return PTR_ERR(base);
 719
 720         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 721         if (!res) {
 722                 dev_err(&pdev->dev, "no irq resource\n");
 723                 return -EINVAL;
 724         }
 725         irq = res->start;
 726
 727         div_clk = devm_clk_get(&pdev->dev, "div-clk");
 728         if (IS_ERR(div_clk)) {
 729                 dev_err(&pdev->dev, "missing controller clock");
 730                 return PTR_ERR(div_clk);
 731         }
 732
 733         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
 734         if (!i2c_dev) {
 735                 dev_err(&pdev->dev, "Could not allocate struct tegra_i2c_dev");
 736                 return -ENOMEM;
 737         }
 738
 739         i2c_dev->base = base;
 740         i2c_dev->div_clk = div_clk;
 741         i2c_dev->adapter.algo = &tegra_i2c_algo;
 742         i2c_dev->irq = irq;
 743         i2c_dev->cont_id = pdev->id;
 744         i2c_dev->dev = &pdev->dev;
 745
 746         ret = of_property_read_u32(i2c_dev->dev->of_node, "clock-frequency",
 747                                         &i2c_dev->bus_clk_rate);
 748         if (ret)
 749                 i2c_dev->bus_clk_rate = 100000; /* default clock rate */
 750
 751         i2c_dev->hw = &tegra20_i2c_hw;
 752
 753         if (pdev->dev.of_node) {
 754                 const struct of_device_id *match;
 755                 match = of_match_device(tegra_i2c_of_match, &pdev->dev);
 756                 i2c_dev->hw = match->data;
 757                 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
 758                                                 "nvidia,tegra20-i2c-dvc");
 759         } else if (pdev->id == 3) {
 760                 i2c_dev->is_dvc = 1;
 761         }
 762         init_completion(&i2c_dev->msg_complete);
 763
 764         if (!i2c_dev->hw->has_single_clk_source) {
 765                 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
 766                 if (IS_ERR(fast_clk)) {
 767                         dev_err(&pdev->dev, "missing fast clock");
 768                         return PTR_ERR(fast_clk);
 769                 }
 770                 i2c_dev->fast_clk = fast_clk;
 771         }
 772
 773         platform_set_drvdata(pdev, i2c_dev);
 774
 775         ret = tegra_i2c_init(i2c_dev);
 776         if (ret) {
 777                 dev_err(&pdev->dev, "Failed to initialize i2c controller");
 778                 return ret;
 779         }
 780
 781         ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
 782                         tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
 783         if (ret) {
 784                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
 785                 return ret;
 786         }
 787
 788         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
 789         i2c_dev->adapter.owner = THIS_MODULE;
 790         i2c_dev->adapter.class = I2C_CLASS_HWMON;
 791         strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
 792                 sizeof(i2c_dev->adapter.name));
 793         i2c_dev->adapter.algo = &tegra_i2c_algo;
 794         i2c_dev->adapter.dev.parent = &pdev->dev;
 795         i2c_dev->adapter.nr = pdev->id;
 796         i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
 797
 798         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
 799         if (ret) {
 800                 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
 801                 return ret;
 802         }
 803
 804         return 0;
 805 }
 806
 807 static int tegra_i2c_remove(struct platform_device *pdev)
 808 {
 809         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 810         i2c_del_adapter(&i2c_dev->adapter);
 811         return 0;
 812 }
 813
 814 #ifdef CONFIG_PM_SLEEP
 815 static int tegra_i2c_suspend(struct device *dev)
 816 {
 817         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 818
 819         i2c_lock_adapter(&i2c_dev->adapter);
 820         i2c_dev->is_suspended = true;
 821         i2c_unlock_adapter(&i2c_dev->adapter);
 822
 823         return 0;
 824 }
 825
 826 static int tegra_i2c_resume(struct device *dev)
 827 {
 828         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 829         int ret;
 830
 831         i2c_lock_adapter(&i2c_dev->adapter);
 832
 833         ret = tegra_i2c_init(i2c_dev);
 834
 835         if (ret) {
 836                 i2c_unlock_adapter(&i2c_dev->adapter);
 837                 return ret;
 838         }
 839
 840         i2c_dev->is_suspended = false;
 841
 842         i2c_unlock_adapter(&i2c_dev->adapter);
 843
 844         return 0;
 845 }
 846
 847 static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume);
 848 #define TEGRA_I2C_PM    (&tegra_i2c_pm)
 849 #else
 850 #define TEGRA_I2C_PM    NULL
 851 #endif
 852
 853 static struct platform_driver tegra_i2c_driver = {
 854         .probe   = tegra_i2c_probe,
 855         .remove  = tegra_i2c_remove,
 856         .driver  = {
 857                 .name  = "tegra-i2c",
 858                 .owner = THIS_MODULE,
 859                 .of_match_table = tegra_i2c_of_match,
 860                 .pm    = TEGRA_I2C_PM,
 861         },
 862 };
 863
 864 static int __init tegra_i2c_init_driver(void)
 865 {
 866         return platform_driver_register(&tegra_i2c_driver);
 867 }
 868
 869 static void __exit tegra_i2c_exit_driver(void)
 870 {
 871         platform_driver_unregister(&tegra_i2c_driver);
 872 }
 873
 874 subsys_initcall(tegra_i2c_init_driver);
 875 module_exit(tegra_i2c_exit_driver);
 876
 877 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
 878 MODULE_AUTHOR("Colin Cross");
 879 MODULE_LICENSE("GPL v2");