Pileus Git - ~andy/linux/blob - drivers/i2c/busses/i2c-tegra.c

   1 /*
   2  * drivers/i2c/busses/i2c-tegra.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Colin Cross <ccross@android.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/clk.h>
  22 #include <linux/err.h>
  23 #include <linux/i2c.h>
  24 #include <linux/io.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/slab.h>
  28 #include <linux/i2c-tegra.h>
  29 #include <linux/of_i2c.h>
  30 #include <linux/of_device.h>
  31 #include <linux/module.h>
  32 #include <linux/clk/tegra.h>
  33
  34 #include <asm/unaligned.h>
  35
  36 #define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
  37 #define BYTES_PER_FIFO_WORD 4
  38
  39 #define I2C_CNFG                                0x000
  40 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT             12
  41 #define I2C_CNFG_PACKET_MODE_EN                 (1<<10)
  42 #define I2C_CNFG_NEW_MASTER_FSM                 (1<<11)
  43 #define I2C_STATUS                              0x01C
  44 #define I2C_SL_CNFG                             0x020
  45 #define I2C_SL_CNFG_NACK                        (1<<1)
  46 #define I2C_SL_CNFG_NEWSL                       (1<<2)
  47 #define I2C_SL_ADDR1                            0x02c
  48 #define I2C_SL_ADDR2                            0x030
  49 #define I2C_TX_FIFO                             0x050
  50 #define I2C_RX_FIFO                             0x054
  51 #define I2C_PACKET_TRANSFER_STATUS              0x058
  52 #define I2C_FIFO_CONTROL                        0x05c
  53 #define I2C_FIFO_CONTROL_TX_FLUSH               (1<<1)
  54 #define I2C_FIFO_CONTROL_RX_FLUSH               (1<<0)
  55 #define I2C_FIFO_CONTROL_TX_TRIG_SHIFT          5
  56 #define I2C_FIFO_CONTROL_RX_TRIG_SHIFT          2
  57 #define I2C_FIFO_STATUS                         0x060
  58 #define I2C_FIFO_STATUS_TX_MASK                 0xF0
  59 #define I2C_FIFO_STATUS_TX_SHIFT                4
  60 #define I2C_FIFO_STATUS_RX_MASK                 0x0F
  61 #define I2C_FIFO_STATUS_RX_SHIFT                0
  62 #define I2C_INT_MASK                            0x064
  63 #define I2C_INT_STATUS                          0x068
  64 #define I2C_INT_PACKET_XFER_COMPLETE            (1<<7)
  65 #define I2C_INT_ALL_PACKETS_XFER_COMPLETE       (1<<6)
  66 #define I2C_INT_TX_FIFO_OVERFLOW                (1<<5)
  67 #define I2C_INT_RX_FIFO_UNDERFLOW               (1<<4)
  68 #define I2C_INT_NO_ACK                          (1<<3)
  69 #define I2C_INT_ARBITRATION_LOST                (1<<2)
  70 #define I2C_INT_TX_FIFO_DATA_REQ                (1<<1)
  71 #define I2C_INT_RX_FIFO_DATA_REQ                (1<<0)
  72 #define I2C_CLK_DIVISOR                         0x06c
  73 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT     16
  74 #define I2C_CLK_MULTIPLIER_STD_FAST_MODE        8
  75
  76 #define DVC_CTRL_REG1                           0x000
  77 #define DVC_CTRL_REG1_INTR_EN                   (1<<10)
  78 #define DVC_CTRL_REG2                           0x004
  79 #define DVC_CTRL_REG3                           0x008
  80 #define DVC_CTRL_REG3_SW_PROG                   (1<<26)
  81 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          (1<<30)
  82 #define DVC_STATUS                              0x00c
  83 #define DVC_STATUS_I2C_DONE_INTR                (1<<30)
  84
  85 #define I2C_ERR_NONE                            0x00
  86 #define I2C_ERR_NO_ACK                          0x01
  87 #define I2C_ERR_ARBITRATION_LOST                0x02
  88 #define I2C_ERR_UNKNOWN_INTERRUPT               0x04
  89
  90 #define PACKET_HEADER0_HEADER_SIZE_SHIFT        28
  91 #define PACKET_HEADER0_PACKET_ID_SHIFT          16
  92 #define PACKET_HEADER0_CONT_ID_SHIFT            12
  93 #define PACKET_HEADER0_PROTOCOL_I2C             (1<<4)
  94
  95 #define I2C_HEADER_HIGHSPEED_MODE               (1<<22)
  96 #define I2C_HEADER_CONT_ON_NAK                  (1<<21)
  97 #define I2C_HEADER_SEND_START_BYTE              (1<<20)
  98 #define I2C_HEADER_READ                         (1<<19)
  99 #define I2C_HEADER_10BIT_ADDR                   (1<<18)
 100 #define I2C_HEADER_IE_ENABLE                    (1<<17)
 101 #define I2C_HEADER_REPEAT_START                 (1<<16)
 102 #define I2C_HEADER_CONTINUE_XFER                (1<<15)
 103 #define I2C_HEADER_MASTER_ADDR_SHIFT            12
 104 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
 105 /*
 106  * msg_end_type: The bus control which need to be send at end of transfer.
 107  * @MSG_END_STOP: Send stop pulse at end of transfer.
 108  * @MSG_END_REPEAT_START: Send repeat start at end of transfer.
 109  * @MSG_END_CONTINUE: The following on message is coming and so do not send
 110  *              stop or repeat start.
 111  */
 112 enum msg_end_type {
 113         MSG_END_STOP,
 114         MSG_END_REPEAT_START,
 115         MSG_END_CONTINUE,
 116 };
 117
 118 /**
 119  * struct tegra_i2c_hw_feature : Different HW support on Tegra
 120  * @has_continue_xfer_support: Continue transfer supports.
 121  * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
 122  *              complete interrupt per packet basis.
 123  * @has_single_clk_source: The i2c controller has single clock source. Tegra30
 124  *              and earlier Socs has two clock sources i.e. div-clk and
 125  *              fast-clk.
 126  * @clk_divisor_hs_mode: Clock divisor in HS mode.
 127  * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
 128  *              applicable if there is no fast clock source i.e. single clock
 129  *              source.
 130  */
 131
 132 struct tegra_i2c_hw_feature {
 133         bool has_continue_xfer_support;
 134         bool has_per_pkt_xfer_complete_irq;
 135         bool has_single_clk_source;
 136         int clk_divisor_hs_mode;
 137         int clk_divisor_std_fast_mode;
 138 };
 139
 140 /**
 141  * struct tegra_i2c_dev - per device i2c context
 142  * @dev: device reference for power management
 143  * @hw: Tegra i2c hw feature.
 144  * @adapter: core i2c layer adapter information
 145  * @div_clk: clock reference for div clock of i2c controller.
 146  * @fast_clk: clock reference for fast clock of i2c controller.
 147  * @base: ioremapped registers cookie
 148  * @cont_id: i2c controller id, used for for packet header
 149  * @irq: irq number of transfer complete interrupt
 150  * @is_dvc: identifies the DVC i2c controller, has a different register layout
 151  * @msg_complete: transfer completion notifier
 152  * @msg_err: error code for completed message
 153  * @msg_buf: pointer to current message data
 154  * @msg_buf_remaining: size of unsent data in the message buffer
 155  * @msg_read: identifies read transfers
 156  * @bus_clk_rate: current i2c bus clock rate
 157  * @is_suspended: prevents i2c controller accesses after suspend is called
 158  */
 159 struct tegra_i2c_dev {
 160         struct device *dev;
 161         const struct tegra_i2c_hw_feature *hw;
 162         struct i2c_adapter adapter;
 163         struct clk *div_clk;
 164         struct clk *fast_clk;
 165         void __iomem *base;
 166         int cont_id;
 167         int irq;
 168         bool irq_disabled;
 169         int is_dvc;
 170         struct completion msg_complete;
 171         int msg_err;
 172         u8 *msg_buf;
 173         size_t msg_buf_remaining;
 174         int msg_read;
 175         unsigned long bus_clk_rate;
 176         bool is_suspended;
 177 };
 178
 179 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
 180 {
 181         writel(val, i2c_dev->base + reg);
 182 }
 183
 184 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 185 {
 186         return readl(i2c_dev->base + reg);
 187 }
 188
 189 /*
 190  * i2c_writel and i2c_readl will offset the register if necessary to talk
 191  * to the I2C block inside the DVC block
 192  */
 193 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev,
 194         unsigned long reg)
 195 {
 196         if (i2c_dev->is_dvc)
 197                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 198         return reg;
 199 }
 200
 201 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 202         unsigned long reg)
 203 {
 204         writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 205
 206         /* Read back register to make sure that register writes completed */
 207         if (reg != I2C_TX_FIFO)
 208                 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 209 }
 210
 211 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
 212 {
 213         return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 214 }
 215
 216 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 217         unsigned long reg, int len)
 218 {
 219         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 220 }
 221
 222 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 223         unsigned long reg, int len)
 224 {
 225         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 226 }
 227
 228 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 229 {
 230         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 231         int_mask &= ~mask;
 232         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 233 }
 234
 235 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 236 {
 237         u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
 238         int_mask |= mask;
 239         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 240 }
 241
 242 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 243 {
 244         unsigned long timeout = jiffies + HZ;
 245         u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
 246         val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
 247         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 248
 249         while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
 250                 (I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
 251                 if (time_after(jiffies, timeout)) {
 252                         dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
 253                         return -ETIMEDOUT;
 254                 }
 255                 msleep(1);
 256         }
 257         return 0;
 258 }
 259
 260 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 261 {
 262         u32 val;
 263         int rx_fifo_avail;
 264         u8 *buf = i2c_dev->msg_buf;
 265         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 266         int words_to_transfer;
 267
 268         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 269         rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
 270                 I2C_FIFO_STATUS_RX_SHIFT;
 271
 272         /* Rounds down to not include partial word at the end of buf */
 273         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 274         if (words_to_transfer > rx_fifo_avail)
 275                 words_to_transfer = rx_fifo_avail;
 276
 277         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 278
 279         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 280         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 281         rx_fifo_avail -= words_to_transfer;
 282
 283         /*
 284          * If there is a partial word at the end of buf, handle it manually to
 285          * prevent overwriting past the end of buf
 286          */
 287         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 288                 BUG_ON(buf_remaining > 3);
 289                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 290                 memcpy(buf, &val, buf_remaining);
 291                 buf_remaining = 0;
 292                 rx_fifo_avail--;
 293         }
 294
 295         BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
 296         i2c_dev->msg_buf_remaining = buf_remaining;
 297         i2c_dev->msg_buf = buf;
 298         return 0;
 299 }
 300
 301 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 302 {
 303         u32 val;
 304         int tx_fifo_avail;
 305         u8 *buf = i2c_dev->msg_buf;
 306         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 307         int words_to_transfer;
 308
 309         val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 310         tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
 311                 I2C_FIFO_STATUS_TX_SHIFT;
 312
 313         /* Rounds down to not include partial word at the end of buf */
 314         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 315
 316         /* It's very common to have < 4 bytes, so optimize that case. */
 317         if (words_to_transfer) {
 318                 if (words_to_transfer > tx_fifo_avail)
 319                         words_to_transfer = tx_fifo_avail;
 320
 321                 /*
 322                  * Update state before writing to FIFO.  If this casues us
 323                  * to finish writing all bytes (AKA buf_remaining goes to 0) we
 324                  * have a potential for an interrupt (PACKET_XFER_COMPLETE is
 325                  * not maskable).  We need to make sure that the isr sees
 326                  * buf_remaining as 0 and doesn't call us back re-entrantly.
 327                  */
 328                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 329                 tx_fifo_avail -= words_to_transfer;
 330                 i2c_dev->msg_buf_remaining = buf_remaining;
 331                 i2c_dev->msg_buf = buf +
 332                         words_to_transfer * BYTES_PER_FIFO_WORD;
 333                 barrier();
 334
 335                 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 336
 337                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 338         }
 339
 340         /*
 341          * If there is a partial word at the end of buf, handle it manually to
 342          * prevent reading past the end of buf, which could cross a page
 343          * boundary and fault.
 344          */
 345         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 346                 BUG_ON(buf_remaining > 3);
 347                 memcpy(&val, buf, buf_remaining);
 348
 349                 /* Again update before writing to FIFO to make sure isr sees. */
 350                 i2c_dev->msg_buf_remaining = 0;
 351                 i2c_dev->msg_buf = NULL;
 352                 barrier();
 353
 354                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 355         }
 356
 357         return 0;
 358 }
 359
 360 /*
 361  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 362  * block.  This block is identical to the rest of the I2C blocks, except that
 363  * it only supports master mode, it has registers moved around, and it needs
 364  * some extra init to get it into I2C mode.  The register moves are handled
 365  * by i2c_readl and i2c_writel
 366  */
 367 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 368 {
 369         u32 val = 0;
 370         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 371         val |= DVC_CTRL_REG3_SW_PROG;
 372         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 373         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 374
 375         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 376         val |= DVC_CTRL_REG1_INTR_EN;
 377         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 378 }
 379
 380 static inline int tegra_i2c_clock_enable(struct tegra_i2c_dev *i2c_dev)
 381 {
 382         int ret;
 383         if (!i2c_dev->hw->has_single_clk_source) {
 384                 ret = clk_prepare_enable(i2c_dev->fast_clk);
 385                 if (ret < 0) {
 386                         dev_err(i2c_dev->dev,
 387                                 "Enabling fast clk failed, err %d\n", ret);
 388                         return ret;
 389                 }
 390         }
 391         ret = clk_prepare_enable(i2c_dev->div_clk);
 392         if (ret < 0) {
 393                 dev_err(i2c_dev->dev,
 394                         "Enabling div clk failed, err %d\n", ret);
 395                 clk_disable_unprepare(i2c_dev->fast_clk);
 396         }
 397         return ret;
 398 }
 399
 400 static inline void tegra_i2c_clock_disable(struct tegra_i2c_dev *i2c_dev)
 401 {
 402         clk_disable_unprepare(i2c_dev->div_clk);
 403         if (!i2c_dev->hw->has_single_clk_source)
 404                 clk_disable_unprepare(i2c_dev->fast_clk);
 405 }
 406
 407 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 408 {
 409         u32 val;
 410         int err = 0;
 411         int clk_multiplier = I2C_CLK_MULTIPLIER_STD_FAST_MODE;
 412         u32 clk_divisor;
 413
 414         tegra_i2c_clock_enable(i2c_dev);
 415
 416         tegra_periph_reset_assert(i2c_dev->div_clk);
 417         udelay(2);
 418         tegra_periph_reset_deassert(i2c_dev->div_clk);
 419
 420         if (i2c_dev->is_dvc)
 421                 tegra_dvc_init(i2c_dev);
 422
 423         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 424                 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
 425         i2c_writel(i2c_dev, val, I2C_CNFG);
 426         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 427
 428         clk_multiplier *= (i2c_dev->hw->clk_divisor_std_fast_mode + 1);
 429         clk_set_rate(i2c_dev->div_clk, i2c_dev->bus_clk_rate * clk_multiplier);
 430
 431         /* Make sure clock divisor programmed correctly */
 432         clk_divisor = i2c_dev->hw->clk_divisor_hs_mode;
 433         clk_divisor |= i2c_dev->hw->clk_divisor_std_fast_mode <<
 434                                         I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
 435         i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
 436
 437         if (!i2c_dev->is_dvc) {
 438                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 439                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 440                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 441                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 442                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 443
 444         }
 445
 446         val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
 447                 0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
 448         i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
 449
 450         if (tegra_i2c_flush_fifos(i2c_dev))
 451                 err = -ETIMEDOUT;
 452
 453         tegra_i2c_clock_disable(i2c_dev);
 454
 455         if (i2c_dev->irq_disabled) {
 456                 i2c_dev->irq_disabled = 0;
 457                 enable_irq(i2c_dev->irq);
 458         }
 459
 460         return err;
 461 }
 462
 463 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 464 {
 465         u32 status;
 466         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 467         struct tegra_i2c_dev *i2c_dev = dev_id;
 468
 469         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 470
 471         if (status == 0) {
 472                 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
 473                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 474                          i2c_readl(i2c_dev, I2C_STATUS),
 475                          i2c_readl(i2c_dev, I2C_CNFG));
 476                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 477
 478                 if (!i2c_dev->irq_disabled) {
 479                         disable_irq_nosync(i2c_dev->irq);
 480                         i2c_dev->irq_disabled = 1;
 481                 }
 482                 goto err;
 483         }
 484
 485         if (unlikely(status & status_err)) {
 486                 if (status & I2C_INT_NO_ACK)
 487                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 488                 if (status & I2C_INT_ARBITRATION_LOST)
 489                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 490                 goto err;
 491         }
 492
 493         if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 494                 if (i2c_dev->msg_buf_remaining)
 495                         tegra_i2c_empty_rx_fifo(i2c_dev);
 496                 else
 497                         BUG();
 498         }
 499
 500         if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 501                 if (i2c_dev->msg_buf_remaining)
 502                         tegra_i2c_fill_tx_fifo(i2c_dev);
 503                 else
 504                         tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
 505         }
 506
 507         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 508         if (i2c_dev->is_dvc)
 509                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 510
 511         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 512                 BUG_ON(i2c_dev->msg_buf_remaining);
 513                 complete(&i2c_dev->msg_complete);
 514         }
 515         return IRQ_HANDLED;
 516 err:
 517         /* An error occurred, mask all interrupts */
 518         tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 519                 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 520                 I2C_INT_RX_FIFO_DATA_REQ);
 521         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 522         if (i2c_dev->is_dvc)
 523                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 524
 525         complete(&i2c_dev->msg_complete);
 526         return IRQ_HANDLED;
 527 }
 528
 529 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
 530         struct i2c_msg *msg, enum msg_end_type end_state)
 531 {
 532         u32 packet_header;
 533         u32 int_mask;
 534         int ret;
 535
 536         tegra_i2c_flush_fifos(i2c_dev);
 537
 538         if (msg->len == 0)
 539                 return -EINVAL;
 540
 541         i2c_dev->msg_buf = msg->buf;
 542         i2c_dev->msg_buf_remaining = msg->len;
 543         i2c_dev->msg_err = I2C_ERR_NONE;
 544         i2c_dev->msg_read = (msg->flags & I2C_M_RD);
 545         INIT_COMPLETION(i2c_dev->msg_complete);
 546
 547         packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 548                         PACKET_HEADER0_PROTOCOL_I2C |
 549                         (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 550                         (1 << PACKET_HEADER0_PACKET_ID_SHIFT);
 551         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 552
 553         packet_header = msg->len - 1;
 554         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 555
 556         packet_header = I2C_HEADER_IE_ENABLE;
 557         if (end_state == MSG_END_CONTINUE)
 558                 packet_header |= I2C_HEADER_CONTINUE_XFER;
 559         else if (end_state == MSG_END_REPEAT_START)
 560                 packet_header |= I2C_HEADER_REPEAT_START;
 561         if (msg->flags & I2C_M_TEN) {
 562                 packet_header |= msg->addr;
 563                 packet_header |= I2C_HEADER_10BIT_ADDR;
 564         } else {
 565                 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
 566         }
 567         if (msg->flags & I2C_M_IGNORE_NAK)
 568                 packet_header |= I2C_HEADER_CONT_ON_NAK;
 569         if (msg->flags & I2C_M_RD)
 570                 packet_header |= I2C_HEADER_READ;
 571         i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
 572
 573         if (!(msg->flags & I2C_M_RD))
 574                 tegra_i2c_fill_tx_fifo(i2c_dev);
 575
 576         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 577         if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
 578                 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
 579         if (msg->flags & I2C_M_RD)
 580                 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
 581         else if (i2c_dev->msg_buf_remaining)
 582                 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
 583         tegra_i2c_unmask_irq(i2c_dev, int_mask);
 584         dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n",
 585                 i2c_readl(i2c_dev, I2C_INT_MASK));
 586
 587         ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
 588         tegra_i2c_mask_irq(i2c_dev, int_mask);
 589
 590         if (ret == 0) {
 591                 dev_err(i2c_dev->dev, "i2c transfer timed out\n");
 592
 593                 tegra_i2c_init(i2c_dev);
 594                 return -ETIMEDOUT;
 595         }
 596
 597         dev_dbg(i2c_dev->dev, "transfer complete: %d %d %d\n",
 598                 ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
 599
 600         if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
 601                 return 0;
 602
 603         /*
 604          * NACK interrupt is generated before the I2C controller generates the
 605          * STOP condition on the bus. So wait for 2 clock periods before resetting
 606          * the controller so that STOP condition has been delivered properly.
 607          */
 608         if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
 609                 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
 610
 611         tegra_i2c_init(i2c_dev);
 612         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
 613                 if (msg->flags & I2C_M_IGNORE_NAK)
 614                         return 0;
 615                 return -EREMOTEIO;
 616         }
 617
 618         return -EIO;
 619 }
 620
 621 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 622         int num)
 623 {
 624         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 625         int i;
 626         int ret = 0;
 627
 628         if (i2c_dev->is_suspended)
 629                 return -EBUSY;
 630
 631         tegra_i2c_clock_enable(i2c_dev);
 632         for (i = 0; i < num; i++) {
 633                 enum msg_end_type end_type = MSG_END_STOP;
 634                 if (i < (num - 1)) {
 635                         if (msgs[i + 1].flags & I2C_M_NOSTART)
 636                                 end_type = MSG_END_CONTINUE;
 637                         else
 638                                 end_type = MSG_END_REPEAT_START;
 639                 }
 640                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
 641                 if (ret)
 642                         break;
 643         }
 644         tegra_i2c_clock_disable(i2c_dev);
 645         return ret ?: i;
 646 }
 647
 648 static u32 tegra_i2c_func(struct i2c_adapter *adap)
 649 {
 650         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
 651         u32 ret = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
 652                                 I2C_FUNC_PROTOCOL_MANGLING;
 653
 654         if (i2c_dev->hw->has_continue_xfer_support)
 655                 ret |= I2C_FUNC_NOSTART;
 656         return ret;
 657 }
 658
 659 static const struct i2c_algorithm tegra_i2c_algo = {
 660         .master_xfer    = tegra_i2c_xfer,
 661         .functionality  = tegra_i2c_func,
 662 };
 663
 664 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
 665         .has_continue_xfer_support = false,
 666         .has_per_pkt_xfer_complete_irq = false,
 667         .has_single_clk_source = false,
 668         .clk_divisor_hs_mode = 3,
 669         .clk_divisor_std_fast_mode = 0,
 670 };
 671
 672 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
 673         .has_continue_xfer_support = true,
 674         .has_per_pkt_xfer_complete_irq = false,
 675         .has_single_clk_source = false,
 676         .clk_divisor_hs_mode = 3,
 677         .clk_divisor_std_fast_mode = 0,
 678 };
 679
 680 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
 681         .has_continue_xfer_support = true,
 682         .has_per_pkt_xfer_complete_irq = true,
 683         .has_single_clk_source = true,
 684         .clk_divisor_hs_mode = 1,
 685         .clk_divisor_std_fast_mode = 0x19,
 686 };
 687
 688 #if defined(CONFIG_OF)
 689 /* Match table for of_platform binding */
 690 static const struct of_device_id tegra_i2c_of_match[] = {
 691         { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
 692         { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
 693         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
 694         { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
 695         {},
 696 };
 697 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
 698 #endif
 699
 700 static int tegra_i2c_probe(struct platform_device *pdev)
 701 {
 702         struct tegra_i2c_dev *i2c_dev;
 703         struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;
 704         struct resource *res;
 705         struct clk *div_clk;
 706         struct clk *fast_clk;
 707         const unsigned int *prop;
 708         void __iomem *base;
 709         int irq;
 710         int ret = 0;
 711
 712         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 713         if (!res) {
 714                 dev_err(&pdev->dev, "no mem resource\n");
 715                 return -EINVAL;
 716         }
 717
 718         base = devm_ioremap_resource(&pdev->dev, res);
 719         if (IS_ERR(base))
 720                 return PTR_ERR(base);
 721
 722         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 723         if (!res) {
 724                 dev_err(&pdev->dev, "no irq resource\n");
 725                 return -EINVAL;
 726         }
 727         irq = res->start;
 728
 729         div_clk = devm_clk_get(&pdev->dev, "div-clk");
 730         if (IS_ERR(div_clk)) {
 731                 dev_err(&pdev->dev, "missing controller clock");
 732                 return PTR_ERR(div_clk);
 733         }
 734
 735         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
 736         if (!i2c_dev) {
 737                 dev_err(&pdev->dev, "Could not allocate struct tegra_i2c_dev");
 738                 return -ENOMEM;
 739         }
 740
 741         i2c_dev->base = base;
 742         i2c_dev->div_clk = div_clk;
 743         i2c_dev->adapter.algo = &tegra_i2c_algo;
 744         i2c_dev->irq = irq;
 745         i2c_dev->cont_id = pdev->id;
 746         i2c_dev->dev = &pdev->dev;
 747
 748         i2c_dev->bus_clk_rate = 100000; /* default clock rate */
 749         if (pdata) {
 750                 i2c_dev->bus_clk_rate = pdata->bus_clk_rate;
 751
 752         } else if (i2c_dev->dev->of_node) {    /* if there is a device tree node ... */
 753                 prop = of_get_property(i2c_dev->dev->of_node,
 754                                 "clock-frequency", NULL);
 755                 if (prop)
 756                         i2c_dev->bus_clk_rate = be32_to_cpup(prop);
 757         }
 758
 759         i2c_dev->hw = &tegra20_i2c_hw;
 760
 761         if (pdev->dev.of_node) {
 762                 const struct of_device_id *match;
 763                 match = of_match_device(of_match_ptr(tegra_i2c_of_match),
 764                                                 &pdev->dev);
 765                 i2c_dev->hw = match->data;
 766                 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node,
 767                                                 "nvidia,tegra20-i2c-dvc");
 768         } else if (pdev->id == 3) {
 769                 i2c_dev->is_dvc = 1;
 770         }
 771         init_completion(&i2c_dev->msg_complete);
 772
 773         if (!i2c_dev->hw->has_single_clk_source) {
 774                 fast_clk = devm_clk_get(&pdev->dev, "fast-clk");
 775                 if (IS_ERR(fast_clk)) {
 776                         dev_err(&pdev->dev, "missing fast clock");
 777                         return PTR_ERR(fast_clk);
 778                 }
 779                 i2c_dev->fast_clk = fast_clk;
 780         }
 781
 782         platform_set_drvdata(pdev, i2c_dev);
 783
 784         ret = tegra_i2c_init(i2c_dev);
 785         if (ret) {
 786                 dev_err(&pdev->dev, "Failed to initialize i2c controller");
 787                 return ret;
 788         }
 789
 790         ret = devm_request_irq(&pdev->dev, i2c_dev->irq,
 791                         tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev);
 792         if (ret) {
 793                 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
 794                 return ret;
 795         }
 796
 797         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
 798         i2c_dev->adapter.owner = THIS_MODULE;
 799         i2c_dev->adapter.class = I2C_CLASS_HWMON;
 800         strlcpy(i2c_dev->adapter.name, "Tegra I2C adapter",
 801                 sizeof(i2c_dev->adapter.name));
 802         i2c_dev->adapter.algo = &tegra_i2c_algo;
 803         i2c_dev->adapter.dev.parent = &pdev->dev;
 804         i2c_dev->adapter.nr = pdev->id;
 805         i2c_dev->adapter.dev.of_node = pdev->dev.of_node;
 806
 807         ret = i2c_add_numbered_adapter(&i2c_dev->adapter);
 808         if (ret) {
 809                 dev_err(&pdev->dev, "Failed to add I2C adapter\n");
 810                 return ret;
 811         }
 812
 813         of_i2c_register_devices(&i2c_dev->adapter);
 814
 815         return 0;
 816 }
 817
 818 static int tegra_i2c_remove(struct platform_device *pdev)
 819 {
 820         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 821         i2c_del_adapter(&i2c_dev->adapter);
 822         return 0;
 823 }
 824
 825 #ifdef CONFIG_PM_SLEEP
 826 static int tegra_i2c_suspend(struct device *dev)
 827 {
 828         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 829
 830         i2c_lock_adapter(&i2c_dev->adapter);
 831         i2c_dev->is_suspended = true;
 832         i2c_unlock_adapter(&i2c_dev->adapter);
 833
 834         return 0;
 835 }
 836
 837 static int tegra_i2c_resume(struct device *dev)
 838 {
 839         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
 840         int ret;
 841
 842         i2c_lock_adapter(&i2c_dev->adapter);
 843
 844         ret = tegra_i2c_init(i2c_dev);
 845
 846         if (ret) {
 847                 i2c_unlock_adapter(&i2c_dev->adapter);
 848                 return ret;
 849         }
 850
 851         i2c_dev->is_suspended = false;
 852
 853         i2c_unlock_adapter(&i2c_dev->adapter);
 854
 855         return 0;
 856 }
 857
 858 static SIMPLE_DEV_PM_OPS(tegra_i2c_pm, tegra_i2c_suspend, tegra_i2c_resume);
 859 #define TEGRA_I2C_PM    (&tegra_i2c_pm)
 860 #else
 861 #define TEGRA_I2C_PM    NULL
 862 #endif
 863
 864 static struct platform_driver tegra_i2c_driver = {
 865         .probe   = tegra_i2c_probe,
 866         .remove  = tegra_i2c_remove,
 867         .driver  = {
 868                 .name  = "tegra-i2c",
 869                 .owner = THIS_MODULE,
 870                 .of_match_table = of_match_ptr(tegra_i2c_of_match),
 871                 .pm    = TEGRA_I2C_PM,
 872         },
 873 };
 874
 875 static int __init tegra_i2c_init_driver(void)
 876 {
 877         return platform_driver_register(&tegra_i2c_driver);
 878 }
 879
 880 static void __exit tegra_i2c_exit_driver(void)
 881 {
 882         platform_driver_unregister(&tegra_i2c_driver);
 883 }
 884
 885 subsys_initcall(tegra_i2c_init_driver);
 886 module_exit(tegra_i2c_exit_driver);
 887
 888 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");
 889 MODULE_AUTHOR("Colin Cross");
 890 MODULE_LICENSE("GPL v2");