2 * Provides I2C support for Philips PNX010x/PNX4008 boards.
4 * Authors: Dennis Kovalev <dkovalev@ru.mvista.com>
5 * Vitaly Wool <vwool@ru.mvista.com>
7 * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/ioport.h>
16 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/timer.h>
19 #include <linux/completion.h>
20 #include <linux/platform_device.h>
21 #include <linux/i2c-pnx.h>
23 #include <linux/err.h>
24 #include <linux/clk.h>
25 #include <linux/slab.h>
26 #include <linux/of_i2c.h>
28 #define I2C_PNX_TIMEOUT_DEFAULT 10 /* msec */
29 #define I2C_PNX_SPEED_KHZ_DEFAULT 100
30 #define I2C_PNX_REGION_SIZE 0x100
33 mstatus_tdi = 0x00000001,
34 mstatus_afi = 0x00000002,
35 mstatus_nai = 0x00000004,
36 mstatus_drmi = 0x00000008,
37 mstatus_active = 0x00000020,
38 mstatus_scl = 0x00000040,
39 mstatus_sda = 0x00000080,
40 mstatus_rff = 0x00000100,
41 mstatus_rfe = 0x00000200,
42 mstatus_tff = 0x00000400,
43 mstatus_tfe = 0x00000800,
47 mcntrl_tdie = 0x00000001,
48 mcntrl_afie = 0x00000002,
49 mcntrl_naie = 0x00000004,
50 mcntrl_drmie = 0x00000008,
51 mcntrl_drsie = 0x00000010,
52 mcntrl_rffie = 0x00000020,
53 mcntrl_daie = 0x00000040,
54 mcntrl_tffie = 0x00000080,
55 mcntrl_reset = 0x00000100,
56 mcntrl_cdbmode = 0x00000400,
65 #define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */
66 #define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */
67 #define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */
68 #define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */
69 #define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */
70 #define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */
71 #define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */
72 #define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */
73 #define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c) /* Tx FIFO level (RO) */
74 #define I2C_REG_RXB(a) ((a)->ioaddr + 0x20) /* Num of bytes Rx-ed (RO) */
75 #define I2C_REG_TXB(a) ((a)->ioaddr + 0x24) /* Num of bytes Tx-ed (RO) */
76 #define I2C_REG_TXS(a) ((a)->ioaddr + 0x28) /* Tx slave FIFO (RO) */
77 #define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c) /* Tx slave FIFO level (RO) */
79 static inline int wait_timeout(struct i2c_pnx_algo_data *data)
81 long timeout = data->timeout;
83 (ioread32(I2C_REG_STS(data)) & mstatus_active)) {
87 return (timeout <= 0);
90 static inline int wait_reset(struct i2c_pnx_algo_data *data)
92 long timeout = data->timeout;
94 (ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) {
98 return (timeout <= 0);
101 static inline void i2c_pnx_arm_timer(struct i2c_pnx_algo_data *alg_data)
103 struct timer_list *timer = &alg_data->mif.timer;
104 unsigned long expires = msecs_to_jiffies(alg_data->timeout);
109 del_timer_sync(timer);
111 dev_dbg(&alg_data->adapter.dev, "Timer armed at %lu plus %lu jiffies.\n",
114 timer->expires = jiffies + expires;
115 timer->data = (unsigned long)alg_data;
121 * i2c_pnx_start - start a device
122 * @slave_addr: slave address
123 * @adap: pointer to adapter structure
125 * Generate a START signal in the desired mode.
127 static int i2c_pnx_start(unsigned char slave_addr,
128 struct i2c_pnx_algo_data *alg_data)
130 dev_dbg(&alg_data->adapter.dev, "%s(): addr 0x%x mode %d\n", __func__,
131 slave_addr, alg_data->mif.mode);
133 /* Check for 7 bit slave addresses only */
134 if (slave_addr & ~0x7f) {
135 dev_err(&alg_data->adapter.dev,
136 "%s: Invalid slave address %x. Only 7-bit addresses are supported\n",
137 alg_data->adapter.name, slave_addr);
141 /* First, make sure bus is idle */
142 if (wait_timeout(alg_data)) {
143 /* Somebody else is monopolizing the bus */
144 dev_err(&alg_data->adapter.dev,
145 "%s: Bus busy. Slave addr = %02x, cntrl = %x, stat = %x\n",
146 alg_data->adapter.name, slave_addr,
147 ioread32(I2C_REG_CTL(alg_data)),
148 ioread32(I2C_REG_STS(alg_data)));
150 } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) {
151 /* Sorry, we lost the bus */
152 dev_err(&alg_data->adapter.dev,
153 "%s: Arbitration failure. Slave addr = %02x\n",
154 alg_data->adapter.name, slave_addr);
159 * OK, I2C is enabled and we have the bus.
160 * Clear the current TDI and AFI status flags.
162 iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi,
163 I2C_REG_STS(alg_data));
165 dev_dbg(&alg_data->adapter.dev, "%s(): sending %#x\n", __func__,
166 (slave_addr << 1) | start_bit | alg_data->mif.mode);
168 /* Write the slave address, START bit and R/W bit */
169 iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode,
170 I2C_REG_TX(alg_data));
172 dev_dbg(&alg_data->adapter.dev, "%s(): exit\n", __func__);
178 * i2c_pnx_stop - stop a device
179 * @adap: pointer to I2C adapter structure
181 * Generate a STOP signal to terminate the master transaction.
183 static void i2c_pnx_stop(struct i2c_pnx_algo_data *alg_data)
185 /* Only 1 msec max timeout due to interrupt context */
188 dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
189 __func__, ioread32(I2C_REG_STS(alg_data)));
191 /* Write a STOP bit to TX FIFO */
192 iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data));
194 /* Wait until the STOP is seen. */
195 while (timeout > 0 &&
196 (ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) {
197 /* may be called from interrupt context */
202 dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
203 __func__, ioread32(I2C_REG_STS(alg_data)));
207 * i2c_pnx_master_xmit - transmit data to slave
208 * @adap: pointer to I2C adapter structure
210 * Sends one byte of data to the slave
212 static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data)
216 dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
217 __func__, ioread32(I2C_REG_STS(alg_data)));
219 if (alg_data->mif.len > 0) {
220 /* We still have something to talk about... */
221 val = *alg_data->mif.buf++;
223 if (alg_data->mif.len == 1)
227 iowrite32(val, I2C_REG_TX(alg_data));
229 dev_dbg(&alg_data->adapter.dev, "%s(): xmit %#x [%d]\n",
230 __func__, val, alg_data->mif.len + 1);
232 if (alg_data->mif.len == 0) {
233 if (alg_data->last) {
234 /* Wait until the STOP is seen. */
235 if (wait_timeout(alg_data))
236 dev_err(&alg_data->adapter.dev,
237 "The bus is still active after timeout\n");
239 /* Disable master interrupts */
240 iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
241 ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
242 I2C_REG_CTL(alg_data));
244 del_timer_sync(&alg_data->mif.timer);
246 dev_dbg(&alg_data->adapter.dev,
247 "%s(): Waking up xfer routine.\n",
250 complete(&alg_data->mif.complete);
252 } else if (alg_data->mif.len == 0) {
253 /* zero-sized transfer */
254 i2c_pnx_stop(alg_data);
256 /* Disable master interrupts. */
257 iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
258 ~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
259 I2C_REG_CTL(alg_data));
262 del_timer_sync(&alg_data->mif.timer);
263 dev_dbg(&alg_data->adapter.dev,
264 "%s(): Waking up xfer routine after zero-xfer.\n",
267 complete(&alg_data->mif.complete);
270 dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
271 __func__, ioread32(I2C_REG_STS(alg_data)));
277 * i2c_pnx_master_rcv - receive data from slave
278 * @adap: pointer to I2C adapter structure
280 * Reads one byte data from the slave
282 static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data)
284 unsigned int val = 0;
287 dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
288 __func__, ioread32(I2C_REG_STS(alg_data)));
290 /* Check, whether there is already data,
291 * or we didn't 'ask' for it yet.
293 if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) {
294 dev_dbg(&alg_data->adapter.dev,
295 "%s(): Write dummy data to fill Rx-fifo...\n",
298 if (alg_data->mif.len == 1) {
299 /* Last byte, do not acknowledge next rcv. */
303 * Enable interrupt RFDAIE (data in Rx fifo),
304 * and disable DRMIE (need data for Tx)
306 ctl = ioread32(I2C_REG_CTL(alg_data));
307 ctl |= mcntrl_rffie | mcntrl_daie;
308 ctl &= ~mcntrl_drmie;
309 iowrite32(ctl, I2C_REG_CTL(alg_data));
313 * Now we'll 'ask' for data:
314 * For each byte we want to receive, we must
315 * write a (dummy) byte to the Tx-FIFO.
317 iowrite32(val, I2C_REG_TX(alg_data));
323 if (alg_data->mif.len > 0) {
324 val = ioread32(I2C_REG_RX(alg_data));
325 *alg_data->mif.buf++ = (u8) (val & 0xff);
326 dev_dbg(&alg_data->adapter.dev, "%s(): rcv 0x%x [%d]\n",
327 __func__, val, alg_data->mif.len);
330 if (alg_data->mif.len == 0) {
332 /* Wait until the STOP is seen. */
333 if (wait_timeout(alg_data))
334 dev_err(&alg_data->adapter.dev,
335 "The bus is still active after timeout\n");
337 /* Disable master interrupts */
338 ctl = ioread32(I2C_REG_CTL(alg_data));
339 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
340 mcntrl_drmie | mcntrl_daie);
341 iowrite32(ctl, I2C_REG_CTL(alg_data));
344 del_timer_sync(&alg_data->mif.timer);
345 complete(&alg_data->mif.complete);
349 dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
350 __func__, ioread32(I2C_REG_STS(alg_data)));
355 static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id)
357 struct i2c_pnx_algo_data *alg_data = dev_id;
360 dev_dbg(&alg_data->adapter.dev,
361 "%s(): mstat = %x mctrl = %x, mode = %d\n",
363 ioread32(I2C_REG_STS(alg_data)),
364 ioread32(I2C_REG_CTL(alg_data)),
366 stat = ioread32(I2C_REG_STS(alg_data));
368 /* let's see what kind of event this is */
369 if (stat & mstatus_afi) {
370 /* We lost arbitration in the midst of a transfer */
371 alg_data->mif.ret = -EIO;
373 /* Disable master interrupts. */
374 ctl = ioread32(I2C_REG_CTL(alg_data));
375 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
377 iowrite32(ctl, I2C_REG_CTL(alg_data));
379 /* Stop timer, to prevent timeout. */
380 del_timer_sync(&alg_data->mif.timer);
381 complete(&alg_data->mif.complete);
382 } else if (stat & mstatus_nai) {
383 /* Slave did not acknowledge, generate a STOP */
384 dev_dbg(&alg_data->adapter.dev,
385 "%s(): Slave did not acknowledge, generating a STOP.\n",
387 i2c_pnx_stop(alg_data);
389 /* Disable master interrupts. */
390 ctl = ioread32(I2C_REG_CTL(alg_data));
391 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
393 iowrite32(ctl, I2C_REG_CTL(alg_data));
395 /* Our return value. */
396 alg_data->mif.ret = -EIO;
398 /* Stop timer, to prevent timeout. */
399 del_timer_sync(&alg_data->mif.timer);
400 complete(&alg_data->mif.complete);
404 * - Master Tx needs data.
405 * - There is data in the Rx-fifo
406 * The latter is only the case if we have requested for data,
407 * via a dummy write. (See 'i2c_pnx_master_rcv'.)
408 * We therefore check, as a sanity check, whether that interrupt
411 if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) {
412 if (alg_data->mif.mode == I2C_SMBUS_WRITE) {
413 i2c_pnx_master_xmit(alg_data);
414 } else if (alg_data->mif.mode == I2C_SMBUS_READ) {
415 i2c_pnx_master_rcv(alg_data);
420 /* Clear TDI and AFI bits */
421 stat = ioread32(I2C_REG_STS(alg_data));
422 iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data));
424 dev_dbg(&alg_data->adapter.dev,
425 "%s(): exiting, stat = %x ctrl = %x.\n",
426 __func__, ioread32(I2C_REG_STS(alg_data)),
427 ioread32(I2C_REG_CTL(alg_data)));
432 static void i2c_pnx_timeout(unsigned long data)
434 struct i2c_pnx_algo_data *alg_data = (struct i2c_pnx_algo_data *)data;
437 dev_err(&alg_data->adapter.dev,
438 "Master timed out. stat = %04x, cntrl = %04x. Resetting master...\n",
439 ioread32(I2C_REG_STS(alg_data)),
440 ioread32(I2C_REG_CTL(alg_data)));
442 /* Reset master and disable interrupts */
443 ctl = ioread32(I2C_REG_CTL(alg_data));
444 ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie);
445 iowrite32(ctl, I2C_REG_CTL(alg_data));
448 iowrite32(ctl, I2C_REG_CTL(alg_data));
449 wait_reset(alg_data);
450 alg_data->mif.ret = -EIO;
451 complete(&alg_data->mif.complete);
454 static inline void bus_reset_if_active(struct i2c_pnx_algo_data *alg_data)
458 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) {
459 dev_err(&alg_data->adapter.dev,
460 "%s: Bus is still active after xfer. Reset it...\n",
461 alg_data->adapter.name);
462 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
463 I2C_REG_CTL(alg_data));
464 wait_reset(alg_data);
465 } else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) {
466 /* If there is data in the fifo's after transfer,
467 * flush fifo's by reset.
469 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
470 I2C_REG_CTL(alg_data));
471 wait_reset(alg_data);
472 } else if (stat & mstatus_nai) {
473 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
474 I2C_REG_CTL(alg_data));
475 wait_reset(alg_data);
480 * i2c_pnx_xfer - generic transfer entry point
481 * @adap: pointer to I2C adapter structure
482 * @msgs: array of messages
483 * @num: number of messages
485 * Initiates the transfer
488 i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
490 struct i2c_msg *pmsg;
491 int rc = 0, completed = 0, i;
492 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
493 u32 stat = ioread32(I2C_REG_STS(alg_data));
495 dev_dbg(&alg_data->adapter.dev,
496 "%s(): entering: %d messages, stat = %04x.\n",
497 __func__, num, ioread32(I2C_REG_STS(alg_data)));
499 bus_reset_if_active(alg_data);
501 /* Process transactions in a loop. */
502 for (i = 0; rc >= 0 && i < num; i++) {
508 if (pmsg->flags & I2C_M_TEN) {
509 dev_err(&alg_data->adapter.dev,
510 "%s: 10 bits addr not supported!\n",
511 alg_data->adapter.name);
516 alg_data->mif.buf = pmsg->buf;
517 alg_data->mif.len = pmsg->len;
518 alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ?
519 I2C_SMBUS_READ : I2C_SMBUS_WRITE;
520 alg_data->mif.ret = 0;
521 alg_data->last = (i == num - 1);
523 dev_dbg(&alg_data->adapter.dev, "%s(): mode %d, %d bytes\n",
524 __func__, alg_data->mif.mode, alg_data->mif.len);
526 i2c_pnx_arm_timer(alg_data);
528 /* initialize the completion var */
529 init_completion(&alg_data->mif.complete);
531 /* Enable master interrupt */
532 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie |
533 mcntrl_naie | mcntrl_drmie,
534 I2C_REG_CTL(alg_data));
536 /* Put start-code and slave-address on the bus. */
537 rc = i2c_pnx_start(addr, alg_data);
541 /* Wait for completion */
542 wait_for_completion(&alg_data->mif.complete);
544 if (!(rc = alg_data->mif.ret))
546 dev_dbg(&alg_data->adapter.dev,
547 "%s(): Complete, return code = %d.\n",
550 /* Clear TDI and AFI bits in case they are set. */
551 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) {
552 dev_dbg(&alg_data->adapter.dev,
553 "%s: TDI still set... clearing now.\n",
554 alg_data->adapter.name);
555 iowrite32(stat, I2C_REG_STS(alg_data));
557 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) {
558 dev_dbg(&alg_data->adapter.dev,
559 "%s: AFI still set... clearing now.\n",
560 alg_data->adapter.name);
561 iowrite32(stat, I2C_REG_STS(alg_data));
565 bus_reset_if_active(alg_data);
567 /* Cleanup to be sure... */
568 alg_data->mif.buf = NULL;
569 alg_data->mif.len = 0;
571 dev_dbg(&alg_data->adapter.dev, "%s(): exiting, stat = %x\n",
572 __func__, ioread32(I2C_REG_STS(alg_data)));
574 if (completed != num)
575 return ((rc < 0) ? rc : -EREMOTEIO);
580 static u32 i2c_pnx_func(struct i2c_adapter *adapter)
582 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
585 static struct i2c_algorithm pnx_algorithm = {
586 .master_xfer = i2c_pnx_xfer,
587 .functionality = i2c_pnx_func,
591 static int i2c_pnx_controller_suspend(struct device *dev)
593 struct i2c_pnx_algo_data *alg_data = dev_get_drvdata(dev);
595 clk_disable(alg_data->clk);
600 static int i2c_pnx_controller_resume(struct device *dev)
602 struct i2c_pnx_algo_data *alg_data = dev_get_drvdata(dev);
604 return clk_enable(alg_data->clk);
607 static SIMPLE_DEV_PM_OPS(i2c_pnx_pm,
608 i2c_pnx_controller_suspend, i2c_pnx_controller_resume);
609 #define PNX_I2C_PM (&i2c_pnx_pm)
611 #define PNX_I2C_PM NULL
614 static int __devinit i2c_pnx_probe(struct platform_device *pdev)
618 struct i2c_pnx_algo_data *alg_data;
620 struct resource *res;
621 u32 speed = I2C_PNX_SPEED_KHZ_DEFAULT * 1000;
623 alg_data = kzalloc(sizeof(*alg_data), GFP_KERNEL);
629 platform_set_drvdata(pdev, alg_data);
631 alg_data->adapter.dev.parent = &pdev->dev;
632 alg_data->adapter.algo = &pnx_algorithm;
633 alg_data->adapter.algo_data = alg_data;
634 alg_data->adapter.nr = pdev->id;
636 alg_data->timeout = I2C_PNX_TIMEOUT_DEFAULT;
638 alg_data->adapter.dev.of_node = of_node_get(pdev->dev.of_node);
639 if (pdev->dev.of_node) {
640 of_property_read_u32(pdev->dev.of_node, "clock-frequency",
643 * At this point, it is planned to add an OF timeout property.
644 * As soon as there is a consensus about how to call and handle
645 * this, sth. like the following can be put here:
647 * of_property_read_u32(pdev->dev.of_node, "timeout",
648 * &alg_data->timeout);
652 alg_data->clk = clk_get(&pdev->dev, NULL);
653 if (IS_ERR(alg_data->clk)) {
654 ret = PTR_ERR(alg_data->clk);
658 init_timer(&alg_data->mif.timer);
659 alg_data->mif.timer.function = i2c_pnx_timeout;
660 alg_data->mif.timer.data = (unsigned long)alg_data;
662 snprintf(alg_data->adapter.name, sizeof(alg_data->adapter.name),
665 /* Register I/O resource */
666 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
668 dev_err(&pdev->dev, "Unable to get mem resource.\n");
672 if (!request_mem_region(res->start, I2C_PNX_REGION_SIZE,
675 "I/O region 0x%08x for I2C already in use.\n",
681 alg_data->base = res->start;
682 alg_data->ioaddr = ioremap(res->start, I2C_PNX_REGION_SIZE);
683 if (!alg_data->ioaddr) {
684 dev_err(&pdev->dev, "Couldn't ioremap I2C I/O region\n");
689 ret = clk_enable(alg_data->clk);
693 freq = clk_get_rate(alg_data->clk);
696 * Clock Divisor High This value is the number of system clocks
697 * the serial clock (SCL) will be high.
698 * For example, if the system clock period is 50 ns and the maximum
699 * desired serial period is 10000 ns (100 kHz), then CLKHI would be
700 * set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value
701 * programmed into CLKHI will vary from this slightly due to
702 * variations in the output pad's rise and fall times as well as
703 * the deglitching filter length.
706 tmp = (freq / speed) / 2 - 2;
709 iowrite32(tmp, I2C_REG_CKH(alg_data));
710 iowrite32(tmp, I2C_REG_CKL(alg_data));
712 iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data));
713 if (wait_reset(alg_data)) {
717 init_completion(&alg_data->mif.complete);
719 alg_data->irq = platform_get_irq(pdev, 0);
720 if (alg_data->irq < 0) {
721 dev_err(&pdev->dev, "Failed to get IRQ from platform resource\n");
724 ret = request_irq(alg_data->irq, i2c_pnx_interrupt,
725 0, pdev->name, alg_data);
729 /* Register this adapter with the I2C subsystem */
730 ret = i2c_add_numbered_adapter(&alg_data->adapter);
732 dev_err(&pdev->dev, "I2C: Failed to add bus\n");
736 of_i2c_register_devices(&alg_data->adapter);
738 dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n",
739 alg_data->adapter.name, res->start, alg_data->irq);
744 free_irq(alg_data->irq, alg_data);
746 clk_disable(alg_data->clk);
748 iounmap(alg_data->ioaddr);
750 release_mem_region(res->start, I2C_PNX_REGION_SIZE);
752 clk_put(alg_data->clk);
756 platform_set_drvdata(pdev, NULL);
760 static int __devexit i2c_pnx_remove(struct platform_device *pdev)
762 struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
764 free_irq(alg_data->irq, alg_data);
765 i2c_del_adapter(&alg_data->adapter);
766 clk_disable(alg_data->clk);
767 iounmap(alg_data->ioaddr);
768 release_mem_region(alg_data->base, I2C_PNX_REGION_SIZE);
769 clk_put(alg_data->clk);
771 platform_set_drvdata(pdev, NULL);
777 static const struct of_device_id i2c_pnx_of_match[] = {
778 { .compatible = "nxp,pnx-i2c" },
781 MODULE_DEVICE_TABLE(of, i2c_pnx_of_match);
784 static struct platform_driver i2c_pnx_driver = {
787 .owner = THIS_MODULE,
788 .of_match_table = of_match_ptr(i2c_pnx_of_match),
791 .probe = i2c_pnx_probe,
792 .remove = __devexit_p(i2c_pnx_remove),
795 static int __init i2c_adap_pnx_init(void)
797 return platform_driver_register(&i2c_pnx_driver);
800 static void __exit i2c_adap_pnx_exit(void)
802 platform_driver_unregister(&i2c_pnx_driver);
805 MODULE_AUTHOR("Vitaly Wool, Dennis Kovalev <source@mvista.com>");
806 MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses");
807 MODULE_LICENSE("GPL");
808 MODULE_ALIAS("platform:pnx-i2c");
810 /* We need to make sure I2C is initialized before USB */
811 subsys_initcall(i2c_adap_pnx_init);
812 module_exit(i2c_adap_pnx_exit);