Pileus Git - ~andy/linux/blob - drivers/i2c/busses/i2c-octeon.c

   1 /*
   2  * (C) Copyright 2009-2010
   3  * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
   4  *
   5  * Portions Copyright (C) 2010, 2011 Cavium Networks, Inc.
   6  *
   7  * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/platform_device.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/delay.h>
  19 #include <linux/sched.h>
  20 #include <linux/slab.h>
  21 #include <linux/init.h>
  22 #include <linux/i2c.h>
  23 #include <linux/io.h>
  24 #include <linux/of.h>
  25
  26 #include <asm/octeon/octeon.h>
  27
  28 #define DRV_NAME "i2c-octeon"
  29
  30 /* The previous out-of-tree version was implicitly version 1.0. */
  31 #define DRV_VERSION     "2.0"
  32
  33 /* register offsets */
  34 #define SW_TWSI  0x00
  35 #define TWSI_INT 0x10
  36
  37 /* Controller command patterns */
  38 #define SW_TWSI_V               0x8000000000000000ull
  39 #define SW_TWSI_EOP_TWSI_DATA   0x0C00000100000000ull
  40 #define SW_TWSI_EOP_TWSI_CTL    0x0C00000200000000ull
  41 #define SW_TWSI_EOP_TWSI_CLKCTL 0x0C00000300000000ull
  42 #define SW_TWSI_EOP_TWSI_STAT   0x0C00000300000000ull
  43 #define SW_TWSI_EOP_TWSI_RST    0x0C00000700000000ull
  44 #define SW_TWSI_OP_TWSI_CLK     0x0800000000000000ull
  45 #define SW_TWSI_R               0x0100000000000000ull
  46
  47 /* Controller command and status bits */
  48 #define TWSI_CTL_CE   0x80
  49 #define TWSI_CTL_ENAB 0x40
  50 #define TWSI_CTL_STA  0x20
  51 #define TWSI_CTL_STP  0x10
  52 #define TWSI_CTL_IFLG 0x08
  53 #define TWSI_CTL_AAK  0x04
  54
  55 /* Some status values */
  56 #define STAT_START      0x08
  57 #define STAT_RSTART     0x10
  58 #define STAT_TXADDR_ACK 0x18
  59 #define STAT_TXDATA_ACK 0x28
  60 #define STAT_RXADDR_ACK 0x40
  61 #define STAT_RXDATA_ACK 0x50
  62 #define STAT_IDLE       0xF8
  63
  64 struct octeon_i2c {
  65         wait_queue_head_t queue;
  66         struct i2c_adapter adap;
  67         int irq;
  68         u32 twsi_freq;
  69         int sys_freq;
  70         resource_size_t twsi_phys;
  71         void __iomem *twsi_base;
  72         resource_size_t regsize;
  73         struct device *dev;
  74 };
  75
  76 /**
  77  * octeon_i2c_write_sw - write an I2C core register.
  78  * @i2c: The struct octeon_i2c.
  79  * @eop_reg: Register selector.
  80  * @data: Value to be written.
  81  *
  82  * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
  83  */
  84 static void octeon_i2c_write_sw(struct octeon_i2c *i2c,
  85                                 u64 eop_reg,
  86                                 u8 data)
  87 {
  88         u64 tmp;
  89
  90         __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
  91         do {
  92                 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
  93         } while ((tmp & SW_TWSI_V) != 0);
  94 }
  95
  96 /**
  97  * octeon_i2c_read_sw - write an I2C core register.
  98  * @i2c: The struct octeon_i2c.
  99  * @eop_reg: Register selector.
 100  *
 101  * Returns the data.
 102  *
 103  * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
 104  */
 105 static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)
 106 {
 107         u64 tmp;
 108
 109         __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
 110         do {
 111                 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
 112         } while ((tmp & SW_TWSI_V) != 0);
 113
 114         return tmp & 0xFF;
 115 }
 116
 117 /**
 118  * octeon_i2c_write_int - write the TWSI_INT register
 119  * @i2c: The struct octeon_i2c.
 120  * @data: Value to be written.
 121  */
 122 static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
 123 {
 124         __raw_writeq(data, i2c->twsi_base + TWSI_INT);
 125         __raw_readq(i2c->twsi_base + TWSI_INT);
 126 }
 127
 128 /**
 129  * octeon_i2c_int_enable - enable the TS interrupt.
 130  * @i2c: The struct octeon_i2c.
 131  *
 132  * The interrupt will be asserted when there is non-STAT_IDLE state in
 133  * the SW_TWSI_EOP_TWSI_STAT register.
 134  */
 135 static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
 136 {
 137         octeon_i2c_write_int(i2c, 0x40);
 138 }
 139
 140 /**
 141  * octeon_i2c_int_disable - disable the TS interrupt.
 142  * @i2c: The struct octeon_i2c.
 143  */
 144 static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
 145 {
 146         octeon_i2c_write_int(i2c, 0);
 147 }
 148
 149 /**
 150  * octeon_i2c_unblock - unblock the bus.
 151  * @i2c: The struct octeon_i2c.
 152  *
 153  * If there was a reset while a device was driving 0 to bus,
 154  * bus is blocked. We toggle it free manually by some clock
 155  * cycles and send a stop.
 156  */
 157 static void octeon_i2c_unblock(struct octeon_i2c *i2c)
 158 {
 159         int i;
 160
 161         dev_dbg(i2c->dev, "%s\n", __func__);
 162         for (i = 0; i < 9; i++) {
 163                 octeon_i2c_write_int(i2c, 0x0);
 164                 udelay(5);
 165                 octeon_i2c_write_int(i2c, 0x200);
 166                 udelay(5);
 167         }
 168         octeon_i2c_write_int(i2c, 0x300);
 169         udelay(5);
 170         octeon_i2c_write_int(i2c, 0x100);
 171         udelay(5);
 172         octeon_i2c_write_int(i2c, 0x0);
 173 }
 174
 175 /**
 176  * octeon_i2c_isr - the interrupt service routine.
 177  * @int: The irq, unused.
 178  * @dev_id: Our struct octeon_i2c.
 179  */
 180 static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
 181 {
 182         struct octeon_i2c *i2c = dev_id;
 183
 184         octeon_i2c_int_disable(i2c);
 185         wake_up(&i2c->queue);
 186
 187         return IRQ_HANDLED;
 188 }
 189
 190
 191 static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
 192 {
 193         return (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0;
 194 }
 195
 196 /**
 197  * octeon_i2c_wait - wait for the IFLG to be set.
 198  * @i2c: The struct octeon_i2c.
 199  *
 200  * Returns 0 on success, otherwise a negative errno.
 201  */
 202 static int octeon_i2c_wait(struct octeon_i2c *i2c)
 203 {
 204         int result;
 205
 206         octeon_i2c_int_enable(i2c);
 207
 208         result = wait_event_timeout(i2c->queue,
 209                                         octeon_i2c_test_iflg(i2c),
 210                                         i2c->adap.timeout);
 211
 212         octeon_i2c_int_disable(i2c);
 213
 214         if (result < 0) {
 215                 dev_dbg(i2c->dev, "%s: wait interrupted\n", __func__);
 216                 return result;
 217         } else if (result == 0) {
 218                 dev_dbg(i2c->dev, "%s: timeout\n", __func__);
 219                 return -ETIMEDOUT;
 220         }
 221
 222         return 0;
 223 }
 224
 225 /**
 226  * octeon_i2c_start - send START to the bus.
 227  * @i2c: The struct octeon_i2c.
 228  *
 229  * Returns 0 on success, otherwise a negative errno.
 230  */
 231 static int octeon_i2c_start(struct octeon_i2c *i2c)
 232 {
 233         u8 data;
 234         int result;
 235
 236         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 237                                 TWSI_CTL_ENAB | TWSI_CTL_STA);
 238
 239         result = octeon_i2c_wait(i2c);
 240         if (result) {
 241                 if (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) {
 242                         /*
 243                          * Controller refused to send start flag May
 244                          * be a client is holding SDA low - let's try
 245                          * to free it.
 246                          */
 247                         octeon_i2c_unblock(i2c);
 248                         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 249                                             TWSI_CTL_ENAB | TWSI_CTL_STA);
 250
 251                         result = octeon_i2c_wait(i2c);
 252                 }
 253                 if (result)
 254                         return result;
 255         }
 256
 257         data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
 258         if ((data != STAT_START) && (data != STAT_RSTART)) {
 259                 dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data);
 260                 return -EIO;
 261         }
 262
 263         return 0;
 264 }
 265
 266 /**
 267  * octeon_i2c_stop - send STOP to the bus.
 268  * @i2c: The struct octeon_i2c.
 269  *
 270  * Returns 0 on success, otherwise a negative errno.
 271  */
 272 static int octeon_i2c_stop(struct octeon_i2c *i2c)
 273 {
 274         u8 data;
 275
 276         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 277                             TWSI_CTL_ENAB | TWSI_CTL_STP);
 278
 279         data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
 280
 281         if (data != STAT_IDLE) {
 282                 dev_err(i2c->dev, "%s: bad status(0x%x)\n", __func__, data);
 283                 return -EIO;
 284         }
 285         return 0;
 286 }
 287
 288 /**
 289  * octeon_i2c_write - send data to the bus.
 290  * @i2c: The struct octeon_i2c.
 291  * @target: Target address.
 292  * @data: Pointer to the data to be sent.
 293  * @length: Length of the data.
 294  *
 295  * The address is sent over the bus, then the data.
 296  *
 297  * Returns 0 on success, otherwise a negative errno.
 298  */
 299 static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
 300                             const u8 *data, int length)
 301 {
 302         int i, result;
 303         u8 tmp;
 304
 305         result = octeon_i2c_start(i2c);
 306         if (result)
 307                 return result;
 308
 309         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);
 310         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
 311
 312         result = octeon_i2c_wait(i2c);
 313         if (result)
 314                 return result;
 315
 316         for (i = 0; i < length; i++) {
 317                 tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
 318                 if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {
 319                         dev_err(i2c->dev,
 320                                 "%s: bad status before write (0x%x)\n",
 321                                 __func__, tmp);
 322                         return -EIO;
 323                 }
 324
 325                 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
 326                 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
 327
 328                 result = octeon_i2c_wait(i2c);
 329                 if (result)
 330                         return result;
 331         }
 332
 333         return 0;
 334 }
 335
 336 /**
 337  * octeon_i2c_read - receive data from the bus.
 338  * @i2c: The struct octeon_i2c.
 339  * @target: Target address.
 340  * @data: Pointer to the location to store the datae .
 341  * @length: Length of the data.
 342  *
 343  * The address is sent over the bus, then the data is read.
 344  *
 345  * Returns 0 on success, otherwise a negative errno.
 346  */
 347 static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
 348                            u8 *data, int length)
 349 {
 350         int i, result;
 351         u8 tmp;
 352
 353         if (length < 1)
 354                 return -EINVAL;
 355
 356         result = octeon_i2c_start(i2c);
 357         if (result)
 358                 return result;
 359
 360         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target<<1) | 1);
 361         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
 362
 363         result = octeon_i2c_wait(i2c);
 364         if (result)
 365                 return result;
 366
 367         for (i = 0; i < length; i++) {
 368                 tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
 369                 if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {
 370                         dev_err(i2c->dev,
 371                                 "%s: bad status before read (0x%x)\n",
 372                                 __func__, tmp);
 373                         return -EIO;
 374                 }
 375
 376                 if (i+1 < length)
 377                         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 378                                                 TWSI_CTL_ENAB | TWSI_CTL_AAK);
 379                 else
 380                         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
 381                                                 TWSI_CTL_ENAB);
 382
 383                 result = octeon_i2c_wait(i2c);
 384                 if (result)
 385                         return result;
 386
 387                 data[i] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA);
 388         }
 389         return 0;
 390 }
 391
 392 /**
 393  * octeon_i2c_xfer - The driver's master_xfer function.
 394  * @adap: Pointer to the i2c_adapter structure.
 395  * @msgs: Pointer to the messages to be processed.
 396  * @num: Length of the MSGS array.
 397  *
 398  * Returns the number of messages processed, or a negative errno on
 399  * failure.
 400  */
 401 static int octeon_i2c_xfer(struct i2c_adapter *adap,
 402                            struct i2c_msg *msgs,
 403                            int num)
 404 {
 405         struct i2c_msg *pmsg;
 406         int i;
 407         int ret = 0;
 408         struct octeon_i2c *i2c = i2c_get_adapdata(adap);
 409
 410         for (i = 0; ret == 0 && i < num; i++) {
 411                 pmsg = &msgs[i];
 412                 dev_dbg(i2c->dev,
 413                         "Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",
 414                          pmsg->flags & I2C_M_RD ? "read" : "write",
 415                          pmsg->len, pmsg->addr, i + 1, num);
 416                 if (pmsg->flags & I2C_M_RD)
 417                         ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
 418                                                 pmsg->len);
 419                 else
 420                         ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
 421                                                 pmsg->len);
 422         }
 423         octeon_i2c_stop(i2c);
 424
 425         return (ret != 0) ? ret : num;
 426 }
 427
 428 static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
 429 {
 430         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 431 }
 432
 433 static const struct i2c_algorithm octeon_i2c_algo = {
 434         .master_xfer = octeon_i2c_xfer,
 435         .functionality = octeon_i2c_functionality,
 436 };
 437
 438 static struct i2c_adapter octeon_i2c_ops = {
 439         .owner = THIS_MODULE,
 440         .name = "OCTEON adapter",
 441         .algo = &octeon_i2c_algo,
 442         .timeout = HZ / 50,
 443 };
 444
 445 /**
 446  * octeon_i2c_setclock - Calculate and set clock divisors.
 447  */
 448 static int octeon_i2c_setclock(struct octeon_i2c *i2c)
 449 {
 450         int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
 451         int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
 452
 453         for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
 454                 /*
 455                  * An mdiv value of less than 2 seems to not work well
 456                  * with ds1337 RTCs, so we constrain it to larger
 457                  * values.
 458                  */
 459                 for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
 460                         /*
 461                          * For given ndiv and mdiv values check the
 462                          * two closest thp values.
 463                          */
 464                         tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
 465                         tclk *= (1 << ndiv_idx);
 466                         thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
 467                         for (inc = 0; inc <= 1; inc++) {
 468                                 thp_idx = thp_base + inc;
 469                                 if (thp_idx < 5 || thp_idx > 0xff)
 470                                         continue;
 471
 472                                 foscl = i2c->sys_freq / (2 * (thp_idx + 1));
 473                                 foscl = foscl / (1 << ndiv_idx);
 474                                 foscl = foscl / (mdiv_idx + 1) / 10;
 475                                 diff = abs(foscl - i2c->twsi_freq);
 476                                 if (diff < delta_hz) {
 477                                         delta_hz = diff;
 478                                         thp = thp_idx;
 479                                         mdiv = mdiv_idx;
 480                                         ndiv = ndiv_idx;
 481                                 }
 482                         }
 483                 }
 484         }
 485         octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp);
 486         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
 487
 488         return 0;
 489 }
 490
 491 static int octeon_i2c_initlowlevel(struct octeon_i2c *i2c)
 492 {
 493         u8 status;
 494         int tries;
 495
 496         /* disable high level controller, enable bus access */
 497         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
 498
 499         /* reset controller */
 500         octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0);
 501
 502         for (tries = 10; tries; tries--) {
 503                 udelay(1);
 504                 status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
 505                 if (status == STAT_IDLE)
 506                         return 0;
 507         }
 508         dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status);
 509         return -EIO;
 510 }
 511
 512 static int octeon_i2c_probe(struct platform_device *pdev)
 513 {
 514         int irq, result = 0;
 515         struct octeon_i2c *i2c;
 516         struct resource *res_mem;
 517
 518         /* All adaptors have an irq.  */
 519         irq = platform_get_irq(pdev, 0);
 520         if (irq < 0)
 521                 return irq;
 522
 523         i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
 524         if (!i2c) {
 525                 dev_err(&pdev->dev, "kzalloc failed\n");
 526                 result = -ENOMEM;
 527                 goto out;
 528         }
 529         i2c->dev = &pdev->dev;
 530
 531         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 532
 533         if (res_mem == NULL) {
 534                 dev_err(i2c->dev, "found no memory resource\n");
 535                 result = -ENXIO;
 536                 goto out;
 537         }
 538         i2c->twsi_phys = res_mem->start;
 539         i2c->regsize = resource_size(res_mem);
 540
 541         /*
 542          * "clock-rate" is a legacy binding, the official binding is
 543          * "clock-frequency".  Try the official one first and then
 544          * fall back if it doesn't exist.
 545          */
 546         if (of_property_read_u32(pdev->dev.of_node,
 547                                  "clock-frequency", &i2c->twsi_freq) &&
 548             of_property_read_u32(pdev->dev.of_node,
 549                                  "clock-rate", &i2c->twsi_freq)) {
 550                 dev_err(i2c->dev,
 551                         "no I2C 'clock-rate' or 'clock-frequency' property\n");
 552                 result = -ENXIO;
 553                 goto out;
 554         }
 555
 556         i2c->sys_freq = octeon_get_io_clock_rate();
 557
 558         if (!devm_request_mem_region(&pdev->dev, i2c->twsi_phys, i2c->regsize,
 559                                       res_mem->name)) {
 560                 dev_err(i2c->dev, "request_mem_region failed\n");
 561                 goto out;
 562         }
 563         i2c->twsi_base = devm_ioremap(&pdev->dev, i2c->twsi_phys, i2c->regsize);
 564
 565         init_waitqueue_head(&i2c->queue);
 566
 567         i2c->irq = irq;
 568
 569         result = devm_request_irq(&pdev->dev, i2c->irq,
 570                                   octeon_i2c_isr, 0, DRV_NAME, i2c);
 571         if (result < 0) {
 572                 dev_err(i2c->dev, "failed to attach interrupt\n");
 573                 goto out;
 574         }
 575
 576         result = octeon_i2c_initlowlevel(i2c);
 577         if (result) {
 578                 dev_err(i2c->dev, "init low level failed\n");
 579                 goto  out;
 580         }
 581
 582         result = octeon_i2c_setclock(i2c);
 583         if (result) {
 584                 dev_err(i2c->dev, "clock init failed\n");
 585                 goto  out;
 586         }
 587
 588         i2c->adap = octeon_i2c_ops;
 589         i2c->adap.dev.parent = &pdev->dev;
 590         i2c->adap.dev.of_node = pdev->dev.of_node;
 591         i2c_set_adapdata(&i2c->adap, i2c);
 592         platform_set_drvdata(pdev, i2c);
 593
 594         result = i2c_add_adapter(&i2c->adap);
 595         if (result < 0) {
 596                 dev_err(i2c->dev, "failed to add adapter\n");
 597                 goto out;
 598         }
 599         dev_info(i2c->dev, "version %s\n", DRV_VERSION);
 600
 601         return 0;
 602
 603 out:
 604         return result;
 605 };
 606
 607 static int octeon_i2c_remove(struct platform_device *pdev)
 608 {
 609         struct octeon_i2c *i2c = platform_get_drvdata(pdev);
 610
 611         i2c_del_adapter(&i2c->adap);
 612         return 0;
 613 };
 614
 615 static struct of_device_id octeon_i2c_match[] = {
 616         {
 617                 .compatible = "cavium,octeon-3860-twsi",
 618         },
 619         {},
 620 };
 621 MODULE_DEVICE_TABLE(of, octeon_i2c_match);
 622
 623 static struct platform_driver octeon_i2c_driver = {
 624         .probe          = octeon_i2c_probe,
 625         .remove         = octeon_i2c_remove,
 626         .driver         = {
 627                 .owner  = THIS_MODULE,
 628                 .name   = DRV_NAME,
 629                 .of_match_table = octeon_i2c_match,
 630         },
 631 };
 632
 633 module_platform_driver(octeon_i2c_driver);
 634
 635 MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
 636 MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
 637 MODULE_LICENSE("GPL");
 638 MODULE_VERSION(DRV_VERSION);