Pileus Git - ~andy/linux/blob - drivers/i2c/busses/i2c-mxs.c

   1 /*
   2  * Freescale MXS I2C bus driver
   3  *
   4  * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
   5  *
   6  * based on a (non-working) driver which was:
   7  *
   8  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   9  *
  10  * TODO: add dma-support if platform-support for it is available
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  */
  18
  19 #include <linux/slab.h>
  20 #include <linux/device.h>
  21 #include <linux/module.h>
  22 #include <linux/i2c.h>
  23 #include <linux/err.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/completion.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/jiffies.h>
  28 #include <linux/io.h>
  29 #include <linux/pinctrl/consumer.h>
  30 #include <linux/stmp_device.h>
  31
  32 #define DRIVER_NAME "mxs-i2c"
  33
  34 #define MXS_I2C_CTRL0           (0x00)
  35 #define MXS_I2C_CTRL0_SET       (0x04)
  36
  37 #define MXS_I2C_CTRL0_SFTRST                    0x80000000
  38 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST          0x02000000
  39 #define MXS_I2C_CTRL0_RETAIN_CLOCK              0x00200000
  40 #define MXS_I2C_CTRL0_POST_SEND_STOP            0x00100000
  41 #define MXS_I2C_CTRL0_PRE_SEND_START            0x00080000
  42 #define MXS_I2C_CTRL0_MASTER_MODE               0x00020000
  43 #define MXS_I2C_CTRL0_DIRECTION                 0x00010000
  44 #define MXS_I2C_CTRL0_XFER_COUNT(v)             ((v) & 0x0000FFFF)
  45
  46 #define MXS_I2C_CTRL1           (0x40)
  47 #define MXS_I2C_CTRL1_SET       (0x44)
  48 #define MXS_I2C_CTRL1_CLR       (0x48)
  49
  50 #define MXS_I2C_CTRL1_BUS_FREE_IRQ              0x80
  51 #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ     0x40
  52 #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ          0x20
  53 #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ    0x10
  54 #define MXS_I2C_CTRL1_EARLY_TERM_IRQ            0x08
  55 #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ           0x04
  56 #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ            0x02
  57 #define MXS_I2C_CTRL1_SLAVE_IRQ                 0x01
  58
  59 #define MXS_I2C_IRQ_MASK        (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
  60                                  MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
  61                                  MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
  62                                  MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
  63                                  MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
  64                                  MXS_I2C_CTRL1_SLAVE_IRQ)
  65
  66 #define MXS_I2C_QUEUECTRL       (0x60)
  67 #define MXS_I2C_QUEUECTRL_SET   (0x64)
  68 #define MXS_I2C_QUEUECTRL_CLR   (0x68)
  69
  70 #define MXS_I2C_QUEUECTRL_QUEUE_RUN             0x20
  71 #define MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE        0x04
  72
  73 #define MXS_I2C_QUEUESTAT       (0x70)
  74 #define MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY        0x00002000
  75 #define MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK  0x0000001F
  76
  77 #define MXS_I2C_QUEUECMD        (0x80)
  78
  79 #define MXS_I2C_QUEUEDATA       (0x90)
  80
  81 #define MXS_I2C_DATA            (0xa0)
  82
  83
  84 #define MXS_CMD_I2C_SELECT      (MXS_I2C_CTRL0_RETAIN_CLOCK |   \
  85                                  MXS_I2C_CTRL0_PRE_SEND_START | \
  86                                  MXS_I2C_CTRL0_MASTER_MODE |    \
  87                                  MXS_I2C_CTRL0_DIRECTION |      \
  88                                  MXS_I2C_CTRL0_XFER_COUNT(1))
  89
  90 #define MXS_CMD_I2C_WRITE       (MXS_I2C_CTRL0_PRE_SEND_START | \
  91                                  MXS_I2C_CTRL0_MASTER_MODE |    \
  92                                  MXS_I2C_CTRL0_DIRECTION)
  93
  94 #define MXS_CMD_I2C_READ        (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
  95                                  MXS_I2C_CTRL0_MASTER_MODE)
  96
  97 /**
  98  * struct mxs_i2c_dev - per device, private MXS-I2C data
  99  *
 100  * @dev: driver model device node
 101  * @regs: IO registers pointer
 102  * @cmd_complete: completion object for transaction wait
 103  * @cmd_err: error code for last transaction
 104  * @adapter: i2c subsystem adapter node
 105  */
 106 struct mxs_i2c_dev {
 107         struct device *dev;
 108         void __iomem *regs;
 109         struct completion cmd_complete;
 110         u32 cmd_err;
 111         struct i2c_adapter adapter;
 112 };
 113
 114 static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
 115 {
 116         stmp_reset_block(i2c->regs);
 117         writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
 118         writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE,
 119                         i2c->regs + MXS_I2C_QUEUECTRL_SET);
 120 }
 121
 122 static void mxs_i2c_pioq_setup_read(struct mxs_i2c_dev *i2c, u8 addr, int len,
 123                                         int flags)
 124 {
 125         u32 data;
 126
 127         writel(MXS_CMD_I2C_SELECT, i2c->regs + MXS_I2C_QUEUECMD);
 128
 129         data = (addr << 1) | I2C_SMBUS_READ;
 130         writel(data, i2c->regs + MXS_I2C_DATA);
 131
 132         data = MXS_CMD_I2C_READ | MXS_I2C_CTRL0_XFER_COUNT(len) | flags;
 133         writel(data, i2c->regs + MXS_I2C_QUEUECMD);
 134 }
 135
 136 static void mxs_i2c_pioq_setup_write(struct mxs_i2c_dev *i2c,
 137                                     u8 addr, u8 *buf, int len, int flags)
 138 {
 139         u32 data;
 140         int i, shifts_left;
 141
 142         data = MXS_CMD_I2C_WRITE | MXS_I2C_CTRL0_XFER_COUNT(len + 1) | flags;
 143         writel(data, i2c->regs + MXS_I2C_QUEUECMD);
 144
 145         /*
 146          * We have to copy the slave address (u8) and buffer (arbitrary number
 147          * of u8) into the data register (u32). To achieve that, the u8 are put
 148          * into the MSBs of 'data' which is then shifted for the next u8. When
 149          * appropriate, 'data' is written to MXS_I2C_DATA. So, the first u32
 150          * looks like this:
 151          *
 152          *  3          2          1          0
 153          * 10987654|32109876|54321098|76543210
 154          * --------+--------+--------+--------
 155          * buffer+2|buffer+1|buffer+0|slave_addr
 156          */
 157
 158         data = ((addr << 1) | I2C_SMBUS_WRITE) << 24;
 159
 160         for (i = 0; i < len; i++) {
 161                 data >>= 8;
 162                 data |= buf[i] << 24;
 163                 if ((i & 3) == 2)
 164                         writel(data, i2c->regs + MXS_I2C_DATA);
 165         }
 166
 167         /* Write out the remaining bytes if any */
 168         shifts_left = 24 - (i & 3) * 8;
 169         if (shifts_left)
 170                 writel(data >> shifts_left, i2c->regs + MXS_I2C_DATA);
 171 }
 172
 173 /*
 174  * TODO: should be replaceable with a waitqueue and RD_QUEUE_IRQ (setting the
 175  * rd_threshold to 1). Couldn't get this to work, though.
 176  */
 177 static int mxs_i2c_wait_for_data(struct mxs_i2c_dev *i2c)
 178 {
 179         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
 180
 181         while (readl(i2c->regs + MXS_I2C_QUEUESTAT)
 182                         & MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY) {
 183                         if (time_after(jiffies, timeout))
 184                                 return -ETIMEDOUT;
 185                         cond_resched();
 186         }
 187
 188         return 0;
 189 }
 190
 191 static int mxs_i2c_finish_read(struct mxs_i2c_dev *i2c, u8 *buf, int len)
 192 {
 193         u32 data;
 194         int i;
 195
 196         for (i = 0; i < len; i++) {
 197                 if ((i & 3) == 0) {
 198                         if (mxs_i2c_wait_for_data(i2c))
 199                                 return -ETIMEDOUT;
 200                         data = readl(i2c->regs + MXS_I2C_QUEUEDATA);
 201                 }
 202                 buf[i] = data & 0xff;
 203                 data >>= 8;
 204         }
 205
 206         return 0;
 207 }
 208
 209 /*
 210  * Low level master read/write transaction.
 211  */
 212 static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
 213                                 int stop)
 214 {
 215         struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
 216         int ret;
 217         int flags;
 218
 219         dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 220                 msg->addr, msg->len, msg->flags, stop);
 221
 222         if (msg->len == 0)
 223                 return -EINVAL;
 224
 225         init_completion(&i2c->cmd_complete);
 226         i2c->cmd_err = 0;
 227
 228         flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
 229
 230         if (msg->flags & I2C_M_RD)
 231                 mxs_i2c_pioq_setup_read(i2c, msg->addr, msg->len, flags);
 232         else
 233                 mxs_i2c_pioq_setup_write(i2c, msg->addr, msg->buf, msg->len,
 234                                         flags);
 235
 236         writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
 237                         i2c->regs + MXS_I2C_QUEUECTRL_SET);
 238
 239         ret = wait_for_completion_timeout(&i2c->cmd_complete,
 240                                                 msecs_to_jiffies(1000));
 241         if (ret == 0)
 242                 goto timeout;
 243
 244         if ((!i2c->cmd_err) && (msg->flags & I2C_M_RD)) {
 245                 ret = mxs_i2c_finish_read(i2c, msg->buf, msg->len);
 246                 if (ret)
 247                         goto timeout;
 248         }
 249
 250         if (i2c->cmd_err == -ENXIO)
 251                 mxs_i2c_reset(i2c);
 252         else
 253                 writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
 254                                 i2c->regs + MXS_I2C_QUEUECTRL_CLR);
 255
 256         dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err);
 257
 258         return i2c->cmd_err;
 259
 260 timeout:
 261         dev_dbg(i2c->dev, "Timeout!\n");
 262         mxs_i2c_reset(i2c);
 263         return -ETIMEDOUT;
 264 }
 265
 266 static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 267                         int num)
 268 {
 269         int i;
 270         int err;
 271
 272         for (i = 0; i < num; i++) {
 273                 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
 274                 if (err)
 275                         return err;
 276         }
 277
 278         return num;
 279 }
 280
 281 static u32 mxs_i2c_func(struct i2c_adapter *adap)
 282 {
 283         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 284 }
 285
 286 static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
 287 {
 288         struct mxs_i2c_dev *i2c = dev_id;
 289         u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
 290         bool is_last_cmd;
 291
 292         if (!stat)
 293                 return IRQ_NONE;
 294
 295         if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
 296                 i2c->cmd_err = -ENXIO;
 297         else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
 298                     MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
 299                     MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
 300                 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
 301                 i2c->cmd_err = -EIO;
 302
 303         is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) &
 304                 MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0;
 305
 306         if (is_last_cmd || i2c->cmd_err)
 307                 complete(&i2c->cmd_complete);
 308
 309         writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
 310
 311         return IRQ_HANDLED;
 312 }
 313
 314 static const struct i2c_algorithm mxs_i2c_algo = {
 315         .master_xfer = mxs_i2c_xfer,
 316         .functionality = mxs_i2c_func,
 317 };
 318
 319 static int __devinit mxs_i2c_probe(struct platform_device *pdev)
 320 {
 321         struct device *dev = &pdev->dev;
 322         struct mxs_i2c_dev *i2c;
 323         struct i2c_adapter *adap;
 324         struct pinctrl *pinctrl;
 325         struct resource *res;
 326         resource_size_t res_size;
 327         int err, irq;
 328
 329         pinctrl = devm_pinctrl_get_select_default(dev);
 330         if (IS_ERR(pinctrl))
 331                 return PTR_ERR(pinctrl);
 332
 333         i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
 334         if (!i2c)
 335                 return -ENOMEM;
 336
 337         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 338         if (!res)
 339                 return -ENOENT;
 340
 341         res_size = resource_size(res);
 342         if (!devm_request_mem_region(dev, res->start, res_size, res->name))
 343                 return -EBUSY;
 344
 345         i2c->regs = devm_ioremap_nocache(dev, res->start, res_size);
 346         if (!i2c->regs)
 347                 return -EBUSY;
 348
 349         irq = platform_get_irq(pdev, 0);
 350         if (irq < 0)
 351                 return irq;
 352
 353         err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
 354         if (err)
 355                 return err;
 356
 357         i2c->dev = dev;
 358         platform_set_drvdata(pdev, i2c);
 359
 360         /* Do reset to enforce correct startup after pinmuxing */
 361         mxs_i2c_reset(i2c);
 362
 363         adap = &i2c->adapter;
 364         strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
 365         adap->owner = THIS_MODULE;
 366         adap->algo = &mxs_i2c_algo;
 367         adap->dev.parent = dev;
 368         adap->nr = pdev->id;
 369         i2c_set_adapdata(adap, i2c);
 370         err = i2c_add_numbered_adapter(adap);
 371         if (err) {
 372                 dev_err(dev, "Failed to add adapter (%d)\n", err);
 373                 writel(MXS_I2C_CTRL0_SFTRST,
 374                                 i2c->regs + MXS_I2C_CTRL0_SET);
 375                 return err;
 376         }
 377
 378         return 0;
 379 }
 380
 381 static int __devexit mxs_i2c_remove(struct platform_device *pdev)
 382 {
 383         struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
 384         int ret;
 385
 386         ret = i2c_del_adapter(&i2c->adapter);
 387         if (ret)
 388                 return -EBUSY;
 389
 390         writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
 391
 392         platform_set_drvdata(pdev, NULL);
 393
 394         return 0;
 395 }
 396
 397 static struct platform_driver mxs_i2c_driver = {
 398         .driver = {
 399                    .name = DRIVER_NAME,
 400                    .owner = THIS_MODULE,
 401                    },
 402         .remove = __devexit_p(mxs_i2c_remove),
 403 };
 404
 405 static int __init mxs_i2c_init(void)
 406 {
 407         return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe);
 408 }
 409 subsys_initcall(mxs_i2c_init);
 410
 411 static void __exit mxs_i2c_exit(void)
 412 {
 413         platform_driver_unregister(&mxs_i2c_driver);
 414 }
 415 module_exit(mxs_i2c_exit);
 416
 417 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
 418 MODULE_DESCRIPTION("MXS I2C Bus Driver");
 419 MODULE_LICENSE("GPL");
 420 MODULE_ALIAS("platform:" DRIVER_NAME);