2 * Driver for the i2c controller on the Marvell line of host bridges
3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
5 * Author: Mark A. Greer <mgreer@mvista.com>
7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/mv643xx_i2c.h>
19 #include <linux/platform_device.h>
22 #include <linux/of_device.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_i2c.h>
25 #include <linux/clk.h>
26 #include <linux/err.h>
28 #define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1)
29 #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7)
30 #define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3)
32 #define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004
33 #define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008
34 #define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010
35 #define MV64XXX_I2C_REG_CONTROL_START 0x00000020
36 #define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040
37 #define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080
39 /* Ctlr status values */
40 #define MV64XXX_I2C_STATUS_BUS_ERR 0x00
41 #define MV64XXX_I2C_STATUS_MAST_START 0x08
42 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
43 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
44 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
45 #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
46 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
47 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
48 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
49 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
50 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
51 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
52 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
53 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
54 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
55 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
56 #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
60 MV64XXX_I2C_STATE_INVALID,
61 MV64XXX_I2C_STATE_IDLE,
62 MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
63 MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
64 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
65 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
66 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
67 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
72 MV64XXX_I2C_ACTION_INVALID,
73 MV64XXX_I2C_ACTION_CONTINUE,
74 MV64XXX_I2C_ACTION_SEND_START,
75 MV64XXX_I2C_ACTION_SEND_RESTART,
76 MV64XXX_I2C_ACTION_SEND_ADDR_1,
77 MV64XXX_I2C_ACTION_SEND_ADDR_2,
78 MV64XXX_I2C_ACTION_SEND_DATA,
79 MV64XXX_I2C_ACTION_RCV_DATA,
80 MV64XXX_I2C_ACTION_RCV_DATA_STOP,
81 MV64XXX_I2C_ACTION_SEND_STOP,
84 struct mv64xxx_i2c_regs {
94 struct mv64xxx_i2c_data {
102 void __iomem *reg_base;
103 struct mv64xxx_i2c_regs reg_offsets;
113 #if defined(CONFIG_HAVE_CLK)
116 wait_queue_head_t waitq;
119 struct i2c_adapter adapter;
122 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
132 static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
143 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
149 drv_data->byte_posn = 0;
150 drv_data->bytes_left = msg->len;
151 drv_data->aborting = 0;
153 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
154 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
156 if (msg->flags & I2C_M_RD)
159 if (msg->flags & I2C_M_TEN) {
160 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
161 drv_data->addr2 = (u32)msg->addr & 0xff;
163 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
169 *****************************************************************************
171 * Finite State Machine & Interrupt Routines
173 *****************************************************************************
176 /* Reset hardware and initialize FSM */
178 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
180 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
181 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
182 drv_data->reg_base + drv_data->reg_offsets.clock);
183 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
184 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
185 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
186 drv_data->reg_base + drv_data->reg_offsets.control);
187 drv_data->state = MV64XXX_I2C_STATE_IDLE;
191 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
194 * If state is idle, then this is likely the remnants of an old
195 * operation that driver has given up on or the user has killed.
196 * If so, issue the stop condition and go to idle.
198 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
199 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
203 /* The status from the ctlr [mostly] tells us what to do next */
205 /* Start condition interrupt */
206 case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
207 case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
208 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
209 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
212 /* Performing a write */
213 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
214 if (drv_data->msg->flags & I2C_M_TEN) {
215 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
217 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
221 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
222 case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
223 if ((drv_data->bytes_left == 0)
224 || (drv_data->aborting
225 && (drv_data->byte_posn != 0))) {
226 if (drv_data->send_stop || drv_data->aborting) {
227 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
228 drv_data->state = MV64XXX_I2C_STATE_IDLE;
231 MV64XXX_I2C_ACTION_SEND_RESTART;
233 MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
236 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
238 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
239 drv_data->bytes_left--;
243 /* Performing a read */
244 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
245 if (drv_data->msg->flags & I2C_M_TEN) {
246 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
248 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
252 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
253 if (drv_data->bytes_left == 0) {
254 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
255 drv_data->state = MV64XXX_I2C_STATE_IDLE;
259 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
260 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
261 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
263 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
264 drv_data->bytes_left--;
266 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
268 if ((drv_data->bytes_left == 1) || drv_data->aborting)
269 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
272 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
273 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
274 drv_data->state = MV64XXX_I2C_STATE_IDLE;
277 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
278 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
279 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
280 /* Doesn't seem to be a device at other end */
281 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
282 drv_data->state = MV64XXX_I2C_STATE_IDLE;
283 drv_data->rc = -ENXIO;
287 dev_err(&drv_data->adapter.dev,
288 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
289 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
290 drv_data->state, status, drv_data->msg->addr,
291 drv_data->msg->flags);
292 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
293 mv64xxx_i2c_hw_init(drv_data);
299 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
301 switch(drv_data->action) {
302 case MV64XXX_I2C_ACTION_SEND_RESTART:
303 /* We should only get here if we have further messages */
304 BUG_ON(drv_data->num_msgs == 0);
306 drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_START;
307 writel(drv_data->cntl_bits,
308 drv_data->reg_base + drv_data->reg_offsets.control);
311 drv_data->num_msgs--;
313 /* Setup for the next message */
314 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
317 * We're never at the start of the message here, and by this
318 * time it's already too late to do any protocol mangling.
319 * Thankfully, do not advertise support for that feature.
321 drv_data->send_stop = drv_data->num_msgs == 1;
324 case MV64XXX_I2C_ACTION_CONTINUE:
325 writel(drv_data->cntl_bits,
326 drv_data->reg_base + drv_data->reg_offsets.control);
329 case MV64XXX_I2C_ACTION_SEND_START:
330 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
331 drv_data->reg_base + drv_data->reg_offsets.control);
334 case MV64XXX_I2C_ACTION_SEND_ADDR_1:
335 writel(drv_data->addr1,
336 drv_data->reg_base + drv_data->reg_offsets.data);
337 writel(drv_data->cntl_bits,
338 drv_data->reg_base + drv_data->reg_offsets.control);
341 case MV64XXX_I2C_ACTION_SEND_ADDR_2:
342 writel(drv_data->addr2,
343 drv_data->reg_base + drv_data->reg_offsets.data);
344 writel(drv_data->cntl_bits,
345 drv_data->reg_base + drv_data->reg_offsets.control);
348 case MV64XXX_I2C_ACTION_SEND_DATA:
349 writel(drv_data->msg->buf[drv_data->byte_posn++],
350 drv_data->reg_base + drv_data->reg_offsets.data);
351 writel(drv_data->cntl_bits,
352 drv_data->reg_base + drv_data->reg_offsets.control);
355 case MV64XXX_I2C_ACTION_RCV_DATA:
356 drv_data->msg->buf[drv_data->byte_posn++] =
357 readl(drv_data->reg_base + drv_data->reg_offsets.data);
358 writel(drv_data->cntl_bits,
359 drv_data->reg_base + drv_data->reg_offsets.control);
362 case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
363 drv_data->msg->buf[drv_data->byte_posn++] =
364 readl(drv_data->reg_base + drv_data->reg_offsets.data);
365 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
366 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
367 drv_data->reg_base + drv_data->reg_offsets.control);
369 wake_up(&drv_data->waitq);
372 case MV64XXX_I2C_ACTION_INVALID:
374 dev_err(&drv_data->adapter.dev,
375 "mv64xxx_i2c_do_action: Invalid action: %d\n",
379 case MV64XXX_I2C_ACTION_SEND_STOP:
380 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
381 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
382 drv_data->reg_base + drv_data->reg_offsets.control);
384 wake_up(&drv_data->waitq);
390 mv64xxx_i2c_intr(int irq, void *dev_id)
392 struct mv64xxx_i2c_data *drv_data = dev_id;
395 irqreturn_t rc = IRQ_NONE;
397 spin_lock_irqsave(&drv_data->lock, flags);
398 while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
399 MV64XXX_I2C_REG_CONTROL_IFLG) {
400 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
401 mv64xxx_i2c_fsm(drv_data, status);
402 mv64xxx_i2c_do_action(drv_data);
405 spin_unlock_irqrestore(&drv_data->lock, flags);
411 *****************************************************************************
413 * I2C Msg Execution Routines
415 *****************************************************************************
418 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
424 time_left = wait_event_timeout(drv_data->waitq,
425 !drv_data->block, drv_data->adapter.timeout);
427 spin_lock_irqsave(&drv_data->lock, flags);
428 if (!time_left) { /* Timed out */
429 drv_data->rc = -ETIMEDOUT;
431 } else if (time_left < 0) { /* Interrupted/Error */
432 drv_data->rc = time_left; /* errno value */
436 if (abort && drv_data->block) {
437 drv_data->aborting = 1;
438 spin_unlock_irqrestore(&drv_data->lock, flags);
440 time_left = wait_event_timeout(drv_data->waitq,
441 !drv_data->block, drv_data->adapter.timeout);
443 if ((time_left <= 0) && drv_data->block) {
444 drv_data->state = MV64XXX_I2C_STATE_IDLE;
445 dev_err(&drv_data->adapter.dev,
446 "mv64xxx: I2C bus locked, block: %d, "
447 "time_left: %d\n", drv_data->block,
449 mv64xxx_i2c_hw_init(drv_data);
452 spin_unlock_irqrestore(&drv_data->lock, flags);
456 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
461 spin_lock_irqsave(&drv_data->lock, flags);
462 mv64xxx_i2c_prepare_for_io(drv_data, msg);
464 drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
465 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
467 drv_data->send_stop = is_last;
469 mv64xxx_i2c_do_action(drv_data);
470 spin_unlock_irqrestore(&drv_data->lock, flags);
472 mv64xxx_i2c_wait_for_completion(drv_data);
477 *****************************************************************************
479 * I2C Core Support Routines (Interface to higher level I2C code)
481 *****************************************************************************
484 mv64xxx_i2c_functionality(struct i2c_adapter *adap)
486 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
490 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
492 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
495 BUG_ON(drv_data->msgs != NULL);
496 drv_data->msgs = msgs;
497 drv_data->num_msgs = num;
499 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
503 drv_data->num_msgs = 0;
504 drv_data->msgs = NULL;
509 static const struct i2c_algorithm mv64xxx_i2c_algo = {
510 .master_xfer = mv64xxx_i2c_xfer,
511 .functionality = mv64xxx_i2c_functionality,
515 *****************************************************************************
517 * Driver Interface & Early Init Routines
519 *****************************************************************************
521 static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
522 { .compatible = "allwinner,sun4i-i2c", .data = &mv64xxx_i2c_regs_sun4i},
523 { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
526 MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
530 mv64xxx_calc_freq(const int tclk, const int n, const int m)
532 return tclk / (10 * (m + 1) * (2 << n));
536 mv64xxx_find_baud_factors(const u32 req_freq, const u32 tclk, u32 *best_n,
539 int freq, delta, best_delta = INT_MAX;
542 for (n = 0; n <= 7; n++)
543 for (m = 0; m <= 15; m++) {
544 freq = mv64xxx_calc_freq(tclk, n, m);
545 delta = req_freq - freq;
546 if (delta >= 0 && delta < best_delta) {
554 if (best_delta == INT_MAX)
560 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
563 const struct of_device_id *device;
564 struct device_node *np = dev->of_node;
568 /* CLK is mandatory when using DT to describe the i2c bus. We
569 * need to know tclk in order to calculate bus clock
572 #if !defined(CONFIG_HAVE_CLK)
573 /* Have OF but no CLK */
576 if (IS_ERR(drv_data->clk)) {
580 tclk = clk_get_rate(drv_data->clk);
582 rc = of_property_read_u32(np, "clock-frequency", &bus_freq);
584 bus_freq = 100000; /* 100kHz by default */
586 if (!mv64xxx_find_baud_factors(bus_freq, tclk,
587 &drv_data->freq_n, &drv_data->freq_m)) {
591 drv_data->irq = irq_of_parse_and_map(np, 0);
593 /* Its not yet defined how timeouts will be specified in device tree.
594 * So hard code the value to 1 second.
596 drv_data->adapter.timeout = HZ;
598 device = of_match_device(mv64xxx_i2c_of_match_table, dev);
602 memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets));
608 #else /* CONFIG_OF */
610 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
615 #endif /* CONFIG_OF */
618 mv64xxx_i2c_probe(struct platform_device *pd)
620 struct mv64xxx_i2c_data *drv_data;
621 struct mv64xxx_i2c_pdata *pdata = pd->dev.platform_data;
625 if ((!pdata && !pd->dev.of_node))
628 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
633 r = platform_get_resource(pd, IORESOURCE_MEM, 0);
634 drv_data->reg_base = devm_ioremap_resource(&pd->dev, r);
635 if (IS_ERR(drv_data->reg_base))
636 return PTR_ERR(drv_data->reg_base);
638 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
639 sizeof(drv_data->adapter.name));
641 init_waitqueue_head(&drv_data->waitq);
642 spin_lock_init(&drv_data->lock);
644 #if defined(CONFIG_HAVE_CLK)
645 /* Not all platforms have a clk */
646 drv_data->clk = devm_clk_get(&pd->dev, NULL);
647 if (!IS_ERR(drv_data->clk)) {
648 clk_prepare(drv_data->clk);
649 clk_enable(drv_data->clk);
653 drv_data->freq_m = pdata->freq_m;
654 drv_data->freq_n = pdata->freq_n;
655 drv_data->irq = platform_get_irq(pd, 0);
656 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
657 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
658 } else if (pd->dev.of_node) {
659 rc = mv64xxx_of_config(drv_data, &pd->dev);
663 if (drv_data->irq < 0) {
668 drv_data->adapter.dev.parent = &pd->dev;
669 drv_data->adapter.algo = &mv64xxx_i2c_algo;
670 drv_data->adapter.owner = THIS_MODULE;
671 drv_data->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
672 drv_data->adapter.nr = pd->id;
673 drv_data->adapter.dev.of_node = pd->dev.of_node;
674 platform_set_drvdata(pd, drv_data);
675 i2c_set_adapdata(&drv_data->adapter, drv_data);
677 mv64xxx_i2c_hw_init(drv_data);
679 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
680 MV64XXX_I2C_CTLR_NAME, drv_data);
682 dev_err(&drv_data->adapter.dev,
683 "mv64xxx: Can't register intr handler irq%d: %d\n",
686 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
687 dev_err(&drv_data->adapter.dev,
688 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
692 of_i2c_register_devices(&drv_data->adapter);
697 free_irq(drv_data->irq, drv_data);
699 #if defined(CONFIG_HAVE_CLK)
700 /* Not all platforms have a clk */
701 if (!IS_ERR(drv_data->clk)) {
702 clk_disable(drv_data->clk);
703 clk_unprepare(drv_data->clk);
710 mv64xxx_i2c_remove(struct platform_device *dev)
712 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev);
714 i2c_del_adapter(&drv_data->adapter);
715 free_irq(drv_data->irq, drv_data);
716 #if defined(CONFIG_HAVE_CLK)
717 /* Not all platforms have a clk */
718 if (!IS_ERR(drv_data->clk)) {
719 clk_disable(drv_data->clk);
720 clk_unprepare(drv_data->clk);
727 static struct platform_driver mv64xxx_i2c_driver = {
728 .probe = mv64xxx_i2c_probe,
729 .remove = mv64xxx_i2c_remove,
731 .owner = THIS_MODULE,
732 .name = MV64XXX_I2C_CTLR_NAME,
733 .of_match_table = of_match_ptr(mv64xxx_i2c_of_match_table),
737 module_platform_driver(mv64xxx_i2c_driver);
739 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
740 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
741 MODULE_LICENSE("GPL");