2 i2c-i801.c - Part of lm_sensors, Linux kernel modules for hardware
4 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 SUPPORTED DEVICES PCI ID
29 82801DB 24C3 (HW PEC supported, 32 byte buffer not supported)
30 82801EB 24D3 (HW PEC supported, 32 byte buffer not supported)
36 This driver supports several versions of Intel's I/O Controller Hubs (ICH).
37 For SMBus support, they are similar to the PIIX4 and are part
38 of Intel's '810' and other chipsets.
39 See the file Documentation/i2c/busses/i2c-i801 for details.
40 I2C Block Read and Process Call are not supported.
43 /* Note: we assume there can only be one I801, with one SMBus interface */
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/kernel.h>
48 #include <linux/stddef.h>
49 #include <linux/delay.h>
50 #include <linux/sched.h>
51 #include <linux/ioport.h>
52 #include <linux/init.h>
53 #include <linux/i2c.h>
56 /* I801 SMBus address offsets */
57 #define SMBHSTSTS (0 + i801_smba)
58 #define SMBHSTCNT (2 + i801_smba)
59 #define SMBHSTCMD (3 + i801_smba)
60 #define SMBHSTADD (4 + i801_smba)
61 #define SMBHSTDAT0 (5 + i801_smba)
62 #define SMBHSTDAT1 (6 + i801_smba)
63 #define SMBBLKDAT (7 + i801_smba)
64 #define SMBPEC (8 + i801_smba) /* ICH4 only */
65 #define SMBAUXSTS (12 + i801_smba) /* ICH4 only */
66 #define SMBAUXCTL (13 + i801_smba) /* ICH4 only */
68 /* PCI Address Constants */
70 #define SMBHSTCFG 0x040
73 /* Host configuration bits for SMBHSTCFG */
74 #define SMBHSTCFG_HST_EN 1
75 #define SMBHSTCFG_SMB_SMI_EN 2
76 #define SMBHSTCFG_I2C_EN 4
79 #define MAX_TIMEOUT 100
80 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
82 /* I801 command constants */
83 #define I801_QUICK 0x00
84 #define I801_BYTE 0x04
85 #define I801_BYTE_DATA 0x08
86 #define I801_WORD_DATA 0x0C
87 #define I801_PROC_CALL 0x10 /* later chips only, unimplemented */
88 #define I801_BLOCK_DATA 0x14
89 #define I801_I2C_BLOCK_DATA 0x18 /* unimplemented */
90 #define I801_BLOCK_LAST 0x34
91 #define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */
92 #define I801_START 0x40
93 #define I801_PEC_EN 0x80 /* ICH4 only */
96 static int i801_transaction(void);
97 static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
98 int command, int hwpec);
100 static unsigned short i801_smba;
101 static struct pci_driver i801_driver;
102 static struct pci_dev *I801_dev;
105 static int __devinit i801_setup(struct pci_dev *dev)
110 if ((dev->device == PCI_DEVICE_ID_INTEL_82801DB_3) ||
111 (dev->device == PCI_DEVICE_ID_INTEL_82801EB_3) ||
112 (dev->device == PCI_DEVICE_ID_INTEL_ESB_4))
117 /* Determine the address of the SMBus area */
118 pci_read_config_word(I801_dev, SMBBA, &i801_smba);
121 dev_err(&dev->dev, "SMBus base address uninitialized, "
126 if (!request_region(i801_smba, (isich4 ? 16 : 8), i801_driver.name)) {
127 dev_err(&dev->dev, "I801_smb region 0x%x already in use!\n",
132 pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
133 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
134 if (!(temp & SMBHSTCFG_HST_EN)) {
135 dev_warn(&dev->dev, "enabling SMBus device\n");
136 temp |= SMBHSTCFG_HST_EN;
138 pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
140 if (temp & SMBHSTCFG_SMB_SMI_EN)
141 dev_dbg(&dev->dev, "I801 using Interrupt SMI# for SMBus.\n");
143 dev_dbg(&dev->dev, "I801 using PCI Interrupt for SMBus.\n");
145 pci_read_config_byte(I801_dev, SMBREV, &temp);
146 dev_dbg(&dev->dev, "SMBREV = 0x%X\n", temp);
147 dev_dbg(&dev->dev, "I801_smba = 0x%X\n", i801_smba);
152 static int i801_transaction(void)
158 dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
159 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
160 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
163 /* Make sure the SMBus host is ready to start transmitting */
164 /* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
165 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
166 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting...\n",
168 outb_p(temp, SMBHSTSTS);
169 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
170 dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp);
173 dev_dbg(&I801_dev->dev, "Successfull!\n");
177 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
179 /* We will always wait for a fraction of a second! */
182 temp = inb_p(SMBHSTSTS);
183 } while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
185 /* If the SMBus is still busy, we give up */
186 if (timeout >= MAX_TIMEOUT) {
187 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
193 dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n");
198 dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked "
199 "until next hard reset. (sorry!)\n");
200 /* Clock stops and slave is stuck in mid-transmission */
205 dev_dbg(&I801_dev->dev, "Error: no response!\n");
208 if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
209 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
211 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
212 dev_dbg(&I801_dev->dev, "Failed reset at end of transaction "
215 dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
216 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
217 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
222 /* All-inclusive block transaction function */
223 static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
224 int command, int hwpec)
231 unsigned char hostc, errmask;
233 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
234 if (read_write == I2C_SMBUS_WRITE) {
235 /* set I2C_EN bit in configuration register */
236 pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
237 pci_write_config_byte(I801_dev, SMBHSTCFG,
238 hostc | SMBHSTCFG_I2C_EN);
240 dev_err(&I801_dev->dev,
241 "I2C_SMBUS_I2C_BLOCK_READ not DB!\n");
246 if (read_write == I2C_SMBUS_WRITE) {
247 len = data->block[0];
252 outb_p(len, SMBHSTDAT0);
253 outb_p(data->block[1], SMBBLKDAT);
255 len = 32; /* max for reads */
258 if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
259 /* set 32 byte buffer */
262 for (i = 1; i <= len; i++) {
263 if (i == len && read_write == I2C_SMBUS_READ)
264 smbcmd = I801_BLOCK_LAST;
266 smbcmd = I801_BLOCK_DATA;
267 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
269 dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
270 "ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
271 inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
272 inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
274 /* Make sure the SMBus host is ready to start transmitting */
275 temp = inb_p(SMBHSTSTS);
277 /* Erronenous conditions before transaction:
278 * Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
281 /* Erronenous conditions during transaction:
282 * Failed, Bus_Err, Dev_Err, Intr */
285 if (temp & errmask) {
286 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). "
287 "Resetting...\n", temp);
288 outb_p(temp, SMBHSTSTS);
289 if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
290 dev_err(&I801_dev->dev,
291 "Reset failed! (%02x)\n", temp);
296 /* if die in middle of block transaction, fail */
303 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
305 /* We will always wait for a fraction of a second! */
309 temp = inb_p(SMBHSTSTS);
311 while ((!(temp & 0x80))
312 && (timeout++ < MAX_TIMEOUT));
314 /* If the SMBus is still busy, we give up */
315 if (timeout >= MAX_TIMEOUT) {
317 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
322 dev_dbg(&I801_dev->dev,
323 "Error: Failed bus transaction\n");
324 } else if (temp & 0x08) {
326 dev_err(&I801_dev->dev, "Bus collision!\n");
327 } else if (temp & 0x04) {
329 dev_dbg(&I801_dev->dev, "Error: no response!\n");
332 if (i == 1 && read_write == I2C_SMBUS_READ) {
333 len = inb_p(SMBHSTDAT0);
338 data->block[0] = len;
341 /* Retrieve/store value in SMBBLKDAT */
342 if (read_write == I2C_SMBUS_READ)
343 data->block[i] = inb_p(SMBBLKDAT);
344 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
345 outb_p(data->block[i+1], SMBBLKDAT);
346 if ((temp & 0x9e) != 0x00)
347 outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
349 if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
350 dev_dbg(&I801_dev->dev,
351 "Bad status (%02x) at end of transaction\n",
354 dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, "
355 "ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
356 inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
357 inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
364 /* wait for INTR bit as advised by Intel */
368 temp = inb_p(SMBHSTSTS);
369 } while ((!(temp & 0x02))
370 && (timeout++ < MAX_TIMEOUT));
372 if (timeout >= MAX_TIMEOUT) {
373 dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
375 outb_p(temp, SMBHSTSTS);
379 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
380 /* restore saved configuration register value */
381 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
386 /* Return -1 on error. */
387 static s32 i801_access(struct i2c_adapter * adap, u16 addr,
388 unsigned short flags, char read_write, u8 command,
389 int size, union i2c_smbus_data * data)
395 hwpec = isich4 && (flags & I2C_CLIENT_PEC)
396 && size != I2C_SMBUS_QUICK
397 && size != I2C_SMBUS_I2C_BLOCK_DATA;
400 case I2C_SMBUS_QUICK:
401 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
406 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
408 if (read_write == I2C_SMBUS_WRITE)
409 outb_p(command, SMBHSTCMD);
412 case I2C_SMBUS_BYTE_DATA:
413 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
415 outb_p(command, SMBHSTCMD);
416 if (read_write == I2C_SMBUS_WRITE)
417 outb_p(data->byte, SMBHSTDAT0);
418 xact = I801_BYTE_DATA;
420 case I2C_SMBUS_WORD_DATA:
421 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
423 outb_p(command, SMBHSTCMD);
424 if (read_write == I2C_SMBUS_WRITE) {
425 outb_p(data->word & 0xff, SMBHSTDAT0);
426 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
428 xact = I801_WORD_DATA;
430 case I2C_SMBUS_BLOCK_DATA:
431 case I2C_SMBUS_I2C_BLOCK_DATA:
432 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
434 outb_p(command, SMBHSTCMD);
437 case I2C_SMBUS_PROC_CALL:
439 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
443 outb_p(hwpec, SMBAUXCTL); /* enable/disable hardware PEC */
446 ret = i801_block_transaction(data, read_write, size, hwpec);
448 outb_p(xact | ENABLE_INT9, SMBHSTCNT);
449 ret = i801_transaction();
452 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
453 time, so we forcibly disable it after every transaction. */
455 outb_p(0, SMBAUXCTL);
461 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
464 switch (xact & 0x7f) {
465 case I801_BYTE: /* Result put in SMBHSTDAT0 */
467 data->byte = inb_p(SMBHSTDAT0);
470 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
477 static u32 i801_func(struct i2c_adapter *adapter)
479 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
480 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
481 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
482 | (isich4 ? I2C_FUNC_SMBUS_HWPEC_CALC : 0);
485 static struct i2c_algorithm smbus_algorithm = {
486 .smbus_xfer = i801_access,
487 .functionality = i801_func,
490 static struct i2c_adapter i801_adapter = {
491 .owner = THIS_MODULE,
492 .class = I2C_CLASS_HWMON,
493 .algo = &smbus_algorithm,
496 static struct pci_device_id i801_ids[] = {
497 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
498 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
499 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
500 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
501 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
502 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
503 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
504 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
505 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
506 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
507 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
511 MODULE_DEVICE_TABLE (pci, i801_ids);
513 static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
517 if ((err = i801_setup(dev)))
520 /* set up the driverfs linkage to our parent device */
521 i801_adapter.dev.parent = &dev->dev;
523 snprintf(i801_adapter.name, I2C_NAME_SIZE,
524 "SMBus I801 adapter at %04x", i801_smba);
525 return i2c_add_adapter(&i801_adapter);
528 static void __devexit i801_remove(struct pci_dev *dev)
530 i2c_del_adapter(&i801_adapter);
531 release_region(i801_smba, (isich4 ? 16 : 8));
534 static struct pci_driver i801_driver = {
535 .name = "i801_smbus",
536 .id_table = i801_ids,
538 .remove = __devexit_p(i801_remove),
541 static int __init i2c_i801_init(void)
543 return pci_register_driver(&i801_driver);
546 static void __exit i2c_i801_exit(void)
548 pci_unregister_driver(&i801_driver);
551 MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
552 "Philip Edelbrock <phil@netroedge.com>, "
553 "and Mark D. Studebaker <mdsxyz123@yahoo.com>");
554 MODULE_DESCRIPTION("I801 SMBus driver");
555 MODULE_LICENSE("GPL");
557 module_init(i2c_i801_init);
558 module_exit(i2c_i801_exit);