Pileus Git - ~andy/linux/blob - drivers/i2c/busses/i2c-davinci.c

   1 /*
   2  * TI DAVINCI I2C adapter driver.
   3  *
   4  * Copyright (C) 2006 Texas Instruments.
   5  * Copyright (C) 2007 MontaVista Software Inc.
   6  *
   7  * Updated by Vinod & Sudhakar Feb 2005
   8  *
   9  * ----------------------------------------------------------------------------
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  * ----------------------------------------------------------------------------
  25  *
  26  */
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/i2c.h>
  31 #include <linux/clk.h>
  32 #include <linux/errno.h>
  33 #include <linux/sched.h>
  34 #include <linux/err.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/io.h>
  38 #include <linux/slab.h>
  39 #include <linux/cpufreq.h>
  40 #include <linux/gpio.h>
  41 #include <linux/of_i2c.h>
  42 #include <linux/of_device.h>
  43
  44 #include <mach/hardware.h>
  45 #include <linux/platform_data/i2c-davinci.h>
  46
  47 /* ----- global defines ----------------------------------------------- */
  48
  49 #define DAVINCI_I2C_TIMEOUT     (1*HZ)
  50 #define DAVINCI_I2C_MAX_TRIES   2
  51 #define I2C_DAVINCI_INTR_ALL    (DAVINCI_I2C_IMR_AAS | \
  52                                  DAVINCI_I2C_IMR_SCD | \
  53                                  DAVINCI_I2C_IMR_ARDY | \
  54                                  DAVINCI_I2C_IMR_NACK | \
  55                                  DAVINCI_I2C_IMR_AL)
  56
  57 #define DAVINCI_I2C_OAR_REG     0x00
  58 #define DAVINCI_I2C_IMR_REG     0x04
  59 #define DAVINCI_I2C_STR_REG     0x08
  60 #define DAVINCI_I2C_CLKL_REG    0x0c
  61 #define DAVINCI_I2C_CLKH_REG    0x10
  62 #define DAVINCI_I2C_CNT_REG     0x14
  63 #define DAVINCI_I2C_DRR_REG     0x18
  64 #define DAVINCI_I2C_SAR_REG     0x1c
  65 #define DAVINCI_I2C_DXR_REG     0x20
  66 #define DAVINCI_I2C_MDR_REG     0x24
  67 #define DAVINCI_I2C_IVR_REG     0x28
  68 #define DAVINCI_I2C_EMDR_REG    0x2c
  69 #define DAVINCI_I2C_PSC_REG     0x30
  70
  71 #define DAVINCI_I2C_IVR_AAS     0x07
  72 #define DAVINCI_I2C_IVR_SCD     0x06
  73 #define DAVINCI_I2C_IVR_XRDY    0x05
  74 #define DAVINCI_I2C_IVR_RDR     0x04
  75 #define DAVINCI_I2C_IVR_ARDY    0x03
  76 #define DAVINCI_I2C_IVR_NACK    0x02
  77 #define DAVINCI_I2C_IVR_AL      0x01
  78
  79 #define DAVINCI_I2C_STR_BB      BIT(12)
  80 #define DAVINCI_I2C_STR_RSFULL  BIT(11)
  81 #define DAVINCI_I2C_STR_SCD     BIT(5)
  82 #define DAVINCI_I2C_STR_ARDY    BIT(2)
  83 #define DAVINCI_I2C_STR_NACK    BIT(1)
  84 #define DAVINCI_I2C_STR_AL      BIT(0)
  85
  86 #define DAVINCI_I2C_MDR_NACK    BIT(15)
  87 #define DAVINCI_I2C_MDR_STT     BIT(13)
  88 #define DAVINCI_I2C_MDR_STP     BIT(11)
  89 #define DAVINCI_I2C_MDR_MST     BIT(10)
  90 #define DAVINCI_I2C_MDR_TRX     BIT(9)
  91 #define DAVINCI_I2C_MDR_XA      BIT(8)
  92 #define DAVINCI_I2C_MDR_RM      BIT(7)
  93 #define DAVINCI_I2C_MDR_IRS     BIT(5)
  94
  95 #define DAVINCI_I2C_IMR_AAS     BIT(6)
  96 #define DAVINCI_I2C_IMR_SCD     BIT(5)
  97 #define DAVINCI_I2C_IMR_XRDY    BIT(4)
  98 #define DAVINCI_I2C_IMR_RRDY    BIT(3)
  99 #define DAVINCI_I2C_IMR_ARDY    BIT(2)
 100 #define DAVINCI_I2C_IMR_NACK    BIT(1)
 101 #define DAVINCI_I2C_IMR_AL      BIT(0)
 102
 103 struct davinci_i2c_dev {
 104         struct device           *dev;
 105         void __iomem            *base;
 106         struct completion       cmd_complete;
 107         struct clk              *clk;
 108         int                     cmd_err;
 109         u8                      *buf;
 110         size_t                  buf_len;
 111         int                     irq;
 112         int                     stop;
 113         u8                      terminate;
 114         struct i2c_adapter      adapter;
 115 #ifdef CONFIG_CPU_FREQ
 116         struct completion       xfr_complete;
 117         struct notifier_block   freq_transition;
 118 #endif
 119         struct davinci_i2c_platform_data *pdata;
 120 };
 121
 122 /* default platform data to use if not supplied in the platform_device */
 123 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
 124         .bus_freq       = 100,
 125         .bus_delay      = 0,
 126 };
 127
 128 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
 129                                          int reg, u16 val)
 130 {
 131         __raw_writew(val, i2c_dev->base + reg);
 132 }
 133
 134 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
 135 {
 136         return __raw_readw(i2c_dev->base + reg);
 137 }
 138
 139 /* Generate a pulse on the i2c clock pin. */
 140 static void generic_i2c_clock_pulse(unsigned int scl_pin)
 141 {
 142         u16 i;
 143
 144         if (scl_pin) {
 145                 /* Send high and low on the SCL line */
 146                 for (i = 0; i < 9; i++) {
 147                         gpio_set_value(scl_pin, 0);
 148                         udelay(20);
 149                         gpio_set_value(scl_pin, 1);
 150                         udelay(20);
 151                 }
 152         }
 153 }
 154
 155 /* This routine does i2c bus recovery as specified in the
 156  * i2c protocol Rev. 03 section 3.16 titled "Bus clear"
 157  */
 158 static void i2c_recover_bus(struct davinci_i2c_dev *dev)
 159 {
 160         u32 flag = 0;
 161         struct davinci_i2c_platform_data *pdata = dev->pdata;
 162
 163         dev_err(dev->dev, "initiating i2c bus recovery\n");
 164         /* Send NACK to the slave */
 165         flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 166         flag |=  DAVINCI_I2C_MDR_NACK;
 167         /* write the data into mode register */
 168         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 169         generic_i2c_clock_pulse(pdata->scl_pin);
 170         /* Send STOP */
 171         flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 172         flag |= DAVINCI_I2C_MDR_STP;
 173         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 174 }
 175
 176 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
 177                                                                 int val)
 178 {
 179         u16 w;
 180
 181         w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
 182         if (!val)       /* put I2C into reset */
 183                 w &= ~DAVINCI_I2C_MDR_IRS;
 184         else            /* take I2C out of reset */
 185                 w |= DAVINCI_I2C_MDR_IRS;
 186
 187         davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
 188 }
 189
 190 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
 191 {
 192         struct davinci_i2c_platform_data *pdata = dev->pdata;
 193         u16 psc;
 194         u32 clk;
 195         u32 d;
 196         u32 clkh;
 197         u32 clkl;
 198         u32 input_clock = clk_get_rate(dev->clk);
 199
 200         /* NOTE: I2C Clock divider programming info
 201          * As per I2C specs the following formulas provide prescaler
 202          * and low/high divider values
 203          * input clk --> PSC Div -----------> ICCL/H Div --> output clock
 204          *                       module clk
 205          *
 206          * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
 207          *
 208          * Thus,
 209          * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
 210          *
 211          * where if PSC == 0, d = 7,
 212          *       if PSC == 1, d = 6
 213          *       if PSC > 1 , d = 5
 214          */
 215
 216         /* get minimum of 7 MHz clock, but max of 12 MHz */
 217         psc = (input_clock / 7000000) - 1;
 218         if ((input_clock / (psc + 1)) > 12000000)
 219                 psc++;  /* better to run under spec than over */
 220         d = (psc >= 2) ? 5 : 7 - psc;
 221
 222         clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1);
 223         clkh = clk >> 1;
 224         clkl = clk - clkh;
 225
 226         davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
 227         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
 228         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
 229
 230         dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
 231 }
 232
 233 /*
 234  * This function configures I2C and brings I2C out of reset.
 235  * This function is called during I2C init function. This function
 236  * also gets called if I2C encounters any errors.
 237  */
 238 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
 239 {
 240         struct davinci_i2c_platform_data *pdata = dev->pdata;
 241
 242         /* put I2C into reset */
 243         davinci_i2c_reset_ctrl(dev, 0);
 244
 245         /* compute clock dividers */
 246         i2c_davinci_calc_clk_dividers(dev);
 247
 248         /* Respond at reserved "SMBus Host" slave address" (and zero);
 249          * we seem to have no option to not respond...
 250          */
 251         davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
 252
 253         dev_dbg(dev->dev, "PSC  = %d\n",
 254                 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
 255         dev_dbg(dev->dev, "CLKL = %d\n",
 256                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
 257         dev_dbg(dev->dev, "CLKH = %d\n",
 258                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
 259         dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
 260                 pdata->bus_freq, pdata->bus_delay);
 261
 262
 263         /* Take the I2C module out of reset: */
 264         davinci_i2c_reset_ctrl(dev, 1);
 265
 266         /* Enable interrupts */
 267         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
 268
 269         return 0;
 270 }
 271
 272 /*
 273  * Waiting for bus not busy
 274  */
 275 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
 276                                          char allow_sleep)
 277 {
 278         unsigned long timeout;
 279         static u16 to_cnt;
 280
 281         timeout = jiffies + dev->adapter.timeout;
 282         while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
 283                & DAVINCI_I2C_STR_BB) {
 284                 if (to_cnt <= DAVINCI_I2C_MAX_TRIES) {
 285                         if (time_after(jiffies, timeout)) {
 286                                 dev_warn(dev->dev,
 287                                 "timeout waiting for bus ready\n");
 288                                 to_cnt++;
 289                                 return -ETIMEDOUT;
 290                         } else {
 291                                 to_cnt = 0;
 292                                 i2c_recover_bus(dev);
 293                                 i2c_davinci_init(dev);
 294                         }
 295                 }
 296                 if (allow_sleep)
 297                         schedule_timeout(1);
 298         }
 299
 300         return 0;
 301 }
 302
 303 /*
 304  * Low level master read/write transaction. This function is called
 305  * from i2c_davinci_xfer.
 306  */
 307 static int
 308 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
 309 {
 310         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 311         struct davinci_i2c_platform_data *pdata = dev->pdata;
 312         u32 flag;
 313         u16 w;
 314         int r;
 315
 316         /* Introduce a delay, required for some boards (e.g Davinci EVM) */
 317         if (pdata->bus_delay)
 318                 udelay(pdata->bus_delay);
 319
 320         /* set the slave address */
 321         davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
 322
 323         dev->buf = msg->buf;
 324         dev->buf_len = msg->len;
 325         dev->stop = stop;
 326
 327         davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
 328
 329         INIT_COMPLETION(dev->cmd_complete);
 330         dev->cmd_err = 0;
 331
 332         /* Take I2C out of reset and configure it as master */
 333         flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
 334
 335         /* if the slave address is ten bit address, enable XA bit */
 336         if (msg->flags & I2C_M_TEN)
 337                 flag |= DAVINCI_I2C_MDR_XA;
 338         if (!(msg->flags & I2C_M_RD))
 339                 flag |= DAVINCI_I2C_MDR_TRX;
 340         if (msg->len == 0)
 341                 flag |= DAVINCI_I2C_MDR_RM;
 342
 343         /* Enable receive or transmit interrupts */
 344         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
 345         if (msg->flags & I2C_M_RD)
 346                 w |= DAVINCI_I2C_IMR_RRDY;
 347         else
 348                 w |= DAVINCI_I2C_IMR_XRDY;
 349         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
 350
 351         dev->terminate = 0;
 352
 353         /*
 354          * Write mode register first as needed for correct behaviour
 355          * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
 356          * occurring before we have loaded DXR
 357          */
 358         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 359
 360         /*
 361          * First byte should be set here, not after interrupt,
 362          * because transmit-data-ready interrupt can come before
 363          * NACK-interrupt during sending of previous message and
 364          * ICDXR may have wrong data
 365          * It also saves us one interrupt, slightly faster
 366          */
 367         if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
 368                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
 369                 dev->buf_len--;
 370         }
 371
 372         /* Set STT to begin transmit now DXR is loaded */
 373         flag |= DAVINCI_I2C_MDR_STT;
 374         if (stop && msg->len != 0)
 375                 flag |= DAVINCI_I2C_MDR_STP;
 376         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 377
 378         r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
 379                                                       dev->adapter.timeout);
 380         if (r == 0) {
 381                 dev_err(dev->dev, "controller timed out\n");
 382                 i2c_recover_bus(dev);
 383                 i2c_davinci_init(dev);
 384                 dev->buf_len = 0;
 385                 return -ETIMEDOUT;
 386         }
 387         if (dev->buf_len) {
 388                 /* This should be 0 if all bytes were transferred
 389                  * or dev->cmd_err denotes an error.
 390                  * A signal may have aborted the transfer.
 391                  */
 392                 if (r >= 0) {
 393                         dev_err(dev->dev, "abnormal termination buf_len=%i\n",
 394                                 dev->buf_len);
 395                         r = -EREMOTEIO;
 396                 }
 397                 dev->terminate = 1;
 398                 wmb();
 399                 dev->buf_len = 0;
 400         }
 401         if (r < 0)
 402                 return r;
 403
 404         /* no error */
 405         if (likely(!dev->cmd_err))
 406                 return msg->len;
 407
 408         /* We have an error */
 409         if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
 410                 i2c_davinci_init(dev);
 411                 return -EIO;
 412         }
 413
 414         if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
 415                 if (msg->flags & I2C_M_IGNORE_NAK)
 416                         return msg->len;
 417                 if (stop) {
 418                         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 419                         w |= DAVINCI_I2C_MDR_STP;
 420                         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 421                 }
 422                 return -EREMOTEIO;
 423         }
 424         return -EIO;
 425 }
 426
 427 /*
 428  * Prepare controller for a transaction and call i2c_davinci_xfer_msg
 429  */
 430 static int
 431 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 432 {
 433         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 434         int i;
 435         int ret;
 436
 437         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 438
 439         ret = i2c_davinci_wait_bus_not_busy(dev, 1);
 440         if (ret < 0) {
 441                 dev_warn(dev->dev, "timeout waiting for bus ready\n");
 442                 return ret;
 443         }
 444
 445         for (i = 0; i < num; i++) {
 446                 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 447                 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
 448                         ret);
 449                 if (ret < 0)
 450                         return ret;
 451         }
 452
 453 #ifdef CONFIG_CPU_FREQ
 454         complete(&dev->xfr_complete);
 455 #endif
 456
 457         return num;
 458 }
 459
 460 static u32 i2c_davinci_func(struct i2c_adapter *adap)
 461 {
 462         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 463 }
 464
 465 static void terminate_read(struct davinci_i2c_dev *dev)
 466 {
 467         u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 468         w |= DAVINCI_I2C_MDR_NACK;
 469         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 470
 471         /* Throw away data */
 472         davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
 473         if (!dev->terminate)
 474                 dev_err(dev->dev, "RDR IRQ while no data requested\n");
 475 }
 476 static void terminate_write(struct davinci_i2c_dev *dev)
 477 {
 478         u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 479         w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
 480         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 481
 482         if (!dev->terminate)
 483                 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
 484 }
 485
 486 /*
 487  * Interrupt service routine. This gets called whenever an I2C interrupt
 488  * occurs.
 489  */
 490 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
 491 {
 492         struct davinci_i2c_dev *dev = dev_id;
 493         u32 stat;
 494         int count = 0;
 495         u16 w;
 496
 497         while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
 498                 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
 499                 if (count++ == 100) {
 500                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 501                         break;
 502                 }
 503
 504                 switch (stat) {
 505                 case DAVINCI_I2C_IVR_AL:
 506                         /* Arbitration lost, must retry */
 507                         dev->cmd_err |= DAVINCI_I2C_STR_AL;
 508                         dev->buf_len = 0;
 509                         complete(&dev->cmd_complete);
 510                         break;
 511
 512                 case DAVINCI_I2C_IVR_NACK:
 513                         dev->cmd_err |= DAVINCI_I2C_STR_NACK;
 514                         dev->buf_len = 0;
 515                         complete(&dev->cmd_complete);
 516                         break;
 517
 518                 case DAVINCI_I2C_IVR_ARDY:
 519                         davinci_i2c_write_reg(dev,
 520                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
 521                         if (((dev->buf_len == 0) && (dev->stop != 0)) ||
 522                             (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
 523                                 w = davinci_i2c_read_reg(dev,
 524                                                          DAVINCI_I2C_MDR_REG);
 525                                 w |= DAVINCI_I2C_MDR_STP;
 526                                 davinci_i2c_write_reg(dev,
 527                                                       DAVINCI_I2C_MDR_REG, w);
 528                         }
 529                         complete(&dev->cmd_complete);
 530                         break;
 531
 532                 case DAVINCI_I2C_IVR_RDR:
 533                         if (dev->buf_len) {
 534                                 *dev->buf++ =
 535                                     davinci_i2c_read_reg(dev,
 536                                                          DAVINCI_I2C_DRR_REG);
 537                                 dev->buf_len--;
 538                                 if (dev->buf_len)
 539                                         continue;
 540
 541                                 davinci_i2c_write_reg(dev,
 542                                         DAVINCI_I2C_STR_REG,
 543                                         DAVINCI_I2C_IMR_RRDY);
 544                         } else {
 545                                 /* signal can terminate transfer */
 546                                 terminate_read(dev);
 547                         }
 548                         break;
 549
 550                 case DAVINCI_I2C_IVR_XRDY:
 551                         if (dev->buf_len) {
 552                                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
 553                                                       *dev->buf++);
 554                                 dev->buf_len--;
 555                                 if (dev->buf_len)
 556                                         continue;
 557
 558                                 w = davinci_i2c_read_reg(dev,
 559                                                          DAVINCI_I2C_IMR_REG);
 560                                 w &= ~DAVINCI_I2C_IMR_XRDY;
 561                                 davinci_i2c_write_reg(dev,
 562                                                       DAVINCI_I2C_IMR_REG,
 563                                                       w);
 564                         } else {
 565                                 /* signal can terminate transfer */
 566                                 terminate_write(dev);
 567                         }
 568                         break;
 569
 570                 case DAVINCI_I2C_IVR_SCD:
 571                         davinci_i2c_write_reg(dev,
 572                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
 573                         complete(&dev->cmd_complete);
 574                         break;
 575
 576                 case DAVINCI_I2C_IVR_AAS:
 577                         dev_dbg(dev->dev, "Address as slave interrupt\n");
 578                         break;
 579
 580                 default:
 581                         dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
 582                         break;
 583                 }
 584         }
 585
 586         return count ? IRQ_HANDLED : IRQ_NONE;
 587 }
 588
 589 #ifdef CONFIG_CPU_FREQ
 590 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
 591                                      unsigned long val, void *data)
 592 {
 593         struct davinci_i2c_dev *dev;
 594
 595         dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
 596         if (val == CPUFREQ_PRECHANGE) {
 597                 wait_for_completion(&dev->xfr_complete);
 598                 davinci_i2c_reset_ctrl(dev, 0);
 599         } else if (val == CPUFREQ_POSTCHANGE) {
 600                 i2c_davinci_calc_clk_dividers(dev);
 601                 davinci_i2c_reset_ctrl(dev, 1);
 602         }
 603
 604         return 0;
 605 }
 606
 607 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
 608 {
 609         dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
 610
 611         return cpufreq_register_notifier(&dev->freq_transition,
 612                                          CPUFREQ_TRANSITION_NOTIFIER);
 613 }
 614
 615 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
 616 {
 617         cpufreq_unregister_notifier(&dev->freq_transition,
 618                                     CPUFREQ_TRANSITION_NOTIFIER);
 619 }
 620 #else
 621 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
 622 {
 623         return 0;
 624 }
 625
 626 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
 627 {
 628 }
 629 #endif
 630
 631 static struct i2c_algorithm i2c_davinci_algo = {
 632         .master_xfer    = i2c_davinci_xfer,
 633         .functionality  = i2c_davinci_func,
 634 };
 635
 636 static const struct of_device_id davinci_i2c_of_match[] = {
 637         {.compatible = "ti,davinci-i2c", },
 638         {},
 639 };
 640 MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
 641
 642 static int davinci_i2c_probe(struct platform_device *pdev)
 643 {
 644         struct davinci_i2c_dev *dev;
 645         struct i2c_adapter *adap;
 646         struct resource *mem, *irq, *ioarea;
 647         int r;
 648
 649         /* NOTE: driver uses the static register mapping */
 650         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 651         if (!mem) {
 652                 dev_err(&pdev->dev, "no mem resource?\n");
 653                 return -ENODEV;
 654         }
 655
 656         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 657         if (!irq) {
 658                 dev_err(&pdev->dev, "no irq resource?\n");
 659                 return -ENODEV;
 660         }
 661
 662         ioarea = request_mem_region(mem->start, resource_size(mem),
 663                                     pdev->name);
 664         if (!ioarea) {
 665                 dev_err(&pdev->dev, "I2C region already claimed\n");
 666                 return -EBUSY;
 667         }
 668
 669         dev = kzalloc(sizeof(struct davinci_i2c_dev), GFP_KERNEL);
 670         if (!dev) {
 671                 r = -ENOMEM;
 672                 goto err_release_region;
 673         }
 674
 675         init_completion(&dev->cmd_complete);
 676 #ifdef CONFIG_CPU_FREQ
 677         init_completion(&dev->xfr_complete);
 678 #endif
 679         dev->dev = get_device(&pdev->dev);
 680         dev->irq = irq->start;
 681         dev->pdata = dev->dev->platform_data;
 682         platform_set_drvdata(pdev, dev);
 683
 684         if (!dev->pdata && pdev->dev.of_node) {
 685                 u32 prop;
 686
 687                 dev->pdata = devm_kzalloc(&pdev->dev,
 688                         sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
 689                 if (!dev->pdata) {
 690                         r = -ENOMEM;
 691                         goto err_free_mem;
 692                 }
 693                 memcpy(dev->pdata, &davinci_i2c_platform_data_default,
 694                         sizeof(struct davinci_i2c_platform_data));
 695                 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
 696                         &prop))
 697                         dev->pdata->bus_freq = prop / 1000;
 698         } else if (!dev->pdata) {
 699                 dev->pdata = &davinci_i2c_platform_data_default;
 700         }
 701
 702         dev->clk = clk_get(&pdev->dev, NULL);
 703         if (IS_ERR(dev->clk)) {
 704                 r = -ENODEV;
 705                 goto err_free_mem;
 706         }
 707         clk_prepare_enable(dev->clk);
 708
 709         dev->base = ioremap(mem->start, resource_size(mem));
 710         if (!dev->base) {
 711                 r = -EBUSY;
 712                 goto err_mem_ioremap;
 713         }
 714
 715         i2c_davinci_init(dev);
 716
 717         r = request_irq(dev->irq, i2c_davinci_isr, 0, pdev->name, dev);
 718         if (r) {
 719                 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
 720                 goto err_unuse_clocks;
 721         }
 722
 723         r = i2c_davinci_cpufreq_register(dev);
 724         if (r) {
 725                 dev_err(&pdev->dev, "failed to register cpufreq\n");
 726                 goto err_free_irq;
 727         }
 728
 729         adap = &dev->adapter;
 730         i2c_set_adapdata(adap, dev);
 731         adap->owner = THIS_MODULE;
 732         adap->class = I2C_CLASS_HWMON;
 733         strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
 734         adap->algo = &i2c_davinci_algo;
 735         adap->dev.parent = &pdev->dev;
 736         adap->timeout = DAVINCI_I2C_TIMEOUT;
 737         adap->dev.of_node = pdev->dev.of_node;
 738
 739         adap->nr = pdev->id;
 740         r = i2c_add_numbered_adapter(adap);
 741         if (r) {
 742                 dev_err(&pdev->dev, "failure adding adapter\n");
 743                 goto err_free_irq;
 744         }
 745         of_i2c_register_devices(adap);
 746
 747         return 0;
 748
 749 err_free_irq:
 750         free_irq(dev->irq, dev);
 751 err_unuse_clocks:
 752         iounmap(dev->base);
 753 err_mem_ioremap:
 754         clk_disable_unprepare(dev->clk);
 755         clk_put(dev->clk);
 756         dev->clk = NULL;
 757 err_free_mem:
 758         platform_set_drvdata(pdev, NULL);
 759         put_device(&pdev->dev);
 760         kfree(dev);
 761 err_release_region:
 762         release_mem_region(mem->start, resource_size(mem));
 763
 764         return r;
 765 }
 766
 767 static int davinci_i2c_remove(struct platform_device *pdev)
 768 {
 769         struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
 770         struct resource *mem;
 771
 772         i2c_davinci_cpufreq_deregister(dev);
 773
 774         platform_set_drvdata(pdev, NULL);
 775         i2c_del_adapter(&dev->adapter);
 776         put_device(&pdev->dev);
 777
 778         clk_disable_unprepare(dev->clk);
 779         clk_put(dev->clk);
 780         dev->clk = NULL;
 781
 782         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
 783         free_irq(dev->irq, dev);
 784         iounmap(dev->base);
 785         kfree(dev);
 786
 787         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 788         release_mem_region(mem->start, resource_size(mem));
 789         return 0;
 790 }
 791
 792 #ifdef CONFIG_PM
 793 static int davinci_i2c_suspend(struct device *dev)
 794 {
 795         struct platform_device *pdev = to_platform_device(dev);
 796         struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 797
 798         /* put I2C into reset */
 799         davinci_i2c_reset_ctrl(i2c_dev, 0);
 800         clk_disable_unprepare(i2c_dev->clk);
 801
 802         return 0;
 803 }
 804
 805 static int davinci_i2c_resume(struct device *dev)
 806 {
 807         struct platform_device *pdev = to_platform_device(dev);
 808         struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 809
 810         clk_prepare_enable(i2c_dev->clk);
 811         /* take I2C out of reset */
 812         davinci_i2c_reset_ctrl(i2c_dev, 1);
 813
 814         return 0;
 815 }
 816
 817 static const struct dev_pm_ops davinci_i2c_pm = {
 818         .suspend        = davinci_i2c_suspend,
 819         .resume         = davinci_i2c_resume,
 820 };
 821
 822 #define davinci_i2c_pm_ops (&davinci_i2c_pm)
 823 #else
 824 #define davinci_i2c_pm_ops NULL
 825 #endif
 826
 827 /* work with hotplug and coldplug */
 828 MODULE_ALIAS("platform:i2c_davinci");
 829
 830 static struct platform_driver davinci_i2c_driver = {
 831         .probe          = davinci_i2c_probe,
 832         .remove         = davinci_i2c_remove,
 833         .driver         = {
 834                 .name   = "i2c_davinci",
 835                 .owner  = THIS_MODULE,
 836                 .pm     = davinci_i2c_pm_ops,
 837                 .of_match_table = of_match_ptr(davinci_i2c_of_match),
 838         },
 839 };
 840
 841 /* I2C may be needed to bring up other drivers */
 842 static int __init davinci_i2c_init_driver(void)
 843 {
 844         return platform_driver_register(&davinci_i2c_driver);
 845 }
 846 subsys_initcall(davinci_i2c_init_driver);
 847
 848 static void __exit davinci_i2c_exit_driver(void)
 849 {
 850         platform_driver_unregister(&davinci_i2c_driver);
 851 }
 852 module_exit(davinci_i2c_exit_driver);
 853
 854 MODULE_AUTHOR("Texas Instruments India");
 855 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
 856 MODULE_LICENSE("GPL");