Pileus Git - ~andy/linux/blob - drivers/i2c/busses/i2c-bfin-twi.c

   1 /*
   2  * Blackfin On-Chip Two Wire Interface Driver
   3  *
   4  * Copyright 2005-2007 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/i2c.h>
  15 #include <linux/slab.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/timer.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/delay.h>
  24
  25 #include <asm/blackfin.h>
  26 #include <asm/portmux.h>
  27 #include <asm/irq.h>
  28 #include <asm/bfin_twi.h>
  29
  30 /* SMBus mode*/
  31 #define TWI_I2C_MODE_STANDARD           1
  32 #define TWI_I2C_MODE_STANDARDSUB        2
  33 #define TWI_I2C_MODE_COMBINED           3
  34 #define TWI_I2C_MODE_REPEAT             4
  35
  36 struct bfin_twi_iface {
  37         int                     irq;
  38         spinlock_t              lock;
  39         char                    read_write;
  40         u8                      command;
  41         u8                      *transPtr;
  42         int                     readNum;
  43         int                     writeNum;
  44         int                     cur_mode;
  45         int                     manual_stop;
  46         int                     result;
  47         struct i2c_adapter      adap;
  48         struct completion       complete;
  49         struct i2c_msg          *pmsg;
  50         int                     msg_num;
  51         int                     cur_msg;
  52         u16                     saved_clkdiv;
  53         u16                     saved_control;
  54         void __iomem            *regs_base;
  55 };
  56
  57
  58 #define DEFINE_TWI_REG(reg, off) \
  59 static inline u16 read_##reg(struct bfin_twi_iface *iface) \
  60         { return bfin_read16(iface->regs_base + (off)); } \
  61 static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
  62         { bfin_write16(iface->regs_base + (off), v); }
  63
  64 DEFINE_TWI_REG(CLKDIV, 0x00)
  65 DEFINE_TWI_REG(CONTROL, 0x04)
  66 DEFINE_TWI_REG(SLAVE_CTL, 0x08)
  67 DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
  68 DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
  69 DEFINE_TWI_REG(MASTER_CTL, 0x14)
  70 DEFINE_TWI_REG(MASTER_STAT, 0x18)
  71 DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
  72 DEFINE_TWI_REG(INT_STAT, 0x20)
  73 DEFINE_TWI_REG(INT_MASK, 0x24)
  74 DEFINE_TWI_REG(FIFO_CTL, 0x28)
  75 DEFINE_TWI_REG(FIFO_STAT, 0x2C)
  76 DEFINE_TWI_REG(XMT_DATA8, 0x80)
  77 DEFINE_TWI_REG(XMT_DATA16, 0x84)
  78 DEFINE_TWI_REG(RCV_DATA8, 0x88)
  79 DEFINE_TWI_REG(RCV_DATA16, 0x8C)
  80
  81 static const u16 pin_req[2][3] = {
  82         {P_TWI0_SCL, P_TWI0_SDA, 0},
  83         {P_TWI1_SCL, P_TWI1_SDA, 0},
  84 };
  85
  86 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
  87                                         unsigned short twi_int_status)
  88 {
  89         unsigned short mast_stat = read_MASTER_STAT(iface);
  90
  91         if (twi_int_status & XMTSERV) {
  92                 /* Transmit next data */
  93                 if (iface->writeNum > 0) {
  94                         SSYNC();
  95                         write_XMT_DATA8(iface, *(iface->transPtr++));
  96                         iface->writeNum--;
  97                 }
  98                 /* start receive immediately after complete sending in
  99                  * combine mode.
 100                  */
 101                 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
 102                         write_MASTER_CTL(iface,
 103                                 read_MASTER_CTL(iface) | MDIR);
 104                 else if (iface->manual_stop)
 105                         write_MASTER_CTL(iface,
 106                                 read_MASTER_CTL(iface) | STOP);
 107                 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 108                          iface->cur_msg + 1 < iface->msg_num) {
 109                         if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
 110                                 write_MASTER_CTL(iface,
 111                                         read_MASTER_CTL(iface) | MDIR);
 112                         else
 113                                 write_MASTER_CTL(iface,
 114                                         read_MASTER_CTL(iface) & ~MDIR);
 115                 }
 116         }
 117         if (twi_int_status & RCVSERV) {
 118                 if (iface->readNum > 0) {
 119                         /* Receive next data */
 120                         *(iface->transPtr) = read_RCV_DATA8(iface);
 121                         if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 122                                 /* Change combine mode into sub mode after
 123                                  * read first data.
 124                                  */
 125                                 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 126                                 /* Get read number from first byte in block
 127                                  * combine mode.
 128                                  */
 129                                 if (iface->readNum == 1 && iface->manual_stop)
 130                                         iface->readNum = *iface->transPtr + 1;
 131                         }
 132                         iface->transPtr++;
 133                         iface->readNum--;
 134                 }
 135
 136                 if (iface->readNum == 0) {
 137                         if (iface->manual_stop) {
 138                                 /* Temporary workaround to avoid possible bus stall -
 139                                  * Flush FIFO before issuing the STOP condition
 140                                  */
 141                                 read_RCV_DATA16(iface);
 142                                 write_MASTER_CTL(iface,
 143                                         read_MASTER_CTL(iface) | STOP);
 144                         } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 145                                         iface->cur_msg + 1 < iface->msg_num) {
 146                                 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
 147                                         write_MASTER_CTL(iface,
 148                                                 read_MASTER_CTL(iface) | MDIR);
 149                                 else
 150                                         write_MASTER_CTL(iface,
 151                                                 read_MASTER_CTL(iface) & ~MDIR);
 152                         }
 153                 }
 154         }
 155         if (twi_int_status & MERR) {
 156                 write_INT_MASK(iface, 0);
 157                 write_MASTER_STAT(iface, 0x3e);
 158                 write_MASTER_CTL(iface, 0);
 159                 iface->result = -EIO;
 160
 161                 if (mast_stat & LOSTARB)
 162                         dev_dbg(&iface->adap.dev, "Lost Arbitration\n");
 163                 if (mast_stat & ANAK)
 164                         dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n");
 165                 if (mast_stat & DNAK)
 166                         dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n");
 167                 if (mast_stat & BUFRDERR)
 168                         dev_dbg(&iface->adap.dev, "Buffer Read Error\n");
 169                 if (mast_stat & BUFWRERR)
 170                         dev_dbg(&iface->adap.dev, "Buffer Write Error\n");
 171
 172                 /* Faulty slave devices, may drive SDA low after a transfer
 173                  * finishes. To release the bus this code generates up to 9
 174                  * extra clocks until SDA is released.
 175                  */
 176
 177                 if (read_MASTER_STAT(iface) & SDASEN) {
 178                         int cnt = 9;
 179                         do {
 180                                 write_MASTER_CTL(iface, SCLOVR);
 181                                 udelay(6);
 182                                 write_MASTER_CTL(iface, 0);
 183                                 udelay(6);
 184                         } while ((read_MASTER_STAT(iface) & SDASEN) && cnt--);
 185
 186                         write_MASTER_CTL(iface, SDAOVR | SCLOVR);
 187                         udelay(6);
 188                         write_MASTER_CTL(iface, SDAOVR);
 189                         udelay(6);
 190                         write_MASTER_CTL(iface, 0);
 191                 }
 192
 193                 /* If it is a quick transfer, only address without data,
 194                  * not an err, return 1.
 195                  */
 196                 if (iface->cur_mode == TWI_I2C_MODE_STANDARD &&
 197                         iface->transPtr == NULL &&
 198                         (twi_int_status & MCOMP) && (mast_stat & DNAK))
 199                         iface->result = 1;
 200
 201                 complete(&iface->complete);
 202                 return;
 203         }
 204         if (twi_int_status & MCOMP) {
 205                 if (twi_int_status & (XMTSERV | RCVSERV) &&
 206                         (read_MASTER_CTL(iface) & MEN) == 0 &&
 207                         (iface->cur_mode == TWI_I2C_MODE_REPEAT ||
 208                         iface->cur_mode == TWI_I2C_MODE_COMBINED)) {
 209                         iface->result = -1;
 210                         write_INT_MASK(iface, 0);
 211                         write_MASTER_CTL(iface, 0);
 212                 } else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 213                         if (iface->readNum == 0) {
 214                                 /* set the read number to 1 and ask for manual
 215                                  * stop in block combine mode
 216                                  */
 217                                 iface->readNum = 1;
 218                                 iface->manual_stop = 1;
 219                                 write_MASTER_CTL(iface,
 220                                         read_MASTER_CTL(iface) | (0xff << 6));
 221                         } else {
 222                                 /* set the readd number in other
 223                                  * combine mode.
 224                                  */
 225                                 write_MASTER_CTL(iface,
 226                                         (read_MASTER_CTL(iface) &
 227                                         (~(0xff << 6))) |
 228                                         (iface->readNum << 6));
 229                         }
 230                         /* remove restart bit and enable master receive */
 231                         write_MASTER_CTL(iface,
 232                                 read_MASTER_CTL(iface) & ~RSTART);
 233                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 234                                 iface->cur_msg + 1 < iface->msg_num) {
 235                         iface->cur_msg++;
 236                         iface->transPtr = iface->pmsg[iface->cur_msg].buf;
 237                         iface->writeNum = iface->readNum =
 238                                 iface->pmsg[iface->cur_msg].len;
 239                         /* Set Transmit device address */
 240                         write_MASTER_ADDR(iface,
 241                                 iface->pmsg[iface->cur_msg].addr);
 242                         if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
 243                                 iface->read_write = I2C_SMBUS_READ;
 244                         else {
 245                                 iface->read_write = I2C_SMBUS_WRITE;
 246                                 /* Transmit first data */
 247                                 if (iface->writeNum > 0) {
 248                                         write_XMT_DATA8(iface,
 249                                                 *(iface->transPtr++));
 250                                         iface->writeNum--;
 251                                 }
 252                         }
 253
 254                         if (iface->pmsg[iface->cur_msg].len <= 255) {
 255                                 write_MASTER_CTL(iface,
 256                                         (read_MASTER_CTL(iface) &
 257                                         (~(0xff << 6))) |
 258                                         (iface->pmsg[iface->cur_msg].len << 6));
 259                                 iface->manual_stop = 0;
 260                         } else {
 261                                 write_MASTER_CTL(iface,
 262                                         (read_MASTER_CTL(iface) |
 263                                         (0xff << 6)));
 264                                 iface->manual_stop = 1;
 265                         }
 266                         /* remove restart bit before last message */
 267                         if (iface->cur_msg + 1 == iface->msg_num)
 268                                 write_MASTER_CTL(iface,
 269                                         read_MASTER_CTL(iface) & ~RSTART);
 270                 } else {
 271                         iface->result = 1;
 272                         write_INT_MASK(iface, 0);
 273                         write_MASTER_CTL(iface, 0);
 274                 }
 275                 complete(&iface->complete);
 276         }
 277 }
 278
 279 /* Interrupt handler */
 280 static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
 281 {
 282         struct bfin_twi_iface *iface = dev_id;
 283         unsigned long flags;
 284         unsigned short twi_int_status;
 285
 286         spin_lock_irqsave(&iface->lock, flags);
 287         while (1) {
 288                 twi_int_status = read_INT_STAT(iface);
 289                 if (!twi_int_status)
 290                         break;
 291                 /* Clear interrupt status */
 292                 write_INT_STAT(iface, twi_int_status);
 293                 bfin_twi_handle_interrupt(iface, twi_int_status);
 294                 SSYNC();
 295         }
 296         spin_unlock_irqrestore(&iface->lock, flags);
 297         return IRQ_HANDLED;
 298 }
 299
 300 /*
 301  * One i2c master transfer
 302  */
 303 static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
 304                                 struct i2c_msg *msgs, int num)
 305 {
 306         struct bfin_twi_iface *iface = adap->algo_data;
 307         struct i2c_msg *pmsg;
 308         int rc = 0;
 309
 310         if (!(read_CONTROL(iface) & TWI_ENA))
 311                 return -ENXIO;
 312
 313         if (read_MASTER_STAT(iface) & BUSBUSY)
 314                 return -EAGAIN;
 315
 316         iface->pmsg = msgs;
 317         iface->msg_num = num;
 318         iface->cur_msg = 0;
 319
 320         pmsg = &msgs[0];
 321         if (pmsg->flags & I2C_M_TEN) {
 322                 dev_err(&adap->dev, "10 bits addr not supported!\n");
 323                 return -EINVAL;
 324         }
 325
 326         if (iface->msg_num > 1)
 327                 iface->cur_mode = TWI_I2C_MODE_REPEAT;
 328         iface->manual_stop = 0;
 329         iface->transPtr = pmsg->buf;
 330         iface->writeNum = iface->readNum = pmsg->len;
 331         iface->result = 0;
 332         init_completion(&(iface->complete));
 333         /* Set Transmit device address */
 334         write_MASTER_ADDR(iface, pmsg->addr);
 335
 336         /* FIFO Initiation. Data in FIFO should be
 337          *  discarded before start a new operation.
 338          */
 339         write_FIFO_CTL(iface, 0x3);
 340         SSYNC();
 341         write_FIFO_CTL(iface, 0);
 342         SSYNC();
 343
 344         if (pmsg->flags & I2C_M_RD)
 345                 iface->read_write = I2C_SMBUS_READ;
 346         else {
 347                 iface->read_write = I2C_SMBUS_WRITE;
 348                 /* Transmit first data */
 349                 if (iface->writeNum > 0) {
 350                         write_XMT_DATA8(iface, *(iface->transPtr++));
 351                         iface->writeNum--;
 352                         SSYNC();
 353                 }
 354         }
 355
 356         /* clear int stat */
 357         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 358
 359         /* Interrupt mask . Enable XMT, RCV interrupt */
 360         write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 361         SSYNC();
 362
 363         if (pmsg->len <= 255)
 364                 write_MASTER_CTL(iface, pmsg->len << 6);
 365         else {
 366                 write_MASTER_CTL(iface, 0xff << 6);
 367                 iface->manual_stop = 1;
 368         }
 369
 370         /* Master enable */
 371         write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 372                 (iface->msg_num > 1 ? RSTART : 0) |
 373                 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 374                 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 375         SSYNC();
 376
 377         while (!iface->result) {
 378                 if (!wait_for_completion_timeout(&iface->complete,
 379                         adap->timeout)) {
 380                         iface->result = -1;
 381                         dev_err(&adap->dev, "master transfer timeout\n");
 382                 }
 383         }
 384
 385         if (iface->result == 1)
 386                 rc = iface->cur_msg + 1;
 387         else
 388                 rc = iface->result;
 389
 390         return rc;
 391 }
 392
 393 /*
 394  * Generic i2c master transfer entrypoint
 395  */
 396 static int bfin_twi_master_xfer(struct i2c_adapter *adap,
 397                                 struct i2c_msg *msgs, int num)
 398 {
 399         return bfin_twi_do_master_xfer(adap, msgs, num);
 400 }
 401
 402 /*
 403  * One I2C SMBus transfer
 404  */
 405 int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 406                         unsigned short flags, char read_write,
 407                         u8 command, int size, union i2c_smbus_data *data)
 408 {
 409         struct bfin_twi_iface *iface = adap->algo_data;
 410         int rc = 0;
 411
 412         if (!(read_CONTROL(iface) & TWI_ENA))
 413                 return -ENXIO;
 414
 415         if (read_MASTER_STAT(iface) & BUSBUSY)
 416                 return -EAGAIN;
 417
 418         iface->writeNum = 0;
 419         iface->readNum = 0;
 420
 421         /* Prepare datas & select mode */
 422         switch (size) {
 423         case I2C_SMBUS_QUICK:
 424                 iface->transPtr = NULL;
 425                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 426                 break;
 427         case I2C_SMBUS_BYTE:
 428                 if (data == NULL)
 429                         iface->transPtr = NULL;
 430                 else {
 431                         if (read_write == I2C_SMBUS_READ)
 432                                 iface->readNum = 1;
 433                         else
 434                                 iface->writeNum = 1;
 435                         iface->transPtr = &data->byte;
 436                 }
 437                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 438                 break;
 439         case I2C_SMBUS_BYTE_DATA:
 440                 if (read_write == I2C_SMBUS_READ) {
 441                         iface->readNum = 1;
 442                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 443                 } else {
 444                         iface->writeNum = 1;
 445                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 446                 }
 447                 iface->transPtr = &data->byte;
 448                 break;
 449         case I2C_SMBUS_WORD_DATA:
 450                 if (read_write == I2C_SMBUS_READ) {
 451                         iface->readNum = 2;
 452                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 453                 } else {
 454                         iface->writeNum = 2;
 455                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 456                 }
 457                 iface->transPtr = (u8 *)&data->word;
 458                 break;
 459         case I2C_SMBUS_PROC_CALL:
 460                 iface->writeNum = 2;
 461                 iface->readNum = 2;
 462                 iface->cur_mode = TWI_I2C_MODE_COMBINED;
 463                 iface->transPtr = (u8 *)&data->word;
 464                 break;
 465         case I2C_SMBUS_BLOCK_DATA:
 466                 if (read_write == I2C_SMBUS_READ) {
 467                         iface->readNum = 0;
 468                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 469                 } else {
 470                         iface->writeNum = data->block[0] + 1;
 471                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 472                 }
 473                 iface->transPtr = data->block;
 474                 break;
 475         case I2C_SMBUS_I2C_BLOCK_DATA:
 476                 if (read_write == I2C_SMBUS_READ) {
 477                         iface->readNum = data->block[0];
 478                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 479                 } else {
 480                         iface->writeNum = data->block[0];
 481                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 482                 }
 483                 iface->transPtr = (u8 *)&data->block[1];
 484                 break;
 485         default:
 486                 return -1;
 487         }
 488
 489         iface->result = 0;
 490         iface->manual_stop = 0;
 491         iface->read_write = read_write;
 492         iface->command = command;
 493         init_completion(&(iface->complete));
 494
 495         /* FIFO Initiation. Data in FIFO should be discarded before
 496          * start a new operation.
 497          */
 498         write_FIFO_CTL(iface, 0x3);
 499         SSYNC();
 500         write_FIFO_CTL(iface, 0);
 501
 502         /* clear int stat */
 503         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 504
 505         /* Set Transmit device address */
 506         write_MASTER_ADDR(iface, addr);
 507         SSYNC();
 508
 509         switch (iface->cur_mode) {
 510         case TWI_I2C_MODE_STANDARDSUB:
 511                 write_XMT_DATA8(iface, iface->command);
 512                 write_INT_MASK(iface, MCOMP | MERR |
 513                         ((iface->read_write == I2C_SMBUS_READ) ?
 514                         RCVSERV : XMTSERV));
 515                 SSYNC();
 516
 517                 if (iface->writeNum + 1 <= 255)
 518                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 519                 else {
 520                         write_MASTER_CTL(iface, 0xff << 6);
 521                         iface->manual_stop = 1;
 522                 }
 523                 /* Master enable */
 524                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 525                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 526                 break;
 527         case TWI_I2C_MODE_COMBINED:
 528                 write_XMT_DATA8(iface, iface->command);
 529                 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 530                 SSYNC();
 531
 532                 if (iface->writeNum > 0)
 533                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 534                 else
 535                         write_MASTER_CTL(iface, 0x1 << 6);
 536                 /* Master enable */
 537                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | RSTART |
 538                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 539                 break;
 540         default:
 541                 write_MASTER_CTL(iface, 0);
 542                 if (size != I2C_SMBUS_QUICK) {
 543                         /* Don't access xmit data register when this is a
 544                          * read operation.
 545                          */
 546                         if (iface->read_write != I2C_SMBUS_READ) {
 547                                 if (iface->writeNum > 0) {
 548                                         write_XMT_DATA8(iface,
 549                                                 *(iface->transPtr++));
 550                                         if (iface->writeNum <= 255)
 551                                                 write_MASTER_CTL(iface,
 552                                                         iface->writeNum << 6);
 553                                         else {
 554                                                 write_MASTER_CTL(iface,
 555                                                         0xff << 6);
 556                                                 iface->manual_stop = 1;
 557                                         }
 558                                         iface->writeNum--;
 559                                 } else {
 560                                         write_XMT_DATA8(iface, iface->command);
 561                                         write_MASTER_CTL(iface, 1 << 6);
 562                                 }
 563                         } else {
 564                                 if (iface->readNum > 0 && iface->readNum <= 255)
 565                                         write_MASTER_CTL(iface,
 566                                                 iface->readNum << 6);
 567                                 else if (iface->readNum > 255) {
 568                                         write_MASTER_CTL(iface, 0xff << 6);
 569                                         iface->manual_stop = 1;
 570                                 } else
 571                                         break;
 572                         }
 573                 }
 574                 write_INT_MASK(iface, MCOMP | MERR |
 575                         ((iface->read_write == I2C_SMBUS_READ) ?
 576                         RCVSERV : XMTSERV));
 577                 SSYNC();
 578
 579                 /* Master enable */
 580                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 581                         ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 582                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 583                 break;
 584         }
 585         SSYNC();
 586
 587         while (!iface->result) {
 588                 if (!wait_for_completion_timeout(&iface->complete,
 589                         adap->timeout)) {
 590                         iface->result = -1;
 591                         dev_err(&adap->dev, "smbus transfer timeout\n");
 592                 }
 593         }
 594
 595         rc = (iface->result >= 0) ? 0 : -1;
 596
 597         return rc;
 598 }
 599
 600 /*
 601  * Generic I2C SMBus transfer entrypoint
 602  */
 603 int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 604                         unsigned short flags, char read_write,
 605                         u8 command, int size, union i2c_smbus_data *data)
 606 {
 607         return bfin_twi_do_smbus_xfer(adap, addr, flags,
 608                         read_write, command, size, data);
 609 }
 610
 611 /*
 612  * Return what the adapter supports
 613  */
 614 static u32 bfin_twi_functionality(struct i2c_adapter *adap)
 615 {
 616         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 617                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 618                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
 619                I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
 620 }
 621
 622 static struct i2c_algorithm bfin_twi_algorithm = {
 623         .master_xfer   = bfin_twi_master_xfer,
 624         .smbus_xfer    = bfin_twi_smbus_xfer,
 625         .functionality = bfin_twi_functionality,
 626 };
 627
 628 static int i2c_bfin_twi_suspend(struct device *dev)
 629 {
 630         struct bfin_twi_iface *iface = dev_get_drvdata(dev);
 631
 632         iface->saved_clkdiv = read_CLKDIV(iface);
 633         iface->saved_control = read_CONTROL(iface);
 634
 635         free_irq(iface->irq, iface);
 636
 637         /* Disable TWI */
 638         write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
 639
 640         return 0;
 641 }
 642
 643 static int i2c_bfin_twi_resume(struct device *dev)
 644 {
 645         struct bfin_twi_iface *iface = dev_get_drvdata(dev);
 646
 647         int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
 648                 0, to_platform_device(dev)->name, iface);
 649         if (rc) {
 650                 dev_err(dev, "Can't get IRQ %d !\n", iface->irq);
 651                 return -ENODEV;
 652         }
 653
 654         /* Resume TWI interface clock as specified */
 655         write_CLKDIV(iface, iface->saved_clkdiv);
 656
 657         /* Resume TWI */
 658         write_CONTROL(iface, iface->saved_control);
 659
 660         return 0;
 661 }
 662
 663 static SIMPLE_DEV_PM_OPS(i2c_bfin_twi_pm,
 664                          i2c_bfin_twi_suspend, i2c_bfin_twi_resume);
 665
 666 static int i2c_bfin_twi_probe(struct platform_device *pdev)
 667 {
 668         struct bfin_twi_iface *iface;
 669         struct i2c_adapter *p_adap;
 670         struct resource *res;
 671         int rc;
 672         unsigned int clkhilow;
 673
 674         iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
 675         if (!iface) {
 676                 dev_err(&pdev->dev, "Cannot allocate memory\n");
 677                 rc = -ENOMEM;
 678                 goto out_error_nomem;
 679         }
 680
 681         spin_lock_init(&(iface->lock));
 682
 683         /* Find and map our resources */
 684         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 685         if (res == NULL) {
 686                 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
 687                 rc = -ENOENT;
 688                 goto out_error_get_res;
 689         }
 690
 691         iface->regs_base = ioremap(res->start, resource_size(res));
 692         if (iface->regs_base == NULL) {
 693                 dev_err(&pdev->dev, "Cannot map IO\n");
 694                 rc = -ENXIO;
 695                 goto out_error_ioremap;
 696         }
 697
 698         iface->irq = platform_get_irq(pdev, 0);
 699         if (iface->irq < 0) {
 700                 dev_err(&pdev->dev, "No IRQ specified\n");
 701                 rc = -ENOENT;
 702                 goto out_error_no_irq;
 703         }
 704
 705         p_adap = &iface->adap;
 706         p_adap->nr = pdev->id;
 707         strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
 708         p_adap->algo = &bfin_twi_algorithm;
 709         p_adap->algo_data = iface;
 710         p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 711         p_adap->dev.parent = &pdev->dev;
 712         p_adap->timeout = 5 * HZ;
 713         p_adap->retries = 3;
 714
 715         rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
 716         if (rc) {
 717                 dev_err(&pdev->dev, "Can't setup pin mux!\n");
 718                 goto out_error_pin_mux;
 719         }
 720
 721         rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
 722                 0, pdev->name, iface);
 723         if (rc) {
 724                 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
 725                 rc = -ENODEV;
 726                 goto out_error_req_irq;
 727         }
 728
 729         /* Set TWI internal clock as 10MHz */
 730         write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
 731
 732         /*
 733          * We will not end up with a CLKDIV=0 because no one will specify
 734          * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
 735          */
 736         clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
 737
 738         /* Set Twi interface clock as specified */
 739         write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
 740
 741         /* Enable TWI */
 742         write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
 743         SSYNC();
 744
 745         rc = i2c_add_numbered_adapter(p_adap);
 746         if (rc < 0) {
 747                 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
 748                 goto out_error_add_adapter;
 749         }
 750
 751         platform_set_drvdata(pdev, iface);
 752
 753         dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
 754                 "regs_base@%p\n", iface->regs_base);
 755
 756         return 0;
 757
 758 out_error_add_adapter:
 759         free_irq(iface->irq, iface);
 760 out_error_req_irq:
 761 out_error_no_irq:
 762         peripheral_free_list(pin_req[pdev->id]);
 763 out_error_pin_mux:
 764         iounmap(iface->regs_base);
 765 out_error_ioremap:
 766 out_error_get_res:
 767         kfree(iface);
 768 out_error_nomem:
 769         return rc;
 770 }
 771
 772 static int i2c_bfin_twi_remove(struct platform_device *pdev)
 773 {
 774         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 775
 776         platform_set_drvdata(pdev, NULL);
 777
 778         i2c_del_adapter(&(iface->adap));
 779         free_irq(iface->irq, iface);
 780         peripheral_free_list(pin_req[pdev->id]);
 781         iounmap(iface->regs_base);
 782         kfree(iface);
 783
 784         return 0;
 785 }
 786
 787 static struct platform_driver i2c_bfin_twi_driver = {
 788         .probe          = i2c_bfin_twi_probe,
 789         .remove         = i2c_bfin_twi_remove,
 790         .driver         = {
 791                 .name   = "i2c-bfin-twi",
 792                 .owner  = THIS_MODULE,
 793                 .pm     = &i2c_bfin_twi_pm,
 794         },
 795 };
 796
 797 static int __init i2c_bfin_twi_init(void)
 798 {
 799         return platform_driver_register(&i2c_bfin_twi_driver);
 800 }
 801
 802 static void __exit i2c_bfin_twi_exit(void)
 803 {
 804         platform_driver_unregister(&i2c_bfin_twi_driver);
 805 }
 806
 807 subsys_initcall(i2c_bfin_twi_init);
 808 module_exit(i2c_bfin_twi_exit);
 809
 810 MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
 811 MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
 812 MODULE_LICENSE("GPL");
 813 MODULE_ALIAS("platform:i2c-bfin-twi");