Pileus Git - ~andy/linux/blob - drivers/i2c/busses/i2c-bfin-twi.c

   1 /*
   2  * Blackfin On-Chip Two Wire Interface Driver
   3  *
   4  * Copyright 2005-2007 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/i2c.h>
  15 #include <linux/slab.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/timer.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/delay.h>
  24
  25 #include <asm/blackfin.h>
  26 #include <asm/portmux.h>
  27 #include <asm/irq.h>
  28 #include <asm/bfin_twi.h>
  29
  30 /* SMBus mode*/
  31 #define TWI_I2C_MODE_STANDARD           1
  32 #define TWI_I2C_MODE_STANDARDSUB        2
  33 #define TWI_I2C_MODE_COMBINED           3
  34 #define TWI_I2C_MODE_REPEAT             4
  35
  36 struct bfin_twi_iface {
  37         int                     irq;
  38         spinlock_t              lock;
  39         char                    read_write;
  40         u8                      command;
  41         u8                      *transPtr;
  42         int                     readNum;
  43         int                     writeNum;
  44         int                     cur_mode;
  45         int                     manual_stop;
  46         int                     result;
  47         struct i2c_adapter      adap;
  48         struct completion       complete;
  49         struct i2c_msg          *pmsg;
  50         int                     msg_num;
  51         int                     cur_msg;
  52         u16                     saved_clkdiv;
  53         u16                     saved_control;
  54         void __iomem            *regs_base;
  55 };
  56
  57
  58 #define DEFINE_TWI_REG(reg, off) \
  59 static inline u16 read_##reg(struct bfin_twi_iface *iface) \
  60         { return bfin_read16(iface->regs_base + (off)); } \
  61 static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
  62         { bfin_write16(iface->regs_base + (off), v); }
  63
  64 DEFINE_TWI_REG(CLKDIV, 0x00)
  65 DEFINE_TWI_REG(CONTROL, 0x04)
  66 DEFINE_TWI_REG(SLAVE_CTL, 0x08)
  67 DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
  68 DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
  69 DEFINE_TWI_REG(MASTER_CTL, 0x14)
  70 DEFINE_TWI_REG(MASTER_STAT, 0x18)
  71 DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
  72 DEFINE_TWI_REG(INT_STAT, 0x20)
  73 DEFINE_TWI_REG(INT_MASK, 0x24)
  74 DEFINE_TWI_REG(FIFO_CTL, 0x28)
  75 DEFINE_TWI_REG(FIFO_STAT, 0x2C)
  76 DEFINE_TWI_REG(XMT_DATA8, 0x80)
  77 DEFINE_TWI_REG(XMT_DATA16, 0x84)
  78 DEFINE_TWI_REG(RCV_DATA8, 0x88)
  79 DEFINE_TWI_REG(RCV_DATA16, 0x8C)
  80
  81 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
  82                                         unsigned short twi_int_status)
  83 {
  84         unsigned short mast_stat = read_MASTER_STAT(iface);
  85
  86         if (twi_int_status & XMTSERV) {
  87                 /* Transmit next data */
  88                 if (iface->writeNum > 0) {
  89                         SSYNC();
  90                         write_XMT_DATA8(iface, *(iface->transPtr++));
  91                         iface->writeNum--;
  92                 }
  93                 /* start receive immediately after complete sending in
  94                  * combine mode.
  95                  */
  96                 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
  97                         write_MASTER_CTL(iface,
  98                                 read_MASTER_CTL(iface) | MDIR);
  99                 else if (iface->manual_stop)
 100                         write_MASTER_CTL(iface,
 101                                 read_MASTER_CTL(iface) | STOP);
 102                 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 103                          iface->cur_msg + 1 < iface->msg_num) {
 104                         if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
 105                                 write_MASTER_CTL(iface,
 106                                         read_MASTER_CTL(iface) | MDIR);
 107                         else
 108                                 write_MASTER_CTL(iface,
 109                                         read_MASTER_CTL(iface) & ~MDIR);
 110                 }
 111         }
 112         if (twi_int_status & RCVSERV) {
 113                 if (iface->readNum > 0) {
 114                         /* Receive next data */
 115                         *(iface->transPtr) = read_RCV_DATA8(iface);
 116                         if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 117                                 /* Change combine mode into sub mode after
 118                                  * read first data.
 119                                  */
 120                                 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 121                                 /* Get read number from first byte in block
 122                                  * combine mode.
 123                                  */
 124                                 if (iface->readNum == 1 && iface->manual_stop)
 125                                         iface->readNum = *iface->transPtr + 1;
 126                         }
 127                         iface->transPtr++;
 128                         iface->readNum--;
 129                 }
 130
 131                 if (iface->readNum == 0) {
 132                         if (iface->manual_stop) {
 133                                 /* Temporary workaround to avoid possible bus stall -
 134                                  * Flush FIFO before issuing the STOP condition
 135                                  */
 136                                 read_RCV_DATA16(iface);
 137                                 write_MASTER_CTL(iface,
 138                                         read_MASTER_CTL(iface) | STOP);
 139                         } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 140                                         iface->cur_msg + 1 < iface->msg_num) {
 141                                 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
 142                                         write_MASTER_CTL(iface,
 143                                                 read_MASTER_CTL(iface) | MDIR);
 144                                 else
 145                                         write_MASTER_CTL(iface,
 146                                                 read_MASTER_CTL(iface) & ~MDIR);
 147                         }
 148                 }
 149         }
 150         if (twi_int_status & MERR) {
 151                 write_INT_MASK(iface, 0);
 152                 write_MASTER_STAT(iface, 0x3e);
 153                 write_MASTER_CTL(iface, 0);
 154                 iface->result = -EIO;
 155
 156                 if (mast_stat & LOSTARB)
 157                         dev_dbg(&iface->adap.dev, "Lost Arbitration\n");
 158                 if (mast_stat & ANAK)
 159                         dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n");
 160                 if (mast_stat & DNAK)
 161                         dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n");
 162                 if (mast_stat & BUFRDERR)
 163                         dev_dbg(&iface->adap.dev, "Buffer Read Error\n");
 164                 if (mast_stat & BUFWRERR)
 165                         dev_dbg(&iface->adap.dev, "Buffer Write Error\n");
 166
 167                 /* Faulty slave devices, may drive SDA low after a transfer
 168                  * finishes. To release the bus this code generates up to 9
 169                  * extra clocks until SDA is released.
 170                  */
 171
 172                 if (read_MASTER_STAT(iface) & SDASEN) {
 173                         int cnt = 9;
 174                         do {
 175                                 write_MASTER_CTL(iface, SCLOVR);
 176                                 udelay(6);
 177                                 write_MASTER_CTL(iface, 0);
 178                                 udelay(6);
 179                         } while ((read_MASTER_STAT(iface) & SDASEN) && cnt--);
 180
 181                         write_MASTER_CTL(iface, SDAOVR | SCLOVR);
 182                         udelay(6);
 183                         write_MASTER_CTL(iface, SDAOVR);
 184                         udelay(6);
 185                         write_MASTER_CTL(iface, 0);
 186                 }
 187
 188                 /* If it is a quick transfer, only address without data,
 189                  * not an err, return 1.
 190                  */
 191                 if (iface->cur_mode == TWI_I2C_MODE_STANDARD &&
 192                         iface->transPtr == NULL &&
 193                         (twi_int_status & MCOMP) && (mast_stat & DNAK))
 194                         iface->result = 1;
 195
 196                 complete(&iface->complete);
 197                 return;
 198         }
 199         if (twi_int_status & MCOMP) {
 200                 if (twi_int_status & (XMTSERV | RCVSERV) &&
 201                         (read_MASTER_CTL(iface) & MEN) == 0 &&
 202                         (iface->cur_mode == TWI_I2C_MODE_REPEAT ||
 203                         iface->cur_mode == TWI_I2C_MODE_COMBINED)) {
 204                         iface->result = -1;
 205                         write_INT_MASK(iface, 0);
 206                         write_MASTER_CTL(iface, 0);
 207                 } else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 208                         if (iface->readNum == 0) {
 209                                 /* set the read number to 1 and ask for manual
 210                                  * stop in block combine mode
 211                                  */
 212                                 iface->readNum = 1;
 213                                 iface->manual_stop = 1;
 214                                 write_MASTER_CTL(iface,
 215                                         read_MASTER_CTL(iface) | (0xff << 6));
 216                         } else {
 217                                 /* set the readd number in other
 218                                  * combine mode.
 219                                  */
 220                                 write_MASTER_CTL(iface,
 221                                         (read_MASTER_CTL(iface) &
 222                                         (~(0xff << 6))) |
 223                                         (iface->readNum << 6));
 224                         }
 225                         /* remove restart bit and enable master receive */
 226                         write_MASTER_CTL(iface,
 227                                 read_MASTER_CTL(iface) & ~RSTART);
 228                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 229                                 iface->cur_msg + 1 < iface->msg_num) {
 230                         iface->cur_msg++;
 231                         iface->transPtr = iface->pmsg[iface->cur_msg].buf;
 232                         iface->writeNum = iface->readNum =
 233                                 iface->pmsg[iface->cur_msg].len;
 234                         /* Set Transmit device address */
 235                         write_MASTER_ADDR(iface,
 236                                 iface->pmsg[iface->cur_msg].addr);
 237                         if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
 238                                 iface->read_write = I2C_SMBUS_READ;
 239                         else {
 240                                 iface->read_write = I2C_SMBUS_WRITE;
 241                                 /* Transmit first data */
 242                                 if (iface->writeNum > 0) {
 243                                         write_XMT_DATA8(iface,
 244                                                 *(iface->transPtr++));
 245                                         iface->writeNum--;
 246                                 }
 247                         }
 248
 249                         if (iface->pmsg[iface->cur_msg].len <= 255) {
 250                                 write_MASTER_CTL(iface,
 251                                         (read_MASTER_CTL(iface) &
 252                                         (~(0xff << 6))) |
 253                                         (iface->pmsg[iface->cur_msg].len << 6));
 254                                 iface->manual_stop = 0;
 255                         } else {
 256                                 write_MASTER_CTL(iface,
 257                                         (read_MASTER_CTL(iface) |
 258                                         (0xff << 6)));
 259                                 iface->manual_stop = 1;
 260                         }
 261                         /* remove restart bit before last message */
 262                         if (iface->cur_msg + 1 == iface->msg_num)
 263                                 write_MASTER_CTL(iface,
 264                                         read_MASTER_CTL(iface) & ~RSTART);
 265                 } else {
 266                         iface->result = 1;
 267                         write_INT_MASK(iface, 0);
 268                         write_MASTER_CTL(iface, 0);
 269                 }
 270                 complete(&iface->complete);
 271         }
 272 }
 273
 274 /* Interrupt handler */
 275 static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
 276 {
 277         struct bfin_twi_iface *iface = dev_id;
 278         unsigned long flags;
 279         unsigned short twi_int_status;
 280
 281         spin_lock_irqsave(&iface->lock, flags);
 282         while (1) {
 283                 twi_int_status = read_INT_STAT(iface);
 284                 if (!twi_int_status)
 285                         break;
 286                 /* Clear interrupt status */
 287                 write_INT_STAT(iface, twi_int_status);
 288                 bfin_twi_handle_interrupt(iface, twi_int_status);
 289                 SSYNC();
 290         }
 291         spin_unlock_irqrestore(&iface->lock, flags);
 292         return IRQ_HANDLED;
 293 }
 294
 295 /*
 296  * One i2c master transfer
 297  */
 298 static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
 299                                 struct i2c_msg *msgs, int num)
 300 {
 301         struct bfin_twi_iface *iface = adap->algo_data;
 302         struct i2c_msg *pmsg;
 303         int rc = 0;
 304
 305         if (!(read_CONTROL(iface) & TWI_ENA))
 306                 return -ENXIO;
 307
 308         if (read_MASTER_STAT(iface) & BUSBUSY)
 309                 return -EAGAIN;
 310
 311         iface->pmsg = msgs;
 312         iface->msg_num = num;
 313         iface->cur_msg = 0;
 314
 315         pmsg = &msgs[0];
 316         if (pmsg->flags & I2C_M_TEN) {
 317                 dev_err(&adap->dev, "10 bits addr not supported!\n");
 318                 return -EINVAL;
 319         }
 320
 321         if (iface->msg_num > 1)
 322                 iface->cur_mode = TWI_I2C_MODE_REPEAT;
 323         iface->manual_stop = 0;
 324         iface->transPtr = pmsg->buf;
 325         iface->writeNum = iface->readNum = pmsg->len;
 326         iface->result = 0;
 327         init_completion(&(iface->complete));
 328         /* Set Transmit device address */
 329         write_MASTER_ADDR(iface, pmsg->addr);
 330
 331         /* FIFO Initiation. Data in FIFO should be
 332          *  discarded before start a new operation.
 333          */
 334         write_FIFO_CTL(iface, 0x3);
 335         SSYNC();
 336         write_FIFO_CTL(iface, 0);
 337         SSYNC();
 338
 339         if (pmsg->flags & I2C_M_RD)
 340                 iface->read_write = I2C_SMBUS_READ;
 341         else {
 342                 iface->read_write = I2C_SMBUS_WRITE;
 343                 /* Transmit first data */
 344                 if (iface->writeNum > 0) {
 345                         write_XMT_DATA8(iface, *(iface->transPtr++));
 346                         iface->writeNum--;
 347                         SSYNC();
 348                 }
 349         }
 350
 351         /* clear int stat */
 352         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 353
 354         /* Interrupt mask . Enable XMT, RCV interrupt */
 355         write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 356         SSYNC();
 357
 358         if (pmsg->len <= 255)
 359                 write_MASTER_CTL(iface, pmsg->len << 6);
 360         else {
 361                 write_MASTER_CTL(iface, 0xff << 6);
 362                 iface->manual_stop = 1;
 363         }
 364
 365         /* Master enable */
 366         write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 367                 (iface->msg_num > 1 ? RSTART : 0) |
 368                 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 369                 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 370         SSYNC();
 371
 372         while (!iface->result) {
 373                 if (!wait_for_completion_timeout(&iface->complete,
 374                         adap->timeout)) {
 375                         iface->result = -1;
 376                         dev_err(&adap->dev, "master transfer timeout\n");
 377                 }
 378         }
 379
 380         if (iface->result == 1)
 381                 rc = iface->cur_msg + 1;
 382         else
 383                 rc = iface->result;
 384
 385         return rc;
 386 }
 387
 388 /*
 389  * Generic i2c master transfer entrypoint
 390  */
 391 static int bfin_twi_master_xfer(struct i2c_adapter *adap,
 392                                 struct i2c_msg *msgs, int num)
 393 {
 394         return bfin_twi_do_master_xfer(adap, msgs, num);
 395 }
 396
 397 /*
 398  * One I2C SMBus transfer
 399  */
 400 int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 401                         unsigned short flags, char read_write,
 402                         u8 command, int size, union i2c_smbus_data *data)
 403 {
 404         struct bfin_twi_iface *iface = adap->algo_data;
 405         int rc = 0;
 406
 407         if (!(read_CONTROL(iface) & TWI_ENA))
 408                 return -ENXIO;
 409
 410         if (read_MASTER_STAT(iface) & BUSBUSY)
 411                 return -EAGAIN;
 412
 413         iface->writeNum = 0;
 414         iface->readNum = 0;
 415
 416         /* Prepare datas & select mode */
 417         switch (size) {
 418         case I2C_SMBUS_QUICK:
 419                 iface->transPtr = NULL;
 420                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 421                 break;
 422         case I2C_SMBUS_BYTE:
 423                 if (data == NULL)
 424                         iface->transPtr = NULL;
 425                 else {
 426                         if (read_write == I2C_SMBUS_READ)
 427                                 iface->readNum = 1;
 428                         else
 429                                 iface->writeNum = 1;
 430                         iface->transPtr = &data->byte;
 431                 }
 432                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 433                 break;
 434         case I2C_SMBUS_BYTE_DATA:
 435                 if (read_write == I2C_SMBUS_READ) {
 436                         iface->readNum = 1;
 437                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 438                 } else {
 439                         iface->writeNum = 1;
 440                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 441                 }
 442                 iface->transPtr = &data->byte;
 443                 break;
 444         case I2C_SMBUS_WORD_DATA:
 445                 if (read_write == I2C_SMBUS_READ) {
 446                         iface->readNum = 2;
 447                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 448                 } else {
 449                         iface->writeNum = 2;
 450                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 451                 }
 452                 iface->transPtr = (u8 *)&data->word;
 453                 break;
 454         case I2C_SMBUS_PROC_CALL:
 455                 iface->writeNum = 2;
 456                 iface->readNum = 2;
 457                 iface->cur_mode = TWI_I2C_MODE_COMBINED;
 458                 iface->transPtr = (u8 *)&data->word;
 459                 break;
 460         case I2C_SMBUS_BLOCK_DATA:
 461                 if (read_write == I2C_SMBUS_READ) {
 462                         iface->readNum = 0;
 463                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 464                 } else {
 465                         iface->writeNum = data->block[0] + 1;
 466                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 467                 }
 468                 iface->transPtr = data->block;
 469                 break;
 470         case I2C_SMBUS_I2C_BLOCK_DATA:
 471                 if (read_write == I2C_SMBUS_READ) {
 472                         iface->readNum = data->block[0];
 473                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 474                 } else {
 475                         iface->writeNum = data->block[0];
 476                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 477                 }
 478                 iface->transPtr = (u8 *)&data->block[1];
 479                 break;
 480         default:
 481                 return -1;
 482         }
 483
 484         iface->result = 0;
 485         iface->manual_stop = 0;
 486         iface->read_write = read_write;
 487         iface->command = command;
 488         init_completion(&(iface->complete));
 489
 490         /* FIFO Initiation. Data in FIFO should be discarded before
 491          * start a new operation.
 492          */
 493         write_FIFO_CTL(iface, 0x3);
 494         SSYNC();
 495         write_FIFO_CTL(iface, 0);
 496
 497         /* clear int stat */
 498         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 499
 500         /* Set Transmit device address */
 501         write_MASTER_ADDR(iface, addr);
 502         SSYNC();
 503
 504         switch (iface->cur_mode) {
 505         case TWI_I2C_MODE_STANDARDSUB:
 506                 write_XMT_DATA8(iface, iface->command);
 507                 write_INT_MASK(iface, MCOMP | MERR |
 508                         ((iface->read_write == I2C_SMBUS_READ) ?
 509                         RCVSERV : XMTSERV));
 510                 SSYNC();
 511
 512                 if (iface->writeNum + 1 <= 255)
 513                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 514                 else {
 515                         write_MASTER_CTL(iface, 0xff << 6);
 516                         iface->manual_stop = 1;
 517                 }
 518                 /* Master enable */
 519                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 520                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 521                 break;
 522         case TWI_I2C_MODE_COMBINED:
 523                 write_XMT_DATA8(iface, iface->command);
 524                 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 525                 SSYNC();
 526
 527                 if (iface->writeNum > 0)
 528                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 529                 else
 530                         write_MASTER_CTL(iface, 0x1 << 6);
 531                 /* Master enable */
 532                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | RSTART |
 533                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 534                 break;
 535         default:
 536                 write_MASTER_CTL(iface, 0);
 537                 if (size != I2C_SMBUS_QUICK) {
 538                         /* Don't access xmit data register when this is a
 539                          * read operation.
 540                          */
 541                         if (iface->read_write != I2C_SMBUS_READ) {
 542                                 if (iface->writeNum > 0) {
 543                                         write_XMT_DATA8(iface,
 544                                                 *(iface->transPtr++));
 545                                         if (iface->writeNum <= 255)
 546                                                 write_MASTER_CTL(iface,
 547                                                         iface->writeNum << 6);
 548                                         else {
 549                                                 write_MASTER_CTL(iface,
 550                                                         0xff << 6);
 551                                                 iface->manual_stop = 1;
 552                                         }
 553                                         iface->writeNum--;
 554                                 } else {
 555                                         write_XMT_DATA8(iface, iface->command);
 556                                         write_MASTER_CTL(iface, 1 << 6);
 557                                 }
 558                         } else {
 559                                 if (iface->readNum > 0 && iface->readNum <= 255)
 560                                         write_MASTER_CTL(iface,
 561                                                 iface->readNum << 6);
 562                                 else if (iface->readNum > 255) {
 563                                         write_MASTER_CTL(iface, 0xff << 6);
 564                                         iface->manual_stop = 1;
 565                                 } else
 566                                         break;
 567                         }
 568                 }
 569                 write_INT_MASK(iface, MCOMP | MERR |
 570                         ((iface->read_write == I2C_SMBUS_READ) ?
 571                         RCVSERV : XMTSERV));
 572                 SSYNC();
 573
 574                 /* Master enable */
 575                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 576                         ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 577                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 578                 break;
 579         }
 580         SSYNC();
 581
 582         while (!iface->result) {
 583                 if (!wait_for_completion_timeout(&iface->complete,
 584                         adap->timeout)) {
 585                         iface->result = -1;
 586                         dev_err(&adap->dev, "smbus transfer timeout\n");
 587                 }
 588         }
 589
 590         rc = (iface->result >= 0) ? 0 : -1;
 591
 592         return rc;
 593 }
 594
 595 /*
 596  * Generic I2C SMBus transfer entrypoint
 597  */
 598 int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 599                         unsigned short flags, char read_write,
 600                         u8 command, int size, union i2c_smbus_data *data)
 601 {
 602         return bfin_twi_do_smbus_xfer(adap, addr, flags,
 603                         read_write, command, size, data);
 604 }
 605
 606 /*
 607  * Return what the adapter supports
 608  */
 609 static u32 bfin_twi_functionality(struct i2c_adapter *adap)
 610 {
 611         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 612                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 613                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
 614                I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
 615 }
 616
 617 static struct i2c_algorithm bfin_twi_algorithm = {
 618         .master_xfer   = bfin_twi_master_xfer,
 619         .smbus_xfer    = bfin_twi_smbus_xfer,
 620         .functionality = bfin_twi_functionality,
 621 };
 622
 623 static int i2c_bfin_twi_suspend(struct device *dev)
 624 {
 625         struct bfin_twi_iface *iface = dev_get_drvdata(dev);
 626
 627         iface->saved_clkdiv = read_CLKDIV(iface);
 628         iface->saved_control = read_CONTROL(iface);
 629
 630         free_irq(iface->irq, iface);
 631
 632         /* Disable TWI */
 633         write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
 634
 635         return 0;
 636 }
 637
 638 static int i2c_bfin_twi_resume(struct device *dev)
 639 {
 640         struct bfin_twi_iface *iface = dev_get_drvdata(dev);
 641
 642         int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
 643                 0, to_platform_device(dev)->name, iface);
 644         if (rc) {
 645                 dev_err(dev, "Can't get IRQ %d !\n", iface->irq);
 646                 return -ENODEV;
 647         }
 648
 649         /* Resume TWI interface clock as specified */
 650         write_CLKDIV(iface, iface->saved_clkdiv);
 651
 652         /* Resume TWI */
 653         write_CONTROL(iface, iface->saved_control);
 654
 655         return 0;
 656 }
 657
 658 static SIMPLE_DEV_PM_OPS(i2c_bfin_twi_pm,
 659                          i2c_bfin_twi_suspend, i2c_bfin_twi_resume);
 660
 661 static int i2c_bfin_twi_probe(struct platform_device *pdev)
 662 {
 663         struct bfin_twi_iface *iface;
 664         struct i2c_adapter *p_adap;
 665         struct resource *res;
 666         int rc;
 667         unsigned int clkhilow;
 668
 669         iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
 670         if (!iface) {
 671                 dev_err(&pdev->dev, "Cannot allocate memory\n");
 672                 rc = -ENOMEM;
 673                 goto out_error_nomem;
 674         }
 675
 676         spin_lock_init(&(iface->lock));
 677
 678         /* Find and map our resources */
 679         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 680         if (res == NULL) {
 681                 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
 682                 rc = -ENOENT;
 683                 goto out_error_get_res;
 684         }
 685
 686         iface->regs_base = ioremap(res->start, resource_size(res));
 687         if (iface->regs_base == NULL) {
 688                 dev_err(&pdev->dev, "Cannot map IO\n");
 689                 rc = -ENXIO;
 690                 goto out_error_ioremap;
 691         }
 692
 693         iface->irq = platform_get_irq(pdev, 0);
 694         if (iface->irq < 0) {
 695                 dev_err(&pdev->dev, "No IRQ specified\n");
 696                 rc = -ENOENT;
 697                 goto out_error_no_irq;
 698         }
 699
 700         p_adap = &iface->adap;
 701         p_adap->nr = pdev->id;
 702         strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
 703         p_adap->algo = &bfin_twi_algorithm;
 704         p_adap->algo_data = iface;
 705         p_adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 706         p_adap->dev.parent = &pdev->dev;
 707         p_adap->timeout = 5 * HZ;
 708         p_adap->retries = 3;
 709
 710         rc = peripheral_request_list((unsigned short *)pdev->dev.platform_data,
 711                                         "i2c-bfin-twi");
 712         if (rc) {
 713                 dev_err(&pdev->dev, "Can't setup pin mux!\n");
 714                 goto out_error_pin_mux;
 715         }
 716
 717         rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
 718                 0, pdev->name, iface);
 719         if (rc) {
 720                 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
 721                 rc = -ENODEV;
 722                 goto out_error_req_irq;
 723         }
 724
 725         /* Set TWI internal clock as 10MHz */
 726         write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
 727
 728         /*
 729          * We will not end up with a CLKDIV=0 because no one will specify
 730          * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
 731          */
 732         clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
 733
 734         /* Set Twi interface clock as specified */
 735         write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
 736
 737         /* Enable TWI */
 738         write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
 739         SSYNC();
 740
 741         rc = i2c_add_numbered_adapter(p_adap);
 742         if (rc < 0) {
 743                 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
 744                 goto out_error_add_adapter;
 745         }
 746
 747         platform_set_drvdata(pdev, iface);
 748
 749         dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
 750                 "regs_base@%p\n", iface->regs_base);
 751
 752         return 0;
 753
 754 out_error_add_adapter:
 755         free_irq(iface->irq, iface);
 756 out_error_req_irq:
 757 out_error_no_irq:
 758         peripheral_free_list((unsigned short *)pdev->dev.platform_data);
 759 out_error_pin_mux:
 760         iounmap(iface->regs_base);
 761 out_error_ioremap:
 762 out_error_get_res:
 763         kfree(iface);
 764 out_error_nomem:
 765         return rc;
 766 }
 767
 768 static int i2c_bfin_twi_remove(struct platform_device *pdev)
 769 {
 770         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 771
 772         platform_set_drvdata(pdev, NULL);
 773
 774         i2c_del_adapter(&(iface->adap));
 775         free_irq(iface->irq, iface);
 776         peripheral_free_list((unsigned short *)pdev->dev.platform_data);
 777         iounmap(iface->regs_base);
 778         kfree(iface);
 779
 780         return 0;
 781 }
 782
 783 static struct platform_driver i2c_bfin_twi_driver = {
 784         .probe          = i2c_bfin_twi_probe,
 785         .remove         = i2c_bfin_twi_remove,
 786         .driver         = {
 787                 .name   = "i2c-bfin-twi",
 788                 .owner  = THIS_MODULE,
 789                 .pm     = &i2c_bfin_twi_pm,
 790         },
 791 };
 792
 793 static int __init i2c_bfin_twi_init(void)
 794 {
 795         return platform_driver_register(&i2c_bfin_twi_driver);
 796 }
 797
 798 static void __exit i2c_bfin_twi_exit(void)
 799 {
 800         platform_driver_unregister(&i2c_bfin_twi_driver);
 801 }
 802
 803 subsys_initcall(i2c_bfin_twi_init);
 804 module_exit(i2c_bfin_twi_exit);
 805
 806 MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
 807 MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
 808 MODULE_LICENSE("GPL");
 809 MODULE_ALIAS("platform:i2c-bfin-twi");