Pileus Git - ~andy/linux/blob - drivers/hwmon/w83627hf.c

   1 /*
   2     w83627hf.c - Part of lm_sensors, Linux kernel modules for hardware
   3                 monitoring
   4     Copyright (c) 1998 - 2003  Frodo Looijaard <frodol@dds.nl>,
   5     Philip Edelbrock <phil@netroedge.com>,
   6     and Mark Studebaker <mdsxyz123@yahoo.com>
   7     Ported to 2.6 by Bernhard C. Schrenk <clemy@clemy.org>
   8     Copyright (c) 2007  Jean Delvare <khali@linux-fr.org>
   9
  10     This program is free software; you can redistribute it and/or modify
  11     it under the terms of the GNU General Public License as published by
  12     the Free Software Foundation; either version 2 of the License, or
  13     (at your option) any later version.
  14
  15     This program is distributed in the hope that it will be useful,
  16     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18     GNU General Public License for more details.
  19
  20     You should have received a copy of the GNU General Public License
  21     along with this program; if not, write to the Free Software
  22     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23 */
  24
  25 /*
  26     Supports following chips:
  27
  28     Chip        #vin    #fanin  #pwm    #temp   wchipid vendid  i2c     ISA
  29     w83627hf    9       3       2       3       0x20    0x5ca3  no      yes(LPC)
  30     w83627thf   7       3       3       3       0x90    0x5ca3  no      yes(LPC)
  31     w83637hf    7       3       3       3       0x80    0x5ca3  no      yes(LPC)
  32     w83687thf   7       3       3       3       0x90    0x5ca3  no      yes(LPC)
  33     w83697hf    8       2       2       2       0x60    0x5ca3  no      yes(LPC)
  34
  35     For other winbond chips, and for i2c support in the above chips,
  36     use w83781d.c.
  37
  38     Note: automatic ("cruise") fan control for 697, 637 & 627thf not
  39     supported yet.
  40 */
  41
  42 #include <linux/module.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/jiffies.h>
  46 #include <linux/platform_device.h>
  47 #include <linux/hwmon.h>
  48 #include <linux/hwmon-vid.h>
  49 #include <linux/err.h>
  50 #include <linux/mutex.h>
  51 #include <linux/ioport.h>
  52 #include <asm/io.h>
  53 #include "lm75.h"
  54
  55 static struct platform_device *pdev;
  56
  57 #define DRVNAME "w83627hf"
  58 enum chips { w83627hf, w83627thf, w83697hf, w83637hf, w83687thf };
  59
  60 static u16 force_addr;
  61 module_param(force_addr, ushort, 0);
  62 MODULE_PARM_DESC(force_addr,
  63                  "Initialize the base address of the sensors");
  64 static u8 force_i2c = 0x1f;
  65 module_param(force_i2c, byte, 0);
  66 MODULE_PARM_DESC(force_i2c,
  67                  "Initialize the i2c address of the sensors");
  68
  69 static int reset;
  70 module_param(reset, bool, 0);
  71 MODULE_PARM_DESC(reset, "Set to one to reset chip on load");
  72
  73 static int init = 1;
  74 module_param(init, bool, 0);
  75 MODULE_PARM_DESC(init, "Set to zero to bypass chip initialization");
  76
  77 /* modified from kernel/include/traps.c */
  78 static int REG;         /* The register to read/write */
  79 #define DEV     0x07    /* Register: Logical device select */
  80 static int VAL;         /* The value to read/write */
  81
  82 /* logical device numbers for superio_select (below) */
  83 #define W83627HF_LD_FDC         0x00
  84 #define W83627HF_LD_PRT         0x01
  85 #define W83627HF_LD_UART1       0x02
  86 #define W83627HF_LD_UART2       0x03
  87 #define W83627HF_LD_KBC         0x05
  88 #define W83627HF_LD_CIR         0x06 /* w83627hf only */
  89 #define W83627HF_LD_GAME        0x07
  90 #define W83627HF_LD_MIDI        0x07
  91 #define W83627HF_LD_GPIO1       0x07
  92 #define W83627HF_LD_GPIO5       0x07 /* w83627thf only */
  93 #define W83627HF_LD_GPIO2       0x08
  94 #define W83627HF_LD_GPIO3       0x09
  95 #define W83627HF_LD_GPIO4       0x09 /* w83627thf only */
  96 #define W83627HF_LD_ACPI        0x0a
  97 #define W83627HF_LD_HWM         0x0b
  98
  99 #define DEVID   0x20    /* Register: Device ID */
 100
 101 #define W83627THF_GPIO5_EN      0x30 /* w83627thf only */
 102 #define W83627THF_GPIO5_IOSR    0xf3 /* w83627thf only */
 103 #define W83627THF_GPIO5_DR      0xf4 /* w83627thf only */
 104
 105 #define W83687THF_VID_EN        0x29 /* w83687thf only */
 106 #define W83687THF_VID_CFG       0xF0 /* w83687thf only */
 107 #define W83687THF_VID_DATA      0xF1 /* w83687thf only */
 108
 109 static inline void
 110 superio_outb(int reg, int val)
 111 {
 112         outb(reg, REG);
 113         outb(val, VAL);
 114 }
 115
 116 static inline int
 117 superio_inb(int reg)
 118 {
 119         outb(reg, REG);
 120         return inb(VAL);
 121 }
 122
 123 static inline void
 124 superio_select(int ld)
 125 {
 126         outb(DEV, REG);
 127         outb(ld, VAL);
 128 }
 129
 130 static inline void
 131 superio_enter(void)
 132 {
 133         outb(0x87, REG);
 134         outb(0x87, REG);
 135 }
 136
 137 static inline void
 138 superio_exit(void)
 139 {
 140         outb(0xAA, REG);
 141 }
 142
 143 #define W627_DEVID 0x52
 144 #define W627THF_DEVID 0x82
 145 #define W697_DEVID 0x60
 146 #define W637_DEVID 0x70
 147 #define W687THF_DEVID 0x85
 148 #define WINB_ACT_REG 0x30
 149 #define WINB_BASE_REG 0x60
 150 /* Constants specified below */
 151
 152 /* Alignment of the base address */
 153 #define WINB_ALIGNMENT          ~7
 154
 155 /* Offset & size of I/O region we are interested in */
 156 #define WINB_REGION_OFFSET      5
 157 #define WINB_REGION_SIZE        2
 158
 159 /* Where are the sensors address/data registers relative to the region offset */
 160 #define W83781D_ADDR_REG_OFFSET 0
 161 #define W83781D_DATA_REG_OFFSET 1
 162
 163 /* The W83781D registers */
 164 /* The W83782D registers for nr=7,8 are in bank 5 */
 165 #define W83781D_REG_IN_MAX(nr) ((nr < 7) ? (0x2b + (nr) * 2) : \
 166                                            (0x554 + (((nr) - 7) * 2)))
 167 #define W83781D_REG_IN_MIN(nr) ((nr < 7) ? (0x2c + (nr) * 2) : \
 168                                            (0x555 + (((nr) - 7) * 2)))
 169 #define W83781D_REG_IN(nr)     ((nr < 7) ? (0x20 + (nr)) : \
 170                                            (0x550 + (nr) - 7))
 171
 172 #define W83781D_REG_FAN_MIN(nr) (0x3a + (nr))
 173 #define W83781D_REG_FAN(nr) (0x27 + (nr))
 174
 175 #define W83781D_REG_TEMP2_CONFIG 0x152
 176 #define W83781D_REG_TEMP3_CONFIG 0x252
 177 #define W83781D_REG_TEMP(nr)            ((nr == 3) ? (0x0250) : \
 178                                         ((nr == 2) ? (0x0150) : \
 179                                                      (0x27)))
 180 #define W83781D_REG_TEMP_HYST(nr)       ((nr == 3) ? (0x253) : \
 181                                         ((nr == 2) ? (0x153) : \
 182                                                      (0x3A)))
 183 #define W83781D_REG_TEMP_OVER(nr)       ((nr == 3) ? (0x255) : \
 184                                         ((nr == 2) ? (0x155) : \
 185                                                      (0x39)))
 186
 187 #define W83781D_REG_BANK 0x4E
 188
 189 #define W83781D_REG_CONFIG 0x40
 190 #define W83781D_REG_ALARM1 0x459
 191 #define W83781D_REG_ALARM2 0x45A
 192 #define W83781D_REG_ALARM3 0x45B
 193
 194 #define W83781D_REG_BEEP_CONFIG 0x4D
 195 #define W83781D_REG_BEEP_INTS1 0x56
 196 #define W83781D_REG_BEEP_INTS2 0x57
 197 #define W83781D_REG_BEEP_INTS3 0x453
 198
 199 #define W83781D_REG_VID_FANDIV 0x47
 200
 201 #define W83781D_REG_CHIPID 0x49
 202 #define W83781D_REG_WCHIPID 0x58
 203 #define W83781D_REG_CHIPMAN 0x4F
 204 #define W83781D_REG_PIN 0x4B
 205
 206 #define W83781D_REG_VBAT 0x5D
 207
 208 #define W83627HF_REG_PWM1 0x5A
 209 #define W83627HF_REG_PWM2 0x5B
 210
 211 #define W83627THF_REG_PWM1              0x01    /* 697HF/637HF/687THF too */
 212 #define W83627THF_REG_PWM2              0x03    /* 697HF/637HF/687THF too */
 213 #define W83627THF_REG_PWM3              0x11    /* 637HF/687THF too */
 214
 215 #define W83627THF_REG_VRM_OVT_CFG       0x18    /* 637HF/687THF too */
 216
 217 static const u8 regpwm_627hf[] = { W83627HF_REG_PWM1, W83627HF_REG_PWM2 };
 218 static const u8 regpwm[] = { W83627THF_REG_PWM1, W83627THF_REG_PWM2,
 219                              W83627THF_REG_PWM3 };
 220 #define W836X7HF_REG_PWM(type, nr) (((type) == w83627hf) ? \
 221                                      regpwm_627hf[(nr) - 1] : regpwm[(nr) - 1])
 222
 223 #define W83627HF_REG_PWM_FREQ           0x5C    /* Only for the 627HF */
 224
 225 #define W83637HF_REG_PWM_FREQ1          0x00    /* 697HF/687THF too */
 226 #define W83637HF_REG_PWM_FREQ2          0x02    /* 697HF/687THF too */
 227 #define W83637HF_REG_PWM_FREQ3          0x10    /* 687THF too */
 228
 229 static const u8 W83637HF_REG_PWM_FREQ[] = { W83637HF_REG_PWM_FREQ1,
 230                                         W83637HF_REG_PWM_FREQ2,
 231                                         W83637HF_REG_PWM_FREQ3 };
 232
 233 #define W83627HF_BASE_PWM_FREQ  46870
 234
 235 #define W83781D_REG_I2C_ADDR 0x48
 236 #define W83781D_REG_I2C_SUBADDR 0x4A
 237
 238 /* Sensor selection */
 239 #define W83781D_REG_SCFG1 0x5D
 240 static const u8 BIT_SCFG1[] = { 0x02, 0x04, 0x08 };
 241 #define W83781D_REG_SCFG2 0x59
 242 static const u8 BIT_SCFG2[] = { 0x10, 0x20, 0x40 };
 243 #define W83781D_DEFAULT_BETA 3435
 244
 245 /* Conversions. Limit checking is only done on the TO_REG
 246    variants. Note that you should be a bit careful with which arguments
 247    these macros are called: arguments may be evaluated more than once.
 248    Fixing this is just not worth it. */
 249 #define IN_TO_REG(val)  (SENSORS_LIMIT((((val) + 8)/16),0,255))
 250 #define IN_FROM_REG(val) ((val) * 16)
 251
 252 static inline u8 FAN_TO_REG(long rpm, int div)
 253 {
 254         if (rpm == 0)
 255                 return 255;
 256         rpm = SENSORS_LIMIT(rpm, 1, 1000000);
 257         return SENSORS_LIMIT((1350000 + rpm * div / 2) / (rpm * div), 1,
 258                              254);
 259 }
 260
 261 #define TEMP_MIN (-128000)
 262 #define TEMP_MAX ( 127000)
 263
 264 /* TEMP: 0.001C/bit (-128C to +127C)
 265    REG: 1C/bit, two's complement */
 266 static u8 TEMP_TO_REG(int temp)
 267 {
 268         int ntemp = SENSORS_LIMIT(temp, TEMP_MIN, TEMP_MAX);
 269         ntemp += (ntemp<0 ? -500 : 500);
 270         return (u8)(ntemp / 1000);
 271 }
 272
 273 static int TEMP_FROM_REG(u8 reg)
 274 {
 275         return (s8)reg * 1000;
 276 }
 277
 278 #define FAN_FROM_REG(val,div) ((val)==0?-1:(val)==255?0:1350000/((val)*(div)))
 279
 280 #define PWM_TO_REG(val) (SENSORS_LIMIT((val),0,255))
 281
 282 static inline unsigned long pwm_freq_from_reg_627hf(u8 reg)
 283 {
 284         unsigned long freq;
 285         freq = W83627HF_BASE_PWM_FREQ >> reg;
 286         return freq;
 287 }
 288 static inline u8 pwm_freq_to_reg_627hf(unsigned long val)
 289 {
 290         u8 i;
 291         /* Only 5 dividers (1 2 4 8 16)
 292            Search for the nearest available frequency */
 293         for (i = 0; i < 4; i++) {
 294                 if (val > (((W83627HF_BASE_PWM_FREQ >> i) +
 295                             (W83627HF_BASE_PWM_FREQ >> (i+1))) / 2))
 296                         break;
 297         }
 298         return i;
 299 }
 300
 301 static inline unsigned long pwm_freq_from_reg(u8 reg)
 302 {
 303         /* Clock bit 8 -> 180 kHz or 24 MHz */
 304         unsigned long clock = (reg & 0x80) ? 180000UL : 24000000UL;
 305
 306         reg &= 0x7f;
 307         /* This should not happen but anyway... */
 308         if (reg == 0)
 309                 reg++;
 310         return (clock / (reg << 8));
 311 }
 312 static inline u8 pwm_freq_to_reg(unsigned long val)
 313 {
 314         /* Minimum divider value is 0x01 and maximum is 0x7F */
 315         if (val >= 93750)       /* The highest we can do */
 316                 return 0x01;
 317         if (val >= 720) /* Use 24 MHz clock */
 318                 return (24000000UL / (val << 8));
 319         if (val < 6)            /* The lowest we can do */
 320                 return 0xFF;
 321         else                    /* Use 180 kHz clock */
 322                 return (0x80 | (180000UL / (val << 8)));
 323 }
 324
 325 #define BEEP_MASK_FROM_REG(val)          (val)
 326 #define BEEP_MASK_TO_REG(val)           ((val) & 0xffffff)
 327 #define BEEP_ENABLE_TO_REG(val)         ((val)?1:0)
 328 #define BEEP_ENABLE_FROM_REG(val)       ((val)?1:0)
 329
 330 #define DIV_FROM_REG(val) (1 << (val))
 331
 332 static inline u8 DIV_TO_REG(long val)
 333 {
 334         int i;
 335         val = SENSORS_LIMIT(val, 1, 128) >> 1;
 336         for (i = 0; i < 7; i++) {
 337                 if (val == 0)
 338                         break;
 339                 val >>= 1;
 340         }
 341         return ((u8) i);
 342 }
 343
 344 /* For each registered chip, we need to keep some data in memory.
 345    The structure is dynamically allocated. */
 346 struct w83627hf_data {
 347         unsigned short addr;
 348         const char *name;
 349         struct class_device *class_dev;
 350         struct mutex lock;
 351         enum chips type;
 352
 353         struct mutex update_lock;
 354         char valid;             /* !=0 if following fields are valid */
 355         unsigned long last_updated;     /* In jiffies */
 356
 357         u8 in[9];               /* Register value */
 358         u8 in_max[9];           /* Register value */
 359         u8 in_min[9];           /* Register value */
 360         u8 fan[3];              /* Register value */
 361         u8 fan_min[3];          /* Register value */
 362         u8 temp;
 363         u8 temp_max;            /* Register value */
 364         u8 temp_max_hyst;       /* Register value */
 365         u16 temp_add[2];        /* Register value */
 366         u16 temp_max_add[2];    /* Register value */
 367         u16 temp_max_hyst_add[2]; /* Register value */
 368         u8 fan_div[3];          /* Register encoding, shifted right */
 369         u8 vid;                 /* Register encoding, combined */
 370         u32 alarms;             /* Register encoding, combined */
 371         u32 beep_mask;          /* Register encoding, combined */
 372         u8 beep_enable;         /* Boolean */
 373         u8 pwm[3];              /* Register value */
 374         u8 pwm_freq[3];         /* Register value */
 375         u16 sens[3];            /* 782D/783S only.
 376                                    1 = pentium diode; 2 = 3904 diode;
 377                                    3000-5000 = thermistor beta.
 378                                    Default = 3435.
 379                                    Other Betas unimplemented */
 380         u8 vrm;
 381         u8 vrm_ovt;             /* Register value, 627THF/637HF/687THF only */
 382 };
 383
 384 struct w83627hf_sio_data {
 385         enum chips type;
 386 };
 387
 388
 389 static int w83627hf_probe(struct platform_device *pdev);
 390 static int w83627hf_remove(struct platform_device *pdev);
 391
 392 static int w83627hf_read_value(struct w83627hf_data *data, u16 reg);
 393 static int w83627hf_write_value(struct w83627hf_data *data, u16 reg, u16 value);
 394 static struct w83627hf_data *w83627hf_update_device(struct device *dev);
 395 static void w83627hf_init_device(struct platform_device *pdev);
 396
 397 static struct platform_driver w83627hf_driver = {
 398         .driver = {
 399                 .owner  = THIS_MODULE,
 400                 .name   = DRVNAME,
 401         },
 402         .probe          = w83627hf_probe,
 403         .remove         = __devexit_p(w83627hf_remove),
 404 };
 405
 406 /* following are the sysfs callback functions */
 407 #define show_in_reg(reg) \
 408 static ssize_t show_##reg (struct device *dev, char *buf, int nr) \
 409 { \
 410         struct w83627hf_data *data = w83627hf_update_device(dev); \
 411         return sprintf(buf,"%ld\n", (long)IN_FROM_REG(data->reg[nr])); \
 412 }
 413 show_in_reg(in)
 414 show_in_reg(in_min)
 415 show_in_reg(in_max)
 416
 417 #define store_in_reg(REG, reg) \
 418 static ssize_t \
 419 store_in_##reg (struct device *dev, const char *buf, size_t count, int nr) \
 420 { \
 421         struct w83627hf_data *data = dev_get_drvdata(dev); \
 422         u32 val; \
 423          \
 424         val = simple_strtoul(buf, NULL, 10); \
 425          \
 426         mutex_lock(&data->update_lock); \
 427         data->in_##reg[nr] = IN_TO_REG(val); \
 428         w83627hf_write_value(data, W83781D_REG_IN_##REG(nr), \
 429                             data->in_##reg[nr]); \
 430          \
 431         mutex_unlock(&data->update_lock); \
 432         return count; \
 433 }
 434 store_in_reg(MIN, min)
 435 store_in_reg(MAX, max)
 436
 437 #define sysfs_in_offset(offset) \
 438 static ssize_t \
 439 show_regs_in_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
 440 { \
 441         return show_in(dev, buf, offset); \
 442 } \
 443 static DEVICE_ATTR(in##offset##_input, S_IRUGO, show_regs_in_##offset, NULL);
 444
 445 #define sysfs_in_reg_offset(reg, offset) \
 446 static ssize_t show_regs_in_##reg##offset (struct device *dev, struct device_attribute *attr, char *buf) \
 447 { \
 448         return show_in_##reg (dev, buf, offset); \
 449 } \
 450 static ssize_t \
 451 store_regs_in_##reg##offset (struct device *dev, struct device_attribute *attr, \
 452                             const char *buf, size_t count) \
 453 { \
 454         return store_in_##reg (dev, buf, count, offset); \
 455 } \
 456 static DEVICE_ATTR(in##offset##_##reg, S_IRUGO| S_IWUSR, \
 457                   show_regs_in_##reg##offset, store_regs_in_##reg##offset);
 458
 459 #define sysfs_in_offsets(offset) \
 460 sysfs_in_offset(offset) \
 461 sysfs_in_reg_offset(min, offset) \
 462 sysfs_in_reg_offset(max, offset)
 463
 464 sysfs_in_offsets(1);
 465 sysfs_in_offsets(2);
 466 sysfs_in_offsets(3);
 467 sysfs_in_offsets(4);
 468 sysfs_in_offsets(5);
 469 sysfs_in_offsets(6);
 470 sysfs_in_offsets(7);
 471 sysfs_in_offsets(8);
 472
 473 /* use a different set of functions for in0 */
 474 static ssize_t show_in_0(struct w83627hf_data *data, char *buf, u8 reg)
 475 {
 476         long in0;
 477
 478         if ((data->vrm_ovt & 0x01) &&
 479                 (w83627thf == data->type || w83637hf == data->type
 480                  || w83687thf == data->type))
 481
 482                 /* use VRM9 calculation */
 483                 in0 = (long)((reg * 488 + 70000 + 50) / 100);
 484         else
 485                 /* use VRM8 (standard) calculation */
 486                 in0 = (long)IN_FROM_REG(reg);
 487
 488         return sprintf(buf,"%ld\n", in0);
 489 }
 490
 491 static ssize_t show_regs_in_0(struct device *dev, struct device_attribute *attr, char *buf)
 492 {
 493         struct w83627hf_data *data = w83627hf_update_device(dev);
 494         return show_in_0(data, buf, data->in[0]);
 495 }
 496
 497 static ssize_t show_regs_in_min0(struct device *dev, struct device_attribute *attr, char *buf)
 498 {
 499         struct w83627hf_data *data = w83627hf_update_device(dev);
 500         return show_in_0(data, buf, data->in_min[0]);
 501 }
 502
 503 static ssize_t show_regs_in_max0(struct device *dev, struct device_attribute *attr, char *buf)
 504 {
 505         struct w83627hf_data *data = w83627hf_update_device(dev);
 506         return show_in_0(data, buf, data->in_max[0]);
 507 }
 508
 509 static ssize_t store_regs_in_min0(struct device *dev, struct device_attribute *attr,
 510         const char *buf, size_t count)
 511 {
 512         struct w83627hf_data *data = dev_get_drvdata(dev);
 513         u32 val;
 514
 515         val = simple_strtoul(buf, NULL, 10);
 516
 517         mutex_lock(&data->update_lock);
 518
 519         if ((data->vrm_ovt & 0x01) &&
 520                 (w83627thf == data->type || w83637hf == data->type
 521                  || w83687thf == data->type))
 522
 523                 /* use VRM9 calculation */
 524                 data->in_min[0] =
 525                         SENSORS_LIMIT(((val * 100) - 70000 + 244) / 488, 0,
 526                                         255);
 527         else
 528                 /* use VRM8 (standard) calculation */
 529                 data->in_min[0] = IN_TO_REG(val);
 530
 531         w83627hf_write_value(data, W83781D_REG_IN_MIN(0), data->in_min[0]);
 532         mutex_unlock(&data->update_lock);
 533         return count;
 534 }
 535
 536 static ssize_t store_regs_in_max0(struct device *dev, struct device_attribute *attr,
 537         const char *buf, size_t count)
 538 {
 539         struct w83627hf_data *data = dev_get_drvdata(dev);
 540         u32 val;
 541
 542         val = simple_strtoul(buf, NULL, 10);
 543
 544         mutex_lock(&data->update_lock);
 545
 546         if ((data->vrm_ovt & 0x01) &&
 547                 (w83627thf == data->type || w83637hf == data->type
 548                  || w83687thf == data->type))
 549
 550                 /* use VRM9 calculation */
 551                 data->in_max[0] =
 552                         SENSORS_LIMIT(((val * 100) - 70000 + 244) / 488, 0,
 553                                         255);
 554         else
 555                 /* use VRM8 (standard) calculation */
 556                 data->in_max[0] = IN_TO_REG(val);
 557
 558         w83627hf_write_value(data, W83781D_REG_IN_MAX(0), data->in_max[0]);
 559         mutex_unlock(&data->update_lock);
 560         return count;
 561 }
 562
 563 static DEVICE_ATTR(in0_input, S_IRUGO, show_regs_in_0, NULL);
 564 static DEVICE_ATTR(in0_min, S_IRUGO | S_IWUSR,
 565         show_regs_in_min0, store_regs_in_min0);
 566 static DEVICE_ATTR(in0_max, S_IRUGO | S_IWUSR,
 567         show_regs_in_max0, store_regs_in_max0);
 568
 569 #define show_fan_reg(reg) \
 570 static ssize_t show_##reg (struct device *dev, char *buf, int nr) \
 571 { \
 572         struct w83627hf_data *data = w83627hf_update_device(dev); \
 573         return sprintf(buf,"%ld\n", \
 574                 FAN_FROM_REG(data->reg[nr-1], \
 575                             (long)DIV_FROM_REG(data->fan_div[nr-1]))); \
 576 }
 577 show_fan_reg(fan);
 578 show_fan_reg(fan_min);
 579
 580 static ssize_t
 581 store_fan_min(struct device *dev, const char *buf, size_t count, int nr)
 582 {
 583         struct w83627hf_data *data = dev_get_drvdata(dev);
 584         u32 val;
 585
 586         val = simple_strtoul(buf, NULL, 10);
 587
 588         mutex_lock(&data->update_lock);
 589         data->fan_min[nr - 1] =
 590             FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr - 1]));
 591         w83627hf_write_value(data, W83781D_REG_FAN_MIN(nr),
 592                             data->fan_min[nr - 1]);
 593
 594         mutex_unlock(&data->update_lock);
 595         return count;
 596 }
 597
 598 #define sysfs_fan_offset(offset) \
 599 static ssize_t show_regs_fan_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
 600 { \
 601         return show_fan(dev, buf, offset); \
 602 } \
 603 static DEVICE_ATTR(fan##offset##_input, S_IRUGO, show_regs_fan_##offset, NULL);
 604
 605 #define sysfs_fan_min_offset(offset) \
 606 static ssize_t show_regs_fan_min##offset (struct device *dev, struct device_attribute *attr, char *buf) \
 607 { \
 608         return show_fan_min(dev, buf, offset); \
 609 } \
 610 static ssize_t \
 611 store_regs_fan_min##offset (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
 612 { \
 613         return store_fan_min(dev, buf, count, offset); \
 614 } \
 615 static DEVICE_ATTR(fan##offset##_min, S_IRUGO | S_IWUSR, \
 616                   show_regs_fan_min##offset, store_regs_fan_min##offset);
 617
 618 sysfs_fan_offset(1);
 619 sysfs_fan_min_offset(1);
 620 sysfs_fan_offset(2);
 621 sysfs_fan_min_offset(2);
 622 sysfs_fan_offset(3);
 623 sysfs_fan_min_offset(3);
 624
 625 #define show_temp_reg(reg) \
 626 static ssize_t show_##reg (struct device *dev, char *buf, int nr) \
 627 { \
 628         struct w83627hf_data *data = w83627hf_update_device(dev); \
 629         if (nr >= 2) {  /* TEMP2 and TEMP3 */ \
 630                 return sprintf(buf,"%ld\n", \
 631                         (long)LM75_TEMP_FROM_REG(data->reg##_add[nr-2])); \
 632         } else {        /* TEMP1 */ \
 633                 return sprintf(buf,"%ld\n", (long)TEMP_FROM_REG(data->reg)); \
 634         } \
 635 }
 636 show_temp_reg(temp);
 637 show_temp_reg(temp_max);
 638 show_temp_reg(temp_max_hyst);
 639
 640 #define store_temp_reg(REG, reg) \
 641 static ssize_t \
 642 store_temp_##reg (struct device *dev, const char *buf, size_t count, int nr) \
 643 { \
 644         struct w83627hf_data *data = dev_get_drvdata(dev); \
 645         u32 val; \
 646          \
 647         val = simple_strtoul(buf, NULL, 10); \
 648          \
 649         mutex_lock(&data->update_lock); \
 650          \
 651         if (nr >= 2) {  /* TEMP2 and TEMP3 */ \
 652                 data->temp_##reg##_add[nr-2] = LM75_TEMP_TO_REG(val); \
 653                 w83627hf_write_value(data, W83781D_REG_TEMP_##REG(nr), \
 654                                 data->temp_##reg##_add[nr-2]); \
 655         } else {        /* TEMP1 */ \
 656                 data->temp_##reg = TEMP_TO_REG(val); \
 657                 w83627hf_write_value(data, W83781D_REG_TEMP_##REG(nr), \
 658                         data->temp_##reg); \
 659         } \
 660          \
 661         mutex_unlock(&data->update_lock); \
 662         return count; \
 663 }
 664 store_temp_reg(OVER, max);
 665 store_temp_reg(HYST, max_hyst);
 666
 667 #define sysfs_temp_offset(offset) \
 668 static ssize_t \
 669 show_regs_temp_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
 670 { \
 671         return show_temp(dev, buf, offset); \
 672 } \
 673 static DEVICE_ATTR(temp##offset##_input, S_IRUGO, show_regs_temp_##offset, NULL);
 674
 675 #define sysfs_temp_reg_offset(reg, offset) \
 676 static ssize_t show_regs_temp_##reg##offset (struct device *dev, struct device_attribute *attr, char *buf) \
 677 { \
 678         return show_temp_##reg (dev, buf, offset); \
 679 } \
 680 static ssize_t \
 681 store_regs_temp_##reg##offset (struct device *dev, struct device_attribute *attr, \
 682                               const char *buf, size_t count) \
 683 { \
 684         return store_temp_##reg (dev, buf, count, offset); \
 685 } \
 686 static DEVICE_ATTR(temp##offset##_##reg, S_IRUGO| S_IWUSR, \
 687                   show_regs_temp_##reg##offset, store_regs_temp_##reg##offset);
 688
 689 #define sysfs_temp_offsets(offset) \
 690 sysfs_temp_offset(offset) \
 691 sysfs_temp_reg_offset(max, offset) \
 692 sysfs_temp_reg_offset(max_hyst, offset)
 693
 694 sysfs_temp_offsets(1);
 695 sysfs_temp_offsets(2);
 696 sysfs_temp_offsets(3);
 697
 698 static ssize_t
 699 show_vid_reg(struct device *dev, struct device_attribute *attr, char *buf)
 700 {
 701         struct w83627hf_data *data = w83627hf_update_device(dev);
 702         return sprintf(buf, "%ld\n", (long) vid_from_reg(data->vid, data->vrm));
 703 }
 704 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
 705
 706 static ssize_t
 707 show_vrm_reg(struct device *dev, struct device_attribute *attr, char *buf)
 708 {
 709         struct w83627hf_data *data = w83627hf_update_device(dev);
 710         return sprintf(buf, "%ld\n", (long) data->vrm);
 711 }
 712 static ssize_t
 713 store_vrm_reg(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
 714 {
 715         struct w83627hf_data *data = dev_get_drvdata(dev);
 716         u32 val;
 717
 718         val = simple_strtoul(buf, NULL, 10);
 719         data->vrm = val;
 720
 721         return count;
 722 }
 723 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
 724
 725 static ssize_t
 726 show_alarms_reg(struct device *dev, struct device_attribute *attr, char *buf)
 727 {
 728         struct w83627hf_data *data = w83627hf_update_device(dev);
 729         return sprintf(buf, "%ld\n", (long) data->alarms);
 730 }
 731 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms_reg, NULL);
 732
 733 #define show_beep_reg(REG, reg) \
 734 static ssize_t show_beep_##reg (struct device *dev, struct device_attribute *attr, char *buf) \
 735 { \
 736         struct w83627hf_data *data = w83627hf_update_device(dev); \
 737         return sprintf(buf,"%ld\n", \
 738                       (long)BEEP_##REG##_FROM_REG(data->beep_##reg)); \
 739 }
 740 show_beep_reg(ENABLE, enable)
 741 show_beep_reg(MASK, mask)
 742
 743 #define BEEP_ENABLE                     0       /* Store beep_enable */
 744 #define BEEP_MASK                       1       /* Store beep_mask */
 745
 746 static ssize_t
 747 store_beep_reg(struct device *dev, const char *buf, size_t count,
 748                int update_mask)
 749 {
 750         struct w83627hf_data *data = dev_get_drvdata(dev);
 751         u32 val, val2;
 752
 753         val = simple_strtoul(buf, NULL, 10);
 754
 755         mutex_lock(&data->update_lock);
 756
 757         if (update_mask == BEEP_MASK) { /* We are storing beep_mask */
 758                 data->beep_mask = BEEP_MASK_TO_REG(val);
 759                 w83627hf_write_value(data, W83781D_REG_BEEP_INTS1,
 760                                     data->beep_mask & 0xff);
 761                 w83627hf_write_value(data, W83781D_REG_BEEP_INTS3,
 762                                     ((data->beep_mask) >> 16) & 0xff);
 763                 val2 = (data->beep_mask >> 8) & 0x7f;
 764         } else {                /* We are storing beep_enable */
 765                 val2 =
 766                     w83627hf_read_value(data, W83781D_REG_BEEP_INTS2) & 0x7f;
 767                 data->beep_enable = BEEP_ENABLE_TO_REG(val);
 768         }
 769
 770         w83627hf_write_value(data, W83781D_REG_BEEP_INTS2,
 771                             val2 | data->beep_enable << 7);
 772
 773         mutex_unlock(&data->update_lock);
 774         return count;
 775 }
 776
 777 #define sysfs_beep(REG, reg) \
 778 static ssize_t show_regs_beep_##reg (struct device *dev, struct device_attribute *attr, char *buf) \
 779 { \
 780         return show_beep_##reg(dev, attr, buf); \
 781 } \
 782 static ssize_t \
 783 store_regs_beep_##reg (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
 784 { \
 785         return store_beep_reg(dev, buf, count, BEEP_##REG); \
 786 } \
 787 static DEVICE_ATTR(beep_##reg, S_IRUGO | S_IWUSR, \
 788                   show_regs_beep_##reg, store_regs_beep_##reg);
 789
 790 sysfs_beep(ENABLE, enable);
 791 sysfs_beep(MASK, mask);
 792
 793 static ssize_t
 794 show_fan_div_reg(struct device *dev, char *buf, int nr)
 795 {
 796         struct w83627hf_data *data = w83627hf_update_device(dev);
 797         return sprintf(buf, "%ld\n",
 798                        (long) DIV_FROM_REG(data->fan_div[nr - 1]));
 799 }
 800
 801 /* Note: we save and restore the fan minimum here, because its value is
 802    determined in part by the fan divisor.  This follows the principle of
 803    least surprise; the user doesn't expect the fan minimum to change just
 804    because the divisor changed. */
 805 static ssize_t
 806 store_fan_div_reg(struct device *dev, const char *buf, size_t count, int nr)
 807 {
 808         struct w83627hf_data *data = dev_get_drvdata(dev);
 809         unsigned long min;
 810         u8 reg;
 811         unsigned long val = simple_strtoul(buf, NULL, 10);
 812
 813         mutex_lock(&data->update_lock);
 814
 815         /* Save fan_min */
 816         min = FAN_FROM_REG(data->fan_min[nr],
 817                            DIV_FROM_REG(data->fan_div[nr]));
 818
 819         data->fan_div[nr] = DIV_TO_REG(val);
 820
 821         reg = (w83627hf_read_value(data, nr==2 ? W83781D_REG_PIN : W83781D_REG_VID_FANDIV)
 822                & (nr==0 ? 0xcf : 0x3f))
 823             | ((data->fan_div[nr] & 0x03) << (nr==0 ? 4 : 6));
 824         w83627hf_write_value(data, nr==2 ? W83781D_REG_PIN : W83781D_REG_VID_FANDIV, reg);
 825
 826         reg = (w83627hf_read_value(data, W83781D_REG_VBAT)
 827                & ~(1 << (5 + nr)))
 828             | ((data->fan_div[nr] & 0x04) << (3 + nr));
 829         w83627hf_write_value(data, W83781D_REG_VBAT, reg);
 830
 831         /* Restore fan_min */
 832         data->fan_min[nr] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
 833         w83627hf_write_value(data, W83781D_REG_FAN_MIN(nr+1), data->fan_min[nr]);
 834
 835         mutex_unlock(&data->update_lock);
 836         return count;
 837 }
 838
 839 #define sysfs_fan_div(offset) \
 840 static ssize_t show_regs_fan_div_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
 841 { \
 842         return show_fan_div_reg(dev, buf, offset); \
 843 } \
 844 static ssize_t \
 845 store_regs_fan_div_##offset (struct device *dev, struct device_attribute *attr, \
 846                             const char *buf, size_t count) \
 847 { \
 848         return store_fan_div_reg(dev, buf, count, offset - 1); \
 849 } \
 850 static DEVICE_ATTR(fan##offset##_div, S_IRUGO | S_IWUSR, \
 851                   show_regs_fan_div_##offset, store_regs_fan_div_##offset);
 852
 853 sysfs_fan_div(1);
 854 sysfs_fan_div(2);
 855 sysfs_fan_div(3);
 856
 857 static ssize_t
 858 show_pwm_reg(struct device *dev, char *buf, int nr)
 859 {
 860         struct w83627hf_data *data = w83627hf_update_device(dev);
 861         return sprintf(buf, "%ld\n", (long) data->pwm[nr - 1]);
 862 }
 863
 864 static ssize_t
 865 store_pwm_reg(struct device *dev, const char *buf, size_t count, int nr)
 866 {
 867         struct w83627hf_data *data = dev_get_drvdata(dev);
 868         u32 val;
 869
 870         val = simple_strtoul(buf, NULL, 10);
 871
 872         mutex_lock(&data->update_lock);
 873
 874         if (data->type == w83627thf) {
 875                 /* bits 0-3 are reserved  in 627THF */
 876                 data->pwm[nr - 1] = PWM_TO_REG(val) & 0xf0;
 877                 w83627hf_write_value(data,
 878                                      W836X7HF_REG_PWM(data->type, nr),
 879                                      data->pwm[nr - 1] |
 880                                      (w83627hf_read_value(data,
 881                                      W836X7HF_REG_PWM(data->type, nr)) & 0x0f));
 882         } else {
 883                 data->pwm[nr - 1] = PWM_TO_REG(val);
 884                 w83627hf_write_value(data,
 885                                      W836X7HF_REG_PWM(data->type, nr),
 886                                      data->pwm[nr - 1]);
 887         }
 888
 889         mutex_unlock(&data->update_lock);
 890         return count;
 891 }
 892
 893 #define sysfs_pwm(offset) \
 894 static ssize_t show_regs_pwm_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
 895 { \
 896         return show_pwm_reg(dev, buf, offset); \
 897 } \
 898 static ssize_t \
 899 store_regs_pwm_##offset (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
 900 { \
 901         return store_pwm_reg(dev, buf, count, offset); \
 902 } \
 903 static DEVICE_ATTR(pwm##offset, S_IRUGO | S_IWUSR, \
 904                   show_regs_pwm_##offset, store_regs_pwm_##offset);
 905
 906 sysfs_pwm(1);
 907 sysfs_pwm(2);
 908 sysfs_pwm(3);
 909
 910 static ssize_t
 911 show_pwm_freq_reg(struct device *dev, char *buf, int nr)
 912 {
 913         struct w83627hf_data *data = w83627hf_update_device(dev);
 914         if (data->type == w83627hf)
 915                 return sprintf(buf, "%ld\n",
 916                         pwm_freq_from_reg_627hf(data->pwm_freq[nr - 1]));
 917         else
 918                 return sprintf(buf, "%ld\n",
 919                         pwm_freq_from_reg(data->pwm_freq[nr - 1]));
 920 }
 921
 922 static ssize_t
 923 store_pwm_freq_reg(struct device *dev, const char *buf, size_t count, int nr)
 924 {
 925         struct w83627hf_data *data = dev_get_drvdata(dev);
 926         static const u8 mask[]={0xF8, 0x8F};
 927         u32 val;
 928
 929         val = simple_strtoul(buf, NULL, 10);
 930
 931         mutex_lock(&data->update_lock);
 932
 933         if (data->type == w83627hf) {
 934                 data->pwm_freq[nr - 1] = pwm_freq_to_reg_627hf(val);
 935                 w83627hf_write_value(data, W83627HF_REG_PWM_FREQ,
 936                                 (data->pwm_freq[nr - 1] << ((nr - 1)*4)) |
 937                                 (w83627hf_read_value(data,
 938                                 W83627HF_REG_PWM_FREQ) & mask[nr - 1]));
 939         } else {
 940                 data->pwm_freq[nr - 1] = pwm_freq_to_reg(val);
 941                 w83627hf_write_value(data, W83637HF_REG_PWM_FREQ[nr - 1],
 942                                 data->pwm_freq[nr - 1]);
 943         }
 944
 945         mutex_unlock(&data->update_lock);
 946         return count;
 947 }
 948
 949 #define sysfs_pwm_freq(offset) \
 950 static ssize_t show_regs_pwm_freq_##offset(struct device *dev, \
 951                 struct device_attribute *attr, char *buf) \
 952 { \
 953         return show_pwm_freq_reg(dev, buf, offset); \
 954 } \
 955 static ssize_t \
 956 store_regs_pwm_freq_##offset(struct device *dev, \
 957                 struct device_attribute *attr, const char *buf, size_t count) \
 958 { \
 959         return store_pwm_freq_reg(dev, buf, count, offset); \
 960 } \
 961 static DEVICE_ATTR(pwm##offset##_freq, S_IRUGO | S_IWUSR, \
 962                   show_regs_pwm_freq_##offset, store_regs_pwm_freq_##offset);
 963
 964 sysfs_pwm_freq(1);
 965 sysfs_pwm_freq(2);
 966 sysfs_pwm_freq(3);
 967
 968 static ssize_t
 969 show_sensor_reg(struct device *dev, char *buf, int nr)
 970 {
 971         struct w83627hf_data *data = w83627hf_update_device(dev);
 972         return sprintf(buf, "%ld\n", (long) data->sens[nr - 1]);
 973 }
 974
 975 static ssize_t
 976 store_sensor_reg(struct device *dev, const char *buf, size_t count, int nr)
 977 {
 978         struct w83627hf_data *data = dev_get_drvdata(dev);
 979         u32 val, tmp;
 980
 981         val = simple_strtoul(buf, NULL, 10);
 982
 983         mutex_lock(&data->update_lock);
 984
 985         switch (val) {
 986         case 1:         /* PII/Celeron diode */
 987                 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
 988                 w83627hf_write_value(data, W83781D_REG_SCFG1,
 989                                     tmp | BIT_SCFG1[nr - 1]);
 990                 tmp = w83627hf_read_value(data, W83781D_REG_SCFG2);
 991                 w83627hf_write_value(data, W83781D_REG_SCFG2,
 992                                     tmp | BIT_SCFG2[nr - 1]);
 993                 data->sens[nr - 1] = val;
 994                 break;
 995         case 2:         /* 3904 */
 996                 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
 997                 w83627hf_write_value(data, W83781D_REG_SCFG1,
 998                                     tmp | BIT_SCFG1[nr - 1]);
 999                 tmp = w83627hf_read_value(data, W83781D_REG_SCFG2);
1000                 w83627hf_write_value(data, W83781D_REG_SCFG2,
1001                                     tmp & ~BIT_SCFG2[nr - 1]);
1002                 data->sens[nr - 1] = val;
1003                 break;
1004         case W83781D_DEFAULT_BETA:      /* thermistor */
1005                 tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
1006                 w83627hf_write_value(data, W83781D_REG_SCFG1,
1007                                     tmp & ~BIT_SCFG1[nr - 1]);
1008                 data->sens[nr - 1] = val;
1009                 break;
1010         default:
1011                 dev_err(dev,
1012                        "Invalid sensor type %ld; must be 1, 2, or %d\n",
1013                        (long) val, W83781D_DEFAULT_BETA);
1014                 break;
1015         }
1016
1017         mutex_unlock(&data->update_lock);
1018         return count;
1019 }
1020
1021 #define sysfs_sensor(offset) \
1022 static ssize_t show_regs_sensor_##offset (struct device *dev, struct device_attribute *attr, char *buf) \
1023 { \
1024     return show_sensor_reg(dev, buf, offset); \
1025 } \
1026 static ssize_t \
1027 store_regs_sensor_##offset (struct device *dev, struct device_attribute *attr, const char *buf, size_t count) \
1028 { \
1029     return store_sensor_reg(dev, buf, count, offset); \
1030 } \
1031 static DEVICE_ATTR(temp##offset##_type, S_IRUGO | S_IWUSR, \
1032                   show_regs_sensor_##offset, store_regs_sensor_##offset);
1033
1034 sysfs_sensor(1);
1035 sysfs_sensor(2);
1036 sysfs_sensor(3);
1037
1038 static ssize_t show_name(struct device *dev, struct device_attribute
1039                          *devattr, char *buf)
1040 {
1041         struct w83627hf_data *data = dev_get_drvdata(dev);
1042
1043         return sprintf(buf, "%s\n", data->name);
1044 }
1045 static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
1046
1047 static int __init w83627hf_find(int sioaddr, unsigned short *addr,
1048                                 struct w83627hf_sio_data *sio_data)
1049 {
1050         int err = -ENODEV;
1051         u16 val;
1052
1053         static const __initdata char *names[] = {
1054                 "W83627HF",
1055                 "W83627THF",
1056                 "W83697HF",
1057                 "W83637HF",
1058                 "W83687THF",
1059         };
1060
1061         REG = sioaddr;
1062         VAL = sioaddr + 1;
1063
1064         superio_enter();
1065         val= superio_inb(DEVID);
1066         switch (val) {
1067         case W627_DEVID:
1068                 sio_data->type = w83627hf;
1069                 break;
1070         case W627THF_DEVID:
1071                 sio_data->type = w83627thf;
1072                 break;
1073         case W697_DEVID:
1074                 sio_data->type = w83697hf;
1075                 break;
1076         case W637_DEVID:
1077                 sio_data->type = w83637hf;
1078                 break;
1079         case W687THF_DEVID:
1080                 sio_data->type = w83687thf;
1081                 break;
1082         case 0xff:      /* No device at all */
1083                 goto exit;
1084         default:
1085                 pr_debug(DRVNAME ": Unsupported chip (DEVID=0x%02x)\n", val);
1086                 goto exit;
1087         }
1088
1089         superio_select(W83627HF_LD_HWM);
1090         force_addr &= WINB_ALIGNMENT;
1091         if (force_addr) {
1092                 printk(KERN_WARNING DRVNAME ": Forcing address 0x%x\n",
1093                        force_addr);
1094                 superio_outb(WINB_BASE_REG, force_addr >> 8);
1095                 superio_outb(WINB_BASE_REG + 1, force_addr & 0xff);
1096         }
1097         val = (superio_inb(WINB_BASE_REG) << 8) |
1098                superio_inb(WINB_BASE_REG + 1);
1099         *addr = val & WINB_ALIGNMENT;
1100         if (*addr == 0) {
1101                 printk(KERN_WARNING DRVNAME ": Base address not set, "
1102                        "skipping\n");
1103                 goto exit;
1104         }
1105
1106         val = superio_inb(WINB_ACT_REG);
1107         if (!(val & 0x01)) {
1108                 printk(KERN_WARNING DRVNAME ": Enabling HWM logical device\n");
1109                 superio_outb(WINB_ACT_REG, val | 0x01);
1110         }
1111
1112         err = 0;
1113         pr_info(DRVNAME ": Found %s chip at %#x\n",
1114                 names[sio_data->type], *addr);
1115
1116  exit:
1117         superio_exit();
1118         return err;
1119 }
1120
1121 static struct attribute *w83627hf_attributes[] = {
1122         &dev_attr_in0_input.attr,
1123         &dev_attr_in0_min.attr,
1124         &dev_attr_in0_max.attr,
1125         &dev_attr_in2_input.attr,
1126         &dev_attr_in2_min.attr,
1127         &dev_attr_in2_max.attr,
1128         &dev_attr_in3_input.attr,
1129         &dev_attr_in3_min.attr,
1130         &dev_attr_in3_max.attr,
1131         &dev_attr_in4_input.attr,
1132         &dev_attr_in4_min.attr,
1133         &dev_attr_in4_max.attr,
1134         &dev_attr_in7_input.attr,
1135         &dev_attr_in7_min.attr,
1136         &dev_attr_in7_max.attr,
1137         &dev_attr_in8_input.attr,
1138         &dev_attr_in8_min.attr,
1139         &dev_attr_in8_max.attr,
1140
1141         &dev_attr_fan1_input.attr,
1142         &dev_attr_fan1_min.attr,
1143         &dev_attr_fan1_div.attr,
1144         &dev_attr_fan2_input.attr,
1145         &dev_attr_fan2_min.attr,
1146         &dev_attr_fan2_div.attr,
1147
1148         &dev_attr_temp1_input.attr,
1149         &dev_attr_temp1_max.attr,
1150         &dev_attr_temp1_max_hyst.attr,
1151         &dev_attr_temp1_type.attr,
1152         &dev_attr_temp2_input.attr,
1153         &dev_attr_temp2_max.attr,
1154         &dev_attr_temp2_max_hyst.attr,
1155         &dev_attr_temp2_type.attr,
1156
1157         &dev_attr_alarms.attr,
1158         &dev_attr_beep_enable.attr,
1159         &dev_attr_beep_mask.attr,
1160
1161         &dev_attr_pwm1.attr,
1162         &dev_attr_pwm2.attr,
1163
1164         &dev_attr_name.attr,
1165         NULL
1166 };
1167
1168 static const struct attribute_group w83627hf_group = {
1169         .attrs = w83627hf_attributes,
1170 };
1171
1172 static struct attribute *w83627hf_attributes_opt[] = {
1173         &dev_attr_in1_input.attr,
1174         &dev_attr_in1_min.attr,
1175         &dev_attr_in1_max.attr,
1176         &dev_attr_in5_input.attr,
1177         &dev_attr_in5_min.attr,
1178         &dev_attr_in5_max.attr,
1179         &dev_attr_in6_input.attr,
1180         &dev_attr_in6_min.attr,
1181         &dev_attr_in6_max.attr,
1182
1183         &dev_attr_fan3_input.attr,
1184         &dev_attr_fan3_min.attr,
1185         &dev_attr_fan3_div.attr,
1186
1187         &dev_attr_temp3_input.attr,
1188         &dev_attr_temp3_max.attr,
1189         &dev_attr_temp3_max_hyst.attr,
1190         &dev_attr_temp3_type.attr,
1191
1192         &dev_attr_pwm3.attr,
1193
1194         &dev_attr_pwm1_freq.attr,
1195         &dev_attr_pwm2_freq.attr,
1196         &dev_attr_pwm3_freq.attr,
1197         NULL
1198 };
1199
1200 static const struct attribute_group w83627hf_group_opt = {
1201         .attrs = w83627hf_attributes_opt,
1202 };
1203
1204 static int __devinit w83627hf_probe(struct platform_device *pdev)
1205 {
1206         struct device *dev = &pdev->dev;
1207         struct w83627hf_sio_data *sio_data = dev->platform_data;
1208         struct w83627hf_data *data;
1209         struct resource *res;
1210         int err;
1211
1212         static const char *names[] = {
1213                 "w83627hf",
1214                 "w83627thf",
1215                 "w83697hf",
1216                 "w83637hf",
1217                 "w83687thf",
1218         };
1219
1220         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1221         if (!request_region(res->start, WINB_REGION_SIZE, DRVNAME)) {
1222                 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
1223                         (unsigned long)res->start,
1224                         (unsigned long)(res->start + WINB_REGION_SIZE - 1));
1225                 err = -EBUSY;
1226                 goto ERROR0;
1227         }
1228
1229         if (!(data = kzalloc(sizeof(struct w83627hf_data), GFP_KERNEL))) {
1230                 err = -ENOMEM;
1231                 goto ERROR1;
1232         }
1233         data->addr = res->start;
1234         data->type = sio_data->type;
1235         data->name = names[sio_data->type];
1236         mutex_init(&data->lock);
1237         mutex_init(&data->update_lock);
1238         platform_set_drvdata(pdev, data);
1239
1240         /* Initialize the chip */
1241         w83627hf_init_device(pdev);
1242
1243         /* A few vars need to be filled upon startup */
1244         data->fan_min[0] = w83627hf_read_value(data, W83781D_REG_FAN_MIN(1));
1245         data->fan_min[1] = w83627hf_read_value(data, W83781D_REG_FAN_MIN(2));
1246         data->fan_min[2] = w83627hf_read_value(data, W83781D_REG_FAN_MIN(3));
1247
1248         /* Register common device attributes */
1249         if ((err = sysfs_create_group(&dev->kobj, &w83627hf_group)))
1250                 goto ERROR3;
1251
1252         /* Register chip-specific device attributes */
1253         if (data->type == w83627hf || data->type == w83697hf)
1254                 if ((err = device_create_file(dev, &dev_attr_in5_input))
1255                  || (err = device_create_file(dev, &dev_attr_in5_min))
1256                  || (err = device_create_file(dev, &dev_attr_in5_max))
1257                  || (err = device_create_file(dev, &dev_attr_in6_input))
1258                  || (err = device_create_file(dev, &dev_attr_in6_min))
1259                  || (err = device_create_file(dev, &dev_attr_in6_max))
1260                  || (err = device_create_file(dev, &dev_attr_pwm1_freq))
1261                  || (err = device_create_file(dev, &dev_attr_pwm2_freq)))
1262                         goto ERROR4;
1263
1264         if (data->type != w83697hf)
1265                 if ((err = device_create_file(dev, &dev_attr_in1_input))
1266                  || (err = device_create_file(dev, &dev_attr_in1_min))
1267                  || (err = device_create_file(dev, &dev_attr_in1_max))
1268                  || (err = device_create_file(dev, &dev_attr_fan3_input))
1269                  || (err = device_create_file(dev, &dev_attr_fan3_min))
1270                  || (err = device_create_file(dev, &dev_attr_fan3_div))
1271                  || (err = device_create_file(dev, &dev_attr_temp3_input))
1272                  || (err = device_create_file(dev, &dev_attr_temp3_max))
1273                  || (err = device_create_file(dev, &dev_attr_temp3_max_hyst))
1274                  || (err = device_create_file(dev, &dev_attr_temp3_type)))
1275                         goto ERROR4;
1276
1277         if (data->type != w83697hf && data->vid != 0xff) {
1278                 /* Convert VID to voltage based on VRM */
1279                 data->vrm = vid_which_vrm();
1280
1281                 if ((err = device_create_file(dev, &dev_attr_cpu0_vid))
1282                  || (err = device_create_file(dev, &dev_attr_vrm)))
1283                         goto ERROR4;
1284         }
1285
1286         if (data->type == w83627thf || data->type == w83637hf
1287          || data->type == w83687thf)
1288                 if ((err = device_create_file(dev, &dev_attr_pwm3)))
1289                         goto ERROR4;
1290
1291         if (data->type == w83637hf || data->type == w83687thf)
1292                 if ((err = device_create_file(dev, &dev_attr_pwm1_freq))
1293                  || (err = device_create_file(dev, &dev_attr_pwm2_freq))
1294                  || (err = device_create_file(dev, &dev_attr_pwm3_freq)))
1295                         goto ERROR4;
1296
1297         data->class_dev = hwmon_device_register(dev);
1298         if (IS_ERR(data->class_dev)) {
1299                 err = PTR_ERR(data->class_dev);
1300                 goto ERROR4;
1301         }
1302
1303         return 0;
1304
1305       ERROR4:
1306         sysfs_remove_group(&dev->kobj, &w83627hf_group);
1307         sysfs_remove_group(&dev->kobj, &w83627hf_group_opt);
1308       ERROR3:
1309         kfree(data);
1310       ERROR1:
1311         release_region(res->start, WINB_REGION_SIZE);
1312       ERROR0:
1313         return err;
1314 }
1315
1316 static int __devexit w83627hf_remove(struct platform_device *pdev)
1317 {
1318         struct w83627hf_data *data = platform_get_drvdata(pdev);
1319         struct resource *res;
1320
1321         platform_set_drvdata(pdev, NULL);
1322         hwmon_device_unregister(data->class_dev);
1323
1324         sysfs_remove_group(&pdev->dev.kobj, &w83627hf_group);
1325         sysfs_remove_group(&pdev->dev.kobj, &w83627hf_group_opt);
1326         kfree(data);
1327
1328         res = platform_get_resource(pdev, IORESOURCE_IO, 0);
1329         release_region(res->start, WINB_REGION_SIZE);
1330
1331         return 0;
1332 }
1333
1334
1335 static int w83627hf_read_value(struct w83627hf_data *data, u16 reg)
1336 {
1337         int res, word_sized;
1338
1339         mutex_lock(&data->lock);
1340         word_sized = (((reg & 0xff00) == 0x100)
1341                    || ((reg & 0xff00) == 0x200))
1342                   && (((reg & 0x00ff) == 0x50)
1343                    || ((reg & 0x00ff) == 0x53)
1344                    || ((reg & 0x00ff) == 0x55));
1345         if (reg & 0xff00) {
1346                 outb_p(W83781D_REG_BANK,
1347                        data->addr + W83781D_ADDR_REG_OFFSET);
1348                 outb_p(reg >> 8,
1349                        data->addr + W83781D_DATA_REG_OFFSET);
1350         }
1351         outb_p(reg & 0xff, data->addr + W83781D_ADDR_REG_OFFSET);
1352         res = inb_p(data->addr + W83781D_DATA_REG_OFFSET);
1353         if (word_sized) {
1354                 outb_p((reg & 0xff) + 1,
1355                        data->addr + W83781D_ADDR_REG_OFFSET);
1356                 res =
1357                     (res << 8) + inb_p(data->addr +
1358                                        W83781D_DATA_REG_OFFSET);
1359         }
1360         if (reg & 0xff00) {
1361                 outb_p(W83781D_REG_BANK,
1362                        data->addr + W83781D_ADDR_REG_OFFSET);
1363                 outb_p(0, data->addr + W83781D_DATA_REG_OFFSET);
1364         }
1365         mutex_unlock(&data->lock);
1366         return res;
1367 }
1368
1369 static int __devinit w83627thf_read_gpio5(struct platform_device *pdev)
1370 {
1371         int res = 0xff, sel;
1372
1373         superio_enter();
1374         superio_select(W83627HF_LD_GPIO5);
1375
1376         /* Make sure these GPIO pins are enabled */
1377         if (!(superio_inb(W83627THF_GPIO5_EN) & (1<<3))) {
1378                 dev_dbg(&pdev->dev, "GPIO5 disabled, no VID function\n");
1379                 goto exit;
1380         }
1381
1382         /* Make sure the pins are configured for input
1383            There must be at least five (VRM 9), and possibly 6 (VRM 10) */
1384         sel = superio_inb(W83627THF_GPIO5_IOSR) & 0x3f;
1385         if ((sel & 0x1f) != 0x1f) {
1386                 dev_dbg(&pdev->dev, "GPIO5 not configured for VID "
1387                         "function\n");
1388                 goto exit;
1389         }
1390
1391         dev_info(&pdev->dev, "Reading VID from GPIO5\n");
1392         res = superio_inb(W83627THF_GPIO5_DR) & sel;
1393
1394 exit:
1395         superio_exit();
1396         return res;
1397 }
1398
1399 static int __devinit w83687thf_read_vid(struct platform_device *pdev)
1400 {
1401         int res = 0xff;
1402
1403         superio_enter();
1404         superio_select(W83627HF_LD_HWM);
1405
1406         /* Make sure these GPIO pins are enabled */
1407         if (!(superio_inb(W83687THF_VID_EN) & (1 << 2))) {
1408                 dev_dbg(&pdev->dev, "VID disabled, no VID function\n");
1409                 goto exit;
1410         }
1411
1412         /* Make sure the pins are configured for input */
1413         if (!(superio_inb(W83687THF_VID_CFG) & (1 << 4))) {
1414                 dev_dbg(&pdev->dev, "VID configured as output, "
1415                         "no VID function\n");
1416                 goto exit;
1417         }
1418
1419         res = superio_inb(W83687THF_VID_DATA) & 0x3f;
1420
1421 exit:
1422         superio_exit();
1423         return res;
1424 }
1425
1426 static int w83627hf_write_value(struct w83627hf_data *data, u16 reg, u16 value)
1427 {
1428         int word_sized;
1429
1430         mutex_lock(&data->lock);
1431         word_sized = (((reg & 0xff00) == 0x100)
1432                    || ((reg & 0xff00) == 0x200))
1433                   && (((reg & 0x00ff) == 0x53)
1434                    || ((reg & 0x00ff) == 0x55));
1435         if (reg & 0xff00) {
1436                 outb_p(W83781D_REG_BANK,
1437                        data->addr + W83781D_ADDR_REG_OFFSET);
1438                 outb_p(reg >> 8,
1439                        data->addr + W83781D_DATA_REG_OFFSET);
1440         }
1441         outb_p(reg & 0xff, data->addr + W83781D_ADDR_REG_OFFSET);
1442         if (word_sized) {
1443                 outb_p(value >> 8,
1444                        data->addr + W83781D_DATA_REG_OFFSET);
1445                 outb_p((reg & 0xff) + 1,
1446                        data->addr + W83781D_ADDR_REG_OFFSET);
1447         }
1448         outb_p(value & 0xff,
1449                data->addr + W83781D_DATA_REG_OFFSET);
1450         if (reg & 0xff00) {
1451                 outb_p(W83781D_REG_BANK,
1452                        data->addr + W83781D_ADDR_REG_OFFSET);
1453                 outb_p(0, data->addr + W83781D_DATA_REG_OFFSET);
1454         }
1455         mutex_unlock(&data->lock);
1456         return 0;
1457 }
1458
1459 static void __devinit w83627hf_init_device(struct platform_device *pdev)
1460 {
1461         struct w83627hf_data *data = platform_get_drvdata(pdev);
1462         int i;
1463         enum chips type = data->type;
1464         u8 tmp;
1465
1466         if (reset) {
1467                 /* Resetting the chip has been the default for a long time,
1468                    but repeatedly caused problems (fans going to full
1469                    speed...) so it is now optional. It might even go away if
1470                    nobody reports it as being useful, as I see very little
1471                    reason why this would be needed at all. */
1472                 dev_info(&pdev->dev, "If reset=1 solved a problem you were "
1473                          "having, please report!\n");
1474
1475                 /* save this register */
1476                 i = w83627hf_read_value(data, W83781D_REG_BEEP_CONFIG);
1477                 /* Reset all except Watchdog values and last conversion values
1478                    This sets fan-divs to 2, among others */
1479                 w83627hf_write_value(data, W83781D_REG_CONFIG, 0x80);
1480                 /* Restore the register and disable power-on abnormal beep.
1481                    This saves FAN 1/2/3 input/output values set by BIOS. */
1482                 w83627hf_write_value(data, W83781D_REG_BEEP_CONFIG, i | 0x80);
1483                 /* Disable master beep-enable (reset turns it on).
1484                    Individual beeps should be reset to off but for some reason
1485                    disabling this bit helps some people not get beeped */
1486                 w83627hf_write_value(data, W83781D_REG_BEEP_INTS2, 0);
1487         }
1488
1489         /* Minimize conflicts with other winbond i2c-only clients...  */
1490         /* disable i2c subclients... how to disable main i2c client?? */
1491         /* force i2c address to relatively uncommon address */
1492         w83627hf_write_value(data, W83781D_REG_I2C_SUBADDR, 0x89);
1493         w83627hf_write_value(data, W83781D_REG_I2C_ADDR, force_i2c);
1494
1495         /* Read VID only once */
1496         if (type == w83627hf || type == w83637hf) {
1497                 int lo = w83627hf_read_value(data, W83781D_REG_VID_FANDIV);
1498                 int hi = w83627hf_read_value(data, W83781D_REG_CHIPID);
1499                 data->vid = (lo & 0x0f) | ((hi & 0x01) << 4);
1500         } else if (type == w83627thf) {
1501                 data->vid = w83627thf_read_gpio5(pdev);
1502         } else if (type == w83687thf) {
1503                 data->vid = w83687thf_read_vid(pdev);
1504         }
1505
1506         /* Read VRM & OVT Config only once */
1507         if (type == w83627thf || type == w83637hf || type == w83687thf) {
1508                 data->vrm_ovt =
1509                         w83627hf_read_value(data, W83627THF_REG_VRM_OVT_CFG);
1510         }
1511
1512         tmp = w83627hf_read_value(data, W83781D_REG_SCFG1);
1513         for (i = 1; i <= 3; i++) {
1514                 if (!(tmp & BIT_SCFG1[i - 1])) {
1515                         data->sens[i - 1] = W83781D_DEFAULT_BETA;
1516                 } else {
1517                         if (w83627hf_read_value
1518                             (data,
1519                              W83781D_REG_SCFG2) & BIT_SCFG2[i - 1])
1520                                 data->sens[i - 1] = 1;
1521                         else
1522                                 data->sens[i - 1] = 2;
1523                 }
1524                 if ((type == w83697hf) && (i == 2))
1525                         break;
1526         }
1527
1528         if(init) {
1529                 /* Enable temp2 */
1530                 tmp = w83627hf_read_value(data, W83781D_REG_TEMP2_CONFIG);
1531                 if (tmp & 0x01) {
1532                         dev_warn(&pdev->dev, "Enabling temp2, readings "
1533                                  "might not make sense\n");
1534                         w83627hf_write_value(data, W83781D_REG_TEMP2_CONFIG,
1535                                 tmp & 0xfe);
1536                 }
1537
1538                 /* Enable temp3 */
1539                 if (type != w83697hf) {
1540                         tmp = w83627hf_read_value(data,
1541                                 W83781D_REG_TEMP3_CONFIG);
1542                         if (tmp & 0x01) {
1543                                 dev_warn(&pdev->dev, "Enabling temp3, "
1544                                          "readings might not make sense\n");
1545                                 w83627hf_write_value(data,
1546                                         W83781D_REG_TEMP3_CONFIG, tmp & 0xfe);
1547                         }
1548                 }
1549         }
1550
1551         /* Start monitoring */
1552         w83627hf_write_value(data, W83781D_REG_CONFIG,
1553                             (w83627hf_read_value(data,
1554                                                 W83781D_REG_CONFIG) & 0xf7)
1555                             | 0x01);
1556 }
1557
1558 static struct w83627hf_data *w83627hf_update_device(struct device *dev)
1559 {
1560         struct w83627hf_data *data = dev_get_drvdata(dev);
1561         int i;
1562
1563         mutex_lock(&data->update_lock);
1564
1565         if (time_after(jiffies, data->last_updated + HZ + HZ / 2)
1566             || !data->valid) {
1567                 for (i = 0; i <= 8; i++) {
1568                         /* skip missing sensors */
1569                         if (((data->type == w83697hf) && (i == 1)) ||
1570                             ((data->type != w83627hf && data->type != w83697hf)
1571                             && (i == 5 || i == 6)))
1572                                 continue;
1573                         data->in[i] =
1574                             w83627hf_read_value(data, W83781D_REG_IN(i));
1575                         data->in_min[i] =
1576                             w83627hf_read_value(data,
1577                                                W83781D_REG_IN_MIN(i));
1578                         data->in_max[i] =
1579                             w83627hf_read_value(data,
1580                                                W83781D_REG_IN_MAX(i));
1581                 }
1582                 for (i = 1; i <= 3; i++) {
1583                         data->fan[i - 1] =
1584                             w83627hf_read_value(data, W83781D_REG_FAN(i));
1585                         data->fan_min[i - 1] =
1586                             w83627hf_read_value(data,
1587                                                W83781D_REG_FAN_MIN(i));
1588                 }
1589                 for (i = 1; i <= 3; i++) {
1590                         u8 tmp = w83627hf_read_value(data,
1591                                 W836X7HF_REG_PWM(data->type, i));
1592                         /* bits 0-3 are reserved  in 627THF */
1593                         if (data->type == w83627thf)
1594                                 tmp &= 0xf0;
1595                         data->pwm[i - 1] = tmp;
1596                         if(i == 2 &&
1597                            (data->type == w83627hf || data->type == w83697hf))
1598                                 break;
1599                 }
1600                 if (data->type == w83627hf) {
1601                                 u8 tmp = w83627hf_read_value(data,
1602                                                 W83627HF_REG_PWM_FREQ);
1603                                 data->pwm_freq[0] = tmp & 0x07;
1604                                 data->pwm_freq[1] = (tmp >> 4) & 0x07;
1605                 } else if (data->type != w83627thf) {
1606                         for (i = 1; i <= 3; i++) {
1607                                 data->pwm_freq[i - 1] =
1608                                         w83627hf_read_value(data,
1609                                                 W83637HF_REG_PWM_FREQ[i - 1]);
1610                                 if (i == 2 && (data->type == w83697hf))
1611                                         break;
1612                         }
1613                 }
1614
1615                 data->temp = w83627hf_read_value(data, W83781D_REG_TEMP(1));
1616                 data->temp_max =
1617                     w83627hf_read_value(data, W83781D_REG_TEMP_OVER(1));
1618                 data->temp_max_hyst =
1619                     w83627hf_read_value(data, W83781D_REG_TEMP_HYST(1));
1620                 data->temp_add[0] =
1621                     w83627hf_read_value(data, W83781D_REG_TEMP(2));
1622                 data->temp_max_add[0] =
1623                     w83627hf_read_value(data, W83781D_REG_TEMP_OVER(2));
1624                 data->temp_max_hyst_add[0] =
1625                     w83627hf_read_value(data, W83781D_REG_TEMP_HYST(2));
1626                 if (data->type != w83697hf) {
1627                         data->temp_add[1] =
1628                           w83627hf_read_value(data, W83781D_REG_TEMP(3));
1629                         data->temp_max_add[1] =
1630                           w83627hf_read_value(data, W83781D_REG_TEMP_OVER(3));
1631                         data->temp_max_hyst_add[1] =
1632                           w83627hf_read_value(data, W83781D_REG_TEMP_HYST(3));
1633                 }
1634
1635                 i = w83627hf_read_value(data, W83781D_REG_VID_FANDIV);
1636                 data->fan_div[0] = (i >> 4) & 0x03;
1637                 data->fan_div[1] = (i >> 6) & 0x03;
1638                 if (data->type != w83697hf) {
1639                         data->fan_div[2] = (w83627hf_read_value(data,
1640                                                W83781D_REG_PIN) >> 6) & 0x03;
1641                 }
1642                 i = w83627hf_read_value(data, W83781D_REG_VBAT);
1643                 data->fan_div[0] |= (i >> 3) & 0x04;
1644                 data->fan_div[1] |= (i >> 4) & 0x04;
1645                 if (data->type != w83697hf)
1646                         data->fan_div[2] |= (i >> 5) & 0x04;
1647                 data->alarms =
1648                     w83627hf_read_value(data, W83781D_REG_ALARM1) |
1649                     (w83627hf_read_value(data, W83781D_REG_ALARM2) << 8) |
1650                     (w83627hf_read_value(data, W83781D_REG_ALARM3) << 16);
1651                 i = w83627hf_read_value(data, W83781D_REG_BEEP_INTS2);
1652                 data->beep_enable = i >> 7;
1653                 data->beep_mask = ((i & 0x7f) << 8) |
1654                     w83627hf_read_value(data, W83781D_REG_BEEP_INTS1) |
1655                     w83627hf_read_value(data, W83781D_REG_BEEP_INTS3) << 16;
1656                 data->last_updated = jiffies;
1657                 data->valid = 1;
1658         }
1659
1660         mutex_unlock(&data->update_lock);
1661
1662         return data;
1663 }
1664
1665 static int __init w83627hf_device_add(unsigned short address,
1666                                       const struct w83627hf_sio_data *sio_data)
1667 {
1668         struct resource res = {
1669                 .start  = address + WINB_REGION_OFFSET,
1670                 .end    = address + WINB_REGION_OFFSET + WINB_REGION_SIZE - 1,
1671                 .name   = DRVNAME,
1672                 .flags  = IORESOURCE_IO,
1673         };
1674         int err;
1675
1676         pdev = platform_device_alloc(DRVNAME, address);
1677         if (!pdev) {
1678                 err = -ENOMEM;
1679                 printk(KERN_ERR DRVNAME ": Device allocation failed\n");
1680                 goto exit;
1681         }
1682
1683         err = platform_device_add_resources(pdev, &res, 1);
1684         if (err) {
1685                 printk(KERN_ERR DRVNAME ": Device resource addition failed "
1686                        "(%d)\n", err);
1687                 goto exit_device_put;
1688         }
1689
1690         err = platform_device_add_data(pdev, sio_data,
1691                                        sizeof(struct w83627hf_sio_data));
1692         if (err) {
1693                 printk(KERN_ERR DRVNAME ": Platform data allocation failed\n");
1694                 goto exit_device_put;
1695         }
1696
1697         err = platform_device_add(pdev);
1698         if (err) {
1699                 printk(KERN_ERR DRVNAME ": Device addition failed (%d)\n",
1700                        err);
1701                 goto exit_device_put;
1702         }
1703
1704         return 0;
1705
1706 exit_device_put:
1707         platform_device_put(pdev);
1708 exit:
1709         return err;
1710 }
1711
1712 static int __init sensors_w83627hf_init(void)
1713 {
1714         int err;
1715         unsigned short address;
1716         struct w83627hf_sio_data sio_data;
1717
1718         if (w83627hf_find(0x2e, &address, &sio_data)
1719          && w83627hf_find(0x4e, &address, &sio_data))
1720                 return -ENODEV;
1721
1722         err = platform_driver_register(&w83627hf_driver);
1723         if (err)
1724                 goto exit;
1725
1726         /* Sets global pdev as a side effect */
1727         err = w83627hf_device_add(address, &sio_data);
1728         if (err)
1729                 goto exit_driver;
1730
1731         return 0;
1732
1733 exit_driver:
1734         platform_driver_unregister(&w83627hf_driver);
1735 exit:
1736         return err;
1737 }
1738
1739 static void __exit sensors_w83627hf_exit(void)
1740 {
1741         platform_device_unregister(pdev);
1742         platform_driver_unregister(&w83627hf_driver);
1743 }
1744
1745 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>, "
1746               "Philip Edelbrock <phil@netroedge.com>, "
1747               "and Mark Studebaker <mdsxyz123@yahoo.com>");
1748 MODULE_DESCRIPTION("W83627HF driver");
1749 MODULE_LICENSE("GPL");
1750
1751 module_init(sensors_w83627hf_init);
1752 module_exit(sensors_w83627hf_exit);