4 Copyright (c) 2006-2008 Hans de Goede <hdegoede@redhat.com>
5 Copyright (c) 2008 Alistair John Strachan <alistair@devzero.co.uk>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 This driver supports the sensor part of revision 3 of the custom Abit uGuru
23 chip found on newer Abit uGuru motherboards. Note: because of lack of specs
24 only reading the sensors and their settings is supported.
27 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29 #include <linux/module.h>
30 #include <linux/init.h>
31 #include <linux/slab.h>
32 #include <linux/jiffies.h>
33 #include <linux/mutex.h>
34 #include <linux/err.h>
35 #include <linux/delay.h>
36 #include <linux/platform_device.h>
37 #include <linux/hwmon.h>
38 #include <linux/hwmon-sysfs.h>
39 #include <linux/dmi.h>
42 /* uGuru3 bank addresses */
43 #define ABIT_UGURU3_SETTINGS_BANK 0x01
44 #define ABIT_UGURU3_SENSORS_BANK 0x08
45 #define ABIT_UGURU3_MISC_BANK 0x09
46 #define ABIT_UGURU3_ALARMS_START 0x1E
47 #define ABIT_UGURU3_SETTINGS_START 0x24
48 #define ABIT_UGURU3_VALUES_START 0x80
49 #define ABIT_UGURU3_BOARD_ID 0x0A
50 /* uGuru3 sensor bank flags */ /* Alarm if: */
51 #define ABIT_UGURU3_TEMP_HIGH_ALARM_ENABLE 0x01 /* temp over warn */
52 #define ABIT_UGURU3_VOLT_HIGH_ALARM_ENABLE 0x02 /* volt over max */
53 #define ABIT_UGURU3_VOLT_LOW_ALARM_ENABLE 0x04 /* volt under min */
54 #define ABIT_UGURU3_TEMP_HIGH_ALARM_FLAG 0x10 /* temp is over warn */
55 #define ABIT_UGURU3_VOLT_HIGH_ALARM_FLAG 0x20 /* volt is over max */
56 #define ABIT_UGURU3_VOLT_LOW_ALARM_FLAG 0x40 /* volt is under min */
57 #define ABIT_UGURU3_FAN_LOW_ALARM_ENABLE 0x01 /* fan under min */
58 #define ABIT_UGURU3_BEEP_ENABLE 0x08 /* beep if alarm */
59 #define ABIT_UGURU3_SHUTDOWN_ENABLE 0x80 /* shutdown if alarm */
61 #define ABIT_UGURU3_IN_SENSOR 0
62 #define ABIT_UGURU3_TEMP_SENSOR 1
63 #define ABIT_UGURU3_FAN_SENSOR 2
65 /* Timeouts / Retries, if these turn out to need a lot of fiddling we could
66 convert them to params. Determined by trial and error. I assume this is
67 cpu-speed independent, since the ISA-bus and not the CPU should be the
69 #define ABIT_UGURU3_WAIT_TIMEOUT 250
70 /* Normally the 0xAC at the end of synchronize() is reported after the
71 first read, but sometimes not and we need to poll */
72 #define ABIT_UGURU3_SYNCHRONIZE_TIMEOUT 5
74 #define ABIT_UGURU3_NAME "abituguru3"
75 #define ABIT_UGURU3_DEBUG(format, arg...) \
77 printk(KERN_DEBUG ABIT_UGURU3_NAME ": " format , ## arg)
79 /* Macros to help calculate the sysfs_names array length */
80 #define ABIT_UGURU3_MAX_NO_SENSORS 26
81 /* sum of strlen +1 of: in??_input\0, in??_{min,max}\0, in??_{min,max}_alarm\0,
82 in??_{min,max}_alarm_enable\0, in??_beep\0, in??_shutdown\0, in??_label\0 */
83 #define ABIT_UGURU3_IN_NAMES_LENGTH \
84 (11 + 2 * 9 + 2 * 15 + 2 * 22 + 10 + 14 + 11)
85 /* sum of strlen +1 of: temp??_input\0, temp??_max\0, temp??_crit\0,
86 temp??_alarm\0, temp??_alarm_enable\0, temp??_beep\0, temp??_shutdown\0,
88 #define ABIT_UGURU3_TEMP_NAMES_LENGTH (13 + 11 + 12 + 13 + 20 + 12 + 16 + 13)
89 /* sum of strlen +1 of: fan??_input\0, fan??_min\0, fan??_alarm\0,
90 fan??_alarm_enable\0, fan??_beep\0, fan??_shutdown\0, fan??_label\0 */
91 #define ABIT_UGURU3_FAN_NAMES_LENGTH (12 + 10 + 12 + 19 + 11 + 15 + 12)
92 /* Worst case scenario 16 in sensors (longest names_length) and the rest
93 temp sensors (second longest names_length). */
94 #define ABIT_UGURU3_SYSFS_NAMES_LENGTH (16 * ABIT_UGURU3_IN_NAMES_LENGTH + \
95 (ABIT_UGURU3_MAX_NO_SENSORS - 16) * ABIT_UGURU3_TEMP_NAMES_LENGTH)
97 /* All the macros below are named identical to the openguru2 program
98 reverse engineered by Louis Kruger, hence the names might not be 100%
99 logical. I could come up with better names, but I prefer keeping the names
100 identical so that this driver can be compared with his work more easily. */
101 /* Two i/o-ports are used by uGuru */
102 #define ABIT_UGURU3_BASE 0x00E0
103 #define ABIT_UGURU3_CMD 0x00
104 #define ABIT_UGURU3_DATA 0x04
105 #define ABIT_UGURU3_REGION_LENGTH 5
106 /* The wait_xxx functions return this on success and the last contents
107 of the DATA register (0-255) on failure. */
108 #define ABIT_UGURU3_SUCCESS -1
109 /* uGuru status flags */
110 #define ABIT_UGURU3_STATUS_READY_FOR_READ 0x01
111 #define ABIT_UGURU3_STATUS_BUSY 0x02
115 struct abituguru3_sensor_info {
124 /* Avoid use of flexible array members */
125 #define ABIT_UGURU3_MAX_DMI_NAMES 2
127 struct abituguru3_motherboard_info {
129 const char *dmi_name[ABIT_UGURU3_MAX_DMI_NAMES + 1];
130 /* + 1 -> end of sensors indicated by a sensor with name == NULL */
131 struct abituguru3_sensor_info sensors[ABIT_UGURU3_MAX_NO_SENSORS + 1];
134 /* For the Abit uGuru, we need to keep some data in memory.
135 The structure is dynamically allocated, at the same time when a new
136 abituguru3 device is allocated. */
137 struct abituguru3_data {
138 struct device *hwmon_dev; /* hwmon registered device */
139 struct mutex update_lock; /* protect access to data and uGuru */
140 unsigned short addr; /* uguru base address */
141 char valid; /* !=0 if following fields are valid */
142 unsigned long last_updated; /* In jiffies */
144 /* For convenience the sysfs attr and their names are generated
145 automatically. We have max 10 entries per sensor (for in sensors) */
146 struct sensor_device_attribute_2 sysfs_attr[ABIT_UGURU3_MAX_NO_SENSORS
149 /* Buffer to store the dynamically generated sysfs names */
150 char sysfs_names[ABIT_UGURU3_SYSFS_NAMES_LENGTH];
152 /* Pointer to the sensors info for the detected motherboard */
153 const struct abituguru3_sensor_info *sensors;
155 /* The abituguru3 supports up to 48 sensors, and thus has registers
156 sets for 48 sensors, for convienence reasons / simplicity of the
157 code we always read and store all registers for all 48 sensors */
159 /* Alarms for all 48 sensors (1 bit per sensor) */
162 /* Value of all 48 sensors */
165 /* Settings of all 48 sensors, note in and temp sensors (the first 32
166 sensors) have 3 bytes of settings, while fans only have 2 bytes,
167 for convenience we use 3 bytes for all sensors */
173 static const struct abituguru3_motherboard_info abituguru3_motherboards[] = {
174 { 0x000C, { NULL } /* Unknown, need DMI string */, {
175 { "CPU Core", 0, 0, 10, 1, 0 },
176 { "DDR", 1, 0, 10, 1, 0 },
177 { "DDR VTT", 2, 0, 10, 1, 0 },
178 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
179 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
180 { "MCH 2.5V", 5, 0, 20, 1, 0 },
181 { "ICH 1.05V", 6, 0, 10, 1, 0 },
182 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
183 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
184 { "ATX +5V", 9, 0, 30, 1, 0 },
185 { "+3.3V", 10, 0, 20, 1, 0 },
186 { "5VSB", 11, 0, 30, 1, 0 },
187 { "CPU", 24, 1, 1, 1, 0 },
188 { "System", 25, 1, 1, 1, 0 },
189 { "PWM", 26, 1, 1, 1, 0 },
190 { "CPU Fan", 32, 2, 60, 1, 0 },
191 { "NB Fan", 33, 2, 60, 1, 0 },
192 { "SYS FAN", 34, 2, 60, 1, 0 },
193 { "AUX1 Fan", 35, 2, 60, 1, 0 },
194 { NULL, 0, 0, 0, 0, 0 } }
196 { 0x000D, { NULL } /* Abit AW8, need DMI string */, {
197 { "CPU Core", 0, 0, 10, 1, 0 },
198 { "DDR", 1, 0, 10, 1, 0 },
199 { "DDR VTT", 2, 0, 10, 1, 0 },
200 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
201 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
202 { "MCH 2.5V", 5, 0, 20, 1, 0 },
203 { "ICH 1.05V", 6, 0, 10, 1, 0 },
204 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
205 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
206 { "ATX +5V", 9, 0, 30, 1, 0 },
207 { "+3.3V", 10, 0, 20, 1, 0 },
208 { "5VSB", 11, 0, 30, 1, 0 },
209 { "CPU", 24, 1, 1, 1, 0 },
210 { "System", 25, 1, 1, 1, 0 },
211 { "PWM1", 26, 1, 1, 1, 0 },
212 { "PWM2", 27, 1, 1, 1, 0 },
213 { "PWM3", 28, 1, 1, 1, 0 },
214 { "PWM4", 29, 1, 1, 1, 0 },
215 { "CPU Fan", 32, 2, 60, 1, 0 },
216 { "NB Fan", 33, 2, 60, 1, 0 },
217 { "SYS Fan", 34, 2, 60, 1, 0 },
218 { "AUX1 Fan", 35, 2, 60, 1, 0 },
219 { "AUX2 Fan", 36, 2, 60, 1, 0 },
220 { "AUX3 Fan", 37, 2, 60, 1, 0 },
221 { "AUX4 Fan", 38, 2, 60, 1, 0 },
222 { "AUX5 Fan", 39, 2, 60, 1, 0 },
223 { NULL, 0, 0, 0, 0, 0 } }
225 { 0x000E, { NULL } /* AL-8, need DMI string */, {
226 { "CPU Core", 0, 0, 10, 1, 0 },
227 { "DDR", 1, 0, 10, 1, 0 },
228 { "DDR VTT", 2, 0, 10, 1, 0 },
229 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
230 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
231 { "MCH 2.5V", 5, 0, 20, 1, 0 },
232 { "ICH 1.05V", 6, 0, 10, 1, 0 },
233 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
234 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
235 { "ATX +5V", 9, 0, 30, 1, 0 },
236 { "+3.3V", 10, 0, 20, 1, 0 },
237 { "5VSB", 11, 0, 30, 1, 0 },
238 { "CPU", 24, 1, 1, 1, 0 },
239 { "System", 25, 1, 1, 1, 0 },
240 { "PWM", 26, 1, 1, 1, 0 },
241 { "CPU Fan", 32, 2, 60, 1, 0 },
242 { "NB Fan", 33, 2, 60, 1, 0 },
243 { "SYS Fan", 34, 2, 60, 1, 0 },
244 { NULL, 0, 0, 0, 0, 0 } }
246 { 0x000F, { NULL } /* Unknown, need DMI string */, {
248 { "CPU Core", 0, 0, 10, 1, 0 },
249 { "DDR", 1, 0, 10, 1, 0 },
250 { "DDR VTT", 2, 0, 10, 1, 0 },
251 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
252 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
253 { "MCH 2.5V", 5, 0, 20, 1, 0 },
254 { "ICH 1.05V", 6, 0, 10, 1, 0 },
255 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
256 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
257 { "ATX +5V", 9, 0, 30, 1, 0 },
258 { "+3.3V", 10, 0, 20, 1, 0 },
259 { "5VSB", 11, 0, 30, 1, 0 },
260 { "CPU", 24, 1, 1, 1, 0 },
261 { "System", 25, 1, 1, 1, 0 },
262 { "PWM", 26, 1, 1, 1, 0 },
263 { "CPU Fan", 32, 2, 60, 1, 0 },
264 { "NB Fan", 33, 2, 60, 1, 0 },
265 { "SYS Fan", 34, 2, 60, 1, 0 },
266 { NULL, 0, 0, 0, 0, 0 } }
268 { 0x0010, { NULL } /* Abit NI8 SLI GR, need DMI string */, {
269 { "CPU Core", 0, 0, 10, 1, 0 },
270 { "DDR", 1, 0, 10, 1, 0 },
271 { "DDR VTT", 2, 0, 10, 1, 0 },
272 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
273 { "NB 1.4V", 4, 0, 10, 1, 0 },
274 { "SB 1.5V", 6, 0, 10, 1, 0 },
275 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
276 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
277 { "ATX +5V", 9, 0, 30, 1, 0 },
278 { "+3.3V", 10, 0, 20, 1, 0 },
279 { "5VSB", 11, 0, 30, 1, 0 },
280 { "CPU", 24, 1, 1, 1, 0 },
281 { "SYS", 25, 1, 1, 1, 0 },
282 { "PWM", 26, 1, 1, 1, 0 },
283 { "CPU Fan", 32, 2, 60, 1, 0 },
284 { "NB Fan", 33, 2, 60, 1, 0 },
285 { "SYS Fan", 34, 2, 60, 1, 0 },
286 { "AUX1 Fan", 35, 2, 60, 1, 0 },
287 { "OTES1 Fan", 36, 2, 60, 1, 0 },
288 { NULL, 0, 0, 0, 0, 0 } }
290 { 0x0011, { "AT8 32X", NULL }, {
291 { "CPU Core", 0, 0, 10, 1, 0 },
292 { "DDR", 1, 0, 20, 1, 0 },
293 { "DDR VTT", 2, 0, 10, 1, 0 },
294 { "CPU VDDA 2.5V", 6, 0, 20, 1, 0 },
295 { "NB 1.8V", 4, 0, 10, 1, 0 },
296 { "NB 1.8V Dual", 5, 0, 10, 1, 0 },
297 { "HTV 1.2", 3, 0, 10, 1, 0 },
298 { "PCIE 1.2V", 12, 0, 10, 1, 0 },
299 { "NB 1.2V", 13, 0, 10, 1, 0 },
300 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
301 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
302 { "ATX +5V", 9, 0, 30, 1, 0 },
303 { "+3.3V", 10, 0, 20, 1, 0 },
304 { "5VSB", 11, 0, 30, 1, 0 },
305 { "CPU", 24, 1, 1, 1, 0 },
306 { "NB", 25, 1, 1, 1, 0 },
307 { "System", 26, 1, 1, 1, 0 },
308 { "PWM", 27, 1, 1, 1, 0 },
309 { "CPU Fan", 32, 2, 60, 1, 0 },
310 { "NB Fan", 33, 2, 60, 1, 0 },
311 { "SYS Fan", 34, 2, 60, 1, 0 },
312 { "AUX1 Fan", 35, 2, 60, 1, 0 },
313 { "AUX2 Fan", 36, 2, 60, 1, 0 },
314 { "AUX3 Fan", 37, 2, 60, 1, 0 },
315 { NULL, 0, 0, 0, 0, 0 } }
317 { 0x0012, { NULL } /* Abit AN8 32X, need DMI string */, {
318 { "CPU Core", 0, 0, 10, 1, 0 },
319 { "DDR", 1, 0, 20, 1, 0 },
320 { "DDR VTT", 2, 0, 10, 1, 0 },
321 { "HyperTransport", 3, 0, 10, 1, 0 },
322 { "CPU VDDA 2.5V", 5, 0, 20, 1, 0 },
323 { "NB", 4, 0, 10, 1, 0 },
324 { "SB", 6, 0, 10, 1, 0 },
325 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
326 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
327 { "ATX +5V", 9, 0, 30, 1, 0 },
328 { "+3.3V", 10, 0, 20, 1, 0 },
329 { "5VSB", 11, 0, 30, 1, 0 },
330 { "CPU", 24, 1, 1, 1, 0 },
331 { "SYS", 25, 1, 1, 1, 0 },
332 { "PWM", 26, 1, 1, 1, 0 },
333 { "CPU Fan", 32, 2, 60, 1, 0 },
334 { "NB Fan", 33, 2, 60, 1, 0 },
335 { "SYS Fan", 34, 2, 60, 1, 0 },
336 { "AUX1 Fan", 36, 2, 60, 1, 0 },
337 { NULL, 0, 0, 0, 0, 0 } }
339 { 0x0013, { NULL } /* Abit AW8D, need DMI string */, {
340 { "CPU Core", 0, 0, 10, 1, 0 },
341 { "DDR", 1, 0, 10, 1, 0 },
342 { "DDR VTT", 2, 0, 10, 1, 0 },
343 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
344 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
345 { "MCH 2.5V", 5, 0, 20, 1, 0 },
346 { "ICH 1.05V", 6, 0, 10, 1, 0 },
347 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
348 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
349 { "ATX +5V", 9, 0, 30, 1, 0 },
350 { "+3.3V", 10, 0, 20, 1, 0 },
351 { "5VSB", 11, 0, 30, 1, 0 },
352 { "CPU", 24, 1, 1, 1, 0 },
353 { "System", 25, 1, 1, 1, 0 },
354 { "PWM1", 26, 1, 1, 1, 0 },
355 { "PWM2", 27, 1, 1, 1, 0 },
356 { "PWM3", 28, 1, 1, 1, 0 },
357 { "PWM4", 29, 1, 1, 1, 0 },
358 { "CPU Fan", 32, 2, 60, 1, 0 },
359 { "NB Fan", 33, 2, 60, 1, 0 },
360 { "SYS Fan", 34, 2, 60, 1, 0 },
361 { "AUX1 Fan", 35, 2, 60, 1, 0 },
362 { "AUX2 Fan", 36, 2, 60, 1, 0 },
363 { "AUX3 Fan", 37, 2, 60, 1, 0 },
364 { "AUX4 Fan", 38, 2, 60, 1, 0 },
365 { "AUX5 Fan", 39, 2, 60, 1, 0 },
366 { NULL, 0, 0, 0, 0, 0 } }
368 { 0x0014, { "AB9", "AB9 Pro", NULL }, {
369 { "CPU Core", 0, 0, 10, 1, 0 },
370 { "DDR", 1, 0, 10, 1, 0 },
371 { "DDR VTT", 2, 0, 10, 1, 0 },
372 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
373 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
374 { "MCH 2.5V", 5, 0, 20, 1, 0 },
375 { "ICH 1.05V", 6, 0, 10, 1, 0 },
376 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
377 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
378 { "ATX +5V", 9, 0, 30, 1, 0 },
379 { "+3.3V", 10, 0, 20, 1, 0 },
380 { "5VSB", 11, 0, 30, 1, 0 },
381 { "CPU", 24, 1, 1, 1, 0 },
382 { "System", 25, 1, 1, 1, 0 },
383 { "PWM", 26, 1, 1, 1, 0 },
384 { "CPU Fan", 32, 2, 60, 1, 0 },
385 { "NB Fan", 33, 2, 60, 1, 0 },
386 { "SYS Fan", 34, 2, 60, 1, 0 },
387 { NULL, 0, 0, 0, 0, 0 } }
389 { 0x0015, { NULL } /* Unknown, need DMI string */, {
390 { "CPU Core", 0, 0, 10, 1, 0 },
391 { "DDR", 1, 0, 20, 1, 0 },
392 { "DDR VTT", 2, 0, 10, 1, 0 },
393 { "HyperTransport", 3, 0, 10, 1, 0 },
394 { "CPU VDDA 2.5V", 5, 0, 20, 1, 0 },
395 { "NB", 4, 0, 10, 1, 0 },
396 { "SB", 6, 0, 10, 1, 0 },
397 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
398 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
399 { "ATX +5V", 9, 0, 30, 1, 0 },
400 { "+3.3V", 10, 0, 20, 1, 0 },
401 { "5VSB", 11, 0, 30, 1, 0 },
402 { "CPU", 24, 1, 1, 1, 0 },
403 { "SYS", 25, 1, 1, 1, 0 },
404 { "PWM", 26, 1, 1, 1, 0 },
405 { "CPU Fan", 32, 2, 60, 1, 0 },
406 { "NB Fan", 33, 2, 60, 1, 0 },
407 { "SYS Fan", 34, 2, 60, 1, 0 },
408 { "AUX1 Fan", 33, 2, 60, 1, 0 },
409 { "AUX2 Fan", 35, 2, 60, 1, 0 },
410 { "AUX3 Fan", 36, 2, 60, 1, 0 },
411 { NULL, 0, 0, 0, 0, 0 } }
413 { 0x0016, { "AW9D-MAX", NULL }, {
414 { "CPU Core", 0, 0, 10, 1, 0 },
415 { "DDR2", 1, 0, 20, 1, 0 },
416 { "DDR2 VTT", 2, 0, 10, 1, 0 },
417 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
418 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
419 { "MCH 2.5V", 5, 0, 20, 1, 0 },
420 { "ICH 1.05V", 6, 0, 10, 1, 0 },
421 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
422 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
423 { "ATX +5V", 9, 0, 30, 1, 0 },
424 { "+3.3V", 10, 0, 20, 1, 0 },
425 { "5VSB", 11, 0, 30, 1, 0 },
426 { "CPU", 24, 1, 1, 1, 0 },
427 { "System", 25, 1, 1, 1, 0 },
428 { "PWM1", 26, 1, 1, 1, 0 },
429 { "PWM2", 27, 1, 1, 1, 0 },
430 { "PWM3", 28, 1, 1, 1, 0 },
431 { "PWM4", 29, 1, 1, 1, 0 },
432 { "CPU Fan", 32, 2, 60, 1, 0 },
433 { "NB Fan", 33, 2, 60, 1, 0 },
434 { "SYS Fan", 34, 2, 60, 1, 0 },
435 { "AUX1 Fan", 35, 2, 60, 1, 0 },
436 { "AUX2 Fan", 36, 2, 60, 1, 0 },
437 { "AUX3 Fan", 37, 2, 60, 1, 0 },
438 { "OTES1 Fan", 38, 2, 60, 1, 0 },
439 { NULL, 0, 0, 0, 0, 0 } }
441 { 0x0017, { NULL } /* Unknown, need DMI string */, {
442 { "CPU Core", 0, 0, 10, 1, 0 },
443 { "DDR2", 1, 0, 20, 1, 0 },
444 { "DDR2 VTT", 2, 0, 10, 1, 0 },
445 { "HyperTransport", 3, 0, 10, 1, 0 },
446 { "CPU VDDA 2.5V", 6, 0, 20, 1, 0 },
447 { "NB 1.8V", 4, 0, 10, 1, 0 },
448 { "NB 1.2V ", 13, 0, 10, 1, 0 },
449 { "SB 1.2V", 5, 0, 10, 1, 0 },
450 { "PCIE 1.2V", 12, 0, 10, 1, 0 },
451 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
452 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
453 { "ATX +5V", 9, 0, 30, 1, 0 },
454 { "ATX +3.3V", 10, 0, 20, 1, 0 },
455 { "ATX 5VSB", 11, 0, 30, 1, 0 },
456 { "CPU", 24, 1, 1, 1, 0 },
457 { "System", 26, 1, 1, 1, 0 },
458 { "PWM", 27, 1, 1, 1, 0 },
459 { "CPU FAN", 32, 2, 60, 1, 0 },
460 { "SYS FAN", 34, 2, 60, 1, 0 },
461 { "AUX1 FAN", 35, 2, 60, 1, 0 },
462 { "AUX2 FAN", 36, 2, 60, 1, 0 },
463 { "AUX3 FAN", 37, 2, 60, 1, 0 },
464 { NULL, 0, 0, 0, 0, 0 } }
466 { 0x0018, { "AB9 QuadGT", NULL }, {
467 { "CPU Core", 0, 0, 10, 1, 0 },
468 { "DDR2", 1, 0, 20, 1, 0 },
469 { "DDR2 VTT", 2, 0, 10, 1, 0 },
470 { "CPU VTT", 3, 0, 10, 1, 0 },
471 { "MCH 1.25V", 4, 0, 10, 1, 0 },
472 { "ICHIO 1.5V", 5, 0, 10, 1, 0 },
473 { "ICH 1.05V", 6, 0, 10, 1, 0 },
474 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
475 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
476 { "ATX +5V", 9, 0, 30, 1, 0 },
477 { "+3.3V", 10, 0, 20, 1, 0 },
478 { "5VSB", 11, 0, 30, 1, 0 },
479 { "CPU", 24, 1, 1, 1, 0 },
480 { "System", 25, 1, 1, 1, 0 },
481 { "PWM Phase1", 26, 1, 1, 1, 0 },
482 { "PWM Phase2", 27, 1, 1, 1, 0 },
483 { "PWM Phase3", 28, 1, 1, 1, 0 },
484 { "PWM Phase4", 29, 1, 1, 1, 0 },
485 { "PWM Phase5", 30, 1, 1, 1, 0 },
486 { "CPU Fan", 32, 2, 60, 1, 0 },
487 { "SYS Fan", 34, 2, 60, 1, 0 },
488 { "AUX1 Fan", 33, 2, 60, 1, 0 },
489 { "AUX2 Fan", 35, 2, 60, 1, 0 },
490 { "AUX3 Fan", 36, 2, 60, 1, 0 },
491 { NULL, 0, 0, 0, 0, 0 } }
493 { 0x0019, { "IN9 32X MAX", NULL }, {
494 { "CPU Core", 7, 0, 10, 1, 0 },
495 { "DDR2", 13, 0, 20, 1, 0 },
496 { "DDR2 VTT", 14, 0, 10, 1, 0 },
497 { "CPU VTT", 3, 0, 20, 1, 0 },
498 { "NB 1.2V", 4, 0, 10, 1, 0 },
499 { "SB 1.5V", 6, 0, 10, 1, 0 },
500 { "HyperTransport", 5, 0, 10, 1, 0 },
501 { "ATX +12V (24-Pin)", 12, 0, 60, 1, 0 },
502 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
503 { "ATX +5V", 9, 0, 30, 1, 0 },
504 { "ATX +3.3V", 10, 0, 20, 1, 0 },
505 { "ATX 5VSB", 11, 0, 30, 1, 0 },
506 { "CPU", 24, 1, 1, 1, 0 },
507 { "System", 25, 1, 1, 1, 0 },
508 { "PWM Phase1", 26, 1, 1, 1, 0 },
509 { "PWM Phase2", 27, 1, 1, 1, 0 },
510 { "PWM Phase3", 28, 1, 1, 1, 0 },
511 { "PWM Phase4", 29, 1, 1, 1, 0 },
512 { "PWM Phase5", 30, 1, 1, 1, 0 },
513 { "CPU FAN", 32, 2, 60, 1, 0 },
514 { "SYS FAN", 34, 2, 60, 1, 0 },
515 { "AUX1 FAN", 33, 2, 60, 1, 0 },
516 { "AUX2 FAN", 35, 2, 60, 1, 0 },
517 { "AUX3 FAN", 36, 2, 60, 1, 0 },
518 { NULL, 0, 0, 0, 0, 0 } }
520 { 0x001A, { "IP35 Pro", "IP35 Pro XE", NULL }, {
521 { "CPU Core", 0, 0, 10, 1, 0 },
522 { "DDR2", 1, 0, 20, 1, 0 },
523 { "DDR2 VTT", 2, 0, 10, 1, 0 },
524 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
525 { "MCH 1.25V", 4, 0, 10, 1, 0 },
526 { "ICHIO 1.5V", 5, 0, 10, 1, 0 },
527 { "ICH 1.05V", 6, 0, 10, 1, 0 },
528 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
529 { "ATX +12V (8-pin)", 8, 0, 60, 1, 0 },
530 { "ATX +5V", 9, 0, 30, 1, 0 },
531 { "+3.3V", 10, 0, 20, 1, 0 },
532 { "5VSB", 11, 0, 30, 1, 0 },
533 { "CPU", 24, 1, 1, 1, 0 },
534 { "System", 25, 1, 1, 1, 0 },
535 { "PWM", 26, 1, 1, 1, 0 },
536 { "PWM Phase2", 27, 1, 1, 1, 0 },
537 { "PWM Phase3", 28, 1, 1, 1, 0 },
538 { "PWM Phase4", 29, 1, 1, 1, 0 },
539 { "PWM Phase5", 30, 1, 1, 1, 0 },
540 { "CPU Fan", 32, 2, 60, 1, 0 },
541 { "SYS Fan", 34, 2, 60, 1, 0 },
542 { "AUX1 Fan", 33, 2, 60, 1, 0 },
543 { "AUX2 Fan", 35, 2, 60, 1, 0 },
544 { "AUX3 Fan", 36, 2, 60, 1, 0 },
545 { "AUX4 Fan", 37, 2, 60, 1, 0 },
546 { NULL, 0, 0, 0, 0, 0 } }
548 { 0x001B, { NULL } /* Unknown, need DMI string */, {
549 { "CPU Core", 0, 0, 10, 1, 0 },
550 { "DDR3", 1, 0, 20, 1, 0 },
551 { "DDR3 VTT", 2, 0, 10, 1, 0 },
552 { "CPU VTT", 3, 0, 10, 1, 0 },
553 { "MCH 1.25V", 4, 0, 10, 1, 0 },
554 { "ICHIO 1.5V", 5, 0, 10, 1, 0 },
555 { "ICH 1.05V", 6, 0, 10, 1, 0 },
556 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
557 { "ATX +12V (8-pin)", 8, 0, 60, 1, 0 },
558 { "ATX +5V", 9, 0, 30, 1, 0 },
559 { "+3.3V", 10, 0, 20, 1, 0 },
560 { "5VSB", 11, 0, 30, 1, 0 },
561 { "CPU", 24, 1, 1, 1, 0 },
562 { "System", 25, 1, 1, 1, 0 },
563 { "PWM Phase1", 26, 1, 1, 1, 0 },
564 { "PWM Phase2", 27, 1, 1, 1, 0 },
565 { "PWM Phase3", 28, 1, 1, 1, 0 },
566 { "PWM Phase4", 29, 1, 1, 1, 0 },
567 { "PWM Phase5", 30, 1, 1, 1, 0 },
568 { "CPU Fan", 32, 2, 60, 1, 0 },
569 { "SYS Fan", 34, 2, 60, 1, 0 },
570 { "AUX1 Fan", 33, 2, 60, 1, 0 },
571 { "AUX2 Fan", 35, 2, 60, 1, 0 },
572 { "AUX3 Fan", 36, 2, 60, 1, 0 },
573 { NULL, 0, 0, 0, 0, 0 } }
575 { 0x001C, { "IX38 QuadGT", NULL }, {
576 { "CPU Core", 0, 0, 10, 1, 0 },
577 { "DDR2", 1, 0, 20, 1, 0 },
578 { "DDR2 VTT", 2, 0, 10, 1, 0 },
579 { "CPU VTT", 3, 0, 10, 1, 0 },
580 { "MCH 1.25V", 4, 0, 10, 1, 0 },
581 { "ICHIO 1.5V", 5, 0, 10, 1, 0 },
582 { "ICH 1.05V", 6, 0, 10, 1, 0 },
583 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
584 { "ATX +12V (8-pin)", 8, 0, 60, 1, 0 },
585 { "ATX +5V", 9, 0, 30, 1, 0 },
586 { "+3.3V", 10, 0, 20, 1, 0 },
587 { "5VSB", 11, 0, 30, 1, 0 },
588 { "CPU", 24, 1, 1, 1, 0 },
589 { "System", 25, 1, 1, 1, 0 },
590 { "PWM Phase1", 26, 1, 1, 1, 0 },
591 { "PWM Phase2", 27, 1, 1, 1, 0 },
592 { "PWM Phase3", 28, 1, 1, 1, 0 },
593 { "PWM Phase4", 29, 1, 1, 1, 0 },
594 { "PWM Phase5", 30, 1, 1, 1, 0 },
595 { "CPU Fan", 32, 2, 60, 1, 0 },
596 { "SYS Fan", 34, 2, 60, 1, 0 },
597 { "AUX1 Fan", 33, 2, 60, 1, 0 },
598 { "AUX2 Fan", 35, 2, 60, 1, 0 },
599 { "AUX3 Fan", 36, 2, 60, 1, 0 },
600 { NULL, 0, 0, 0, 0, 0 } }
602 { 0x0000, { NULL }, { { NULL, 0, 0, 0, 0, 0 } } }
606 /* Insmod parameters */
608 module_param(force, bool, 0);
609 MODULE_PARM_DESC(force, "Set to one to force detection.");
610 /* Default verbose is 1, since this driver is still in the testing phase */
611 static bool verbose = 1;
612 module_param(verbose, bool, 0644);
613 MODULE_PARM_DESC(verbose, "Enable/disable verbose error reporting");
615 static const char *never_happen = "This should never happen.";
616 static const char *report_this =
617 "Please report this to the abituguru3 maintainer (see MAINTAINERS)";
619 /* wait while the uguru is busy (usually after a write) */
620 static int abituguru3_wait_while_busy(struct abituguru3_data *data)
623 int timeout = ABIT_UGURU3_WAIT_TIMEOUT;
625 while ((x = inb_p(data->addr + ABIT_UGURU3_DATA)) &
626 ABIT_UGURU3_STATUS_BUSY) {
630 /* sleep a bit before our last try, to give the uGuru3 one
631 last chance to respond. */
635 return ABIT_UGURU3_SUCCESS;
638 /* wait till uguru is ready to be read */
639 static int abituguru3_wait_for_read(struct abituguru3_data *data)
642 int timeout = ABIT_UGURU3_WAIT_TIMEOUT;
644 while (!((x = inb_p(data->addr + ABIT_UGURU3_DATA)) &
645 ABIT_UGURU3_STATUS_READY_FOR_READ)) {
649 /* sleep a bit before our last try, to give the uGuru3 one
650 last chance to respond. */
654 return ABIT_UGURU3_SUCCESS;
657 /* This synchronizes us with the uGuru3's protocol state machine, this
658 must be done before each command. */
659 static int abituguru3_synchronize(struct abituguru3_data *data)
661 int x, timeout = ABIT_UGURU3_SYNCHRONIZE_TIMEOUT;
663 x = abituguru3_wait_while_busy(data);
664 if (x != ABIT_UGURU3_SUCCESS) {
665 ABIT_UGURU3_DEBUG("synchronize timeout during initial busy "
666 "wait, status: 0x%02x\n", x);
670 outb(0x20, data->addr + ABIT_UGURU3_DATA);
671 x = abituguru3_wait_while_busy(data);
672 if (x != ABIT_UGURU3_SUCCESS) {
673 ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x20, "
674 "status: 0x%02x\n", x);
678 outb(0x10, data->addr + ABIT_UGURU3_CMD);
679 x = abituguru3_wait_while_busy(data);
680 if (x != ABIT_UGURU3_SUCCESS) {
681 ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x10, "
682 "status: 0x%02x\n", x);
686 outb(0x00, data->addr + ABIT_UGURU3_CMD);
687 x = abituguru3_wait_while_busy(data);
688 if (x != ABIT_UGURU3_SUCCESS) {
689 ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x00, "
690 "status: 0x%02x\n", x);
694 x = abituguru3_wait_for_read(data);
695 if (x != ABIT_UGURU3_SUCCESS) {
696 ABIT_UGURU3_DEBUG("synchronize timeout waiting for read, "
697 "status: 0x%02x\n", x);
701 while ((x = inb(data->addr + ABIT_UGURU3_CMD)) != 0xAC) {
704 ABIT_UGURU3_DEBUG("synchronize timeout cmd does not "
705 "hold 0xAC after synchronize, cmd: 0x%02x\n",
714 /* Read count bytes from sensor sensor_addr in bank bank_addr and store the
716 static int abituguru3_read(struct abituguru3_data *data, u8 bank, u8 offset,
721 x = abituguru3_synchronize(data);
725 outb(0x1A, data->addr + ABIT_UGURU3_DATA);
726 x = abituguru3_wait_while_busy(data);
727 if (x != ABIT_UGURU3_SUCCESS) {
728 ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after "
729 "sending 0x1A, status: 0x%02x\n", (unsigned int)bank,
730 (unsigned int)offset, x);
734 outb(bank, data->addr + ABIT_UGURU3_CMD);
735 x = abituguru3_wait_while_busy(data);
736 if (x != ABIT_UGURU3_SUCCESS) {
737 ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after "
738 "sending the bank, status: 0x%02x\n",
739 (unsigned int)bank, (unsigned int)offset, x);
743 outb(offset, data->addr + ABIT_UGURU3_CMD);
744 x = abituguru3_wait_while_busy(data);
745 if (x != ABIT_UGURU3_SUCCESS) {
746 ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after "
747 "sending the offset, status: 0x%02x\n",
748 (unsigned int)bank, (unsigned int)offset, x);
752 outb(count, data->addr + ABIT_UGURU3_CMD);
753 x = abituguru3_wait_while_busy(data);
754 if (x != ABIT_UGURU3_SUCCESS) {
755 ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after "
756 "sending the count, status: 0x%02x\n",
757 (unsigned int)bank, (unsigned int)offset, x);
761 for (i = 0; i < count; i++) {
762 x = abituguru3_wait_for_read(data);
763 if (x != ABIT_UGURU3_SUCCESS) {
764 ABIT_UGURU3_DEBUG("timeout reading byte %d from "
765 "0x%02x:0x%02x, status: 0x%02x\n", i,
766 (unsigned int)bank, (unsigned int)offset, x);
769 buf[i] = inb(data->addr + ABIT_UGURU3_CMD);
774 /* Sensor settings are stored 1 byte per offset with the bytes
775 placed add consecutive offsets. */
776 static int abituguru3_read_increment_offset(struct abituguru3_data *data,
777 u8 bank, u8 offset, u8 count,
778 u8 *buf, int offset_count)
782 for (i = 0; i < offset_count; i++) {
783 x = abituguru3_read(data, bank, offset + i, count,
788 return i * count + x;
795 /* Following are the sysfs callback functions. These functions expect:
796 sensor_device_attribute_2->index: index into the data->sensors array
797 sensor_device_attribute_2->nr: register offset, bitmask or NA. */
798 static struct abituguru3_data *abituguru3_update_device(struct device *dev);
800 static ssize_t show_value(struct device *dev,
801 struct device_attribute *devattr, char *buf)
804 struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
805 struct abituguru3_data *data = abituguru3_update_device(dev);
806 const struct abituguru3_sensor_info *sensor;
811 sensor = &data->sensors[attr->index];
813 /* are we reading a setting, or is this a normal read? */
815 value = data->settings[sensor->port][attr->nr];
817 value = data->value[sensor->port];
819 /* convert the value */
820 value = (value * sensor->multiplier) / sensor->divisor +
823 /* alternatively we could update the sensors settings struct for this,
824 but then its contents would differ from the windows sw ini files */
825 if (sensor->type == ABIT_UGURU3_TEMP_SENSOR)
828 return sprintf(buf, "%d\n", value);
831 static ssize_t show_alarm(struct device *dev,
832 struct device_attribute *devattr, char *buf)
835 struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
836 struct abituguru3_data *data = abituguru3_update_device(dev);
841 port = data->sensors[attr->index].port;
843 /* See if the alarm bit for this sensor is set and if a bitmask is
844 given in attr->nr also check if the alarm matches the type of alarm
845 we're looking for (for volt it can be either low or high). The type
846 is stored in a few readonly bits in the settings of the sensor. */
847 if ((data->alarms[port / 8] & (0x01 << (port % 8))) &&
848 (!attr->nr || (data->settings[port][0] & attr->nr)))
849 return sprintf(buf, "1\n");
851 return sprintf(buf, "0\n");
854 static ssize_t show_mask(struct device *dev,
855 struct device_attribute *devattr, char *buf)
857 struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
858 struct abituguru3_data *data = dev_get_drvdata(dev);
860 if (data->settings[data->sensors[attr->index].port][0] & attr->nr)
861 return sprintf(buf, "1\n");
863 return sprintf(buf, "0\n");
866 static ssize_t show_label(struct device *dev,
867 struct device_attribute *devattr, char *buf)
869 struct sensor_device_attribute_2 *attr = to_sensor_dev_attr_2(devattr);
870 struct abituguru3_data *data = dev_get_drvdata(dev);
872 return sprintf(buf, "%s\n", data->sensors[attr->index].name);
875 static ssize_t show_name(struct device *dev,
876 struct device_attribute *devattr, char *buf)
878 return sprintf(buf, "%s\n", ABIT_UGURU3_NAME);
881 /* Sysfs attr templates, the real entries are generated automatically. */
883 struct sensor_device_attribute_2 abituguru3_sysfs_templ[3][10] = { {
884 SENSOR_ATTR_2(in%d_input, 0444, show_value, NULL, 0, 0),
885 SENSOR_ATTR_2(in%d_min, 0444, show_value, NULL, 1, 0),
886 SENSOR_ATTR_2(in%d_max, 0444, show_value, NULL, 2, 0),
887 SENSOR_ATTR_2(in%d_min_alarm, 0444, show_alarm, NULL,
888 ABIT_UGURU3_VOLT_LOW_ALARM_FLAG, 0),
889 SENSOR_ATTR_2(in%d_max_alarm, 0444, show_alarm, NULL,
890 ABIT_UGURU3_VOLT_HIGH_ALARM_FLAG, 0),
891 SENSOR_ATTR_2(in%d_beep, 0444, show_mask, NULL,
892 ABIT_UGURU3_BEEP_ENABLE, 0),
893 SENSOR_ATTR_2(in%d_shutdown, 0444, show_mask, NULL,
894 ABIT_UGURU3_SHUTDOWN_ENABLE, 0),
895 SENSOR_ATTR_2(in%d_min_alarm_enable, 0444, show_mask, NULL,
896 ABIT_UGURU3_VOLT_LOW_ALARM_ENABLE, 0),
897 SENSOR_ATTR_2(in%d_max_alarm_enable, 0444, show_mask, NULL,
898 ABIT_UGURU3_VOLT_HIGH_ALARM_ENABLE, 0),
899 SENSOR_ATTR_2(in%d_label, 0444, show_label, NULL, 0, 0)
901 SENSOR_ATTR_2(temp%d_input, 0444, show_value, NULL, 0, 0),
902 SENSOR_ATTR_2(temp%d_max, 0444, show_value, NULL, 1, 0),
903 SENSOR_ATTR_2(temp%d_crit, 0444, show_value, NULL, 2, 0),
904 SENSOR_ATTR_2(temp%d_alarm, 0444, show_alarm, NULL, 0, 0),
905 SENSOR_ATTR_2(temp%d_beep, 0444, show_mask, NULL,
906 ABIT_UGURU3_BEEP_ENABLE, 0),
907 SENSOR_ATTR_2(temp%d_shutdown, 0444, show_mask, NULL,
908 ABIT_UGURU3_SHUTDOWN_ENABLE, 0),
909 SENSOR_ATTR_2(temp%d_alarm_enable, 0444, show_mask, NULL,
910 ABIT_UGURU3_TEMP_HIGH_ALARM_ENABLE, 0),
911 SENSOR_ATTR_2(temp%d_label, 0444, show_label, NULL, 0, 0)
913 SENSOR_ATTR_2(fan%d_input, 0444, show_value, NULL, 0, 0),
914 SENSOR_ATTR_2(fan%d_min, 0444, show_value, NULL, 1, 0),
915 SENSOR_ATTR_2(fan%d_alarm, 0444, show_alarm, NULL, 0, 0),
916 SENSOR_ATTR_2(fan%d_beep, 0444, show_mask, NULL,
917 ABIT_UGURU3_BEEP_ENABLE, 0),
918 SENSOR_ATTR_2(fan%d_shutdown, 0444, show_mask, NULL,
919 ABIT_UGURU3_SHUTDOWN_ENABLE, 0),
920 SENSOR_ATTR_2(fan%d_alarm_enable, 0444, show_mask, NULL,
921 ABIT_UGURU3_FAN_LOW_ALARM_ENABLE, 0),
922 SENSOR_ATTR_2(fan%d_label, 0444, show_label, NULL, 0, 0)
925 static struct sensor_device_attribute_2 abituguru3_sysfs_attr[] = {
926 SENSOR_ATTR_2(name, 0444, show_name, NULL, 0, 0),
929 static int __devinit abituguru3_probe(struct platform_device *pdev)
931 const int no_sysfs_attr[3] = { 10, 8, 7 };
932 int sensor_index[3] = { 0, 1, 1 };
933 struct abituguru3_data *data;
934 int i, j, type, used, sysfs_names_free, sysfs_attr_i, res = -ENODEV;
935 char *sysfs_filename;
939 data = kzalloc(sizeof(struct abituguru3_data), GFP_KERNEL);
943 data->addr = platform_get_resource(pdev, IORESOURCE_IO, 0)->start;
944 mutex_init(&data->update_lock);
945 platform_set_drvdata(pdev, data);
947 /* Read the motherboard ID */
948 i = abituguru3_read(data, ABIT_UGURU3_MISC_BANK, ABIT_UGURU3_BOARD_ID,
951 goto abituguru3_probe_error;
953 /* Completely read the uGuru to see if one really is there */
954 if (!abituguru3_update_device(&pdev->dev))
955 goto abituguru3_probe_error;
957 /* lookup the ID in our motherboard table */
958 id = ((u16)buf[0] << 8) | (u16)buf[1];
959 for (i = 0; abituguru3_motherboards[i].id; i++)
960 if (abituguru3_motherboards[i].id == id)
962 if (!abituguru3_motherboards[i].id) {
963 pr_err("error unknown motherboard ID: %04X. %s\n",
964 (unsigned int)id, report_this);
965 goto abituguru3_probe_error;
967 data->sensors = abituguru3_motherboards[i].sensors;
969 pr_info("found Abit uGuru3, motherboard ID: %04X\n", (unsigned int)id);
971 /* Fill the sysfs attr array */
973 sysfs_filename = data->sysfs_names;
974 sysfs_names_free = ABIT_UGURU3_SYSFS_NAMES_LENGTH;
975 for (i = 0; data->sensors[i].name; i++) {
976 /* Fail safe check, this should never happen! */
977 if (i >= ABIT_UGURU3_MAX_NO_SENSORS) {
978 pr_err("Fatal error motherboard has more sensors then ABIT_UGURU3_MAX_NO_SENSORS. %s %s\n",
979 never_happen, report_this);
981 goto abituguru3_probe_error;
983 type = data->sensors[i].type;
984 for (j = 0; j < no_sysfs_attr[type]; j++) {
985 used = snprintf(sysfs_filename, sysfs_names_free,
986 abituguru3_sysfs_templ[type][j].dev_attr.attr.
987 name, sensor_index[type]) + 1;
988 data->sysfs_attr[sysfs_attr_i] =
989 abituguru3_sysfs_templ[type][j];
990 data->sysfs_attr[sysfs_attr_i].dev_attr.attr.name =
992 data->sysfs_attr[sysfs_attr_i].index = i;
993 sysfs_filename += used;
994 sysfs_names_free -= used;
997 sensor_index[type]++;
999 /* Fail safe check, this should never happen! */
1000 if (sysfs_names_free < 0) {
1001 pr_err("Fatal error ran out of space for sysfs attr names. %s %s\n",
1002 never_happen, report_this);
1003 res = -ENAMETOOLONG;
1004 goto abituguru3_probe_error;
1007 /* Register sysfs hooks */
1008 for (i = 0; i < sysfs_attr_i; i++)
1009 if (device_create_file(&pdev->dev,
1010 &data->sysfs_attr[i].dev_attr))
1011 goto abituguru3_probe_error;
1012 for (i = 0; i < ARRAY_SIZE(abituguru3_sysfs_attr); i++)
1013 if (device_create_file(&pdev->dev,
1014 &abituguru3_sysfs_attr[i].dev_attr))
1015 goto abituguru3_probe_error;
1017 data->hwmon_dev = hwmon_device_register(&pdev->dev);
1018 if (IS_ERR(data->hwmon_dev)) {
1019 res = PTR_ERR(data->hwmon_dev);
1020 goto abituguru3_probe_error;
1023 return 0; /* success */
1025 abituguru3_probe_error:
1026 for (i = 0; data->sysfs_attr[i].dev_attr.attr.name; i++)
1027 device_remove_file(&pdev->dev, &data->sysfs_attr[i].dev_attr);
1028 for (i = 0; i < ARRAY_SIZE(abituguru3_sysfs_attr); i++)
1029 device_remove_file(&pdev->dev,
1030 &abituguru3_sysfs_attr[i].dev_attr);
1035 static int __devexit abituguru3_remove(struct platform_device *pdev)
1038 struct abituguru3_data *data = platform_get_drvdata(pdev);
1040 platform_set_drvdata(pdev, NULL);
1041 hwmon_device_unregister(data->hwmon_dev);
1042 for (i = 0; data->sysfs_attr[i].dev_attr.attr.name; i++)
1043 device_remove_file(&pdev->dev, &data->sysfs_attr[i].dev_attr);
1044 for (i = 0; i < ARRAY_SIZE(abituguru3_sysfs_attr); i++)
1045 device_remove_file(&pdev->dev,
1046 &abituguru3_sysfs_attr[i].dev_attr);
1052 static struct abituguru3_data *abituguru3_update_device(struct device *dev)
1055 struct abituguru3_data *data = dev_get_drvdata(dev);
1057 mutex_lock(&data->update_lock);
1058 if (!data->valid || time_after(jiffies, data->last_updated + HZ)) {
1059 /* Clear data->valid while updating */
1062 if (abituguru3_read_increment_offset(data,
1063 ABIT_UGURU3_SETTINGS_BANK,
1064 ABIT_UGURU3_ALARMS_START,
1065 1, data->alarms, 48/8) != (48/8))
1067 /* Read in and temp sensors (3 byte settings / sensor) */
1068 for (i = 0; i < 32; i++) {
1069 if (abituguru3_read(data, ABIT_UGURU3_SENSORS_BANK,
1070 ABIT_UGURU3_VALUES_START + i,
1071 1, &data->value[i]) != 1)
1073 if (abituguru3_read_increment_offset(data,
1074 ABIT_UGURU3_SETTINGS_BANK,
1075 ABIT_UGURU3_SETTINGS_START + i * 3,
1077 data->settings[i], 3) != 3)
1080 /* Read temp sensors (2 byte settings / sensor) */
1081 for (i = 0; i < 16; i++) {
1082 if (abituguru3_read(data, ABIT_UGURU3_SENSORS_BANK,
1083 ABIT_UGURU3_VALUES_START + 32 + i,
1084 1, &data->value[32 + i]) != 1)
1086 if (abituguru3_read_increment_offset(data,
1087 ABIT_UGURU3_SETTINGS_BANK,
1088 ABIT_UGURU3_SETTINGS_START + 32 * 3 +
1090 data->settings[32 + i], 2) != 2)
1093 data->last_updated = jiffies;
1097 mutex_unlock(&data->update_lock);
1105 static int abituguru3_suspend(struct platform_device *pdev, pm_message_t state)
1107 struct abituguru3_data *data = platform_get_drvdata(pdev);
1108 /* make sure all communications with the uguru3 are done and no new
1110 mutex_lock(&data->update_lock);
1114 static int abituguru3_resume(struct platform_device *pdev)
1116 struct abituguru3_data *data = platform_get_drvdata(pdev);
1117 mutex_unlock(&data->update_lock);
1121 #define abituguru3_suspend NULL
1122 #define abituguru3_resume NULL
1123 #endif /* CONFIG_PM */
1125 static struct platform_driver abituguru3_driver = {
1127 .owner = THIS_MODULE,
1128 .name = ABIT_UGURU3_NAME,
1130 .probe = abituguru3_probe,
1131 .remove = __devexit_p(abituguru3_remove),
1132 .suspend = abituguru3_suspend,
1133 .resume = abituguru3_resume
1136 static int __init abituguru3_dmi_detect(void)
1138 const char *board_vendor, *board_name;
1139 int i, err = (force) ? 1 : -ENODEV;
1140 const char *const *dmi_name;
1143 board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
1144 if (!board_vendor || strcmp(board_vendor, "http://www.abit.com.tw/"))
1147 board_name = dmi_get_system_info(DMI_BOARD_NAME);
1151 /* At the moment, we don't care about the part of the vendor
1152 * DMI string contained in brackets. Truncate the string at
1153 * the first occurrence of a bracket. Trim any trailing space
1154 * from the substring.
1156 sublen = strcspn(board_name, "(");
1157 while (sublen > 0 && board_name[sublen - 1] == ' ')
1160 for (i = 0; abituguru3_motherboards[i].id; i++) {
1161 dmi_name = abituguru3_motherboards[i].dmi_name;
1162 for ( ; *dmi_name; dmi_name++) {
1163 if (strlen(*dmi_name) != sublen)
1165 if (!strncasecmp(board_name, *dmi_name, sublen))
1170 /* No match found */
1174 /* FIXME: Manual detection should die eventually; we need to collect stable
1175 * DMI model names first before we can rely entirely on CONFIG_DMI.
1178 static int __init abituguru3_detect(void)
1180 /* See if there is an uguru3 there. An idle uGuru3 will hold 0x00 or
1181 0x08 at DATA and 0xAC at CMD. Sometimes the uGuru3 will hold 0x05
1182 or 0x55 at CMD instead, why is unknown. */
1183 u8 data_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_DATA);
1184 u8 cmd_val = inb_p(ABIT_UGURU3_BASE + ABIT_UGURU3_CMD);
1185 if (((data_val == 0x00) || (data_val == 0x08)) &&
1186 ((cmd_val == 0xAC) || (cmd_val == 0x05) ||
1190 ABIT_UGURU3_DEBUG("no Abit uGuru3 found, data = 0x%02X, cmd = "
1191 "0x%02X\n", (unsigned int)data_val, (unsigned int)cmd_val);
1194 pr_info("Assuming Abit uGuru3 is present because of \"force\" parameter\n");
1198 /* No uGuru3 found */
1202 static struct platform_device *abituguru3_pdev;
1204 static int __init abituguru3_init(void)
1206 struct resource res = { .flags = IORESOURCE_IO };
1209 /* Attempt DMI detection first */
1210 err = abituguru3_dmi_detect();
1214 /* Fall back to manual detection if there was no exact
1215 * board name match, or force was specified.
1218 err = abituguru3_detect();
1222 pr_warn("this motherboard was not detected using DMI. "
1223 "Please send the output of \"dmidecode\" to the abituguru3 maintainer (see MAINTAINERS)\n");
1226 err = platform_driver_register(&abituguru3_driver);
1230 abituguru3_pdev = platform_device_alloc(ABIT_UGURU3_NAME,
1232 if (!abituguru3_pdev) {
1233 pr_err("Device allocation failed\n");
1235 goto exit_driver_unregister;
1238 res.start = ABIT_UGURU3_BASE;
1239 res.end = ABIT_UGURU3_BASE + ABIT_UGURU3_REGION_LENGTH - 1;
1240 res.name = ABIT_UGURU3_NAME;
1242 err = platform_device_add_resources(abituguru3_pdev, &res, 1);
1244 pr_err("Device resource addition failed (%d)\n", err);
1245 goto exit_device_put;
1248 err = platform_device_add(abituguru3_pdev);
1250 pr_err("Device addition failed (%d)\n", err);
1251 goto exit_device_put;
1257 platform_device_put(abituguru3_pdev);
1258 exit_driver_unregister:
1259 platform_driver_unregister(&abituguru3_driver);
1264 static void __exit abituguru3_exit(void)
1266 platform_device_unregister(abituguru3_pdev);
1267 platform_driver_unregister(&abituguru3_driver);
1270 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
1271 MODULE_DESCRIPTION("Abit uGuru3 Sensor device");
1272 MODULE_LICENSE("GPL");
1274 module_init(abituguru3_init);
1275 module_exit(abituguru3_exit);