1 /**************************************************************************
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
27 #include <linux/module.h>
30 #include "vmwgfx_drv.h"
31 #include <drm/ttm/ttm_placement.h>
32 #include <drm/ttm/ttm_bo_driver.h>
33 #include <drm/ttm/ttm_object.h>
34 #include <drm/ttm/ttm_module.h>
36 #define VMWGFX_DRIVER_NAME "vmwgfx"
37 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
38 #define VMWGFX_CHIP_SVGAII 0
39 #define VMW_FB_RESERVATION 0
41 #define VMW_MIN_INITIAL_WIDTH 800
42 #define VMW_MIN_INITIAL_HEIGHT 600
46 * Fully encoded drm commands. Might move to vmw_drm.h
49 #define DRM_IOCTL_VMW_GET_PARAM \
50 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
51 struct drm_vmw_getparam_arg)
52 #define DRM_IOCTL_VMW_ALLOC_DMABUF \
53 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
54 union drm_vmw_alloc_dmabuf_arg)
55 #define DRM_IOCTL_VMW_UNREF_DMABUF \
56 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
57 struct drm_vmw_unref_dmabuf_arg)
58 #define DRM_IOCTL_VMW_CURSOR_BYPASS \
59 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
60 struct drm_vmw_cursor_bypass_arg)
62 #define DRM_IOCTL_VMW_CONTROL_STREAM \
63 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
64 struct drm_vmw_control_stream_arg)
65 #define DRM_IOCTL_VMW_CLAIM_STREAM \
66 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
67 struct drm_vmw_stream_arg)
68 #define DRM_IOCTL_VMW_UNREF_STREAM \
69 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
70 struct drm_vmw_stream_arg)
72 #define DRM_IOCTL_VMW_CREATE_CONTEXT \
73 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
74 struct drm_vmw_context_arg)
75 #define DRM_IOCTL_VMW_UNREF_CONTEXT \
76 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
77 struct drm_vmw_context_arg)
78 #define DRM_IOCTL_VMW_CREATE_SURFACE \
79 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
80 union drm_vmw_surface_create_arg)
81 #define DRM_IOCTL_VMW_UNREF_SURFACE \
82 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
83 struct drm_vmw_surface_arg)
84 #define DRM_IOCTL_VMW_REF_SURFACE \
85 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
86 union drm_vmw_surface_reference_arg)
87 #define DRM_IOCTL_VMW_EXECBUF \
88 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
89 struct drm_vmw_execbuf_arg)
90 #define DRM_IOCTL_VMW_GET_3D_CAP \
91 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
92 struct drm_vmw_get_3d_cap_arg)
93 #define DRM_IOCTL_VMW_FENCE_WAIT \
94 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
95 struct drm_vmw_fence_wait_arg)
96 #define DRM_IOCTL_VMW_FENCE_SIGNALED \
97 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
98 struct drm_vmw_fence_signaled_arg)
99 #define DRM_IOCTL_VMW_FENCE_UNREF \
100 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
101 struct drm_vmw_fence_arg)
102 #define DRM_IOCTL_VMW_FENCE_EVENT \
103 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
104 struct drm_vmw_fence_event_arg)
105 #define DRM_IOCTL_VMW_PRESENT \
106 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
107 struct drm_vmw_present_arg)
108 #define DRM_IOCTL_VMW_PRESENT_READBACK \
109 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
110 struct drm_vmw_present_readback_arg)
111 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \
112 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
113 struct drm_vmw_update_layout_arg)
116 * The core DRM version of this macro doesn't account for
120 #define VMW_IOCTL_DEF(ioctl, func, flags) \
121 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
127 static struct drm_ioctl_desc vmw_ioctls[] = {
128 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
129 DRM_AUTH | DRM_UNLOCKED),
130 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
131 DRM_AUTH | DRM_UNLOCKED),
132 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
133 DRM_AUTH | DRM_UNLOCKED),
134 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
135 vmw_kms_cursor_bypass_ioctl,
136 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
138 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
139 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
140 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
141 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
142 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
143 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
145 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
146 DRM_AUTH | DRM_UNLOCKED),
147 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
148 DRM_AUTH | DRM_UNLOCKED),
149 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
150 DRM_AUTH | DRM_UNLOCKED),
151 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
152 DRM_AUTH | DRM_UNLOCKED),
153 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
154 DRM_AUTH | DRM_UNLOCKED),
155 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
156 DRM_AUTH | DRM_UNLOCKED),
157 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
158 DRM_AUTH | DRM_UNLOCKED),
159 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
160 vmw_fence_obj_signaled_ioctl,
161 DRM_AUTH | DRM_UNLOCKED),
162 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
163 DRM_AUTH | DRM_UNLOCKED),
164 VMW_IOCTL_DEF(VMW_FENCE_EVENT,
165 vmw_fence_event_ioctl,
166 DRM_AUTH | DRM_UNLOCKED),
167 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
168 DRM_AUTH | DRM_UNLOCKED),
170 /* these allow direct access to the framebuffers mark as master only */
171 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
172 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
173 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
174 vmw_present_readback_ioctl,
175 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
176 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
177 vmw_kms_update_layout_ioctl,
178 DRM_MASTER | DRM_UNLOCKED),
181 static struct pci_device_id vmw_pci_id_list[] = {
182 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
185 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
187 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
189 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
190 static void vmw_master_init(struct vmw_master *);
191 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
194 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
195 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
197 static void vmw_print_capabilities(uint32_t capabilities)
199 DRM_INFO("Capabilities:\n");
200 if (capabilities & SVGA_CAP_RECT_COPY)
201 DRM_INFO(" Rect copy.\n");
202 if (capabilities & SVGA_CAP_CURSOR)
203 DRM_INFO(" Cursor.\n");
204 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
205 DRM_INFO(" Cursor bypass.\n");
206 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
207 DRM_INFO(" Cursor bypass 2.\n");
208 if (capabilities & SVGA_CAP_8BIT_EMULATION)
209 DRM_INFO(" 8bit emulation.\n");
210 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
211 DRM_INFO(" Alpha cursor.\n");
212 if (capabilities & SVGA_CAP_3D)
214 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
215 DRM_INFO(" Extended Fifo.\n");
216 if (capabilities & SVGA_CAP_MULTIMON)
217 DRM_INFO(" Multimon.\n");
218 if (capabilities & SVGA_CAP_PITCHLOCK)
219 DRM_INFO(" Pitchlock.\n");
220 if (capabilities & SVGA_CAP_IRQMASK)
221 DRM_INFO(" Irq mask.\n");
222 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
223 DRM_INFO(" Display Topology.\n");
224 if (capabilities & SVGA_CAP_GMR)
226 if (capabilities & SVGA_CAP_TRACES)
227 DRM_INFO(" Traces.\n");
228 if (capabilities & SVGA_CAP_GMR2)
229 DRM_INFO(" GMR2.\n");
230 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
231 DRM_INFO(" Screen Object 2.\n");
236 * vmw_execbuf_prepare_dummy_query - Initialize a query result structure at
237 * the start of a buffer object.
239 * @dev_priv: The device private structure.
241 * This function will idle the buffer using an uninterruptible wait, then
242 * map the first page and initialize a pending occlusion query result structure,
243 * Finally it will unmap the buffer.
245 * TODO: Since we're only mapping a single page, we should optimize the map
246 * to use kmap_atomic / iomap_atomic.
248 static void vmw_dummy_query_bo_prepare(struct vmw_private *dev_priv)
250 struct ttm_bo_kmap_obj map;
251 volatile SVGA3dQueryResult *result;
254 struct ttm_bo_device *bdev = &dev_priv->bdev;
255 struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
257 ttm_bo_reserve(bo, false, false, false, 0);
258 spin_lock(&bdev->fence_lock);
259 ret = ttm_bo_wait(bo, false, false, false);
260 spin_unlock(&bdev->fence_lock);
261 if (unlikely(ret != 0))
262 (void) vmw_fallback_wait(dev_priv, false, true, 0, false,
265 ret = ttm_bo_kmap(bo, 0, 1, &map);
266 if (likely(ret == 0)) {
267 result = ttm_kmap_obj_virtual(&map, &dummy);
268 result->totalSize = sizeof(*result);
269 result->state = SVGA3D_QUERYSTATE_PENDING;
270 result->result32 = 0xff;
273 DRM_ERROR("Dummy query buffer map failed.\n");
274 ttm_bo_unreserve(bo);
279 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
281 * @dev_priv: A device private structure.
283 * This function creates a small buffer object that holds the query
284 * result for dummy queries emitted as query barriers.
285 * No interruptible waits are done within this function.
287 * Returns an error if bo creation fails.
289 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
291 return ttm_bo_create(&dev_priv->bdev,
294 &vmw_vram_sys_placement,
296 &dev_priv->dummy_query_bo);
300 static int vmw_request_device(struct vmw_private *dev_priv)
304 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
305 if (unlikely(ret != 0)) {
306 DRM_ERROR("Unable to initialize FIFO.\n");
309 vmw_fence_fifo_up(dev_priv->fman);
310 ret = vmw_dummy_query_bo_create(dev_priv);
311 if (unlikely(ret != 0))
312 goto out_no_query_bo;
313 vmw_dummy_query_bo_prepare(dev_priv);
318 vmw_fence_fifo_down(dev_priv->fman);
319 vmw_fifo_release(dev_priv, &dev_priv->fifo);
323 static void vmw_release_device(struct vmw_private *dev_priv)
326 * Previous destructions should've released
330 BUG_ON(dev_priv->pinned_bo != NULL);
332 ttm_bo_unref(&dev_priv->dummy_query_bo);
333 vmw_fence_fifo_down(dev_priv->fman);
334 vmw_fifo_release(dev_priv, &dev_priv->fifo);
338 * Increase the 3d resource refcount.
339 * If the count was prevously zero, initialize the fifo, switching to svga
340 * mode. Note that the master holds a ref as well, and may request an
341 * explicit switch to svga mode if fb is not running, using @unhide_svga.
343 int vmw_3d_resource_inc(struct vmw_private *dev_priv,
348 mutex_lock(&dev_priv->release_mutex);
349 if (unlikely(dev_priv->num_3d_resources++ == 0)) {
350 ret = vmw_request_device(dev_priv);
351 if (unlikely(ret != 0))
352 --dev_priv->num_3d_resources;
353 } else if (unhide_svga) {
354 mutex_lock(&dev_priv->hw_mutex);
355 vmw_write(dev_priv, SVGA_REG_ENABLE,
356 vmw_read(dev_priv, SVGA_REG_ENABLE) &
357 ~SVGA_REG_ENABLE_HIDE);
358 mutex_unlock(&dev_priv->hw_mutex);
361 mutex_unlock(&dev_priv->release_mutex);
366 * Decrease the 3d resource refcount.
367 * If the count reaches zero, disable the fifo, switching to vga mode.
368 * Note that the master holds a refcount as well, and may request an
369 * explicit switch to vga mode when it releases its refcount to account
370 * for the situation of an X server vt switch to VGA with 3d resources
373 void vmw_3d_resource_dec(struct vmw_private *dev_priv,
378 mutex_lock(&dev_priv->release_mutex);
379 if (unlikely(--dev_priv->num_3d_resources == 0))
380 vmw_release_device(dev_priv);
381 else if (hide_svga) {
382 mutex_lock(&dev_priv->hw_mutex);
383 vmw_write(dev_priv, SVGA_REG_ENABLE,
384 vmw_read(dev_priv, SVGA_REG_ENABLE) |
385 SVGA_REG_ENABLE_HIDE);
386 mutex_unlock(&dev_priv->hw_mutex);
389 n3d = (int32_t) dev_priv->num_3d_resources;
390 mutex_unlock(&dev_priv->release_mutex);
396 * Sets the initial_[width|height] fields on the given vmw_private.
398 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
399 * clamping the value to fb_max_[width|height] fields and the
400 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
401 * If the values appear to be invalid, set them to
402 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
404 static void vmw_get_initial_size(struct vmw_private *dev_priv)
409 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
410 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
412 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
413 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
415 if (width > dev_priv->fb_max_width ||
416 height > dev_priv->fb_max_height) {
419 * This is a host error and shouldn't occur.
422 width = VMW_MIN_INITIAL_WIDTH;
423 height = VMW_MIN_INITIAL_HEIGHT;
426 dev_priv->initial_width = width;
427 dev_priv->initial_height = height;
430 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
432 struct vmw_private *dev_priv;
436 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
437 if (unlikely(dev_priv == NULL)) {
438 DRM_ERROR("Failed allocating a device private struct.\n");
442 pci_set_master(dev->pdev);
445 dev_priv->vmw_chipset = chipset;
446 dev_priv->last_read_seqno = (uint32_t) -100;
447 mutex_init(&dev_priv->hw_mutex);
448 mutex_init(&dev_priv->cmdbuf_mutex);
449 mutex_init(&dev_priv->release_mutex);
450 rwlock_init(&dev_priv->resource_lock);
451 idr_init(&dev_priv->context_idr);
452 idr_init(&dev_priv->surface_idr);
453 idr_init(&dev_priv->stream_idr);
454 mutex_init(&dev_priv->init_mutex);
455 init_waitqueue_head(&dev_priv->fence_queue);
456 init_waitqueue_head(&dev_priv->fifo_queue);
457 dev_priv->fence_queue_waiters = 0;
458 atomic_set(&dev_priv->fifo_queue_waiters, 0);
459 INIT_LIST_HEAD(&dev_priv->surface_lru);
460 dev_priv->used_memory_size = 0;
462 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
463 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
464 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
466 dev_priv->enable_fb = enable_fbdev;
468 mutex_lock(&dev_priv->hw_mutex);
470 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
471 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
472 if (svga_id != SVGA_ID_2) {
474 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
475 mutex_unlock(&dev_priv->hw_mutex);
479 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
481 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
482 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
483 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
484 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
486 vmw_get_initial_size(dev_priv);
488 if (dev_priv->capabilities & SVGA_CAP_GMR) {
489 dev_priv->max_gmr_descriptors =
491 SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
492 dev_priv->max_gmr_ids =
493 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
495 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
496 dev_priv->max_gmr_pages =
497 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
498 dev_priv->memory_size =
499 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
500 dev_priv->memory_size -= dev_priv->vram_size;
503 * An arbitrary limit of 512MiB on surface
504 * memory. But all HWV8 hardware supports GMR2.
506 dev_priv->memory_size = 512*1024*1024;
509 mutex_unlock(&dev_priv->hw_mutex);
511 vmw_print_capabilities(dev_priv->capabilities);
513 if (dev_priv->capabilities & SVGA_CAP_GMR) {
514 DRM_INFO("Max GMR ids is %u\n",
515 (unsigned)dev_priv->max_gmr_ids);
516 DRM_INFO("Max GMR descriptors is %u\n",
517 (unsigned)dev_priv->max_gmr_descriptors);
519 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
520 DRM_INFO("Max number of GMR pages is %u\n",
521 (unsigned)dev_priv->max_gmr_pages);
522 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
523 (unsigned)dev_priv->memory_size / 1024);
525 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
526 dev_priv->vram_start, dev_priv->vram_size / 1024);
527 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
528 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
530 ret = vmw_ttm_global_init(dev_priv);
531 if (unlikely(ret != 0))
535 vmw_master_init(&dev_priv->fbdev_master);
536 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
537 dev_priv->active_master = &dev_priv->fbdev_master;
540 ret = ttm_bo_device_init(&dev_priv->bdev,
541 dev_priv->bo_global_ref.ref.object,
542 &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
544 if (unlikely(ret != 0)) {
545 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
549 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
550 (dev_priv->vram_size >> PAGE_SHIFT));
551 if (unlikely(ret != 0)) {
552 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
556 dev_priv->has_gmr = true;
557 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
558 dev_priv->max_gmr_ids) != 0) {
559 DRM_INFO("No GMR memory available. "
560 "Graphics memory resources are very limited.\n");
561 dev_priv->has_gmr = false;
564 dev_priv->mmio_mtrr = drm_mtrr_add(dev_priv->mmio_start,
565 dev_priv->mmio_size, DRM_MTRR_WC);
567 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
568 dev_priv->mmio_size);
570 if (unlikely(dev_priv->mmio_virt == NULL)) {
572 DRM_ERROR("Failed mapping MMIO.\n");
576 /* Need mmio memory to check for fifo pitchlock cap. */
577 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
578 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
579 !vmw_fifo_have_pitchlock(dev_priv)) {
581 DRM_ERROR("Hardware has no pitchlock\n");
585 dev_priv->tdev = ttm_object_device_init
586 (dev_priv->mem_global_ref.object, 12);
588 if (unlikely(dev_priv->tdev == NULL)) {
589 DRM_ERROR("Unable to initialize TTM object management.\n");
594 dev->dev_private = dev_priv;
596 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
597 dev_priv->stealth = (ret != 0);
598 if (dev_priv->stealth) {
600 * Request at least the mmio PCI resource.
603 DRM_INFO("It appears like vesafb is loaded. "
604 "Ignore above error if any.\n");
605 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
606 if (unlikely(ret != 0)) {
607 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
612 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
613 ret = drm_irq_install(dev);
615 DRM_ERROR("Failed installing irq: %d\n", ret);
620 dev_priv->fman = vmw_fence_manager_init(dev_priv);
621 if (unlikely(dev_priv->fman == NULL))
624 vmw_kms_save_vga(dev_priv);
626 /* Start kms and overlay systems, needs fifo. */
627 ret = vmw_kms_init(dev_priv);
628 if (unlikely(ret != 0))
630 vmw_overlay_init(dev_priv);
632 if (dev_priv->enable_fb) {
633 ret = vmw_3d_resource_inc(dev_priv, true);
634 if (unlikely(ret != 0))
636 vmw_fb_init(dev_priv);
639 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
640 register_pm_notifier(&dev_priv->pm_nb);
645 vmw_overlay_close(dev_priv);
646 vmw_kms_close(dev_priv);
648 vmw_kms_restore_vga(dev_priv);
649 vmw_fence_manager_takedown(dev_priv->fman);
651 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
652 drm_irq_uninstall(dev_priv->dev);
654 if (dev_priv->stealth)
655 pci_release_region(dev->pdev, 2);
657 pci_release_regions(dev->pdev);
659 ttm_object_device_release(&dev_priv->tdev);
661 iounmap(dev_priv->mmio_virt);
663 drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
664 dev_priv->mmio_size, DRM_MTRR_WC);
665 if (dev_priv->has_gmr)
666 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
667 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
669 (void)ttm_bo_device_release(&dev_priv->bdev);
671 vmw_ttm_global_release(dev_priv);
673 idr_destroy(&dev_priv->surface_idr);
674 idr_destroy(&dev_priv->context_idr);
675 idr_destroy(&dev_priv->stream_idr);
680 static int vmw_driver_unload(struct drm_device *dev)
682 struct vmw_private *dev_priv = vmw_priv(dev);
684 unregister_pm_notifier(&dev_priv->pm_nb);
686 if (dev_priv->ctx.cmd_bounce)
687 vfree(dev_priv->ctx.cmd_bounce);
688 if (dev_priv->enable_fb) {
689 vmw_fb_close(dev_priv);
690 vmw_kms_restore_vga(dev_priv);
691 vmw_3d_resource_dec(dev_priv, false);
693 vmw_kms_close(dev_priv);
694 vmw_overlay_close(dev_priv);
695 vmw_fence_manager_takedown(dev_priv->fman);
696 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
697 drm_irq_uninstall(dev_priv->dev);
698 if (dev_priv->stealth)
699 pci_release_region(dev->pdev, 2);
701 pci_release_regions(dev->pdev);
703 ttm_object_device_release(&dev_priv->tdev);
704 iounmap(dev_priv->mmio_virt);
705 drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
706 dev_priv->mmio_size, DRM_MTRR_WC);
707 if (dev_priv->has_gmr)
708 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
709 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
710 (void)ttm_bo_device_release(&dev_priv->bdev);
711 vmw_ttm_global_release(dev_priv);
712 idr_destroy(&dev_priv->surface_idr);
713 idr_destroy(&dev_priv->context_idr);
714 idr_destroy(&dev_priv->stream_idr);
721 static void vmw_preclose(struct drm_device *dev,
722 struct drm_file *file_priv)
724 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
725 struct vmw_private *dev_priv = vmw_priv(dev);
727 vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
730 static void vmw_postclose(struct drm_device *dev,
731 struct drm_file *file_priv)
733 struct vmw_fpriv *vmw_fp;
735 vmw_fp = vmw_fpriv(file_priv);
736 ttm_object_file_release(&vmw_fp->tfile);
737 if (vmw_fp->locked_master)
738 drm_master_put(&vmw_fp->locked_master);
742 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
744 struct vmw_private *dev_priv = vmw_priv(dev);
745 struct vmw_fpriv *vmw_fp;
748 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
749 if (unlikely(vmw_fp == NULL))
752 INIT_LIST_HEAD(&vmw_fp->fence_events);
753 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
754 if (unlikely(vmw_fp->tfile == NULL))
757 file_priv->driver_priv = vmw_fp;
758 dev_priv->bdev.dev_mapping = dev->dev_mapping;
767 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
770 struct drm_file *file_priv = filp->private_data;
771 struct drm_device *dev = file_priv->minor->dev;
772 unsigned int nr = DRM_IOCTL_NR(cmd);
775 * Do extra checking on driver private ioctls.
778 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
779 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
780 struct drm_ioctl_desc *ioctl =
781 &vmw_ioctls[nr - DRM_COMMAND_BASE];
783 if (unlikely(ioctl->cmd_drv != cmd)) {
784 DRM_ERROR("Invalid command format, ioctl %d\n",
785 nr - DRM_COMMAND_BASE);
790 return drm_ioctl(filp, cmd, arg);
793 static int vmw_firstopen(struct drm_device *dev)
795 struct vmw_private *dev_priv = vmw_priv(dev);
796 dev_priv->is_opened = true;
801 static void vmw_lastclose(struct drm_device *dev)
803 struct vmw_private *dev_priv = vmw_priv(dev);
804 struct drm_crtc *crtc;
805 struct drm_mode_set set;
809 * Do nothing on the lastclose call from drm_unload.
812 if (!dev_priv->is_opened)
815 dev_priv->is_opened = false;
820 set.connectors = NULL;
821 set.num_connectors = 0;
823 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
825 ret = crtc->funcs->set_config(&set);
831 static void vmw_master_init(struct vmw_master *vmaster)
833 ttm_lock_init(&vmaster->lock);
834 INIT_LIST_HEAD(&vmaster->fb_surf);
835 mutex_init(&vmaster->fb_surf_mutex);
838 static int vmw_master_create(struct drm_device *dev,
839 struct drm_master *master)
841 struct vmw_master *vmaster;
843 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
844 if (unlikely(vmaster == NULL))
847 vmw_master_init(vmaster);
848 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
849 master->driver_priv = vmaster;
854 static void vmw_master_destroy(struct drm_device *dev,
855 struct drm_master *master)
857 struct vmw_master *vmaster = vmw_master(master);
859 master->driver_priv = NULL;
864 static int vmw_master_set(struct drm_device *dev,
865 struct drm_file *file_priv,
868 struct vmw_private *dev_priv = vmw_priv(dev);
869 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
870 struct vmw_master *active = dev_priv->active_master;
871 struct vmw_master *vmaster = vmw_master(file_priv->master);
874 if (!dev_priv->enable_fb) {
875 ret = vmw_3d_resource_inc(dev_priv, true);
876 if (unlikely(ret != 0))
878 vmw_kms_save_vga(dev_priv);
879 mutex_lock(&dev_priv->hw_mutex);
880 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
881 mutex_unlock(&dev_priv->hw_mutex);
885 BUG_ON(active != &dev_priv->fbdev_master);
886 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
887 if (unlikely(ret != 0))
888 goto out_no_active_lock;
890 ttm_lock_set_kill(&active->lock, true, SIGTERM);
891 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
892 if (unlikely(ret != 0)) {
893 DRM_ERROR("Unable to clean VRAM on "
897 dev_priv->active_master = NULL;
900 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
902 ttm_vt_unlock(&vmaster->lock);
903 BUG_ON(vmw_fp->locked_master != file_priv->master);
904 drm_master_put(&vmw_fp->locked_master);
907 dev_priv->active_master = vmaster;
912 if (!dev_priv->enable_fb) {
913 vmw_kms_restore_vga(dev_priv);
914 vmw_3d_resource_dec(dev_priv, true);
915 mutex_lock(&dev_priv->hw_mutex);
916 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
917 mutex_unlock(&dev_priv->hw_mutex);
922 static void vmw_master_drop(struct drm_device *dev,
923 struct drm_file *file_priv,
926 struct vmw_private *dev_priv = vmw_priv(dev);
927 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
928 struct vmw_master *vmaster = vmw_master(file_priv->master);
932 * Make sure the master doesn't disappear while we have
936 vmw_fp->locked_master = drm_master_get(file_priv->master);
937 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
938 vmw_execbuf_release_pinned_bo(dev_priv, false, 0);
940 if (unlikely((ret != 0))) {
941 DRM_ERROR("Unable to lock TTM at VT switch.\n");
942 drm_master_put(&vmw_fp->locked_master);
945 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
947 if (!dev_priv->enable_fb) {
948 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
949 if (unlikely(ret != 0))
950 DRM_ERROR("Unable to clean VRAM on master drop.\n");
951 vmw_kms_restore_vga(dev_priv);
952 vmw_3d_resource_dec(dev_priv, true);
953 mutex_lock(&dev_priv->hw_mutex);
954 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
955 mutex_unlock(&dev_priv->hw_mutex);
958 dev_priv->active_master = &dev_priv->fbdev_master;
959 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
960 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
962 if (dev_priv->enable_fb)
967 static void vmw_remove(struct pci_dev *pdev)
969 struct drm_device *dev = pci_get_drvdata(pdev);
974 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
977 struct vmw_private *dev_priv =
978 container_of(nb, struct vmw_private, pm_nb);
979 struct vmw_master *vmaster = dev_priv->active_master;
982 case PM_HIBERNATION_PREPARE:
983 case PM_SUSPEND_PREPARE:
984 ttm_suspend_lock(&vmaster->lock);
987 * This empties VRAM and unbinds all GMR bindings.
988 * Buffer contents is moved to swappable memory.
990 vmw_execbuf_release_pinned_bo(dev_priv, false, 0);
991 ttm_bo_swapout_all(&dev_priv->bdev);
994 case PM_POST_HIBERNATION:
995 case PM_POST_SUSPEND:
996 case PM_POST_RESTORE:
997 ttm_suspend_unlock(&vmaster->lock);
1000 case PM_RESTORE_PREPARE:
1009 * These might not be needed with the virtual SVGA device.
1012 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1014 struct drm_device *dev = pci_get_drvdata(pdev);
1015 struct vmw_private *dev_priv = vmw_priv(dev);
1017 if (dev_priv->num_3d_resources != 0) {
1018 DRM_INFO("Can't suspend or hibernate "
1019 "while 3D resources are active.\n");
1023 pci_save_state(pdev);
1024 pci_disable_device(pdev);
1025 pci_set_power_state(pdev, PCI_D3hot);
1029 static int vmw_pci_resume(struct pci_dev *pdev)
1031 pci_set_power_state(pdev, PCI_D0);
1032 pci_restore_state(pdev);
1033 return pci_enable_device(pdev);
1036 static int vmw_pm_suspend(struct device *kdev)
1038 struct pci_dev *pdev = to_pci_dev(kdev);
1039 struct pm_message dummy;
1043 return vmw_pci_suspend(pdev, dummy);
1046 static int vmw_pm_resume(struct device *kdev)
1048 struct pci_dev *pdev = to_pci_dev(kdev);
1050 return vmw_pci_resume(pdev);
1053 static int vmw_pm_prepare(struct device *kdev)
1055 struct pci_dev *pdev = to_pci_dev(kdev);
1056 struct drm_device *dev = pci_get_drvdata(pdev);
1057 struct vmw_private *dev_priv = vmw_priv(dev);
1060 * Release 3d reference held by fbdev and potentially
1063 dev_priv->suspended = true;
1064 if (dev_priv->enable_fb)
1065 vmw_3d_resource_dec(dev_priv, true);
1067 if (dev_priv->num_3d_resources != 0) {
1069 DRM_INFO("Can't suspend or hibernate "
1070 "while 3D resources are active.\n");
1072 if (dev_priv->enable_fb)
1073 vmw_3d_resource_inc(dev_priv, true);
1074 dev_priv->suspended = false;
1081 static void vmw_pm_complete(struct device *kdev)
1083 struct pci_dev *pdev = to_pci_dev(kdev);
1084 struct drm_device *dev = pci_get_drvdata(pdev);
1085 struct vmw_private *dev_priv = vmw_priv(dev);
1088 * Reclaim 3d reference held by fbdev and potentially
1091 if (dev_priv->enable_fb)
1092 vmw_3d_resource_inc(dev_priv, false);
1094 dev_priv->suspended = false;
1097 static const struct dev_pm_ops vmw_pm_ops = {
1098 .prepare = vmw_pm_prepare,
1099 .complete = vmw_pm_complete,
1100 .suspend = vmw_pm_suspend,
1101 .resume = vmw_pm_resume,
1104 static const struct file_operations vmwgfx_driver_fops = {
1105 .owner = THIS_MODULE,
1107 .release = drm_release,
1108 .unlocked_ioctl = vmw_unlocked_ioctl,
1110 .poll = vmw_fops_poll,
1111 .read = vmw_fops_read,
1112 .fasync = drm_fasync,
1113 #if defined(CONFIG_COMPAT)
1114 .compat_ioctl = drm_compat_ioctl,
1116 .llseek = noop_llseek,
1119 static struct drm_driver driver = {
1120 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1122 .load = vmw_driver_load,
1123 .unload = vmw_driver_unload,
1124 .firstopen = vmw_firstopen,
1125 .lastclose = vmw_lastclose,
1126 .irq_preinstall = vmw_irq_preinstall,
1127 .irq_postinstall = vmw_irq_postinstall,
1128 .irq_uninstall = vmw_irq_uninstall,
1129 .irq_handler = vmw_irq_handler,
1130 .get_vblank_counter = vmw_get_vblank_counter,
1131 .enable_vblank = vmw_enable_vblank,
1132 .disable_vblank = vmw_disable_vblank,
1133 .ioctls = vmw_ioctls,
1134 .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
1135 .dma_quiescent = NULL, /*vmw_dma_quiescent, */
1136 .master_create = vmw_master_create,
1137 .master_destroy = vmw_master_destroy,
1138 .master_set = vmw_master_set,
1139 .master_drop = vmw_master_drop,
1140 .open = vmw_driver_open,
1141 .preclose = vmw_preclose,
1142 .postclose = vmw_postclose,
1144 .dumb_create = vmw_dumb_create,
1145 .dumb_map_offset = vmw_dumb_map_offset,
1146 .dumb_destroy = vmw_dumb_destroy,
1148 .fops = &vmwgfx_driver_fops,
1149 .name = VMWGFX_DRIVER_NAME,
1150 .desc = VMWGFX_DRIVER_DESC,
1151 .date = VMWGFX_DRIVER_DATE,
1152 .major = VMWGFX_DRIVER_MAJOR,
1153 .minor = VMWGFX_DRIVER_MINOR,
1154 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1157 static struct pci_driver vmw_pci_driver = {
1158 .name = VMWGFX_DRIVER_NAME,
1159 .id_table = vmw_pci_id_list,
1161 .remove = vmw_remove,
1167 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1169 return drm_get_pci_dev(pdev, ent, &driver);
1172 static int __init vmwgfx_init(void)
1175 ret = drm_pci_init(&driver, &vmw_pci_driver);
1177 DRM_ERROR("Failed initializing DRM.\n");
1181 static void __exit vmwgfx_exit(void)
1183 drm_pci_exit(&driver, &vmw_pci_driver);
1186 module_init(vmwgfx_init);
1187 module_exit(vmwgfx_exit);
1189 MODULE_AUTHOR("VMware Inc. and others");
1190 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1191 MODULE_LICENSE("GPL and additional rights");
1192 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1193 __stringify(VMWGFX_DRIVER_MINOR) "."
1194 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."