Pileus Git - ~andy/linux/blob - drivers/gpu/drm/vmwgfx/vmwgfx_drv.c

   1 /**************************************************************************
   2  *
   3  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27 #include <linux/module.h>
  28
  29 #include <drm/drmP.h>
  30 #include "vmwgfx_drv.h"
  31 #include <drm/ttm/ttm_placement.h>
  32 #include <drm/ttm/ttm_bo_driver.h>
  33 #include <drm/ttm/ttm_object.h>
  34 #include <drm/ttm/ttm_module.h>
  35 #include <linux/dma_remapping.h>
  36
  37 #define VMWGFX_DRIVER_NAME "vmwgfx"
  38 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
  39 #define VMWGFX_CHIP_SVGAII 0
  40 #define VMW_FB_RESERVATION 0
  41
  42 #define VMW_MIN_INITIAL_WIDTH 800
  43 #define VMW_MIN_INITIAL_HEIGHT 600
  44
  45
  46 /**
  47  * Fully encoded drm commands. Might move to vmw_drm.h
  48  */
  49
  50 #define DRM_IOCTL_VMW_GET_PARAM                                 \
  51         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,          \
  52                  struct drm_vmw_getparam_arg)
  53 #define DRM_IOCTL_VMW_ALLOC_DMABUF                              \
  54         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,       \
  55                 union drm_vmw_alloc_dmabuf_arg)
  56 #define DRM_IOCTL_VMW_UNREF_DMABUF                              \
  57         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,        \
  58                 struct drm_vmw_unref_dmabuf_arg)
  59 #define DRM_IOCTL_VMW_CURSOR_BYPASS                             \
  60         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,       \
  61                  struct drm_vmw_cursor_bypass_arg)
  62
  63 #define DRM_IOCTL_VMW_CONTROL_STREAM                            \
  64         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,      \
  65                  struct drm_vmw_control_stream_arg)
  66 #define DRM_IOCTL_VMW_CLAIM_STREAM                              \
  67         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,        \
  68                  struct drm_vmw_stream_arg)
  69 #define DRM_IOCTL_VMW_UNREF_STREAM                              \
  70         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,        \
  71                  struct drm_vmw_stream_arg)
  72
  73 #define DRM_IOCTL_VMW_CREATE_CONTEXT                            \
  74         DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,      \
  75                 struct drm_vmw_context_arg)
  76 #define DRM_IOCTL_VMW_UNREF_CONTEXT                             \
  77         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,       \
  78                 struct drm_vmw_context_arg)
  79 #define DRM_IOCTL_VMW_CREATE_SURFACE                            \
  80         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,     \
  81                  union drm_vmw_surface_create_arg)
  82 #define DRM_IOCTL_VMW_UNREF_SURFACE                             \
  83         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,       \
  84                  struct drm_vmw_surface_arg)
  85 #define DRM_IOCTL_VMW_REF_SURFACE                               \
  86         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,        \
  87                  union drm_vmw_surface_reference_arg)
  88 #define DRM_IOCTL_VMW_EXECBUF                                   \
  89         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,             \
  90                 struct drm_vmw_execbuf_arg)
  91 #define DRM_IOCTL_VMW_GET_3D_CAP                                \
  92         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP,          \
  93                  struct drm_vmw_get_3d_cap_arg)
  94 #define DRM_IOCTL_VMW_FENCE_WAIT                                \
  95         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,         \
  96                  struct drm_vmw_fence_wait_arg)
  97 #define DRM_IOCTL_VMW_FENCE_SIGNALED                            \
  98         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED,     \
  99                  struct drm_vmw_fence_signaled_arg)
 100 #define DRM_IOCTL_VMW_FENCE_UNREF                               \
 101         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF,         \
 102                  struct drm_vmw_fence_arg)
 103 #define DRM_IOCTL_VMW_FENCE_EVENT                               \
 104         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT,         \
 105                  struct drm_vmw_fence_event_arg)
 106 #define DRM_IOCTL_VMW_PRESENT                                   \
 107         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT,             \
 108                  struct drm_vmw_present_arg)
 109 #define DRM_IOCTL_VMW_PRESENT_READBACK                          \
 110         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK,    \
 111                  struct drm_vmw_present_readback_arg)
 112 #define DRM_IOCTL_VMW_UPDATE_LAYOUT                             \
 113         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,       \
 114                  struct drm_vmw_update_layout_arg)
 115 #define DRM_IOCTL_VMW_CREATE_SHADER                             \
 116         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER,      \
 117                  struct drm_vmw_shader_create_arg)
 118 #define DRM_IOCTL_VMW_UNREF_SHADER                              \
 119         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER,        \
 120                  struct drm_vmw_shader_arg)
 121 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE                         \
 122         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE,  \
 123                  union drm_vmw_gb_surface_create_arg)
 124 #define DRM_IOCTL_VMW_GB_SURFACE_REF                            \
 125         DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF,     \
 126                  union drm_vmw_gb_surface_reference_arg)
 127 #define DRM_IOCTL_VMW_SYNCCPU                                   \
 128         DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU,             \
 129                  struct drm_vmw_synccpu_arg)
 130
 131 /**
 132  * The core DRM version of this macro doesn't account for
 133  * DRM_COMMAND_BASE.
 134  */
 135
 136 #define VMW_IOCTL_DEF(ioctl, func, flags) \
 137   [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
 138
 139 /**
 140  * Ioctl definitions.
 141  */
 142
 143 static const struct drm_ioctl_desc vmw_ioctls[] = {
 144         VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
 145                       DRM_AUTH | DRM_UNLOCKED),
 146         VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
 147                       DRM_AUTH | DRM_UNLOCKED),
 148         VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
 149                       DRM_AUTH | DRM_UNLOCKED),
 150         VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
 151                       vmw_kms_cursor_bypass_ioctl,
 152                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 153
 154         VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
 155                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 156         VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
 157                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 158         VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
 159                       DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
 160
 161         VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
 162                       DRM_AUTH | DRM_UNLOCKED),
 163         VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
 164                       DRM_AUTH | DRM_UNLOCKED),
 165         VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
 166                       DRM_AUTH | DRM_UNLOCKED),
 167         VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
 168                       DRM_AUTH | DRM_UNLOCKED),
 169         VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
 170                       DRM_AUTH | DRM_UNLOCKED),
 171         VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
 172                       DRM_AUTH | DRM_UNLOCKED),
 173         VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
 174                       DRM_AUTH | DRM_UNLOCKED),
 175         VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
 176                       vmw_fence_obj_signaled_ioctl,
 177                       DRM_AUTH | DRM_UNLOCKED),
 178         VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
 179                       DRM_AUTH | DRM_UNLOCKED),
 180         VMW_IOCTL_DEF(VMW_FENCE_EVENT,
 181                       vmw_fence_event_ioctl,
 182                       DRM_AUTH | DRM_UNLOCKED),
 183         VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
 184                       DRM_AUTH | DRM_UNLOCKED),
 185
 186         /* these allow direct access to the framebuffers mark as master only */
 187         VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
 188                       DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
 189         VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
 190                       vmw_present_readback_ioctl,
 191                       DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
 192         VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
 193                       vmw_kms_update_layout_ioctl,
 194                       DRM_MASTER | DRM_UNLOCKED),
 195         VMW_IOCTL_DEF(VMW_CREATE_SHADER,
 196                       vmw_shader_define_ioctl,
 197                       DRM_AUTH | DRM_UNLOCKED),
 198         VMW_IOCTL_DEF(VMW_UNREF_SHADER,
 199                       vmw_shader_destroy_ioctl,
 200                       DRM_AUTH | DRM_UNLOCKED),
 201         VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
 202                       vmw_gb_surface_define_ioctl,
 203                       DRM_AUTH | DRM_UNLOCKED),
 204         VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
 205                       vmw_gb_surface_reference_ioctl,
 206                       DRM_AUTH | DRM_UNLOCKED),
 207         VMW_IOCTL_DEF(VMW_SYNCCPU,
 208                       vmw_user_dmabuf_synccpu_ioctl,
 209                       DRM_AUTH | DRM_UNLOCKED),
 210 };
 211
 212 static struct pci_device_id vmw_pci_id_list[] = {
 213         {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
 214         {0, 0, 0}
 215 };
 216 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
 217
 218 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
 219 static int vmw_force_iommu;
 220 static int vmw_restrict_iommu;
 221 static int vmw_force_coherent;
 222 static int vmw_restrict_dma_mask;
 223
 224 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
 225 static void vmw_master_init(struct vmw_master *);
 226 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
 227                               void *ptr);
 228
 229 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
 230 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
 231 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
 232 module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
 233 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
 234 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
 235 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
 236 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
 237 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
 238 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
 239
 240
 241 static void vmw_print_capabilities(uint32_t capabilities)
 242 {
 243         DRM_INFO("Capabilities:\n");
 244         if (capabilities & SVGA_CAP_RECT_COPY)
 245                 DRM_INFO("  Rect copy.\n");
 246         if (capabilities & SVGA_CAP_CURSOR)
 247                 DRM_INFO("  Cursor.\n");
 248         if (capabilities & SVGA_CAP_CURSOR_BYPASS)
 249                 DRM_INFO("  Cursor bypass.\n");
 250         if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
 251                 DRM_INFO("  Cursor bypass 2.\n");
 252         if (capabilities & SVGA_CAP_8BIT_EMULATION)
 253                 DRM_INFO("  8bit emulation.\n");
 254         if (capabilities & SVGA_CAP_ALPHA_CURSOR)
 255                 DRM_INFO("  Alpha cursor.\n");
 256         if (capabilities & SVGA_CAP_3D)
 257                 DRM_INFO("  3D.\n");
 258         if (capabilities & SVGA_CAP_EXTENDED_FIFO)
 259                 DRM_INFO("  Extended Fifo.\n");
 260         if (capabilities & SVGA_CAP_MULTIMON)
 261                 DRM_INFO("  Multimon.\n");
 262         if (capabilities & SVGA_CAP_PITCHLOCK)
 263                 DRM_INFO("  Pitchlock.\n");
 264         if (capabilities & SVGA_CAP_IRQMASK)
 265                 DRM_INFO("  Irq mask.\n");
 266         if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
 267                 DRM_INFO("  Display Topology.\n");
 268         if (capabilities & SVGA_CAP_GMR)
 269                 DRM_INFO("  GMR.\n");
 270         if (capabilities & SVGA_CAP_TRACES)
 271                 DRM_INFO("  Traces.\n");
 272         if (capabilities & SVGA_CAP_GMR2)
 273                 DRM_INFO("  GMR2.\n");
 274         if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
 275                 DRM_INFO("  Screen Object 2.\n");
 276         if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
 277                 DRM_INFO("  Command Buffers.\n");
 278         if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
 279                 DRM_INFO("  Command Buffers 2.\n");
 280         if (capabilities & SVGA_CAP_GBOBJECTS)
 281                 DRM_INFO("  Guest Backed Resources.\n");
 282 }
 283
 284 /**
 285  * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
 286  *
 287  * @dev_priv: A device private structure.
 288  *
 289  * This function creates a small buffer object that holds the query
 290  * result for dummy queries emitted as query barriers.
 291  * The function will then map the first page and initialize a pending
 292  * occlusion query result structure, Finally it will unmap the buffer.
 293  * No interruptible waits are done within this function.
 294  *
 295  * Returns an error if bo creation or initialization fails.
 296  */
 297 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
 298 {
 299         int ret;
 300         struct ttm_buffer_object *bo;
 301         struct ttm_bo_kmap_obj map;
 302         volatile SVGA3dQueryResult *result;
 303         bool dummy;
 304
 305         /*
 306          * Create the bo as pinned, so that a tryreserve will
 307          * immediately succeed. This is because we're the only
 308          * user of the bo currently.
 309          */
 310         ret = ttm_bo_create(&dev_priv->bdev,
 311                             PAGE_SIZE,
 312                             ttm_bo_type_device,
 313                             &vmw_sys_ne_placement,
 314                             0, false, NULL,
 315                             &bo);
 316
 317         if (unlikely(ret != 0))
 318                 return ret;
 319
 320         ret = ttm_bo_reserve(bo, false, true, false, 0);
 321         BUG_ON(ret != 0);
 322
 323         ret = ttm_bo_kmap(bo, 0, 1, &map);
 324         if (likely(ret == 0)) {
 325                 result = ttm_kmap_obj_virtual(&map, &dummy);
 326                 result->totalSize = sizeof(*result);
 327                 result->state = SVGA3D_QUERYSTATE_PENDING;
 328                 result->result32 = 0xff;
 329                 ttm_bo_kunmap(&map);
 330         }
 331         vmw_bo_pin(bo, false);
 332         ttm_bo_unreserve(bo);
 333
 334         if (unlikely(ret != 0)) {
 335                 DRM_ERROR("Dummy query buffer map failed.\n");
 336                 ttm_bo_unref(&bo);
 337         } else
 338                 dev_priv->dummy_query_bo = bo;
 339
 340         return ret;
 341 }
 342
 343 static int vmw_request_device(struct vmw_private *dev_priv)
 344 {
 345         int ret;
 346
 347         ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
 348         if (unlikely(ret != 0)) {
 349                 DRM_ERROR("Unable to initialize FIFO.\n");
 350                 return ret;
 351         }
 352         vmw_fence_fifo_up(dev_priv->fman);
 353         if (dev_priv->has_mob) {
 354                 ret = vmw_otables_setup(dev_priv);
 355                 if (unlikely(ret != 0)) {
 356                         DRM_ERROR("Unable to initialize "
 357                                   "guest Memory OBjects.\n");
 358                         goto out_no_mob;
 359                 }
 360         }
 361         ret = vmw_dummy_query_bo_create(dev_priv);
 362         if (unlikely(ret != 0))
 363                 goto out_no_query_bo;
 364
 365         return 0;
 366
 367 out_no_query_bo:
 368         if (dev_priv->has_mob)
 369                 vmw_otables_takedown(dev_priv);
 370 out_no_mob:
 371         vmw_fence_fifo_down(dev_priv->fman);
 372         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 373         return ret;
 374 }
 375
 376 static void vmw_release_device(struct vmw_private *dev_priv)
 377 {
 378         /*
 379          * Previous destructions should've released
 380          * the pinned bo.
 381          */
 382
 383         BUG_ON(dev_priv->pinned_bo != NULL);
 384
 385         ttm_bo_unref(&dev_priv->dummy_query_bo);
 386         if (dev_priv->has_mob)
 387                 vmw_otables_takedown(dev_priv);
 388         vmw_fence_fifo_down(dev_priv->fman);
 389         vmw_fifo_release(dev_priv, &dev_priv->fifo);
 390 }
 391
 392
 393 /**
 394  * Increase the 3d resource refcount.
 395  * If the count was prevously zero, initialize the fifo, switching to svga
 396  * mode. Note that the master holds a ref as well, and may request an
 397  * explicit switch to svga mode if fb is not running, using @unhide_svga.
 398  */
 399 int vmw_3d_resource_inc(struct vmw_private *dev_priv,
 400                         bool unhide_svga)
 401 {
 402         int ret = 0;
 403
 404         mutex_lock(&dev_priv->release_mutex);
 405         if (unlikely(dev_priv->num_3d_resources++ == 0)) {
 406                 ret = vmw_request_device(dev_priv);
 407                 if (unlikely(ret != 0))
 408                         --dev_priv->num_3d_resources;
 409         } else if (unhide_svga) {
 410                 mutex_lock(&dev_priv->hw_mutex);
 411                 vmw_write(dev_priv, SVGA_REG_ENABLE,
 412                           vmw_read(dev_priv, SVGA_REG_ENABLE) &
 413                           ~SVGA_REG_ENABLE_HIDE);
 414                 mutex_unlock(&dev_priv->hw_mutex);
 415         }
 416
 417         mutex_unlock(&dev_priv->release_mutex);
 418         return ret;
 419 }
 420
 421 /**
 422  * Decrease the 3d resource refcount.
 423  * If the count reaches zero, disable the fifo, switching to vga mode.
 424  * Note that the master holds a refcount as well, and may request an
 425  * explicit switch to vga mode when it releases its refcount to account
 426  * for the situation of an X server vt switch to VGA with 3d resources
 427  * active.
 428  */
 429 void vmw_3d_resource_dec(struct vmw_private *dev_priv,
 430                          bool hide_svga)
 431 {
 432         int32_t n3d;
 433
 434         mutex_lock(&dev_priv->release_mutex);
 435         if (unlikely(--dev_priv->num_3d_resources == 0))
 436                 vmw_release_device(dev_priv);
 437         else if (hide_svga) {
 438                 mutex_lock(&dev_priv->hw_mutex);
 439                 vmw_write(dev_priv, SVGA_REG_ENABLE,
 440                           vmw_read(dev_priv, SVGA_REG_ENABLE) |
 441                           SVGA_REG_ENABLE_HIDE);
 442                 mutex_unlock(&dev_priv->hw_mutex);
 443         }
 444
 445         n3d = (int32_t) dev_priv->num_3d_resources;
 446         mutex_unlock(&dev_priv->release_mutex);
 447
 448         BUG_ON(n3d < 0);
 449 }
 450
 451 /**
 452  * Sets the initial_[width|height] fields on the given vmw_private.
 453  *
 454  * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
 455  * clamping the value to fb_max_[width|height] fields and the
 456  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 457  * If the values appear to be invalid, set them to
 458  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
 459  */
 460 static void vmw_get_initial_size(struct vmw_private *dev_priv)
 461 {
 462         uint32_t width;
 463         uint32_t height;
 464
 465         width = vmw_read(dev_priv, SVGA_REG_WIDTH);
 466         height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
 467
 468         width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
 469         height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
 470
 471         if (width > dev_priv->fb_max_width ||
 472             height > dev_priv->fb_max_height) {
 473
 474                 /*
 475                  * This is a host error and shouldn't occur.
 476                  */
 477
 478                 width = VMW_MIN_INITIAL_WIDTH;
 479                 height = VMW_MIN_INITIAL_HEIGHT;
 480         }
 481
 482         dev_priv->initial_width = width;
 483         dev_priv->initial_height = height;
 484 }
 485
 486 /**
 487  * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
 488  * system.
 489  *
 490  * @dev_priv: Pointer to a struct vmw_private
 491  *
 492  * This functions tries to determine the IOMMU setup and what actions
 493  * need to be taken by the driver to make system pages visible to the
 494  * device.
 495  * If this function decides that DMA is not possible, it returns -EINVAL.
 496  * The driver may then try to disable features of the device that require
 497  * DMA.
 498  */
 499 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
 500 {
 501         static const char *names[vmw_dma_map_max] = {
 502                 [vmw_dma_phys] = "Using physical TTM page addresses.",
 503                 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
 504                 [vmw_dma_map_populate] = "Keeping DMA mappings.",
 505                 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
 506 #ifdef CONFIG_X86
 507         const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
 508
 509 #ifdef CONFIG_INTEL_IOMMU
 510         if (intel_iommu_enabled) {
 511                 dev_priv->map_mode = vmw_dma_map_populate;
 512                 goto out_fixup;
 513         }
 514 #endif
 515
 516         if (!(vmw_force_iommu || vmw_force_coherent)) {
 517                 dev_priv->map_mode = vmw_dma_phys;
 518                 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
 519                 return 0;
 520         }
 521
 522         dev_priv->map_mode = vmw_dma_map_populate;
 523
 524         if (dma_ops->sync_single_for_cpu)
 525                 dev_priv->map_mode = vmw_dma_alloc_coherent;
 526 #ifdef CONFIG_SWIOTLB
 527         if (swiotlb_nr_tbl() == 0)
 528                 dev_priv->map_mode = vmw_dma_map_populate;
 529 #endif
 530
 531 #ifdef CONFIG_INTEL_IOMMU
 532 out_fixup:
 533 #endif
 534         if (dev_priv->map_mode == vmw_dma_map_populate &&
 535             vmw_restrict_iommu)
 536                 dev_priv->map_mode = vmw_dma_map_bind;
 537
 538         if (vmw_force_coherent)
 539                 dev_priv->map_mode = vmw_dma_alloc_coherent;
 540
 541 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
 542         /*
 543          * No coherent page pool
 544          */
 545         if (dev_priv->map_mode == vmw_dma_alloc_coherent)
 546                 return -EINVAL;
 547 #endif
 548
 549 #else /* CONFIG_X86 */
 550         dev_priv->map_mode = vmw_dma_map_populate;
 551 #endif /* CONFIG_X86 */
 552
 553         DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
 554
 555         return 0;
 556 }
 557
 558 /**
 559  * vmw_dma_masks - set required page- and dma masks
 560  *
 561  * @dev: Pointer to struct drm-device
 562  *
 563  * With 32-bit we can only handle 32 bit PFNs. Optionally set that
 564  * restriction also for 64-bit systems.
 565  */
 566 #ifdef CONFIG_INTEL_IOMMU
 567 static int vmw_dma_masks(struct vmw_private *dev_priv)
 568 {
 569         struct drm_device *dev = dev_priv->dev;
 570
 571         if (intel_iommu_enabled &&
 572             (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
 573                 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
 574                 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
 575         }
 576         return 0;
 577 }
 578 #else
 579 static int vmw_dma_masks(struct vmw_private *dev_priv)
 580 {
 581         return 0;
 582 }
 583 #endif
 584
 585 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
 586 {
 587         struct vmw_private *dev_priv;
 588         int ret;
 589         uint32_t svga_id;
 590         enum vmw_res_type i;
 591         bool refuse_dma = false;
 592
 593         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 594         if (unlikely(dev_priv == NULL)) {
 595                 DRM_ERROR("Failed allocating a device private struct.\n");
 596                 return -ENOMEM;
 597         }
 598
 599         pci_set_master(dev->pdev);
 600
 601         dev_priv->dev = dev;
 602         dev_priv->vmw_chipset = chipset;
 603         dev_priv->last_read_seqno = (uint32_t) -100;
 604         mutex_init(&dev_priv->hw_mutex);
 605         mutex_init(&dev_priv->cmdbuf_mutex);
 606         mutex_init(&dev_priv->release_mutex);
 607         mutex_init(&dev_priv->binding_mutex);
 608         rwlock_init(&dev_priv->resource_lock);
 609
 610         for (i = vmw_res_context; i < vmw_res_max; ++i) {
 611                 idr_init(&dev_priv->res_idr[i]);
 612                 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
 613         }
 614
 615         mutex_init(&dev_priv->init_mutex);
 616         init_waitqueue_head(&dev_priv->fence_queue);
 617         init_waitqueue_head(&dev_priv->fifo_queue);
 618         dev_priv->fence_queue_waiters = 0;
 619         atomic_set(&dev_priv->fifo_queue_waiters, 0);
 620
 621         dev_priv->used_memory_size = 0;
 622
 623         dev_priv->io_start = pci_resource_start(dev->pdev, 0);
 624         dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
 625         dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
 626
 627         dev_priv->enable_fb = enable_fbdev;
 628
 629         mutex_lock(&dev_priv->hw_mutex);
 630
 631         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
 632         svga_id = vmw_read(dev_priv, SVGA_REG_ID);
 633         if (svga_id != SVGA_ID_2) {
 634                 ret = -ENOSYS;
 635                 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
 636                 mutex_unlock(&dev_priv->hw_mutex);
 637                 goto out_err0;
 638         }
 639
 640         dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
 641         ret = vmw_dma_select_mode(dev_priv);
 642         if (unlikely(ret != 0)) {
 643                 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
 644                 refuse_dma = true;
 645         }
 646
 647         dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
 648         dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
 649         dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
 650         dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
 651
 652         vmw_get_initial_size(dev_priv);
 653
 654         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 655                 dev_priv->max_gmr_ids =
 656                         vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
 657                 dev_priv->max_gmr_pages =
 658                         vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
 659                 dev_priv->memory_size =
 660                         vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
 661                 dev_priv->memory_size -= dev_priv->vram_size;
 662         } else {
 663                 /*
 664                  * An arbitrary limit of 512MiB on surface
 665                  * memory. But all HWV8 hardware supports GMR2.
 666                  */
 667                 dev_priv->memory_size = 512*1024*1024;
 668         }
 669         dev_priv->max_mob_pages = 0;
 670         dev_priv->max_mob_size = 0;
 671         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
 672                 uint64_t mem_size =
 673                         vmw_read(dev_priv,
 674                                  SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
 675
 676                 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
 677                 dev_priv->prim_bb_mem =
 678                         vmw_read(dev_priv,
 679                                  SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
 680                 dev_priv->max_mob_size =
 681                         vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
 682         } else
 683                 dev_priv->prim_bb_mem = dev_priv->vram_size;
 684
 685         ret = vmw_dma_masks(dev_priv);
 686         if (unlikely(ret != 0)) {
 687                 mutex_unlock(&dev_priv->hw_mutex);
 688                 goto out_err0;
 689         }
 690
 691         if (unlikely(dev_priv->prim_bb_mem < dev_priv->vram_size))
 692                 dev_priv->prim_bb_mem = dev_priv->vram_size;
 693
 694         mutex_unlock(&dev_priv->hw_mutex);
 695
 696         vmw_print_capabilities(dev_priv->capabilities);
 697
 698         if (dev_priv->capabilities & SVGA_CAP_GMR2) {
 699                 DRM_INFO("Max GMR ids is %u\n",
 700                          (unsigned)dev_priv->max_gmr_ids);
 701                 DRM_INFO("Max number of GMR pages is %u\n",
 702                          (unsigned)dev_priv->max_gmr_pages);
 703                 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
 704                          (unsigned)dev_priv->memory_size / 1024);
 705         }
 706         DRM_INFO("Maximum display memory size is %u kiB\n",
 707                  dev_priv->prim_bb_mem / 1024);
 708         DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
 709                  dev_priv->vram_start, dev_priv->vram_size / 1024);
 710         DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
 711                  dev_priv->mmio_start, dev_priv->mmio_size / 1024);
 712
 713         ret = vmw_ttm_global_init(dev_priv);
 714         if (unlikely(ret != 0))
 715                 goto out_err0;
 716
 717
 718         vmw_master_init(&dev_priv->fbdev_master);
 719         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
 720         dev_priv->active_master = &dev_priv->fbdev_master;
 721
 722
 723         ret = ttm_bo_device_init(&dev_priv->bdev,
 724                                  dev_priv->bo_global_ref.ref.object,
 725                                  &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
 726                                  false);
 727         if (unlikely(ret != 0)) {
 728                 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
 729                 goto out_err1;
 730         }
 731
 732         ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
 733                              (dev_priv->vram_size >> PAGE_SHIFT));
 734         if (unlikely(ret != 0)) {
 735                 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
 736                 goto out_err2;
 737         }
 738
 739         dev_priv->has_gmr = true;
 740         if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
 741             refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
 742                                          VMW_PL_GMR) != 0) {
 743                 DRM_INFO("No GMR memory available. "
 744                          "Graphics memory resources are very limited.\n");
 745                 dev_priv->has_gmr = false;
 746         }
 747
 748         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
 749                 dev_priv->has_mob = true;
 750                 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
 751                                    VMW_PL_MOB) != 0) {
 752                         DRM_INFO("No MOB memory available. "
 753                                  "3D will be disabled.\n");
 754                         dev_priv->has_mob = false;
 755                 }
 756         }
 757
 758         dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start,
 759                                                dev_priv->mmio_size);
 760
 761         dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
 762                                          dev_priv->mmio_size);
 763
 764         if (unlikely(dev_priv->mmio_virt == NULL)) {
 765                 ret = -ENOMEM;
 766                 DRM_ERROR("Failed mapping MMIO.\n");
 767                 goto out_err3;
 768         }
 769
 770         /* Need mmio memory to check for fifo pitchlock cap. */
 771         if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
 772             !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
 773             !vmw_fifo_have_pitchlock(dev_priv)) {
 774                 ret = -ENOSYS;
 775                 DRM_ERROR("Hardware has no pitchlock\n");
 776                 goto out_err4;
 777         }
 778
 779         dev_priv->tdev = ttm_object_device_init
 780                 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
 781
 782         if (unlikely(dev_priv->tdev == NULL)) {
 783                 DRM_ERROR("Unable to initialize TTM object management.\n");
 784                 ret = -ENOMEM;
 785                 goto out_err4;
 786         }
 787
 788         dev->dev_private = dev_priv;
 789
 790         ret = pci_request_regions(dev->pdev, "vmwgfx probe");
 791         dev_priv->stealth = (ret != 0);
 792         if (dev_priv->stealth) {
 793                 /**
 794                  * Request at least the mmio PCI resource.
 795                  */
 796
 797                 DRM_INFO("It appears like vesafb is loaded. "
 798                          "Ignore above error if any.\n");
 799                 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
 800                 if (unlikely(ret != 0)) {
 801                         DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
 802                         goto out_no_device;
 803                 }
 804         }
 805
 806         if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
 807                 ret = drm_irq_install(dev);
 808                 if (ret != 0) {
 809                         DRM_ERROR("Failed installing irq: %d\n", ret);
 810                         goto out_no_irq;
 811                 }
 812         }
 813
 814         dev_priv->fman = vmw_fence_manager_init(dev_priv);
 815         if (unlikely(dev_priv->fman == NULL)) {
 816                 ret = -ENOMEM;
 817                 goto out_no_fman;
 818         }
 819
 820         vmw_kms_save_vga(dev_priv);
 821
 822         /* Start kms and overlay systems, needs fifo. */
 823         ret = vmw_kms_init(dev_priv);
 824         if (unlikely(ret != 0))
 825                 goto out_no_kms;
 826         vmw_overlay_init(dev_priv);
 827
 828         if (dev_priv->enable_fb) {
 829                 ret = vmw_3d_resource_inc(dev_priv, true);
 830                 if (unlikely(ret != 0))
 831                         goto out_no_fifo;
 832                 vmw_fb_init(dev_priv);
 833         }
 834
 835         dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
 836         register_pm_notifier(&dev_priv->pm_nb);
 837
 838         return 0;
 839
 840 out_no_fifo:
 841         vmw_overlay_close(dev_priv);
 842         vmw_kms_close(dev_priv);
 843 out_no_kms:
 844         vmw_kms_restore_vga(dev_priv);
 845         vmw_fence_manager_takedown(dev_priv->fman);
 846 out_no_fman:
 847         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
 848                 drm_irq_uninstall(dev_priv->dev);
 849 out_no_irq:
 850         if (dev_priv->stealth)
 851                 pci_release_region(dev->pdev, 2);
 852         else
 853                 pci_release_regions(dev->pdev);
 854 out_no_device:
 855         ttm_object_device_release(&dev_priv->tdev);
 856 out_err4:
 857         iounmap(dev_priv->mmio_virt);
 858 out_err3:
 859         arch_phys_wc_del(dev_priv->mmio_mtrr);
 860         if (dev_priv->has_mob)
 861                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
 862         if (dev_priv->has_gmr)
 863                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 864         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 865 out_err2:
 866         (void)ttm_bo_device_release(&dev_priv->bdev);
 867 out_err1:
 868         vmw_ttm_global_release(dev_priv);
 869 out_err0:
 870         for (i = vmw_res_context; i < vmw_res_max; ++i)
 871                 idr_destroy(&dev_priv->res_idr[i]);
 872
 873         kfree(dev_priv);
 874         return ret;
 875 }
 876
 877 static int vmw_driver_unload(struct drm_device *dev)
 878 {
 879         struct vmw_private *dev_priv = vmw_priv(dev);
 880         enum vmw_res_type i;
 881
 882         unregister_pm_notifier(&dev_priv->pm_nb);
 883
 884         if (dev_priv->ctx.res_ht_initialized)
 885                 drm_ht_remove(&dev_priv->ctx.res_ht);
 886         if (dev_priv->ctx.cmd_bounce)
 887                 vfree(dev_priv->ctx.cmd_bounce);
 888         if (dev_priv->enable_fb) {
 889                 vmw_fb_close(dev_priv);
 890                 vmw_kms_restore_vga(dev_priv);
 891                 vmw_3d_resource_dec(dev_priv, false);
 892         }
 893         vmw_kms_close(dev_priv);
 894         vmw_overlay_close(dev_priv);
 895         vmw_fence_manager_takedown(dev_priv->fman);
 896         if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
 897                 drm_irq_uninstall(dev_priv->dev);
 898         if (dev_priv->stealth)
 899                 pci_release_region(dev->pdev, 2);
 900         else
 901                 pci_release_regions(dev->pdev);
 902
 903         ttm_object_device_release(&dev_priv->tdev);
 904         iounmap(dev_priv->mmio_virt);
 905         arch_phys_wc_del(dev_priv->mmio_mtrr);
 906         if (dev_priv->has_mob)
 907                 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
 908         if (dev_priv->has_gmr)
 909                 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
 910         (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
 911         (void)ttm_bo_device_release(&dev_priv->bdev);
 912         vmw_ttm_global_release(dev_priv);
 913
 914         for (i = vmw_res_context; i < vmw_res_max; ++i)
 915                 idr_destroy(&dev_priv->res_idr[i]);
 916
 917         kfree(dev_priv);
 918
 919         return 0;
 920 }
 921
 922 static void vmw_preclose(struct drm_device *dev,
 923                          struct drm_file *file_priv)
 924 {
 925         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
 926         struct vmw_private *dev_priv = vmw_priv(dev);
 927
 928         vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
 929 }
 930
 931 static void vmw_postclose(struct drm_device *dev,
 932                          struct drm_file *file_priv)
 933 {
 934         struct vmw_fpriv *vmw_fp;
 935
 936         vmw_fp = vmw_fpriv(file_priv);
 937
 938         if (vmw_fp->locked_master) {
 939                 struct vmw_master *vmaster =
 940                         vmw_master(vmw_fp->locked_master);
 941
 942                 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
 943                 ttm_vt_unlock(&vmaster->lock);
 944                 drm_master_put(&vmw_fp->locked_master);
 945         }
 946
 947         vmw_compat_shader_man_destroy(vmw_fp->shman);
 948         ttm_object_file_release(&vmw_fp->tfile);
 949         kfree(vmw_fp);
 950 }
 951
 952 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
 953 {
 954         struct vmw_private *dev_priv = vmw_priv(dev);
 955         struct vmw_fpriv *vmw_fp;
 956         int ret = -ENOMEM;
 957
 958         vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
 959         if (unlikely(vmw_fp == NULL))
 960                 return ret;
 961
 962         INIT_LIST_HEAD(&vmw_fp->fence_events);
 963         vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
 964         if (unlikely(vmw_fp->tfile == NULL))
 965                 goto out_no_tfile;
 966
 967         vmw_fp->shman = vmw_compat_shader_man_create(dev_priv);
 968         if (IS_ERR(vmw_fp->shman))
 969                 goto out_no_shman;
 970
 971         file_priv->driver_priv = vmw_fp;
 972         dev_priv->bdev.dev_mapping = dev->dev_mapping;
 973
 974         return 0;
 975
 976 out_no_shman:
 977         ttm_object_file_release(&vmw_fp->tfile);
 978 out_no_tfile:
 979         kfree(vmw_fp);
 980         return ret;
 981 }
 982
 983 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
 984                                unsigned long arg)
 985 {
 986         struct drm_file *file_priv = filp->private_data;
 987         struct drm_device *dev = file_priv->minor->dev;
 988         unsigned int nr = DRM_IOCTL_NR(cmd);
 989
 990         /*
 991          * Do extra checking on driver private ioctls.
 992          */
 993
 994         if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
 995             && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
 996                 const struct drm_ioctl_desc *ioctl =
 997                     &vmw_ioctls[nr - DRM_COMMAND_BASE];
 998
 999                 if (unlikely(ioctl->cmd_drv != cmd)) {
1000                         DRM_ERROR("Invalid command format, ioctl %d\n",
1001                                   nr - DRM_COMMAND_BASE);
1002                         return -EINVAL;
1003                 }
1004         }
1005
1006         return drm_ioctl(filp, cmd, arg);
1007 }
1008
1009 static void vmw_lastclose(struct drm_device *dev)
1010 {
1011         struct drm_crtc *crtc;
1012         struct drm_mode_set set;
1013         int ret;
1014
1015         set.x = 0;
1016         set.y = 0;
1017         set.fb = NULL;
1018         set.mode = NULL;
1019         set.connectors = NULL;
1020         set.num_connectors = 0;
1021
1022         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1023                 set.crtc = crtc;
1024                 ret = drm_mode_set_config_internal(&set);
1025                 WARN_ON(ret != 0);
1026         }
1027
1028 }
1029
1030 static void vmw_master_init(struct vmw_master *vmaster)
1031 {
1032         ttm_lock_init(&vmaster->lock);
1033         INIT_LIST_HEAD(&vmaster->fb_surf);
1034         mutex_init(&vmaster->fb_surf_mutex);
1035 }
1036
1037 static int vmw_master_create(struct drm_device *dev,
1038                              struct drm_master *master)
1039 {
1040         struct vmw_master *vmaster;
1041
1042         vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1043         if (unlikely(vmaster == NULL))
1044                 return -ENOMEM;
1045
1046         vmw_master_init(vmaster);
1047         ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1048         master->driver_priv = vmaster;
1049
1050         return 0;
1051 }
1052
1053 static void vmw_master_destroy(struct drm_device *dev,
1054                                struct drm_master *master)
1055 {
1056         struct vmw_master *vmaster = vmw_master(master);
1057
1058         master->driver_priv = NULL;
1059         kfree(vmaster);
1060 }
1061
1062
1063 static int vmw_master_set(struct drm_device *dev,
1064                           struct drm_file *file_priv,
1065                           bool from_open)
1066 {
1067         struct vmw_private *dev_priv = vmw_priv(dev);
1068         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1069         struct vmw_master *active = dev_priv->active_master;
1070         struct vmw_master *vmaster = vmw_master(file_priv->master);
1071         int ret = 0;
1072
1073         if (!dev_priv->enable_fb) {
1074                 ret = vmw_3d_resource_inc(dev_priv, true);
1075                 if (unlikely(ret != 0))
1076                         return ret;
1077                 vmw_kms_save_vga(dev_priv);
1078                 mutex_lock(&dev_priv->hw_mutex);
1079                 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
1080                 mutex_unlock(&dev_priv->hw_mutex);
1081         }
1082
1083         if (active) {
1084                 BUG_ON(active != &dev_priv->fbdev_master);
1085                 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1086                 if (unlikely(ret != 0))
1087                         goto out_no_active_lock;
1088
1089                 ttm_lock_set_kill(&active->lock, true, SIGTERM);
1090                 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1091                 if (unlikely(ret != 0)) {
1092                         DRM_ERROR("Unable to clean VRAM on "
1093                                   "master drop.\n");
1094                 }
1095
1096                 dev_priv->active_master = NULL;
1097         }
1098
1099         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1100         if (!from_open) {
1101                 ttm_vt_unlock(&vmaster->lock);
1102                 BUG_ON(vmw_fp->locked_master != file_priv->master);
1103                 drm_master_put(&vmw_fp->locked_master);
1104         }
1105
1106         dev_priv->active_master = vmaster;
1107
1108         return 0;
1109
1110 out_no_active_lock:
1111         if (!dev_priv->enable_fb) {
1112                 vmw_kms_restore_vga(dev_priv);
1113                 vmw_3d_resource_dec(dev_priv, true);
1114                 mutex_lock(&dev_priv->hw_mutex);
1115                 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1116                 mutex_unlock(&dev_priv->hw_mutex);
1117         }
1118         return ret;
1119 }
1120
1121 static void vmw_master_drop(struct drm_device *dev,
1122                             struct drm_file *file_priv,
1123                             bool from_release)
1124 {
1125         struct vmw_private *dev_priv = vmw_priv(dev);
1126         struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1127         struct vmw_master *vmaster = vmw_master(file_priv->master);
1128         int ret;
1129
1130         /**
1131          * Make sure the master doesn't disappear while we have
1132          * it locked.
1133          */
1134
1135         vmw_fp->locked_master = drm_master_get(file_priv->master);
1136         ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
1137         if (unlikely((ret != 0))) {
1138                 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1139                 drm_master_put(&vmw_fp->locked_master);
1140         }
1141
1142         ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1143         vmw_execbuf_release_pinned_bo(dev_priv);
1144
1145         if (!dev_priv->enable_fb) {
1146                 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
1147                 if (unlikely(ret != 0))
1148                         DRM_ERROR("Unable to clean VRAM on master drop.\n");
1149                 vmw_kms_restore_vga(dev_priv);
1150                 vmw_3d_resource_dec(dev_priv, true);
1151                 mutex_lock(&dev_priv->hw_mutex);
1152                 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
1153                 mutex_unlock(&dev_priv->hw_mutex);
1154         }
1155
1156         dev_priv->active_master = &dev_priv->fbdev_master;
1157         ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1158         ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1159
1160         if (dev_priv->enable_fb)
1161                 vmw_fb_on(dev_priv);
1162 }
1163
1164
1165 static void vmw_remove(struct pci_dev *pdev)
1166 {
1167         struct drm_device *dev = pci_get_drvdata(pdev);
1168
1169         drm_put_dev(dev);
1170 }
1171
1172 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1173                               void *ptr)
1174 {
1175         struct vmw_private *dev_priv =
1176                 container_of(nb, struct vmw_private, pm_nb);
1177         struct vmw_master *vmaster = dev_priv->active_master;
1178
1179         switch (val) {
1180         case PM_HIBERNATION_PREPARE:
1181         case PM_SUSPEND_PREPARE:
1182                 ttm_suspend_lock(&vmaster->lock);
1183
1184                 /**
1185                  * This empties VRAM and unbinds all GMR bindings.
1186                  * Buffer contents is moved to swappable memory.
1187                  */
1188                 vmw_execbuf_release_pinned_bo(dev_priv);
1189                 vmw_resource_evict_all(dev_priv);
1190                 ttm_bo_swapout_all(&dev_priv->bdev);
1191
1192                 break;
1193         case PM_POST_HIBERNATION:
1194         case PM_POST_SUSPEND:
1195         case PM_POST_RESTORE:
1196                 ttm_suspend_unlock(&vmaster->lock);
1197
1198                 break;
1199         case PM_RESTORE_PREPARE:
1200                 break;
1201         default:
1202                 break;
1203         }
1204         return 0;
1205 }
1206
1207 /**
1208  * These might not be needed with the virtual SVGA device.
1209  */
1210
1211 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1212 {
1213         struct drm_device *dev = pci_get_drvdata(pdev);
1214         struct vmw_private *dev_priv = vmw_priv(dev);
1215
1216         if (dev_priv->num_3d_resources != 0) {
1217                 DRM_INFO("Can't suspend or hibernate "
1218                          "while 3D resources are active.\n");
1219                 return -EBUSY;
1220         }
1221
1222         pci_save_state(pdev);
1223         pci_disable_device(pdev);
1224         pci_set_power_state(pdev, PCI_D3hot);
1225         return 0;
1226 }
1227
1228 static int vmw_pci_resume(struct pci_dev *pdev)
1229 {
1230         pci_set_power_state(pdev, PCI_D0);
1231         pci_restore_state(pdev);
1232         return pci_enable_device(pdev);
1233 }
1234
1235 static int vmw_pm_suspend(struct device *kdev)
1236 {
1237         struct pci_dev *pdev = to_pci_dev(kdev);
1238         struct pm_message dummy;
1239
1240         dummy.event = 0;
1241
1242         return vmw_pci_suspend(pdev, dummy);
1243 }
1244
1245 static int vmw_pm_resume(struct device *kdev)
1246 {
1247         struct pci_dev *pdev = to_pci_dev(kdev);
1248
1249         return vmw_pci_resume(pdev);
1250 }
1251
1252 static int vmw_pm_prepare(struct device *kdev)
1253 {
1254         struct pci_dev *pdev = to_pci_dev(kdev);
1255         struct drm_device *dev = pci_get_drvdata(pdev);
1256         struct vmw_private *dev_priv = vmw_priv(dev);
1257
1258         /**
1259          * Release 3d reference held by fbdev and potentially
1260          * stop fifo.
1261          */
1262         dev_priv->suspended = true;
1263         if (dev_priv->enable_fb)
1264                         vmw_3d_resource_dec(dev_priv, true);
1265
1266         if (dev_priv->num_3d_resources != 0) {
1267
1268                 DRM_INFO("Can't suspend or hibernate "
1269                          "while 3D resources are active.\n");
1270
1271                 if (dev_priv->enable_fb)
1272                         vmw_3d_resource_inc(dev_priv, true);
1273                 dev_priv->suspended = false;
1274                 return -EBUSY;
1275         }
1276
1277         return 0;
1278 }
1279
1280 static void vmw_pm_complete(struct device *kdev)
1281 {
1282         struct pci_dev *pdev = to_pci_dev(kdev);
1283         struct drm_device *dev = pci_get_drvdata(pdev);
1284         struct vmw_private *dev_priv = vmw_priv(dev);
1285
1286         mutex_lock(&dev_priv->hw_mutex);
1287         vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1288         (void) vmw_read(dev_priv, SVGA_REG_ID);
1289         mutex_unlock(&dev_priv->hw_mutex);
1290
1291         /**
1292          * Reclaim 3d reference held by fbdev and potentially
1293          * start fifo.
1294          */
1295         if (dev_priv->enable_fb)
1296                         vmw_3d_resource_inc(dev_priv, false);
1297
1298         dev_priv->suspended = false;
1299 }
1300
1301 static const struct dev_pm_ops vmw_pm_ops = {
1302         .prepare = vmw_pm_prepare,
1303         .complete = vmw_pm_complete,
1304         .suspend = vmw_pm_suspend,
1305         .resume = vmw_pm_resume,
1306 };
1307
1308 static const struct file_operations vmwgfx_driver_fops = {
1309         .owner = THIS_MODULE,
1310         .open = drm_open,
1311         .release = drm_release,
1312         .unlocked_ioctl = vmw_unlocked_ioctl,
1313         .mmap = vmw_mmap,
1314         .poll = vmw_fops_poll,
1315         .read = vmw_fops_read,
1316 #if defined(CONFIG_COMPAT)
1317         .compat_ioctl = drm_compat_ioctl,
1318 #endif
1319         .llseek = noop_llseek,
1320 };
1321
1322 static struct drm_driver driver = {
1323         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1324         DRIVER_MODESET | DRIVER_PRIME,
1325         .load = vmw_driver_load,
1326         .unload = vmw_driver_unload,
1327         .lastclose = vmw_lastclose,
1328         .irq_preinstall = vmw_irq_preinstall,
1329         .irq_postinstall = vmw_irq_postinstall,
1330         .irq_uninstall = vmw_irq_uninstall,
1331         .irq_handler = vmw_irq_handler,
1332         .get_vblank_counter = vmw_get_vblank_counter,
1333         .enable_vblank = vmw_enable_vblank,
1334         .disable_vblank = vmw_disable_vblank,
1335         .ioctls = vmw_ioctls,
1336         .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
1337         .master_create = vmw_master_create,
1338         .master_destroy = vmw_master_destroy,
1339         .master_set = vmw_master_set,
1340         .master_drop = vmw_master_drop,
1341         .open = vmw_driver_open,
1342         .preclose = vmw_preclose,
1343         .postclose = vmw_postclose,
1344
1345         .dumb_create = vmw_dumb_create,
1346         .dumb_map_offset = vmw_dumb_map_offset,
1347         .dumb_destroy = vmw_dumb_destroy,
1348
1349         .prime_fd_to_handle = vmw_prime_fd_to_handle,
1350         .prime_handle_to_fd = vmw_prime_handle_to_fd,
1351
1352         .fops = &vmwgfx_driver_fops,
1353         .name = VMWGFX_DRIVER_NAME,
1354         .desc = VMWGFX_DRIVER_DESC,
1355         .date = VMWGFX_DRIVER_DATE,
1356         .major = VMWGFX_DRIVER_MAJOR,
1357         .minor = VMWGFX_DRIVER_MINOR,
1358         .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1359 };
1360
1361 static struct pci_driver vmw_pci_driver = {
1362         .name = VMWGFX_DRIVER_NAME,
1363         .id_table = vmw_pci_id_list,
1364         .probe = vmw_probe,
1365         .remove = vmw_remove,
1366         .driver = {
1367                 .pm = &vmw_pm_ops
1368         }
1369 };
1370
1371 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1372 {
1373         return drm_get_pci_dev(pdev, ent, &driver);
1374 }
1375
1376 static int __init vmwgfx_init(void)
1377 {
1378         int ret;
1379         ret = drm_pci_init(&driver, &vmw_pci_driver);
1380         if (ret)
1381                 DRM_ERROR("Failed initializing DRM.\n");
1382         return ret;
1383 }
1384
1385 static void __exit vmwgfx_exit(void)
1386 {
1387         drm_pci_exit(&driver, &vmw_pci_driver);
1388 }
1389
1390 module_init(vmwgfx_init);
1391 module_exit(vmwgfx_exit);
1392
1393 MODULE_AUTHOR("VMware Inc. and others");
1394 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1395 MODULE_LICENSE("GPL and additional rights");
1396 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1397                __stringify(VMWGFX_DRIVER_MINOR) "."
1398                __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1399                "0");