Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/si_blit_shaders.c

   1 /*
   2  * Copyright 2011 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *     Alex Deucher <alexander.deucher@amd.com>
  25  */
  26
  27 #include <linux/types.h>
  28 #include <linux/kernel.h>
  29
  30 const u32 si_default_state[] =
  31 {
  32         0xc0066900,
  33         0x00000000,
  34         0x00000060, /* DB_RENDER_CONTROL */
  35         0x00000000, /* DB_COUNT_CONTROL */
  36         0x00000000, /* DB_DEPTH_VIEW */
  37         0x0000002a, /* DB_RENDER_OVERRIDE */
  38         0x00000000, /* DB_RENDER_OVERRIDE2 */
  39         0x00000000, /* DB_HTILE_DATA_BASE */
  40
  41         0xc0046900,
  42         0x00000008,
  43         0x00000000, /* DB_DEPTH_BOUNDS_MIN */
  44         0x00000000, /* DB_DEPTH_BOUNDS_MAX */
  45         0x00000000, /* DB_STENCIL_CLEAR */
  46         0x00000000, /* DB_DEPTH_CLEAR */
  47
  48         0xc0036900,
  49         0x0000000f,
  50         0x00000000, /* DB_DEPTH_INFO */
  51         0x00000000, /* DB_Z_INFO */
  52         0x00000000, /* DB_STENCIL_INFO */
  53
  54         0xc0016900,
  55         0x00000080,
  56         0x00000000, /* PA_SC_WINDOW_OFFSET */
  57
  58         0xc00d6900,
  59         0x00000083,
  60         0x0000ffff, /* PA_SC_CLIPRECT_RULE */
  61         0x00000000, /* PA_SC_CLIPRECT_0_TL */
  62         0x20002000, /* PA_SC_CLIPRECT_0_BR */
  63         0x00000000,
  64         0x20002000,
  65         0x00000000,
  66         0x20002000,
  67         0x00000000,
  68         0x20002000,
  69         0xaaaaaaaa, /* PA_SC_EDGERULE */
  70         0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
  71         0x0000000f, /* CB_TARGET_MASK */
  72         0x0000000f, /* CB_SHADER_MASK */
  73
  74         0xc0226900,
  75         0x00000094,
  76         0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
  77         0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
  78         0x80000000,
  79         0x20002000,
  80         0x80000000,
  81         0x20002000,
  82         0x80000000,
  83         0x20002000,
  84         0x80000000,
  85         0x20002000,
  86         0x80000000,
  87         0x20002000,
  88         0x80000000,
  89         0x20002000,
  90         0x80000000,
  91         0x20002000,
  92         0x80000000,
  93         0x20002000,
  94         0x80000000,
  95         0x20002000,
  96         0x80000000,
  97         0x20002000,
  98         0x80000000,
  99         0x20002000,
 100         0x80000000,
 101         0x20002000,
 102         0x80000000,
 103         0x20002000,
 104         0x80000000,
 105         0x20002000,
 106         0x80000000,
 107         0x20002000,
 108         0x00000000, /* PA_SC_VPORT_ZMIN_0 */
 109         0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
 110
 111         0xc0026900,
 112         0x000000d9,
 113         0x00000000, /* CP_RINGID */
 114         0x00000000, /* CP_VMID */
 115
 116         0xc0046900,
 117         0x00000100,
 118         0xffffffff, /* VGT_MAX_VTX_INDX */
 119         0x00000000, /* VGT_MIN_VTX_INDX */
 120         0x00000000, /* VGT_INDX_OFFSET */
 121         0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
 122
 123         0xc0046900,
 124         0x00000105,
 125         0x00000000, /* CB_BLEND_RED */
 126         0x00000000, /* CB_BLEND_GREEN */
 127         0x00000000, /* CB_BLEND_BLUE */
 128         0x00000000, /* CB_BLEND_ALPHA */
 129
 130         0xc0016900,
 131         0x000001e0,
 132         0x00000000, /* CB_BLEND0_CONTROL */
 133
 134         0xc00e6900,
 135         0x00000200,
 136         0x00000000, /* DB_DEPTH_CONTROL */
 137         0x00000000, /* DB_EQAA */
 138         0x00cc0010, /* CB_COLOR_CONTROL */
 139         0x00000210, /* DB_SHADER_CONTROL */
 140         0x00010000, /* PA_CL_CLIP_CNTL */
 141         0x00000004, /* PA_SU_SC_MODE_CNTL */
 142         0x00000100, /* PA_CL_VTE_CNTL */
 143         0x00000000, /* PA_CL_VS_OUT_CNTL */
 144         0x00000000, /* PA_CL_NANINF_CNTL */
 145         0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
 146         0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
 147         0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
 148         0x00000000, /*  */
 149         0x00000000, /*  */
 150
 151         0xc0116900,
 152         0x00000280,
 153         0x00000000, /* PA_SU_POINT_SIZE */
 154         0x00000000, /* PA_SU_POINT_MINMAX */
 155         0x00000008, /* PA_SU_LINE_CNTL */
 156         0x00000000, /* PA_SC_LINE_STIPPLE */
 157         0x00000000, /* VGT_OUTPUT_PATH_CNTL */
 158         0x00000000, /* VGT_HOS_CNTL */
 159         0x00000000,
 160         0x00000000,
 161         0x00000000,
 162         0x00000000,
 163         0x00000000,
 164         0x00000000,
 165         0x00000000,
 166         0x00000000,
 167         0x00000000,
 168         0x00000000,
 169         0x00000000, /* VGT_GS_MODE */
 170
 171         0xc0026900,
 172         0x00000292,
 173         0x00000000, /* PA_SC_MODE_CNTL_0 */
 174         0x00000000, /* PA_SC_MODE_CNTL_1 */
 175
 176         0xc0016900,
 177         0x000002a1,
 178         0x00000000, /* VGT_PRIMITIVEID_EN */
 179
 180         0xc0016900,
 181         0x000002a5,
 182         0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
 183
 184         0xc0026900,
 185         0x000002a8,
 186         0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
 187         0x00000000,
 188
 189         0xc0026900,
 190         0x000002ad,
 191         0x00000000, /* VGT_REUSE_OFF */
 192         0x00000000,
 193
 194         0xc0016900,
 195         0x000002d5,
 196         0x00000000, /* VGT_SHADER_STAGES_EN */
 197
 198         0xc0016900,
 199         0x000002dc,
 200         0x0000aa00, /* DB_ALPHA_TO_MASK */
 201
 202         0xc0066900,
 203         0x000002de,
 204         0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
 205         0x00000000,
 206         0x00000000,
 207         0x00000000,
 208         0x00000000,
 209         0x00000000,
 210
 211         0xc0026900,
 212         0x000002e5,
 213         0x00000000, /* VGT_STRMOUT_CONFIG */
 214         0x00000000,
 215
 216         0xc01b6900,
 217         0x000002f5,
 218         0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */
 219         0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */
 220         0x00000000, /* PA_SC_LINE_CNTL */
 221         0x00000000, /* PA_SC_AA_CONFIG */
 222         0x00000005, /* PA_SU_VTX_CNTL */
 223         0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
 224         0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
 225         0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
 226         0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
 227         0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
 228         0x00000000,
 229         0x00000000,
 230         0x00000000,
 231         0x00000000,
 232         0x00000000,
 233         0x00000000,
 234         0x00000000,
 235         0x00000000,
 236         0x00000000,
 237         0x00000000,
 238         0x00000000,
 239         0x00000000,
 240         0x00000000,
 241         0x00000000,
 242         0x00000000,
 243         0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */
 244         0xffffffff,
 245
 246         0xc0026900,
 247         0x00000316,
 248         0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
 249         0x00000010, /*  */
 250 };
 251
 252 const u32 si_default_size = ARRAY_SIZE(si_default_state);