Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/rv770.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/firmware.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include "radeon_drm.h"
  35 #include "rv770d.h"
  36 #include "atom.h"
  37 #include "avivod.h"
  38
  39 #define R700_PFP_UCODE_SIZE 848
  40 #define R700_PM4_UCODE_SIZE 1360
  41
  42 static void rv770_gpu_init(struct radeon_device *rdev);
  43 void rv770_fini(struct radeon_device *rdev);
  44
  45 u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  46 {
  47         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  48         u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
  49
  50         /* Lock the graphics update lock */
  51         tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
  52         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  53
  54         /* update the scanout addresses */
  55         if (radeon_crtc->crtc_id) {
  56                 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  57                 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  58         } else {
  59                 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  60                 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
  61         }
  62         WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  63                (u32)crtc_base);
  64         WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  65                (u32)crtc_base);
  66
  67         /* Wait for update_pending to go high. */
  68         while (!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING));
  69         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
  70
  71         /* Unlock the lock, so double-buffering can take place inside vblank */
  72         tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
  73         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  74
  75         /* Return current update_pending status: */
  76         return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
  77 }
  78
  79 /* get temperature in millidegrees */
  80 u32 rv770_get_temp(struct radeon_device *rdev)
  81 {
  82         u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
  83                 ASIC_T_SHIFT;
  84         u32 actual_temp = 0;
  85
  86         if ((temp >> 9) & 1)
  87                 actual_temp = 0;
  88         else
  89                 actual_temp = (temp >> 1) & 0xff;
  90
  91         return actual_temp * 1000;
  92 }
  93
  94 void rv770_pm_misc(struct radeon_device *rdev)
  95 {
  96         int req_ps_idx = rdev->pm.requested_power_state_index;
  97         int req_cm_idx = rdev->pm.requested_clock_mode_index;
  98         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
  99         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 100
 101         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 102                 if (voltage->voltage != rdev->pm.current_vddc) {
 103                         radeon_atom_set_voltage(rdev, voltage->voltage);
 104                         rdev->pm.current_vddc = voltage->voltage;
 105                         DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
 106                 }
 107         }
 108 }
 109
 110 /*
 111  * GART
 112  */
 113 int rv770_pcie_gart_enable(struct radeon_device *rdev)
 114 {
 115         u32 tmp;
 116         int r, i;
 117
 118         if (rdev->gart.table.vram.robj == NULL) {
 119                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 120                 return -EINVAL;
 121         }
 122         r = radeon_gart_table_vram_pin(rdev);
 123         if (r)
 124                 return r;
 125         radeon_gart_restore(rdev);
 126         /* Setup L2 cache */
 127         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 128                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 129                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 130         WREG32(VM_L2_CNTL2, 0);
 131         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 132         /* Setup TLB control */
 133         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 134                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 135                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 136                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 137         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 138         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 139         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 140         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 141         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 142         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 143         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 144         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 145         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 146         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 147         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 148                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 149         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 150                         (u32)(rdev->dummy_page.addr >> 12));
 151         for (i = 1; i < 7; i++)
 152                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 153
 154         r600_pcie_gart_tlb_flush(rdev);
 155         rdev->gart.ready = true;
 156         return 0;
 157 }
 158
 159 void rv770_pcie_gart_disable(struct radeon_device *rdev)
 160 {
 161         u32 tmp;
 162         int i, r;
 163
 164         /* Disable all tables */
 165         for (i = 0; i < 7; i++)
 166                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 167
 168         /* Setup L2 cache */
 169         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 170                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 171         WREG32(VM_L2_CNTL2, 0);
 172         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 173         /* Setup TLB control */
 174         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 175         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 176         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 177         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 178         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 179         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 180         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 181         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 182         if (rdev->gart.table.vram.robj) {
 183                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 184                 if (likely(r == 0)) {
 185                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 186                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 187                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 188                 }
 189         }
 190 }
 191
 192 void rv770_pcie_gart_fini(struct radeon_device *rdev)
 193 {
 194         radeon_gart_fini(rdev);
 195         rv770_pcie_gart_disable(rdev);
 196         radeon_gart_table_vram_free(rdev);
 197 }
 198
 199
 200 void rv770_agp_enable(struct radeon_device *rdev)
 201 {
 202         u32 tmp;
 203         int i;
 204
 205         /* Setup L2 cache */
 206         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 207                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 208                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 209         WREG32(VM_L2_CNTL2, 0);
 210         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 211         /* Setup TLB control */
 212         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 213                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 214                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 215                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 216         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 217         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 218         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 219         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 220         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 221         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 222         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 223         for (i = 0; i < 7; i++)
 224                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 225 }
 226
 227 static void rv770_mc_program(struct radeon_device *rdev)
 228 {
 229         struct rv515_mc_save save;
 230         u32 tmp;
 231         int i, j;
 232
 233         /* Initialize HDP */
 234         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 235                 WREG32((0x2c14 + j), 0x00000000);
 236                 WREG32((0x2c18 + j), 0x00000000);
 237                 WREG32((0x2c1c + j), 0x00000000);
 238                 WREG32((0x2c20 + j), 0x00000000);
 239                 WREG32((0x2c24 + j), 0x00000000);
 240         }
 241         /* r7xx hw bug.  Read from HDP_DEBUG1 rather
 242          * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
 243          */
 244         tmp = RREG32(HDP_DEBUG1);
 245
 246         rv515_mc_stop(rdev, &save);
 247         if (r600_mc_wait_for_idle(rdev)) {
 248                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 249         }
 250         /* Lockout access through VGA aperture*/
 251         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 252         /* Update configuration */
 253         if (rdev->flags & RADEON_IS_AGP) {
 254                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 255                         /* VRAM before AGP */
 256                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 257                                 rdev->mc.vram_start >> 12);
 258                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 259                                 rdev->mc.gtt_end >> 12);
 260                 } else {
 261                         /* VRAM after AGP */
 262                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 263                                 rdev->mc.gtt_start >> 12);
 264                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 265                                 rdev->mc.vram_end >> 12);
 266                 }
 267         } else {
 268                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 269                         rdev->mc.vram_start >> 12);
 270                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 271                         rdev->mc.vram_end >> 12);
 272         }
 273         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 274         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 275         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 276         WREG32(MC_VM_FB_LOCATION, tmp);
 277         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 278         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 279         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
 280         if (rdev->flags & RADEON_IS_AGP) {
 281                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
 282                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
 283                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 284         } else {
 285                 WREG32(MC_VM_AGP_BASE, 0);
 286                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 287                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 288         }
 289         if (r600_mc_wait_for_idle(rdev)) {
 290                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 291         }
 292         rv515_mc_resume(rdev, &save);
 293         /* we need to own VRAM, so turn off the VGA renderer here
 294          * to stop it overwriting our objects */
 295         rv515_vga_render_disable(rdev);
 296 }
 297
 298
 299 /*
 300  * CP.
 301  */
 302 void r700_cp_stop(struct radeon_device *rdev)
 303 {
 304         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
 305         WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
 306         WREG32(SCRATCH_UMSK, 0);
 307 }
 308
 309 static int rv770_cp_load_microcode(struct radeon_device *rdev)
 310 {
 311         const __be32 *fw_data;
 312         int i;
 313
 314         if (!rdev->me_fw || !rdev->pfp_fw)
 315                 return -EINVAL;
 316
 317         r700_cp_stop(rdev);
 318         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
 319
 320         /* Reset cp */
 321         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
 322         RREG32(GRBM_SOFT_RESET);
 323         mdelay(15);
 324         WREG32(GRBM_SOFT_RESET, 0);
 325
 326         fw_data = (const __be32 *)rdev->pfp_fw->data;
 327         WREG32(CP_PFP_UCODE_ADDR, 0);
 328         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
 329                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
 330         WREG32(CP_PFP_UCODE_ADDR, 0);
 331
 332         fw_data = (const __be32 *)rdev->me_fw->data;
 333         WREG32(CP_ME_RAM_WADDR, 0);
 334         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
 335                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
 336
 337         WREG32(CP_PFP_UCODE_ADDR, 0);
 338         WREG32(CP_ME_RAM_WADDR, 0);
 339         WREG32(CP_ME_RAM_RADDR, 0);
 340         return 0;
 341 }
 342
 343 void r700_cp_fini(struct radeon_device *rdev)
 344 {
 345         r700_cp_stop(rdev);
 346         radeon_ring_fini(rdev);
 347 }
 348
 349 /*
 350  * Core functions
 351  */
 352 static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
 353                                              u32 num_tile_pipes,
 354                                              u32 num_backends,
 355                                              u32 backend_disable_mask)
 356 {
 357         u32 backend_map = 0;
 358         u32 enabled_backends_mask;
 359         u32 enabled_backends_count;
 360         u32 cur_pipe;
 361         u32 swizzle_pipe[R7XX_MAX_PIPES];
 362         u32 cur_backend;
 363         u32 i;
 364         bool force_no_swizzle;
 365
 366         if (num_tile_pipes > R7XX_MAX_PIPES)
 367                 num_tile_pipes = R7XX_MAX_PIPES;
 368         if (num_tile_pipes < 1)
 369                 num_tile_pipes = 1;
 370         if (num_backends > R7XX_MAX_BACKENDS)
 371                 num_backends = R7XX_MAX_BACKENDS;
 372         if (num_backends < 1)
 373                 num_backends = 1;
 374
 375         enabled_backends_mask = 0;
 376         enabled_backends_count = 0;
 377         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
 378                 if (((backend_disable_mask >> i) & 1) == 0) {
 379                         enabled_backends_mask |= (1 << i);
 380                         ++enabled_backends_count;
 381                 }
 382                 if (enabled_backends_count == num_backends)
 383                         break;
 384         }
 385
 386         if (enabled_backends_count == 0) {
 387                 enabled_backends_mask = 1;
 388                 enabled_backends_count = 1;
 389         }
 390
 391         if (enabled_backends_count != num_backends)
 392                 num_backends = enabled_backends_count;
 393
 394         switch (rdev->family) {
 395         case CHIP_RV770:
 396         case CHIP_RV730:
 397                 force_no_swizzle = false;
 398                 break;
 399         case CHIP_RV710:
 400         case CHIP_RV740:
 401         default:
 402                 force_no_swizzle = true;
 403                 break;
 404         }
 405
 406         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
 407         switch (num_tile_pipes) {
 408         case 1:
 409                 swizzle_pipe[0] = 0;
 410                 break;
 411         case 2:
 412                 swizzle_pipe[0] = 0;
 413                 swizzle_pipe[1] = 1;
 414                 break;
 415         case 3:
 416                 if (force_no_swizzle) {
 417                         swizzle_pipe[0] = 0;
 418                         swizzle_pipe[1] = 1;
 419                         swizzle_pipe[2] = 2;
 420                 } else {
 421                         swizzle_pipe[0] = 0;
 422                         swizzle_pipe[1] = 2;
 423                         swizzle_pipe[2] = 1;
 424                 }
 425                 break;
 426         case 4:
 427                 if (force_no_swizzle) {
 428                         swizzle_pipe[0] = 0;
 429                         swizzle_pipe[1] = 1;
 430                         swizzle_pipe[2] = 2;
 431                         swizzle_pipe[3] = 3;
 432                 } else {
 433                         swizzle_pipe[0] = 0;
 434                         swizzle_pipe[1] = 2;
 435                         swizzle_pipe[2] = 3;
 436                         swizzle_pipe[3] = 1;
 437                 }
 438                 break;
 439         case 5:
 440                 if (force_no_swizzle) {
 441                         swizzle_pipe[0] = 0;
 442                         swizzle_pipe[1] = 1;
 443                         swizzle_pipe[2] = 2;
 444                         swizzle_pipe[3] = 3;
 445                         swizzle_pipe[4] = 4;
 446                 } else {
 447                         swizzle_pipe[0] = 0;
 448                         swizzle_pipe[1] = 2;
 449                         swizzle_pipe[2] = 4;
 450                         swizzle_pipe[3] = 1;
 451                         swizzle_pipe[4] = 3;
 452                 }
 453                 break;
 454         case 6:
 455                 if (force_no_swizzle) {
 456                         swizzle_pipe[0] = 0;
 457                         swizzle_pipe[1] = 1;
 458                         swizzle_pipe[2] = 2;
 459                         swizzle_pipe[3] = 3;
 460                         swizzle_pipe[4] = 4;
 461                         swizzle_pipe[5] = 5;
 462                 } else {
 463                         swizzle_pipe[0] = 0;
 464                         swizzle_pipe[1] = 2;
 465                         swizzle_pipe[2] = 4;
 466                         swizzle_pipe[3] = 5;
 467                         swizzle_pipe[4] = 3;
 468                         swizzle_pipe[5] = 1;
 469                 }
 470                 break;
 471         case 7:
 472                 if (force_no_swizzle) {
 473                         swizzle_pipe[0] = 0;
 474                         swizzle_pipe[1] = 1;
 475                         swizzle_pipe[2] = 2;
 476                         swizzle_pipe[3] = 3;
 477                         swizzle_pipe[4] = 4;
 478                         swizzle_pipe[5] = 5;
 479                         swizzle_pipe[6] = 6;
 480                 } else {
 481                         swizzle_pipe[0] = 0;
 482                         swizzle_pipe[1] = 2;
 483                         swizzle_pipe[2] = 4;
 484                         swizzle_pipe[3] = 6;
 485                         swizzle_pipe[4] = 3;
 486                         swizzle_pipe[5] = 1;
 487                         swizzle_pipe[6] = 5;
 488                 }
 489                 break;
 490         case 8:
 491                 if (force_no_swizzle) {
 492                         swizzle_pipe[0] = 0;
 493                         swizzle_pipe[1] = 1;
 494                         swizzle_pipe[2] = 2;
 495                         swizzle_pipe[3] = 3;
 496                         swizzle_pipe[4] = 4;
 497                         swizzle_pipe[5] = 5;
 498                         swizzle_pipe[6] = 6;
 499                         swizzle_pipe[7] = 7;
 500                 } else {
 501                         swizzle_pipe[0] = 0;
 502                         swizzle_pipe[1] = 2;
 503                         swizzle_pipe[2] = 4;
 504                         swizzle_pipe[3] = 6;
 505                         swizzle_pipe[4] = 3;
 506                         swizzle_pipe[5] = 1;
 507                         swizzle_pipe[6] = 7;
 508                         swizzle_pipe[7] = 5;
 509                 }
 510                 break;
 511         }
 512
 513         cur_backend = 0;
 514         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 515                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 516                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 517
 518                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 519
 520                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 521         }
 522
 523         return backend_map;
 524 }
 525
 526 static void rv770_program_channel_remap(struct radeon_device *rdev)
 527 {
 528         u32 tcp_chan_steer, mc_shared_chremap, tmp;
 529         bool force_no_swizzle;
 530
 531         switch (rdev->family) {
 532         case CHIP_RV770:
 533         case CHIP_RV730:
 534                 force_no_swizzle = false;
 535                 break;
 536         case CHIP_RV710:
 537         case CHIP_RV740:
 538         default:
 539                 force_no_swizzle = true;
 540                 break;
 541         }
 542
 543         tmp = RREG32(MC_SHARED_CHMAP);
 544         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 545         case 0:
 546         case 1:
 547         default:
 548                 /* default mapping */
 549                 mc_shared_chremap = 0x00fac688;
 550                 break;
 551         case 2:
 552         case 3:
 553                 if (force_no_swizzle)
 554                         mc_shared_chremap = 0x00fac688;
 555                 else
 556                         mc_shared_chremap = 0x00bbc298;
 557                 break;
 558         }
 559
 560         if (rdev->family == CHIP_RV740)
 561                 tcp_chan_steer = 0x00ef2a60;
 562         else
 563                 tcp_chan_steer = 0x00fac688;
 564
 565         WREG32(TCP_CHAN_STEER, tcp_chan_steer);
 566         WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
 567 }
 568
 569 static void rv770_gpu_init(struct radeon_device *rdev)
 570 {
 571         int i, j, num_qd_pipes;
 572         u32 ta_aux_cntl;
 573         u32 sx_debug_1;
 574         u32 smx_dc_ctl0;
 575         u32 db_debug3;
 576         u32 num_gs_verts_per_thread;
 577         u32 vgt_gs_per_es;
 578         u32 gs_prim_buffer_depth = 0;
 579         u32 sq_ms_fifo_sizes;
 580         u32 sq_config;
 581         u32 sq_thread_resource_mgmt;
 582         u32 hdp_host_path_cntl;
 583         u32 sq_dyn_gpr_size_simd_ab_0;
 584         u32 backend_map;
 585         u32 gb_tiling_config = 0;
 586         u32 cc_rb_backend_disable = 0;
 587         u32 cc_gc_shader_pipe_config = 0;
 588         u32 mc_arb_ramcfg;
 589         u32 db_debug4;
 590
 591         /* setup chip specs */
 592         switch (rdev->family) {
 593         case CHIP_RV770:
 594                 rdev->config.rv770.max_pipes = 4;
 595                 rdev->config.rv770.max_tile_pipes = 8;
 596                 rdev->config.rv770.max_simds = 10;
 597                 rdev->config.rv770.max_backends = 4;
 598                 rdev->config.rv770.max_gprs = 256;
 599                 rdev->config.rv770.max_threads = 248;
 600                 rdev->config.rv770.max_stack_entries = 512;
 601                 rdev->config.rv770.max_hw_contexts = 8;
 602                 rdev->config.rv770.max_gs_threads = 16 * 2;
 603                 rdev->config.rv770.sx_max_export_size = 128;
 604                 rdev->config.rv770.sx_max_export_pos_size = 16;
 605                 rdev->config.rv770.sx_max_export_smx_size = 112;
 606                 rdev->config.rv770.sq_num_cf_insts = 2;
 607
 608                 rdev->config.rv770.sx_num_of_sets = 7;
 609                 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
 610                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 611                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 612                 break;
 613         case CHIP_RV730:
 614                 rdev->config.rv770.max_pipes = 2;
 615                 rdev->config.rv770.max_tile_pipes = 4;
 616                 rdev->config.rv770.max_simds = 8;
 617                 rdev->config.rv770.max_backends = 2;
 618                 rdev->config.rv770.max_gprs = 128;
 619                 rdev->config.rv770.max_threads = 248;
 620                 rdev->config.rv770.max_stack_entries = 256;
 621                 rdev->config.rv770.max_hw_contexts = 8;
 622                 rdev->config.rv770.max_gs_threads = 16 * 2;
 623                 rdev->config.rv770.sx_max_export_size = 256;
 624                 rdev->config.rv770.sx_max_export_pos_size = 32;
 625                 rdev->config.rv770.sx_max_export_smx_size = 224;
 626                 rdev->config.rv770.sq_num_cf_insts = 2;
 627
 628                 rdev->config.rv770.sx_num_of_sets = 7;
 629                 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
 630                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 631                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 632                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 633                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 634                         rdev->config.rv770.sx_max_export_smx_size += 16;
 635                 }
 636                 break;
 637         case CHIP_RV710:
 638                 rdev->config.rv770.max_pipes = 2;
 639                 rdev->config.rv770.max_tile_pipes = 2;
 640                 rdev->config.rv770.max_simds = 2;
 641                 rdev->config.rv770.max_backends = 1;
 642                 rdev->config.rv770.max_gprs = 256;
 643                 rdev->config.rv770.max_threads = 192;
 644                 rdev->config.rv770.max_stack_entries = 256;
 645                 rdev->config.rv770.max_hw_contexts = 4;
 646                 rdev->config.rv770.max_gs_threads = 8 * 2;
 647                 rdev->config.rv770.sx_max_export_size = 128;
 648                 rdev->config.rv770.sx_max_export_pos_size = 16;
 649                 rdev->config.rv770.sx_max_export_smx_size = 112;
 650                 rdev->config.rv770.sq_num_cf_insts = 1;
 651
 652                 rdev->config.rv770.sx_num_of_sets = 7;
 653                 rdev->config.rv770.sc_prim_fifo_size = 0x40;
 654                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 655                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 656                 break;
 657         case CHIP_RV740:
 658                 rdev->config.rv770.max_pipes = 4;
 659                 rdev->config.rv770.max_tile_pipes = 4;
 660                 rdev->config.rv770.max_simds = 8;
 661                 rdev->config.rv770.max_backends = 4;
 662                 rdev->config.rv770.max_gprs = 256;
 663                 rdev->config.rv770.max_threads = 248;
 664                 rdev->config.rv770.max_stack_entries = 512;
 665                 rdev->config.rv770.max_hw_contexts = 8;
 666                 rdev->config.rv770.max_gs_threads = 16 * 2;
 667                 rdev->config.rv770.sx_max_export_size = 256;
 668                 rdev->config.rv770.sx_max_export_pos_size = 32;
 669                 rdev->config.rv770.sx_max_export_smx_size = 224;
 670                 rdev->config.rv770.sq_num_cf_insts = 2;
 671
 672                 rdev->config.rv770.sx_num_of_sets = 7;
 673                 rdev->config.rv770.sc_prim_fifo_size = 0x100;
 674                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 675                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 676
 677                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 678                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 679                         rdev->config.rv770.sx_max_export_smx_size += 16;
 680                 }
 681                 break;
 682         default:
 683                 break;
 684         }
 685
 686         /* Initialize HDP */
 687         j = 0;
 688         for (i = 0; i < 32; i++) {
 689                 WREG32((0x2c14 + j), 0x00000000);
 690                 WREG32((0x2c18 + j), 0x00000000);
 691                 WREG32((0x2c1c + j), 0x00000000);
 692                 WREG32((0x2c20 + j), 0x00000000);
 693                 WREG32((0x2c24 + j), 0x00000000);
 694                 j += 0x18;
 695         }
 696
 697         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 698
 699         /* setup tiling, simd, pipe config */
 700         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 701
 702         switch (rdev->config.rv770.max_tile_pipes) {
 703         case 1:
 704         default:
 705                 gb_tiling_config |= PIPE_TILING(0);
 706                 break;
 707         case 2:
 708                 gb_tiling_config |= PIPE_TILING(1);
 709                 break;
 710         case 4:
 711                 gb_tiling_config |= PIPE_TILING(2);
 712                 break;
 713         case 8:
 714                 gb_tiling_config |= PIPE_TILING(3);
 715                 break;
 716         }
 717         rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
 718
 719         if (rdev->family == CHIP_RV770)
 720                 gb_tiling_config |= BANK_TILING(1);
 721         else
 722                 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
 723         rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
 724         gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
 725         if ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
 726                 rdev->config.rv770.tiling_group_size = 512;
 727         else
 728                 rdev->config.rv770.tiling_group_size = 256;
 729         if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
 730                 gb_tiling_config |= ROW_TILING(3);
 731                 gb_tiling_config |= SAMPLE_SPLIT(3);
 732         } else {
 733                 gb_tiling_config |=
 734                         ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 735                 gb_tiling_config |=
 736                         SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 737         }
 738
 739         gb_tiling_config |= BANK_SWAPS(1);
 740
 741         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
 742         cc_rb_backend_disable |=
 743                 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
 744
 745         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
 746         cc_gc_shader_pipe_config |=
 747                 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
 748         cc_gc_shader_pipe_config |=
 749                 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
 750
 751         if (rdev->family == CHIP_RV740)
 752                 backend_map = 0x28;
 753         else
 754                 backend_map = r700_get_tile_pipe_to_backend_map(rdev,
 755                                                                 rdev->config.rv770.max_tile_pipes,
 756                                                                 (R7XX_MAX_BACKENDS -
 757                                                                  r600_count_pipe_bits((cc_rb_backend_disable &
 758                                                                                        R7XX_MAX_BACKENDS_MASK) >> 16)),
 759                                                                 (cc_rb_backend_disable >> 16));
 760
 761         rdev->config.rv770.tile_config = gb_tiling_config;
 762         gb_tiling_config |= BACKEND_MAP(backend_map);
 763
 764         WREG32(GB_TILING_CONFIG, gb_tiling_config);
 765         WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 766         WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 767
 768         rv770_program_channel_remap(rdev);
 769
 770         WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
 771         WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
 772         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 773         WREG32(CC_SYS_RB_BACKEND_DISABLE,  cc_rb_backend_disable);
 774
 775         WREG32(CGTS_SYS_TCC_DISABLE, 0);
 776         WREG32(CGTS_TCC_DISABLE, 0);
 777         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
 778         WREG32(CGTS_USER_TCC_DISABLE, 0);
 779
 780         num_qd_pipes =
 781                 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
 782         WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
 783         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
 784
 785         /* set HW defaults for 3D engine */
 786         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
 787                                      ROQ_IB2_START(0x2b)));
 788
 789         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
 790
 791         ta_aux_cntl = RREG32(TA_CNTL_AUX);
 792         WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
 793
 794         sx_debug_1 = RREG32(SX_DEBUG_1);
 795         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
 796         WREG32(SX_DEBUG_1, sx_debug_1);
 797
 798         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
 799         smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
 800         smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
 801         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 802
 803         if (rdev->family != CHIP_RV740)
 804                 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
 805                                        GS_FLUSH_CTL(4) |
 806                                        ACK_FLUSH_CTL(3) |
 807                                        SYNC_FLUSH_CTL));
 808
 809         db_debug3 = RREG32(DB_DEBUG3);
 810         db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
 811         switch (rdev->family) {
 812         case CHIP_RV770:
 813         case CHIP_RV740:
 814                 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
 815                 break;
 816         case CHIP_RV710:
 817         case CHIP_RV730:
 818         default:
 819                 db_debug3 |= DB_CLK_OFF_DELAY(2);
 820                 break;
 821         }
 822         WREG32(DB_DEBUG3, db_debug3);
 823
 824         if (rdev->family != CHIP_RV770) {
 825                 db_debug4 = RREG32(DB_DEBUG4);
 826                 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
 827                 WREG32(DB_DEBUG4, db_debug4);
 828         }
 829
 830         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
 831                                         POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
 832                                         SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
 833
 834         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
 835                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
 836                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
 837
 838         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 839
 840         WREG32(VGT_NUM_INSTANCES, 1);
 841
 842         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
 843
 844         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
 845
 846         WREG32(CP_PERFMON_CNTL, 0);
 847
 848         sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
 849                             DONE_FIFO_HIWATER(0xe0) |
 850                             ALU_UPDATE_FIFO_HIWATER(0x8));
 851         switch (rdev->family) {
 852         case CHIP_RV770:
 853         case CHIP_RV730:
 854         case CHIP_RV710:
 855                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
 856                 break;
 857         case CHIP_RV740:
 858         default:
 859                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
 860                 break;
 861         }
 862         WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
 863
 864         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 865          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 866          */
 867         sq_config = RREG32(SQ_CONFIG);
 868         sq_config &= ~(PS_PRIO(3) |
 869                        VS_PRIO(3) |
 870                        GS_PRIO(3) |
 871                        ES_PRIO(3));
 872         sq_config |= (DX9_CONSTS |
 873                       VC_ENABLE |
 874                       EXPORT_SRC_C |
 875                       PS_PRIO(0) |
 876                       VS_PRIO(1) |
 877                       GS_PRIO(2) |
 878                       ES_PRIO(3));
 879         if (rdev->family == CHIP_RV710)
 880                 /* no vertex cache */
 881                 sq_config &= ~VC_ENABLE;
 882
 883         WREG32(SQ_CONFIG, sq_config);
 884
 885         WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 886                                          NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 887                                          NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
 888
 889         WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
 890                                          NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
 891
 892         sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
 893                                    NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
 894                                    NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
 895         if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
 896                 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
 897         else
 898                 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
 899         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 900
 901         WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 902                                                      NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 903
 904         WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 905                                                      NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 906
 907         sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 908                                      SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
 909                                      SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 910                                      SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
 911
 912         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
 913         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
 914         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
 915         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
 916         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
 917         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
 918         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
 919         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
 920
 921         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 922                                           FORCE_EOV_MAX_REZ_CNT(255)));
 923
 924         if (rdev->family == CHIP_RV710)
 925                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
 926                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 927         else
 928                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
 929                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 930
 931         switch (rdev->family) {
 932         case CHIP_RV770:
 933         case CHIP_RV730:
 934         case CHIP_RV740:
 935                 gs_prim_buffer_depth = 384;
 936                 break;
 937         case CHIP_RV710:
 938                 gs_prim_buffer_depth = 128;
 939                 break;
 940         default:
 941                 break;
 942         }
 943
 944         num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
 945         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
 946         /* Max value for this is 256 */
 947         if (vgt_gs_per_es > 256)
 948                 vgt_gs_per_es = 256;
 949
 950         WREG32(VGT_ES_PER_GS, 128);
 951         WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
 952         WREG32(VGT_GS_PER_VS, 2);
 953
 954         /* more default values. 2D/3D driver should adjust as needed */
 955         WREG32(VGT_GS_VERTEX_REUSE, 16);
 956         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 957         WREG32(VGT_STRMOUT_EN, 0);
 958         WREG32(SX_MISC, 0);
 959         WREG32(PA_SC_MODE_CNTL, 0);
 960         WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
 961         WREG32(PA_SC_AA_CONFIG, 0);
 962         WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
 963         WREG32(PA_SC_LINE_STIPPLE, 0);
 964         WREG32(SPI_INPUT_Z, 0);
 965         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
 966         WREG32(CB_COLOR7_FRAG, 0);
 967
 968         /* clear render buffer base addresses */
 969         WREG32(CB_COLOR0_BASE, 0);
 970         WREG32(CB_COLOR1_BASE, 0);
 971         WREG32(CB_COLOR2_BASE, 0);
 972         WREG32(CB_COLOR3_BASE, 0);
 973         WREG32(CB_COLOR4_BASE, 0);
 974         WREG32(CB_COLOR5_BASE, 0);
 975         WREG32(CB_COLOR6_BASE, 0);
 976         WREG32(CB_COLOR7_BASE, 0);
 977
 978         WREG32(TCP_CNTL, 0);
 979
 980         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
 981         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 982
 983         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 984
 985         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
 986                                           NUM_CLIP_SEQ(3)));
 987
 988 }
 989
 990 static int rv770_vram_scratch_init(struct radeon_device *rdev)
 991 {
 992         int r;
 993         u64 gpu_addr;
 994
 995         if (rdev->vram_scratch.robj == NULL) {
 996                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,
 997                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
 998                                      &rdev->vram_scratch.robj);
 999                 if (r) {
1000                         return r;
1001                 }
1002         }
1003
1004         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1005         if (unlikely(r != 0))
1006                 return r;
1007         r = radeon_bo_pin(rdev->vram_scratch.robj,
1008                           RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
1009         if (r) {
1010                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1011                 return r;
1012         }
1013         r = radeon_bo_kmap(rdev->vram_scratch.robj,
1014                                 (void **)&rdev->vram_scratch.ptr);
1015         if (r)
1016                 radeon_bo_unpin(rdev->vram_scratch.robj);
1017         radeon_bo_unreserve(rdev->vram_scratch.robj);
1018
1019         return r;
1020 }
1021
1022 static void rv770_vram_scratch_fini(struct radeon_device *rdev)
1023 {
1024         int r;
1025
1026         if (rdev->vram_scratch.robj == NULL) {
1027                 return;
1028         }
1029         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1030         if (likely(r == 0)) {
1031                 radeon_bo_kunmap(rdev->vram_scratch.robj);
1032                 radeon_bo_unpin(rdev->vram_scratch.robj);
1033                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1034         }
1035         radeon_bo_unref(&rdev->vram_scratch.robj);
1036 }
1037
1038 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1039 {
1040         u64 size_bf, size_af;
1041
1042         if (mc->mc_vram_size > 0xE0000000) {
1043                 /* leave room for at least 512M GTT */
1044                 dev_warn(rdev->dev, "limiting VRAM\n");
1045                 mc->real_vram_size = 0xE0000000;
1046                 mc->mc_vram_size = 0xE0000000;
1047         }
1048         if (rdev->flags & RADEON_IS_AGP) {
1049                 size_bf = mc->gtt_start;
1050                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1051                 if (size_bf > size_af) {
1052                         if (mc->mc_vram_size > size_bf) {
1053                                 dev_warn(rdev->dev, "limiting VRAM\n");
1054                                 mc->real_vram_size = size_bf;
1055                                 mc->mc_vram_size = size_bf;
1056                         }
1057                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1058                 } else {
1059                         if (mc->mc_vram_size > size_af) {
1060                                 dev_warn(rdev->dev, "limiting VRAM\n");
1061                                 mc->real_vram_size = size_af;
1062                                 mc->mc_vram_size = size_af;
1063                         }
1064                         mc->vram_start = mc->gtt_end;
1065                 }
1066                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1067                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1068                                 mc->mc_vram_size >> 20, mc->vram_start,
1069                                 mc->vram_end, mc->real_vram_size >> 20);
1070         } else {
1071                 radeon_vram_location(rdev, &rdev->mc, 0);
1072                 rdev->mc.gtt_base_align = 0;
1073                 radeon_gtt_location(rdev, mc);
1074         }
1075 }
1076
1077 int rv770_mc_init(struct radeon_device *rdev)
1078 {
1079         u32 tmp;
1080         int chansize, numchan;
1081
1082         /* Get VRAM informations */
1083         rdev->mc.vram_is_ddr = true;
1084         tmp = RREG32(MC_ARB_RAMCFG);
1085         if (tmp & CHANSIZE_OVERRIDE) {
1086                 chansize = 16;
1087         } else if (tmp & CHANSIZE_MASK) {
1088                 chansize = 64;
1089         } else {
1090                 chansize = 32;
1091         }
1092         tmp = RREG32(MC_SHARED_CHMAP);
1093         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1094         case 0:
1095         default:
1096                 numchan = 1;
1097                 break;
1098         case 1:
1099                 numchan = 2;
1100                 break;
1101         case 2:
1102                 numchan = 4;
1103                 break;
1104         case 3:
1105                 numchan = 8;
1106                 break;
1107         }
1108         rdev->mc.vram_width = numchan * chansize;
1109         /* Could aper size report 0 ? */
1110         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1111         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1112         /* Setup GPU memory space */
1113         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1114         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1115         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1116         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1117         r700_vram_gtt_location(rdev, &rdev->mc);
1118         radeon_update_bandwidth_info(rdev);
1119
1120         return 0;
1121 }
1122
1123 static int rv770_startup(struct radeon_device *rdev)
1124 {
1125         int r;
1126
1127         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1128                 r = r600_init_microcode(rdev);
1129                 if (r) {
1130                         DRM_ERROR("Failed to load firmware!\n");
1131                         return r;
1132                 }
1133         }
1134
1135         rv770_mc_program(rdev);
1136         if (rdev->flags & RADEON_IS_AGP) {
1137                 rv770_agp_enable(rdev);
1138         } else {
1139                 r = rv770_pcie_gart_enable(rdev);
1140                 if (r)
1141                         return r;
1142         }
1143         r = rv770_vram_scratch_init(rdev);
1144         if (r)
1145                 return r;
1146         rv770_gpu_init(rdev);
1147         r = r600_blit_init(rdev);
1148         if (r) {
1149                 r600_blit_fini(rdev);
1150                 rdev->asic->copy = NULL;
1151                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1152         }
1153
1154         /* allocate wb buffer */
1155         r = radeon_wb_init(rdev);
1156         if (r)
1157                 return r;
1158
1159         /* Enable IRQ */
1160         r = r600_irq_init(rdev);
1161         if (r) {
1162                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1163                 radeon_irq_kms_fini(rdev);
1164                 return r;
1165         }
1166         r600_irq_set(rdev);
1167
1168         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1169         if (r)
1170                 return r;
1171         r = rv770_cp_load_microcode(rdev);
1172         if (r)
1173                 return r;
1174         r = r600_cp_resume(rdev);
1175         if (r)
1176                 return r;
1177
1178         return 0;
1179 }
1180
1181 int rv770_resume(struct radeon_device *rdev)
1182 {
1183         int r;
1184
1185         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1186          * posting will perform necessary task to bring back GPU into good
1187          * shape.
1188          */
1189         /* post card */
1190         atom_asic_init(rdev->mode_info.atom_context);
1191
1192         r = rv770_startup(rdev);
1193         if (r) {
1194                 DRM_ERROR("r600 startup failed on resume\n");
1195                 return r;
1196         }
1197
1198         r = r600_ib_test(rdev);
1199         if (r) {
1200                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1201                 return r;
1202         }
1203
1204         r = r600_audio_init(rdev);
1205         if (r) {
1206                 dev_err(rdev->dev, "radeon: audio init failed\n");
1207                 return r;
1208         }
1209
1210         return r;
1211
1212 }
1213
1214 int rv770_suspend(struct radeon_device *rdev)
1215 {
1216         int r;
1217
1218         r600_audio_fini(rdev);
1219         /* FIXME: we should wait for ring to be empty */
1220         r700_cp_stop(rdev);
1221         rdev->cp.ready = false;
1222         r600_irq_suspend(rdev);
1223         radeon_wb_disable(rdev);
1224         rv770_pcie_gart_disable(rdev);
1225         /* unpin shaders bo */
1226         if (rdev->r600_blit.shader_obj) {
1227                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1228                 if (likely(r == 0)) {
1229                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
1230                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1231                 }
1232         }
1233         return 0;
1234 }
1235
1236 /* Plan is to move initialization in that function and use
1237  * helper function so that radeon_device_init pretty much
1238  * do nothing more than calling asic specific function. This
1239  * should also allow to remove a bunch of callback function
1240  * like vram_info.
1241  */
1242 int rv770_init(struct radeon_device *rdev)
1243 {
1244         int r;
1245
1246         r = radeon_dummy_page_init(rdev);
1247         if (r)
1248                 return r;
1249         /* This don't do much */
1250         r = radeon_gem_init(rdev);
1251         if (r)
1252                 return r;
1253         /* Read BIOS */
1254         if (!radeon_get_bios(rdev)) {
1255                 if (ASIC_IS_AVIVO(rdev))
1256                         return -EINVAL;
1257         }
1258         /* Must be an ATOMBIOS */
1259         if (!rdev->is_atom_bios) {
1260                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
1261                 return -EINVAL;
1262         }
1263         r = radeon_atombios_init(rdev);
1264         if (r)
1265                 return r;
1266         /* Post card if necessary */
1267         if (!r600_card_posted(rdev)) {
1268                 if (!rdev->bios) {
1269                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1270                         return -EINVAL;
1271                 }
1272                 DRM_INFO("GPU not posted. posting now...\n");
1273                 atom_asic_init(rdev->mode_info.atom_context);
1274         }
1275         /* Initialize scratch registers */
1276         r600_scratch_init(rdev);
1277         /* Initialize surface registers */
1278         radeon_surface_init(rdev);
1279         /* Initialize clocks */
1280         radeon_get_clock_info(rdev->ddev);
1281         /* Fence driver */
1282         r = radeon_fence_driver_init(rdev);
1283         if (r)
1284                 return r;
1285         /* initialize AGP */
1286         if (rdev->flags & RADEON_IS_AGP) {
1287                 r = radeon_agp_init(rdev);
1288                 if (r)
1289                         radeon_agp_disable(rdev);
1290         }
1291         r = rv770_mc_init(rdev);
1292         if (r)
1293                 return r;
1294         /* Memory manager */
1295         r = radeon_bo_init(rdev);
1296         if (r)
1297                 return r;
1298
1299         r = radeon_irq_kms_init(rdev);
1300         if (r)
1301                 return r;
1302
1303         rdev->cp.ring_obj = NULL;
1304         r600_ring_init(rdev, 1024 * 1024);
1305
1306         rdev->ih.ring_obj = NULL;
1307         r600_ih_ring_init(rdev, 64 * 1024);
1308
1309         r = r600_pcie_gart_init(rdev);
1310         if (r)
1311                 return r;
1312
1313         rdev->accel_working = true;
1314         r = rv770_startup(rdev);
1315         if (r) {
1316                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1317                 r700_cp_fini(rdev);
1318                 r600_irq_fini(rdev);
1319                 radeon_wb_fini(rdev);
1320                 radeon_irq_kms_fini(rdev);
1321                 rv770_pcie_gart_fini(rdev);
1322                 rdev->accel_working = false;
1323         }
1324         if (rdev->accel_working) {
1325                 r = radeon_ib_pool_init(rdev);
1326                 if (r) {
1327                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1328                         rdev->accel_working = false;
1329                 } else {
1330                         r = r600_ib_test(rdev);
1331                         if (r) {
1332                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1333                                 rdev->accel_working = false;
1334                         }
1335                 }
1336         }
1337
1338         r = r600_audio_init(rdev);
1339         if (r) {
1340                 dev_err(rdev->dev, "radeon: audio init failed\n");
1341                 return r;
1342         }
1343
1344         return 0;
1345 }
1346
1347 void rv770_fini(struct radeon_device *rdev)
1348 {
1349         r600_blit_fini(rdev);
1350         r700_cp_fini(rdev);
1351         r600_irq_fini(rdev);
1352         radeon_wb_fini(rdev);
1353         radeon_irq_kms_fini(rdev);
1354         rv770_pcie_gart_fini(rdev);
1355         rv770_vram_scratch_fini(rdev);
1356         radeon_gem_fini(rdev);
1357         radeon_fence_driver_fini(rdev);
1358         radeon_agp_fini(rdev);
1359         radeon_bo_fini(rdev);
1360         radeon_atombios_fini(rdev);
1361         kfree(rdev->bios);
1362         rdev->bios = NULL;
1363         radeon_dummy_page_fini(rdev);
1364 }