Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/radeon_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <ttm/ttm_bo_api.h>
  33 #include <ttm/ttm_bo_driver.h>
  34 #include <ttm/ttm_placement.h>
  35 #include <ttm/ttm_module.h>
  36 #include <ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/radeon_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include "radeon_reg.h"
  42 #include "radeon.h"
  43
  44 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  45
  46 static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
  47
  48 static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
  49 {
  50         struct radeon_mman *mman;
  51         struct radeon_device *rdev;
  52
  53         mman = container_of(bdev, struct radeon_mman, bdev);
  54         rdev = container_of(mman, struct radeon_device, mman);
  55         return rdev;
  56 }
  57
  58
  59 /*
  60  * Global memory.
  61  */
  62 static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
  63 {
  64         return ttm_mem_global_init(ref->object);
  65 }
  66
  67 static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
  68 {
  69         ttm_mem_global_release(ref->object);
  70 }
  71
  72 static int radeon_ttm_global_init(struct radeon_device *rdev)
  73 {
  74         struct drm_global_reference *global_ref;
  75         int r;
  76
  77         rdev->mman.mem_global_referenced = false;
  78         global_ref = &rdev->mman.mem_global_ref;
  79         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  80         global_ref->size = sizeof(struct ttm_mem_global);
  81         global_ref->init = &radeon_ttm_mem_global_init;
  82         global_ref->release = &radeon_ttm_mem_global_release;
  83         r = drm_global_item_ref(global_ref);
  84         if (r != 0) {
  85                 DRM_ERROR("Failed setting up TTM memory accounting "
  86                           "subsystem.\n");
  87                 return r;
  88         }
  89
  90         rdev->mman.bo_global_ref.mem_glob =
  91                 rdev->mman.mem_global_ref.object;
  92         global_ref = &rdev->mman.bo_global_ref.ref;
  93         global_ref->global_type = DRM_GLOBAL_TTM_BO;
  94         global_ref->size = sizeof(struct ttm_bo_global);
  95         global_ref->init = &ttm_bo_global_init;
  96         global_ref->release = &ttm_bo_global_release;
  97         r = drm_global_item_ref(global_ref);
  98         if (r != 0) {
  99                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 100                 drm_global_item_unref(&rdev->mman.mem_global_ref);
 101                 return r;
 102         }
 103
 104         rdev->mman.mem_global_referenced = true;
 105         return 0;
 106 }
 107
 108 static void radeon_ttm_global_fini(struct radeon_device *rdev)
 109 {
 110         if (rdev->mman.mem_global_referenced) {
 111                 drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
 112                 drm_global_item_unref(&rdev->mman.mem_global_ref);
 113                 rdev->mman.mem_global_referenced = false;
 114         }
 115 }
 116
 117 static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 118 {
 119         return 0;
 120 }
 121
 122 static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 123                                 struct ttm_mem_type_manager *man)
 124 {
 125         struct radeon_device *rdev;
 126
 127         rdev = radeon_get_rdev(bdev);
 128
 129         switch (type) {
 130         case TTM_PL_SYSTEM:
 131                 /* System memory */
 132                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 133                 man->available_caching = TTM_PL_MASK_CACHING;
 134                 man->default_caching = TTM_PL_FLAG_CACHED;
 135                 break;
 136         case TTM_PL_TT:
 137                 man->func = &ttm_bo_manager_func;
 138                 man->gpu_offset = rdev->mc.gtt_start;
 139                 man->available_caching = TTM_PL_MASK_CACHING;
 140                 man->default_caching = TTM_PL_FLAG_CACHED;
 141                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 142 #if __OS_HAS_AGP
 143                 if (rdev->flags & RADEON_IS_AGP) {
 144                         if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) {
 145                                 DRM_ERROR("AGP is not enabled for memory type %u\n",
 146                                           (unsigned)type);
 147                                 return -EINVAL;
 148                         }
 149                         if (!rdev->ddev->agp->cant_use_aperture)
 150                                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 151                         man->available_caching = TTM_PL_FLAG_UNCACHED |
 152                                                  TTM_PL_FLAG_WC;
 153                         man->default_caching = TTM_PL_FLAG_WC;
 154                 }
 155 #endif
 156                 break;
 157         case TTM_PL_VRAM:
 158                 /* "On-card" video ram */
 159                 man->func = &ttm_bo_manager_func;
 160                 man->gpu_offset = rdev->mc.vram_start;
 161                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 162                              TTM_MEMTYPE_FLAG_MAPPABLE;
 163                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 164                 man->default_caching = TTM_PL_FLAG_WC;
 165                 break;
 166         default:
 167                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 168                 return -EINVAL;
 169         }
 170         return 0;
 171 }
 172
 173 static void radeon_evict_flags(struct ttm_buffer_object *bo,
 174                                 struct ttm_placement *placement)
 175 {
 176         struct radeon_bo *rbo;
 177         static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 178
 179         if (!radeon_ttm_bo_is_radeon_bo(bo)) {
 180                 placement->fpfn = 0;
 181                 placement->lpfn = 0;
 182                 placement->placement = &placements;
 183                 placement->busy_placement = &placements;
 184                 placement->num_placement = 1;
 185                 placement->num_busy_placement = 1;
 186                 return;
 187         }
 188         rbo = container_of(bo, struct radeon_bo, tbo);
 189         switch (bo->mem.mem_type) {
 190         case TTM_PL_VRAM:
 191                 if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false)
 192                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
 193                 else
 194                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
 195                 break;
 196         case TTM_PL_TT:
 197         default:
 198                 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
 199         }
 200         *placement = rbo->placement;
 201 }
 202
 203 static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 204 {
 205         return 0;
 206 }
 207
 208 static void radeon_move_null(struct ttm_buffer_object *bo,
 209                              struct ttm_mem_reg *new_mem)
 210 {
 211         struct ttm_mem_reg *old_mem = &bo->mem;
 212
 213         BUG_ON(old_mem->mm_node != NULL);
 214         *old_mem = *new_mem;
 215         new_mem->mm_node = NULL;
 216 }
 217
 218 static int radeon_move_blit(struct ttm_buffer_object *bo,
 219                         bool evict, int no_wait_reserve, bool no_wait_gpu,
 220                         struct ttm_mem_reg *new_mem,
 221                         struct ttm_mem_reg *old_mem)
 222 {
 223         struct radeon_device *rdev;
 224         uint64_t old_start, new_start;
 225         struct radeon_fence *fence, *old_fence;
 226         struct radeon_semaphore *sem = NULL;
 227         int r;
 228
 229         rdev = radeon_get_rdev(bo->bdev);
 230         r = radeon_fence_create(rdev, &fence, radeon_copy_ring_index(rdev));
 231         if (unlikely(r)) {
 232                 return r;
 233         }
 234         old_start = old_mem->start << PAGE_SHIFT;
 235         new_start = new_mem->start << PAGE_SHIFT;
 236
 237         switch (old_mem->mem_type) {
 238         case TTM_PL_VRAM:
 239                 old_start += rdev->mc.vram_start;
 240                 break;
 241         case TTM_PL_TT:
 242                 old_start += rdev->mc.gtt_start;
 243                 break;
 244         default:
 245                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 246                 radeon_fence_unref(&fence);
 247                 return -EINVAL;
 248         }
 249         switch (new_mem->mem_type) {
 250         case TTM_PL_VRAM:
 251                 new_start += rdev->mc.vram_start;
 252                 break;
 253         case TTM_PL_TT:
 254                 new_start += rdev->mc.gtt_start;
 255                 break;
 256         default:
 257                 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 258                 radeon_fence_unref(&fence);
 259                 return -EINVAL;
 260         }
 261         if (!rdev->ring[radeon_copy_ring_index(rdev)].ready) {
 262                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 263                 radeon_fence_unref(&fence);
 264                 return -EINVAL;
 265         }
 266
 267         BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
 268
 269         /* sync other rings */
 270         old_fence = bo->sync_obj;
 271         if (old_fence && old_fence->ring != fence->ring
 272             && !radeon_fence_signaled(old_fence)) {
 273                 bool sync_to_ring[RADEON_NUM_RINGS] = { };
 274                 sync_to_ring[old_fence->ring] = true;
 275
 276                 r = radeon_semaphore_create(rdev, &sem);
 277                 if (r) {
 278                         radeon_fence_unref(&fence);
 279                         return r;
 280                 }
 281
 282                 r = radeon_semaphore_sync_rings(rdev, sem,
 283                                                 sync_to_ring, fence->ring);
 284                 if (r) {
 285                         radeon_semaphore_free(rdev, sem, NULL);
 286                         radeon_fence_unref(&fence);
 287                         return r;
 288                 }
 289         }
 290
 291         r = radeon_copy(rdev, old_start, new_start,
 292                         new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */
 293                         fence);
 294         /* FIXME: handle copy error */
 295         r = ttm_bo_move_accel_cleanup(bo, (void *)fence, NULL,
 296                                       evict, no_wait_reserve, no_wait_gpu, new_mem);
 297         radeon_semaphore_free(rdev, sem, fence);
 298         radeon_fence_unref(&fence);
 299         return r;
 300 }
 301
 302 static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
 303                                 bool evict, bool interruptible,
 304                                 bool no_wait_reserve, bool no_wait_gpu,
 305                                 struct ttm_mem_reg *new_mem)
 306 {
 307         struct radeon_device *rdev;
 308         struct ttm_mem_reg *old_mem = &bo->mem;
 309         struct ttm_mem_reg tmp_mem;
 310         u32 placements;
 311         struct ttm_placement placement;
 312         int r;
 313
 314         rdev = radeon_get_rdev(bo->bdev);
 315         tmp_mem = *new_mem;
 316         tmp_mem.mm_node = NULL;
 317         placement.fpfn = 0;
 318         placement.lpfn = 0;
 319         placement.num_placement = 1;
 320         placement.placement = &placements;
 321         placement.num_busy_placement = 1;
 322         placement.busy_placement = &placements;
 323         placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 324         r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
 325                              interruptible, no_wait_reserve, no_wait_gpu);
 326         if (unlikely(r)) {
 327                 return r;
 328         }
 329
 330         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 331         if (unlikely(r)) {
 332                 goto out_cleanup;
 333         }
 334
 335         r = ttm_tt_bind(bo->ttm, &tmp_mem);
 336         if (unlikely(r)) {
 337                 goto out_cleanup;
 338         }
 339         r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem, old_mem);
 340         if (unlikely(r)) {
 341                 goto out_cleanup;
 342         }
 343         r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
 344 out_cleanup:
 345         ttm_bo_mem_put(bo, &tmp_mem);
 346         return r;
 347 }
 348
 349 static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
 350                                 bool evict, bool interruptible,
 351                                 bool no_wait_reserve, bool no_wait_gpu,
 352                                 struct ttm_mem_reg *new_mem)
 353 {
 354         struct radeon_device *rdev;
 355         struct ttm_mem_reg *old_mem = &bo->mem;
 356         struct ttm_mem_reg tmp_mem;
 357         struct ttm_placement placement;
 358         u32 placements;
 359         int r;
 360
 361         rdev = radeon_get_rdev(bo->bdev);
 362         tmp_mem = *new_mem;
 363         tmp_mem.mm_node = NULL;
 364         placement.fpfn = 0;
 365         placement.lpfn = 0;
 366         placement.num_placement = 1;
 367         placement.placement = &placements;
 368         placement.num_busy_placement = 1;
 369         placement.busy_placement = &placements;
 370         placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 371         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, interruptible, no_wait_reserve, no_wait_gpu);
 372         if (unlikely(r)) {
 373                 return r;
 374         }
 375         r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
 376         if (unlikely(r)) {
 377                 goto out_cleanup;
 378         }
 379         r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, new_mem, old_mem);
 380         if (unlikely(r)) {
 381                 goto out_cleanup;
 382         }
 383 out_cleanup:
 384         ttm_bo_mem_put(bo, &tmp_mem);
 385         return r;
 386 }
 387
 388 static int radeon_bo_move(struct ttm_buffer_object *bo,
 389                         bool evict, bool interruptible,
 390                         bool no_wait_reserve, bool no_wait_gpu,
 391                         struct ttm_mem_reg *new_mem)
 392 {
 393         struct radeon_device *rdev;
 394         struct ttm_mem_reg *old_mem = &bo->mem;
 395         int r;
 396
 397         rdev = radeon_get_rdev(bo->bdev);
 398         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 399                 radeon_move_null(bo, new_mem);
 400                 return 0;
 401         }
 402         if ((old_mem->mem_type == TTM_PL_TT &&
 403              new_mem->mem_type == TTM_PL_SYSTEM) ||
 404             (old_mem->mem_type == TTM_PL_SYSTEM &&
 405              new_mem->mem_type == TTM_PL_TT)) {
 406                 /* bind is enough */
 407                 radeon_move_null(bo, new_mem);
 408                 return 0;
 409         }
 410         if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
 411             rdev->asic->copy.copy == NULL) {
 412                 /* use memcpy */
 413                 goto memcpy;
 414         }
 415
 416         if (old_mem->mem_type == TTM_PL_VRAM &&
 417             new_mem->mem_type == TTM_PL_SYSTEM) {
 418                 r = radeon_move_vram_ram(bo, evict, interruptible,
 419                                         no_wait_reserve, no_wait_gpu, new_mem);
 420         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 421                    new_mem->mem_type == TTM_PL_VRAM) {
 422                 r = radeon_move_ram_vram(bo, evict, interruptible,
 423                                             no_wait_reserve, no_wait_gpu, new_mem);
 424         } else {
 425                 r = radeon_move_blit(bo, evict, no_wait_reserve, no_wait_gpu, new_mem, old_mem);
 426         }
 427
 428         if (r) {
 429 memcpy:
 430                 r = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
 431         }
 432         return r;
 433 }
 434
 435 static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 436 {
 437         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 438         struct radeon_device *rdev = radeon_get_rdev(bdev);
 439
 440         mem->bus.addr = NULL;
 441         mem->bus.offset = 0;
 442         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 443         mem->bus.base = 0;
 444         mem->bus.is_iomem = false;
 445         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 446                 return -EINVAL;
 447         switch (mem->mem_type) {
 448         case TTM_PL_SYSTEM:
 449                 /* system memory */
 450                 return 0;
 451         case TTM_PL_TT:
 452 #if __OS_HAS_AGP
 453                 if (rdev->flags & RADEON_IS_AGP) {
 454                         /* RADEON_IS_AGP is set only if AGP is active */
 455                         mem->bus.offset = mem->start << PAGE_SHIFT;
 456                         mem->bus.base = rdev->mc.agp_base;
 457                         mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
 458                 }
 459 #endif
 460                 break;
 461         case TTM_PL_VRAM:
 462                 mem->bus.offset = mem->start << PAGE_SHIFT;
 463                 /* check if it's visible */
 464                 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
 465                         return -EINVAL;
 466                 mem->bus.base = rdev->mc.aper_base;
 467                 mem->bus.is_iomem = true;
 468 #ifdef __alpha__
 469                 /*
 470                  * Alpha: use bus.addr to hold the ioremap() return,
 471                  * so we can modify bus.base below.
 472                  */
 473                 if (mem->placement & TTM_PL_FLAG_WC)
 474                         mem->bus.addr =
 475                                 ioremap_wc(mem->bus.base + mem->bus.offset,
 476                                            mem->bus.size);
 477                 else
 478                         mem->bus.addr =
 479                                 ioremap_nocache(mem->bus.base + mem->bus.offset,
 480                                                 mem->bus.size);
 481
 482                 /*
 483                  * Alpha: Use just the bus offset plus
 484                  * the hose/domain memory base for bus.base.
 485                  * It then can be used to build PTEs for VRAM
 486                  * access, as done in ttm_bo_vm_fault().
 487                  */
 488                 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
 489                         rdev->ddev->hose->dense_mem_base;
 490 #endif
 491                 break;
 492         default:
 493                 return -EINVAL;
 494         }
 495         return 0;
 496 }
 497
 498 static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 499 {
 500 }
 501
 502 static int radeon_sync_obj_wait(void *sync_obj, void *sync_arg,
 503                                 bool lazy, bool interruptible)
 504 {
 505         return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible);
 506 }
 507
 508 static int radeon_sync_obj_flush(void *sync_obj, void *sync_arg)
 509 {
 510         return 0;
 511 }
 512
 513 static void radeon_sync_obj_unref(void **sync_obj)
 514 {
 515         radeon_fence_unref((struct radeon_fence **)sync_obj);
 516 }
 517
 518 static void *radeon_sync_obj_ref(void *sync_obj)
 519 {
 520         return radeon_fence_ref((struct radeon_fence *)sync_obj);
 521 }
 522
 523 static bool radeon_sync_obj_signaled(void *sync_obj, void *sync_arg)
 524 {
 525         return radeon_fence_signaled((struct radeon_fence *)sync_obj);
 526 }
 527
 528 /*
 529  * TTM backend functions.
 530  */
 531 struct radeon_ttm_tt {
 532         struct ttm_dma_tt               ttm;
 533         struct radeon_device            *rdev;
 534         u64                             offset;
 535 };
 536
 537 static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
 538                                    struct ttm_mem_reg *bo_mem)
 539 {
 540         struct radeon_ttm_tt *gtt = (void*)ttm;
 541         int r;
 542
 543         gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
 544         if (!ttm->num_pages) {
 545                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 546                      ttm->num_pages, bo_mem, ttm);
 547         }
 548         r = radeon_gart_bind(gtt->rdev, gtt->offset,
 549                              ttm->num_pages, ttm->pages, gtt->ttm.dma_address);
 550         if (r) {
 551                 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
 552                           ttm->num_pages, (unsigned)gtt->offset);
 553                 return r;
 554         }
 555         return 0;
 556 }
 557
 558 static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
 559 {
 560         struct radeon_ttm_tt *gtt = (void *)ttm;
 561
 562         radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
 563         return 0;
 564 }
 565
 566 static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
 567 {
 568         struct radeon_ttm_tt *gtt = (void *)ttm;
 569
 570         ttm_dma_tt_fini(&gtt->ttm);
 571         kfree(gtt);
 572 }
 573
 574 static struct ttm_backend_func radeon_backend_func = {
 575         .bind = &radeon_ttm_backend_bind,
 576         .unbind = &radeon_ttm_backend_unbind,
 577         .destroy = &radeon_ttm_backend_destroy,
 578 };
 579
 580 struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
 581                                     unsigned long size, uint32_t page_flags,
 582                                     struct page *dummy_read_page)
 583 {
 584         struct radeon_device *rdev;
 585         struct radeon_ttm_tt *gtt;
 586
 587         rdev = radeon_get_rdev(bdev);
 588 #if __OS_HAS_AGP
 589         if (rdev->flags & RADEON_IS_AGP) {
 590                 return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge,
 591                                          size, page_flags, dummy_read_page);
 592         }
 593 #endif
 594
 595         gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
 596         if (gtt == NULL) {
 597                 return NULL;
 598         }
 599         gtt->ttm.ttm.func = &radeon_backend_func;
 600         gtt->rdev = rdev;
 601         if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 602                 kfree(gtt);
 603                 return NULL;
 604         }
 605         return &gtt->ttm.ttm;
 606 }
 607
 608 static int radeon_ttm_tt_populate(struct ttm_tt *ttm)
 609 {
 610         struct radeon_device *rdev;
 611         struct radeon_ttm_tt *gtt = (void *)ttm;
 612         unsigned i;
 613         int r;
 614         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 615
 616         if (ttm->state != tt_unpopulated)
 617                 return 0;
 618
 619         if (slave && ttm->sg) {
 620                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 621                                                  gtt->ttm.dma_address, ttm->num_pages);
 622                 ttm->state = tt_unbound;
 623                 return 0;
 624         }
 625
 626         rdev = radeon_get_rdev(ttm->bdev);
 627 #if __OS_HAS_AGP
 628         if (rdev->flags & RADEON_IS_AGP) {
 629                 return ttm_agp_tt_populate(ttm);
 630         }
 631 #endif
 632
 633 #ifdef CONFIG_SWIOTLB
 634         if (swiotlb_nr_tbl()) {
 635                 return ttm_dma_populate(&gtt->ttm, rdev->dev);
 636         }
 637 #endif
 638
 639         r = ttm_pool_populate(ttm);
 640         if (r) {
 641                 return r;
 642         }
 643
 644         for (i = 0; i < ttm->num_pages; i++) {
 645                 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i],
 646                                                        0, PAGE_SIZE,
 647                                                        PCI_DMA_BIDIRECTIONAL);
 648                 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) {
 649                         while (--i) {
 650                                 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
 651                                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 652                                 gtt->ttm.dma_address[i] = 0;
 653                         }
 654                         ttm_pool_unpopulate(ttm);
 655                         return -EFAULT;
 656                 }
 657         }
 658         return 0;
 659 }
 660
 661 static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
 662 {
 663         struct radeon_device *rdev;
 664         struct radeon_ttm_tt *gtt = (void *)ttm;
 665         unsigned i;
 666         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 667
 668         if (slave)
 669                 return;
 670
 671         rdev = radeon_get_rdev(ttm->bdev);
 672 #if __OS_HAS_AGP
 673         if (rdev->flags & RADEON_IS_AGP) {
 674                 ttm_agp_tt_unpopulate(ttm);
 675                 return;
 676         }
 677 #endif
 678
 679 #ifdef CONFIG_SWIOTLB
 680         if (swiotlb_nr_tbl()) {
 681                 ttm_dma_unpopulate(&gtt->ttm, rdev->dev);
 682                 return;
 683         }
 684 #endif
 685
 686         for (i = 0; i < ttm->num_pages; i++) {
 687                 if (gtt->ttm.dma_address[i]) {
 688                         pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i],
 689                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 690                 }
 691         }
 692
 693         ttm_pool_unpopulate(ttm);
 694 }
 695
 696 static struct ttm_bo_driver radeon_bo_driver = {
 697         .ttm_tt_create = &radeon_ttm_tt_create,
 698         .ttm_tt_populate = &radeon_ttm_tt_populate,
 699         .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
 700         .invalidate_caches = &radeon_invalidate_caches,
 701         .init_mem_type = &radeon_init_mem_type,
 702         .evict_flags = &radeon_evict_flags,
 703         .move = &radeon_bo_move,
 704         .verify_access = &radeon_verify_access,
 705         .sync_obj_signaled = &radeon_sync_obj_signaled,
 706         .sync_obj_wait = &radeon_sync_obj_wait,
 707         .sync_obj_flush = &radeon_sync_obj_flush,
 708         .sync_obj_unref = &radeon_sync_obj_unref,
 709         .sync_obj_ref = &radeon_sync_obj_ref,
 710         .move_notify = &radeon_bo_move_notify,
 711         .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
 712         .io_mem_reserve = &radeon_ttm_io_mem_reserve,
 713         .io_mem_free = &radeon_ttm_io_mem_free,
 714 };
 715
 716 int radeon_ttm_init(struct radeon_device *rdev)
 717 {
 718         int r;
 719
 720         r = radeon_ttm_global_init(rdev);
 721         if (r) {
 722                 return r;
 723         }
 724         /* No others user of address space so set it to 0 */
 725         r = ttm_bo_device_init(&rdev->mman.bdev,
 726                                rdev->mman.bo_global_ref.ref.object,
 727                                &radeon_bo_driver, DRM_FILE_PAGE_OFFSET,
 728                                rdev->need_dma32);
 729         if (r) {
 730                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
 731                 return r;
 732         }
 733         rdev->mman.initialized = true;
 734         r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
 735                                 rdev->mc.real_vram_size >> PAGE_SHIFT);
 736         if (r) {
 737                 DRM_ERROR("Failed initializing VRAM heap.\n");
 738                 return r;
 739         }
 740         r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
 741                              RADEON_GEM_DOMAIN_VRAM,
 742                              NULL, &rdev->stollen_vga_memory);
 743         if (r) {
 744                 return r;
 745         }
 746         r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
 747         if (r)
 748                 return r;
 749         r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
 750         radeon_bo_unreserve(rdev->stollen_vga_memory);
 751         if (r) {
 752                 radeon_bo_unref(&rdev->stollen_vga_memory);
 753                 return r;
 754         }
 755         DRM_INFO("radeon: %uM of VRAM memory ready\n",
 756                  (unsigned)rdev->mc.real_vram_size / (1024 * 1024));
 757         r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
 758                                 rdev->mc.gtt_size >> PAGE_SHIFT);
 759         if (r) {
 760                 DRM_ERROR("Failed initializing GTT heap.\n");
 761                 return r;
 762         }
 763         DRM_INFO("radeon: %uM of GTT memory ready.\n",
 764                  (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
 765         if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
 766                 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
 767         }
 768
 769         r = radeon_ttm_debugfs_init(rdev);
 770         if (r) {
 771                 DRM_ERROR("Failed to init debugfs\n");
 772                 return r;
 773         }
 774         return 0;
 775 }
 776
 777 void radeon_ttm_fini(struct radeon_device *rdev)
 778 {
 779         int r;
 780
 781         if (!rdev->mman.initialized)
 782                 return;
 783         if (rdev->stollen_vga_memory) {
 784                 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
 785                 if (r == 0) {
 786                         radeon_bo_unpin(rdev->stollen_vga_memory);
 787                         radeon_bo_unreserve(rdev->stollen_vga_memory);
 788                 }
 789                 radeon_bo_unref(&rdev->stollen_vga_memory);
 790         }
 791         ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 792         ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
 793         ttm_bo_device_release(&rdev->mman.bdev);
 794         radeon_gart_fini(rdev);
 795         radeon_ttm_global_fini(rdev);
 796         rdev->mman.initialized = false;
 797         DRM_INFO("radeon: ttm finalized\n");
 798 }
 799
 800 /* this should only be called at bootup or when userspace
 801  * isn't running */
 802 void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
 803 {
 804         struct ttm_mem_type_manager *man;
 805
 806         if (!rdev->mman.initialized)
 807                 return;
 808
 809         man = &rdev->mman.bdev.man[TTM_PL_VRAM];
 810         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
 811         man->size = size >> PAGE_SHIFT;
 812 }
 813
 814 static struct vm_operations_struct radeon_ttm_vm_ops;
 815 static const struct vm_operations_struct *ttm_vm_ops = NULL;
 816
 817 static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
 818 {
 819         struct ttm_buffer_object *bo;
 820         struct radeon_device *rdev;
 821         int r;
 822
 823         bo = (struct ttm_buffer_object *)vma->vm_private_data;
 824         if (bo == NULL) {
 825                 return VM_FAULT_NOPAGE;
 826         }
 827         rdev = radeon_get_rdev(bo->bdev);
 828         mutex_lock(&rdev->vram_mutex);
 829         r = ttm_vm_ops->fault(vma, vmf);
 830         mutex_unlock(&rdev->vram_mutex);
 831         return r;
 832 }
 833
 834 int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
 835 {
 836         struct drm_file *file_priv;
 837         struct radeon_device *rdev;
 838         int r;
 839
 840         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
 841                 return drm_mmap(filp, vma);
 842         }
 843
 844         file_priv = filp->private_data;
 845         rdev = file_priv->minor->dev->dev_private;
 846         if (rdev == NULL) {
 847                 return -EINVAL;
 848         }
 849         r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
 850         if (unlikely(r != 0)) {
 851                 return r;
 852         }
 853         if (unlikely(ttm_vm_ops == NULL)) {
 854                 ttm_vm_ops = vma->vm_ops;
 855                 radeon_ttm_vm_ops = *ttm_vm_ops;
 856                 radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
 857         }
 858         vma->vm_ops = &radeon_ttm_vm_ops;
 859         return 0;
 860 }
 861
 862
 863 #define RADEON_DEBUGFS_MEM_TYPES 2
 864
 865 #if defined(CONFIG_DEBUG_FS)
 866 static int radeon_mm_dump_table(struct seq_file *m, void *data)
 867 {
 868         struct drm_info_node *node = (struct drm_info_node *)m->private;
 869         struct drm_mm *mm = (struct drm_mm *)node->info_ent->data;
 870         struct drm_device *dev = node->minor->dev;
 871         struct radeon_device *rdev = dev->dev_private;
 872         int ret;
 873         struct ttm_bo_global *glob = rdev->mman.bdev.glob;
 874
 875         spin_lock(&glob->lru_lock);
 876         ret = drm_mm_dump_table(m, mm);
 877         spin_unlock(&glob->lru_lock);
 878         return ret;
 879 }
 880 #endif
 881
 882 static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
 883 {
 884 #if defined(CONFIG_DEBUG_FS)
 885         static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+2];
 886         static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+2][32];
 887         unsigned i;
 888
 889         for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) {
 890                 if (i == 0)
 891                         sprintf(radeon_mem_types_names[i], "radeon_vram_mm");
 892                 else
 893                         sprintf(radeon_mem_types_names[i], "radeon_gtt_mm");
 894                 radeon_mem_types_list[i].name = radeon_mem_types_names[i];
 895                 radeon_mem_types_list[i].show = &radeon_mm_dump_table;
 896                 radeon_mem_types_list[i].driver_features = 0;
 897                 if (i == 0)
 898                         radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv;
 899                 else
 900                         radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv;
 901
 902         }
 903         /* Add ttm page pool to debugfs */
 904         sprintf(radeon_mem_types_names[i], "ttm_page_pool");
 905         radeon_mem_types_list[i].name = radeon_mem_types_names[i];
 906         radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs;
 907         radeon_mem_types_list[i].driver_features = 0;
 908         radeon_mem_types_list[i++].data = NULL;
 909 #ifdef CONFIG_SWIOTLB
 910         if (swiotlb_nr_tbl()) {
 911                 sprintf(radeon_mem_types_names[i], "ttm_dma_page_pool");
 912                 radeon_mem_types_list[i].name = radeon_mem_types_names[i];
 913                 radeon_mem_types_list[i].show = &ttm_dma_page_alloc_debugfs;
 914                 radeon_mem_types_list[i].driver_features = 0;
 915                 radeon_mem_types_list[i++].data = NULL;
 916         }
 917 #endif
 918         return radeon_debugfs_add_files(rdev, radeon_mem_types_list, i);
 919
 920 #endif
 921         return 0;
 922 }