2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
32 #include <drm/radeon_drm.h>
33 #include "radeon_reg.h"
39 * IBs (Indirect Buffers) and areas of GPU accessible memory where
40 * commands are stored. You can put a pointer to the IB in the
41 * command ring and the hw will fetch the commands from the IB
42 * and execute them. Generally userspace acceleration drivers
43 * produce command buffers which are send to the kernel and
44 * put in IBs for execution by the requested ring.
46 static int radeon_debugfs_sa_init(struct radeon_device *rdev);
49 * radeon_ib_get - request an IB (Indirect Buffer)
51 * @rdev: radeon_device pointer
52 * @ring: ring index the IB is associated with
53 * @ib: IB object returned
54 * @size: requested IB size
56 * Request an IB (all asics). IBs are allocated using the
58 * Returns 0 on success, error on failure.
60 int radeon_ib_get(struct radeon_device *rdev, int ring,
61 struct radeon_ib *ib, struct radeon_vm *vm,
66 r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256, true);
68 dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
72 r = radeon_semaphore_create(rdev, &ib->semaphore);
79 ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
82 /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
83 * space and soffset is the offset inside the pool bo
85 ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
87 ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
89 ib->is_const_ib = false;
90 for (i = 0; i < RADEON_NUM_RINGS; ++i)
91 ib->sync_to[i] = NULL;
97 * radeon_ib_free - free an IB (Indirect Buffer)
99 * @rdev: radeon_device pointer
100 * @ib: IB object to free
102 * Free an IB (all asics).
104 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
106 radeon_semaphore_free(rdev, &ib->semaphore, ib->fence);
107 radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
108 radeon_fence_unref(&ib->fence);
112 * radeon_ib_sync_to - sync to fence before executing the IB
114 * @ib: IB object to add fence to
115 * @fence: fence to sync to
117 * Sync to the fence before executing the IB
119 void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence)
121 struct radeon_fence *other;
126 other = ib->sync_to[fence->ring];
127 ib->sync_to[fence->ring] = radeon_fence_later(fence, other);
131 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
133 * @rdev: radeon_device pointer
134 * @ib: IB object to schedule
135 * @const_ib: Const IB to schedule (SI only)
137 * Schedule an IB on the associated ring (all asics).
138 * Returns 0 on success, error on failure.
140 * On SI, there are two parallel engines fed from the primary ring,
141 * the CE (Constant Engine) and the DE (Drawing Engine). Since
142 * resource descriptors have moved to memory, the CE allows you to
143 * prime the caches while the DE is updating register state so that
144 * the resource descriptors will be already in cache when the draw is
145 * processed. To accomplish this, the userspace driver submits two
146 * IBs, one for the CE and one for the DE. If there is a CE IB (called
147 * a CONST_IB), it will be put on the ring prior to the DE IB. Prior
148 * to SI there was just a DE IB.
150 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
151 struct radeon_ib *const_ib)
153 struct radeon_ring *ring = &rdev->ring[ib->ring];
154 bool need_sync = false;
157 if (!ib->length_dw || !ring->ready) {
158 /* TODO: Nothings in the ib we should report. */
159 dev_err(rdev->dev, "couldn't schedule ib\n");
163 /* 64 dwords should be enough for fence too */
164 r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8);
166 dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
169 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
170 struct radeon_fence *fence = ib->sync_to[i];
171 if (radeon_fence_need_sync(fence, ib->ring)) {
173 radeon_semaphore_sync_rings(rdev, ib->semaphore,
174 fence->ring, ib->ring);
175 radeon_fence_note_sync(fence, ib->ring);
178 /* immediately free semaphore when we don't need to sync */
180 radeon_semaphore_free(rdev, &ib->semaphore, NULL);
182 /* if we can't remember our last VM flush then flush now! */
183 /* XXX figure out why we have to flush for every IB */
184 if (ib->vm /*&& !ib->vm->last_flush*/) {
185 radeon_ring_vm_flush(rdev, ib->ring, ib->vm);
188 radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
189 radeon_semaphore_free(rdev, &const_ib->semaphore, NULL);
191 radeon_ring_ib_execute(rdev, ib->ring, ib);
192 r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
194 dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
195 radeon_ring_unlock_undo(rdev, ring);
199 const_ib->fence = radeon_fence_ref(ib->fence);
201 /* we just flushed the VM, remember that */
202 if (ib->vm && !ib->vm->last_flush) {
203 ib->vm->last_flush = radeon_fence_ref(ib->fence);
205 radeon_ring_unlock_commit(rdev, ring);
210 * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
212 * @rdev: radeon_device pointer
214 * Initialize the suballocator to manage a pool of memory
215 * for use as IBs (all asics).
216 * Returns 0 on success, error on failure.
218 int radeon_ib_pool_init(struct radeon_device *rdev)
222 if (rdev->ib_pool_ready) {
225 r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
226 RADEON_IB_POOL_SIZE*64*1024,
227 RADEON_GEM_DOMAIN_GTT);
232 r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
237 rdev->ib_pool_ready = true;
238 if (radeon_debugfs_sa_init(rdev)) {
239 dev_err(rdev->dev, "failed to register debugfs file for SA\n");
245 * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
247 * @rdev: radeon_device pointer
249 * Tear down the suballocator managing the pool of memory
250 * for use as IBs (all asics).
252 void radeon_ib_pool_fini(struct radeon_device *rdev)
254 if (rdev->ib_pool_ready) {
255 radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);
256 radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);
257 rdev->ib_pool_ready = false;
262 * radeon_ib_ring_tests - test IBs on the rings
264 * @rdev: radeon_device pointer
266 * Test an IB (Indirect Buffer) on each ring.
267 * If the test fails, disable the ring.
268 * Returns 0 on success, error if the primary GFX ring
271 int radeon_ib_ring_tests(struct radeon_device *rdev)
276 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
277 struct radeon_ring *ring = &rdev->ring[i];
282 r = radeon_ib_test(rdev, i, ring);
286 if (i == RADEON_RING_TYPE_GFX_INDEX) {
287 /* oh, oh, that's really bad */
288 DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
289 rdev->accel_working = false;
293 /* still not good, but we can live with it */
294 DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
303 * Most engines on the GPU are fed via ring buffers. Ring
304 * buffers are areas of GPU accessible memory that the host
305 * writes commands into and the GPU reads commands out of.
306 * There is a rptr (read pointer) that determines where the
307 * GPU is currently reading, and a wptr (write pointer)
308 * which determines where the host has written. When the
309 * pointers are equal, the ring is idle. When the host
310 * writes commands to the ring buffer, it increments the
311 * wptr. The GPU then starts fetching commands and executes
312 * them until the pointers are equal again.
314 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);
317 * radeon_ring_write - write a value to the ring
319 * @ring: radeon_ring structure holding ring information
320 * @v: dword (dw) value to write
322 * Write a value to the requested ring buffer (all asics).
324 void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
327 if (ring->count_dw <= 0) {
328 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
331 ring->ring[ring->wptr++] = v;
332 ring->wptr &= ring->ptr_mask;
334 ring->ring_free_dw--;
338 * radeon_ring_supports_scratch_reg - check if the ring supports
339 * writing to scratch registers
341 * @rdev: radeon_device pointer
342 * @ring: radeon_ring structure holding ring information
344 * Check if a specific ring supports writing to scratch registers (all asics).
345 * Returns true if the ring supports writing to scratch regs, false if not.
347 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
348 struct radeon_ring *ring)
351 case RADEON_RING_TYPE_GFX_INDEX:
352 case CAYMAN_RING_TYPE_CP1_INDEX:
353 case CAYMAN_RING_TYPE_CP2_INDEX:
360 u32 radeon_ring_generic_get_rptr(struct radeon_device *rdev,
361 struct radeon_ring *ring)
365 if (rdev->wb.enabled && ring != &rdev->ring[R600_RING_TYPE_UVD_INDEX])
366 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
368 rptr = RREG32(ring->rptr_reg);
369 rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
374 u32 radeon_ring_generic_get_wptr(struct radeon_device *rdev,
375 struct radeon_ring *ring)
379 wptr = RREG32(ring->wptr_reg);
380 wptr = (wptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
385 void radeon_ring_generic_set_wptr(struct radeon_device *rdev,
386 struct radeon_ring *ring)
388 WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask);
389 (void)RREG32(ring->wptr_reg);
393 * radeon_ring_free_size - update the free size
395 * @rdev: radeon_device pointer
396 * @ring: radeon_ring structure holding ring information
398 * Update the free dw slots in the ring buffer (all asics).
400 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
402 ring->rptr = radeon_ring_get_rptr(rdev, ring);
403 /* This works because ring_size is a power of 2 */
404 ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4));
405 ring->ring_free_dw -= ring->wptr;
406 ring->ring_free_dw &= ring->ptr_mask;
407 if (!ring->ring_free_dw) {
408 ring->ring_free_dw = ring->ring_size / 4;
413 * radeon_ring_alloc - allocate space on the ring buffer
415 * @rdev: radeon_device pointer
416 * @ring: radeon_ring structure holding ring information
417 * @ndw: number of dwords to allocate in the ring buffer
419 * Allocate @ndw dwords in the ring buffer (all asics).
420 * Returns 0 on success, error on failure.
422 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
426 /* make sure we aren't trying to allocate more space than there is on the ring */
427 if (ndw > (ring->ring_size / 4))
429 /* Align requested size with padding so unlock_commit can
431 radeon_ring_free_size(rdev, ring);
432 if (ring->ring_free_dw == (ring->ring_size / 4)) {
433 /* This is an empty ring update lockup info to avoid
436 radeon_ring_lockup_update(ring);
438 ndw = (ndw + ring->align_mask) & ~ring->align_mask;
439 while (ndw > (ring->ring_free_dw - 1)) {
440 radeon_ring_free_size(rdev, ring);
441 if (ndw < ring->ring_free_dw) {
444 r = radeon_fence_wait_next_locked(rdev, ring->idx);
448 ring->count_dw = ndw;
449 ring->wptr_old = ring->wptr;
454 * radeon_ring_lock - lock the ring and allocate space on it
456 * @rdev: radeon_device pointer
457 * @ring: radeon_ring structure holding ring information
458 * @ndw: number of dwords to allocate in the ring buffer
460 * Lock the ring and allocate @ndw dwords in the ring buffer
462 * Returns 0 on success, error on failure.
464 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
468 mutex_lock(&rdev->ring_lock);
469 r = radeon_ring_alloc(rdev, ring, ndw);
471 mutex_unlock(&rdev->ring_lock);
478 * radeon_ring_commit - tell the GPU to execute the new
479 * commands on the ring buffer
481 * @rdev: radeon_device pointer
482 * @ring: radeon_ring structure holding ring information
484 * Update the wptr (write pointer) to tell the GPU to
485 * execute new commands on the ring buffer (all asics).
487 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
489 /* We pad to match fetch size */
490 while (ring->wptr & ring->align_mask) {
491 radeon_ring_write(ring, ring->nop);
494 radeon_ring_set_wptr(rdev, ring);
498 * radeon_ring_unlock_commit - tell the GPU to execute the new
499 * commands on the ring buffer and unlock it
501 * @rdev: radeon_device pointer
502 * @ring: radeon_ring structure holding ring information
504 * Call radeon_ring_commit() then unlock the ring (all asics).
506 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring)
508 radeon_ring_commit(rdev, ring);
509 mutex_unlock(&rdev->ring_lock);
513 * radeon_ring_undo - reset the wptr
515 * @ring: radeon_ring structure holding ring information
517 * Reset the driver's copy of the wptr (all asics).
519 void radeon_ring_undo(struct radeon_ring *ring)
521 ring->wptr = ring->wptr_old;
525 * radeon_ring_unlock_undo - reset the wptr and unlock the ring
527 * @ring: radeon_ring structure holding ring information
529 * Call radeon_ring_undo() then unlock the ring (all asics).
531 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
533 radeon_ring_undo(ring);
534 mutex_unlock(&rdev->ring_lock);
538 * radeon_ring_force_activity - add some nop packets to the ring
540 * @rdev: radeon_device pointer
541 * @ring: radeon_ring structure holding ring information
543 * Add some nop packets to the ring to force activity (all asics).
544 * Used for lockup detection to see if the rptr is advancing.
546 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring)
550 radeon_ring_free_size(rdev, ring);
551 if (ring->rptr == ring->wptr) {
552 r = radeon_ring_alloc(rdev, ring, 1);
554 radeon_ring_write(ring, ring->nop);
555 radeon_ring_commit(rdev, ring);
561 * radeon_ring_lockup_update - update lockup variables
563 * @ring: radeon_ring structure holding ring information
565 * Update the last rptr value and timestamp (all asics).
567 void radeon_ring_lockup_update(struct radeon_ring *ring)
569 ring->last_rptr = ring->rptr;
570 ring->last_activity = jiffies;
574 * radeon_ring_test_lockup() - check if ring is lockedup by recording information
575 * @rdev: radeon device structure
576 * @ring: radeon_ring structure holding ring information
578 * We don't need to initialize the lockup tracking information as we will either
579 * have CP rptr to a different value of jiffies wrap around which will force
580 * initialization of the lockup tracking informations.
582 * A possible false positivie is if we get call after while and last_cp_rptr ==
583 * the current CP rptr, even if it's unlikely it might happen. To avoid this
584 * if the elapsed time since last call is bigger than 2 second than we return
585 * false and update the tracking information. Due to this the caller must call
586 * radeon_ring_test_lockup several time in less than 2sec for lockup to be reported
587 * the fencing code should be cautious about that.
589 * Caller should write to the ring to force CP to do something so we don't get
590 * false positive when CP is just gived nothing to do.
593 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
595 unsigned long cjiffies, elapsed;
598 if (!time_after(cjiffies, ring->last_activity)) {
599 /* likely a wrap around */
600 radeon_ring_lockup_update(ring);
603 ring->rptr = radeon_ring_get_rptr(rdev, ring);
604 if (ring->rptr != ring->last_rptr) {
605 /* CP is still working no lockup */
606 radeon_ring_lockup_update(ring);
609 elapsed = jiffies_to_msecs(cjiffies - ring->last_activity);
610 if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {
611 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
614 /* give a chance to the GPU ... */
619 * radeon_ring_backup - Back up the content of a ring
621 * @rdev: radeon_device pointer
622 * @ring: the ring we want to back up
624 * Saves all unprocessed commits from a ring, returns the number of dwords saved.
626 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
629 unsigned size, ptr, i;
631 /* just in case lock the ring */
632 mutex_lock(&rdev->ring_lock);
635 if (ring->ring_obj == NULL) {
636 mutex_unlock(&rdev->ring_lock);
640 /* it doesn't make sense to save anything if all fences are signaled */
641 if (!radeon_fence_count_emitted(rdev, ring->idx)) {
642 mutex_unlock(&rdev->ring_lock);
646 /* calculate the number of dw on the ring */
647 if (ring->rptr_save_reg)
648 ptr = RREG32(ring->rptr_save_reg);
649 else if (rdev->wb.enabled)
650 ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);
652 /* no way to read back the next rptr */
653 mutex_unlock(&rdev->ring_lock);
657 size = ring->wptr + (ring->ring_size / 4);
659 size &= ring->ptr_mask;
661 mutex_unlock(&rdev->ring_lock);
665 /* and then save the content of the ring */
666 *data = kmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
668 mutex_unlock(&rdev->ring_lock);
671 for (i = 0; i < size; ++i) {
672 (*data)[i] = ring->ring[ptr++];
673 ptr &= ring->ptr_mask;
676 mutex_unlock(&rdev->ring_lock);
681 * radeon_ring_restore - append saved commands to the ring again
683 * @rdev: radeon_device pointer
684 * @ring: ring to append commands to
685 * @size: number of dwords we want to write
686 * @data: saved commands
688 * Allocates space on the ring and restore the previously saved commands.
690 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
691 unsigned size, uint32_t *data)
698 /* restore the saved ring content */
699 r = radeon_ring_lock(rdev, ring, size);
703 for (i = 0; i < size; ++i) {
704 radeon_ring_write(ring, data[i]);
707 radeon_ring_unlock_commit(rdev, ring);
713 * radeon_ring_init - init driver ring struct.
715 * @rdev: radeon_device pointer
716 * @ring: radeon_ring structure holding ring information
717 * @ring_size: size of the ring
718 * @rptr_offs: offset of the rptr writeback location in the WB buffer
719 * @rptr_reg: MMIO offset of the rptr register
720 * @wptr_reg: MMIO offset of the wptr register
721 * @ptr_reg_shift: bit offset of the rptr/wptr values
722 * @ptr_reg_mask: bit mask of the rptr/wptr values
723 * @nop: nop packet for this ring
725 * Initialize the driver information for the selected ring (all asics).
726 * Returns 0 on success, error on failure.
728 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
729 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
730 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop)
734 ring->ring_size = ring_size;
735 ring->rptr_offs = rptr_offs;
736 ring->rptr_reg = rptr_reg;
737 ring->wptr_reg = wptr_reg;
738 ring->ptr_reg_shift = ptr_reg_shift;
739 ring->ptr_reg_mask = ptr_reg_mask;
741 /* Allocate ring buffer */
742 if (ring->ring_obj == NULL) {
743 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
744 RADEON_GEM_DOMAIN_GTT,
745 NULL, &ring->ring_obj);
747 dev_err(rdev->dev, "(%d) ring create failed\n", r);
750 r = radeon_bo_reserve(ring->ring_obj, false);
751 if (unlikely(r != 0))
753 r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
756 radeon_bo_unreserve(ring->ring_obj);
757 dev_err(rdev->dev, "(%d) ring pin failed\n", r);
760 r = radeon_bo_kmap(ring->ring_obj,
761 (void **)&ring->ring);
762 radeon_bo_unreserve(ring->ring_obj);
764 dev_err(rdev->dev, "(%d) ring map failed\n", r);
768 ring->ptr_mask = (ring->ring_size / 4) - 1;
769 ring->ring_free_dw = ring->ring_size / 4;
770 if (rdev->wb.enabled) {
771 u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);
772 ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;
773 ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];
775 if (radeon_debugfs_ring_init(rdev, ring)) {
776 DRM_ERROR("Failed to register debugfs file for rings !\n");
778 radeon_ring_lockup_update(ring);
783 * radeon_ring_fini - tear down the driver ring struct.
785 * @rdev: radeon_device pointer
786 * @ring: radeon_ring structure holding ring information
788 * Tear down the driver information for the selected ring (all asics).
790 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
793 struct radeon_bo *ring_obj;
795 mutex_lock(&rdev->ring_lock);
796 ring_obj = ring->ring_obj;
799 ring->ring_obj = NULL;
800 mutex_unlock(&rdev->ring_lock);
803 r = radeon_bo_reserve(ring_obj, false);
804 if (likely(r == 0)) {
805 radeon_bo_kunmap(ring_obj);
806 radeon_bo_unpin(ring_obj);
807 radeon_bo_unreserve(ring_obj);
809 radeon_bo_unref(&ring_obj);
816 #if defined(CONFIG_DEBUG_FS)
818 static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
820 struct drm_info_node *node = (struct drm_info_node *) m->private;
821 struct drm_device *dev = node->minor->dev;
822 struct radeon_device *rdev = dev->dev_private;
823 int ridx = *(int*)node->info_ent->data;
824 struct radeon_ring *ring = &rdev->ring[ridx];
825 unsigned count, i, j;
828 radeon_ring_free_size(rdev, ring);
829 count = (ring->ring_size / 4) - ring->ring_free_dw;
830 tmp = radeon_ring_get_wptr(rdev, ring);
831 seq_printf(m, "wptr(0x%04x): 0x%08x [%5d]\n", ring->wptr_reg, tmp, tmp);
832 tmp = radeon_ring_get_rptr(rdev, ring);
833 seq_printf(m, "rptr(0x%04x): 0x%08x [%5d]\n", ring->rptr_reg, tmp, tmp);
834 if (ring->rptr_save_reg) {
835 seq_printf(m, "rptr next(0x%04x): 0x%08x\n", ring->rptr_save_reg,
836 RREG32(ring->rptr_save_reg));
838 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n", ring->wptr, ring->wptr);
839 seq_printf(m, "driver's copy of the rptr: 0x%08x [%5d]\n", ring->rptr, ring->rptr);
840 seq_printf(m, "last semaphore signal addr : 0x%016llx\n", ring->last_semaphore_signal_addr);
841 seq_printf(m, "last semaphore wait addr : 0x%016llx\n", ring->last_semaphore_wait_addr);
842 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
843 seq_printf(m, "%u dwords in ring\n", count);
844 /* print 8 dw before current rptr as often it's the last executed
845 * packet that is the root issue
847 i = (ring->rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;
848 for (j = 0; j <= (count + 32); j++) {
849 seq_printf(m, "r[%5d]=0x%08x\n", i, ring->ring[i]);
850 i = (i + 1) & ring->ptr_mask;
855 static int radeon_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
856 static int cayman_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
857 static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
858 static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX;
859 static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
860 static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX;
862 static struct drm_info_list radeon_debugfs_ring_info_list[] = {
863 {"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index},
864 {"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_cp1_index},
865 {"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_cp2_index},
866 {"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index},
867 {"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index},
868 {"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index},
871 static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
873 struct drm_info_node *node = (struct drm_info_node *) m->private;
874 struct drm_device *dev = node->minor->dev;
875 struct radeon_device *rdev = dev->dev_private;
877 radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
883 static struct drm_info_list radeon_debugfs_sa_list[] = {
884 {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
889 static int radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)
891 #if defined(CONFIG_DEBUG_FS)
893 for (i = 0; i < ARRAY_SIZE(radeon_debugfs_ring_info_list); ++i) {
894 struct drm_info_list *info = &radeon_debugfs_ring_info_list[i];
895 int ridx = *(int*)radeon_debugfs_ring_info_list[i].data;
898 if (&rdev->ring[ridx] != ring)
901 r = radeon_debugfs_add_files(rdev, info, 1);
909 static int radeon_debugfs_sa_init(struct radeon_device *rdev)
911 #if defined(CONFIG_DEBUG_FS)
912 return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);