Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25 #include "avivod.h"
  26 #include "atom.h"
  27 #ifdef CONFIG_ACPI
  28 #include <linux/acpi.h>
  29 #endif
  30 #include <linux/power_supply.h>
  31 #include <linux/hwmon.h>
  32 #include <linux/hwmon-sysfs.h>
  33
  34 #define RADEON_IDLE_LOOP_MS 100
  35 #define RADEON_RECLOCK_DELAY_MS 200
  36 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  37 #define RADEON_WAIT_IDLE_TIMEOUT 200
  38
  39 static const char *radeon_pm_state_type_name[5] = {
  40         "Default",
  41         "Powersave",
  42         "Battery",
  43         "Balanced",
  44         "Performance",
  45 };
  46
  47 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  48 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  49 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  50 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  51 static void radeon_pm_update_profile(struct radeon_device *rdev);
  52 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  53
  54 #define ACPI_AC_CLASS           "ac_adapter"
  55
  56 int radeon_pm_get_type_index(struct radeon_device *rdev,
  57                              enum radeon_pm_state_type ps_type,
  58                              int instance)
  59 {
  60         int i;
  61         int found_instance = -1;
  62
  63         for (i = 0; i < rdev->pm.num_power_states; i++) {
  64                 if (rdev->pm.power_state[i].type == ps_type) {
  65                         found_instance++;
  66                         if (found_instance == instance)
  67                                 return i;
  68                 }
  69         }
  70         /* return default if no match */
  71         return rdev->pm.default_power_state_index;
  72 }
  73
  74 #ifdef CONFIG_ACPI
  75 static int radeon_acpi_event(struct notifier_block *nb,
  76                              unsigned long val,
  77                              void *data)
  78 {
  79         struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
  80         struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
  81
  82         if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
  83                 if (power_supply_is_system_supplied() > 0)
  84                         DRM_DEBUG_DRIVER("pm: AC\n");
  85                 else
  86                         DRM_DEBUG_DRIVER("pm: DC\n");
  87
  88                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  89                         if (rdev->pm.profile == PM_PROFILE_AUTO) {
  90                                 mutex_lock(&rdev->pm.mutex);
  91                                 radeon_pm_update_profile(rdev);
  92                                 radeon_pm_set_clocks(rdev);
  93                                 mutex_unlock(&rdev->pm.mutex);
  94                         }
  95                 }
  96         }
  97
  98         return NOTIFY_OK;
  99 }
 100 #endif
 101
 102 static void radeon_pm_update_profile(struct radeon_device *rdev)
 103 {
 104         switch (rdev->pm.profile) {
 105         case PM_PROFILE_DEFAULT:
 106                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
 107                 break;
 108         case PM_PROFILE_AUTO:
 109                 if (power_supply_is_system_supplied() > 0) {
 110                         if (rdev->pm.active_crtc_count > 1)
 111                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 112                         else
 113                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 114                 } else {
 115                         if (rdev->pm.active_crtc_count > 1)
 116                                 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 117                         else
 118                                 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 119                 }
 120                 break;
 121         case PM_PROFILE_LOW:
 122                 if (rdev->pm.active_crtc_count > 1)
 123                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
 124                 else
 125                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
 126                 break;
 127         case PM_PROFILE_MID:
 128                 if (rdev->pm.active_crtc_count > 1)
 129                         rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 130                 else
 131                         rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 132                 break;
 133         case PM_PROFILE_HIGH:
 134                 if (rdev->pm.active_crtc_count > 1)
 135                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 136                 else
 137                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 138                 break;
 139         }
 140
 141         if (rdev->pm.active_crtc_count == 0) {
 142                 rdev->pm.requested_power_state_index =
 143                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 144                 rdev->pm.requested_clock_mode_index =
 145                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 146         } else {
 147                 rdev->pm.requested_power_state_index =
 148                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 149                 rdev->pm.requested_clock_mode_index =
 150                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 151         }
 152 }
 153
 154 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 155 {
 156         struct radeon_bo *bo, *n;
 157
 158         if (list_empty(&rdev->gem.objects))
 159                 return;
 160
 161         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 162                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 163                         ttm_bo_unmap_virtual(&bo->tbo);
 164         }
 165 }
 166
 167 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 168 {
 169         if (rdev->pm.active_crtcs) {
 170                 rdev->pm.vblank_sync = false;
 171                 wait_event_timeout(
 172                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 173                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 174         }
 175 }
 176
 177 static void radeon_set_power_state(struct radeon_device *rdev)
 178 {
 179         u32 sclk, mclk;
 180         bool misc_after = false;
 181
 182         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 183             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 184                 return;
 185
 186         if (radeon_gui_idle(rdev)) {
 187                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 188                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 189                 if (sclk > rdev->pm.default_sclk)
 190                         sclk = rdev->pm.default_sclk;
 191
 192                 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 193                         clock_info[rdev->pm.requested_clock_mode_index].mclk;
 194                 if (mclk > rdev->pm.default_mclk)
 195                         mclk = rdev->pm.default_mclk;
 196
 197                 /* upvolt before raising clocks, downvolt after lowering clocks */
 198                 if (sclk < rdev->pm.current_sclk)
 199                         misc_after = true;
 200
 201                 radeon_sync_with_vblank(rdev);
 202
 203                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 204                         if (!radeon_pm_in_vbl(rdev))
 205                                 return;
 206                 }
 207
 208                 radeon_pm_prepare(rdev);
 209
 210                 if (!misc_after)
 211                         /* voltage, pcie lanes, etc.*/
 212                         radeon_pm_misc(rdev);
 213
 214                 /* set engine clock */
 215                 if (sclk != rdev->pm.current_sclk) {
 216                         radeon_pm_debug_check_in_vbl(rdev, false);
 217                         radeon_set_engine_clock(rdev, sclk);
 218                         radeon_pm_debug_check_in_vbl(rdev, true);
 219                         rdev->pm.current_sclk = sclk;
 220                         DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
 221                 }
 222
 223                 /* set memory clock */
 224                 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 225                         radeon_pm_debug_check_in_vbl(rdev, false);
 226                         radeon_set_memory_clock(rdev, mclk);
 227                         radeon_pm_debug_check_in_vbl(rdev, true);
 228                         rdev->pm.current_mclk = mclk;
 229                         DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
 230                 }
 231
 232                 if (misc_after)
 233                         /* voltage, pcie lanes, etc.*/
 234                         radeon_pm_misc(rdev);
 235
 236                 radeon_pm_finish(rdev);
 237
 238                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 239                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 240         } else
 241                 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
 242 }
 243
 244 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 245 {
 246         int i;
 247
 248         /* no need to take locks, etc. if nothing's going to change */
 249         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 250             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 251                 return;
 252
 253         mutex_lock(&rdev->ddev->struct_mutex);
 254         mutex_lock(&rdev->vram_mutex);
 255         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 256                 if (rdev->ring[i].ring_obj)
 257                         mutex_lock(&rdev->ring[i].mutex);
 258         }
 259
 260         /* gui idle int has issues on older chips it seems */
 261         if (rdev->family >= CHIP_R600) {
 262                 if (rdev->irq.installed) {
 263                         /* wait for GPU idle */
 264                         rdev->pm.gui_idle = false;
 265                         rdev->irq.gui_idle = true;
 266                         radeon_irq_set(rdev);
 267                         wait_event_interruptible_timeout(
 268                                 rdev->irq.idle_queue, rdev->pm.gui_idle,
 269                                 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
 270                         rdev->irq.gui_idle = false;
 271                         radeon_irq_set(rdev);
 272                 }
 273         } else {
 274                 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 275                 if (ring->ready) {
 276                         struct radeon_fence *fence;
 277                         radeon_ring_alloc(rdev, ring, 64);
 278                         radeon_fence_create(rdev, &fence, radeon_ring_index(rdev, ring));
 279                         radeon_fence_emit(rdev, fence);
 280                         radeon_ring_commit(rdev, ring);
 281                         radeon_fence_wait(fence, false);
 282                         radeon_fence_unref(&fence);
 283                 }
 284         }
 285         radeon_unmap_vram_bos(rdev);
 286
 287         if (rdev->irq.installed) {
 288                 for (i = 0; i < rdev->num_crtc; i++) {
 289                         if (rdev->pm.active_crtcs & (1 << i)) {
 290                                 rdev->pm.req_vblank |= (1 << i);
 291                                 drm_vblank_get(rdev->ddev, i);
 292                         }
 293                 }
 294         }
 295
 296         radeon_set_power_state(rdev);
 297
 298         if (rdev->irq.installed) {
 299                 for (i = 0; i < rdev->num_crtc; i++) {
 300                         if (rdev->pm.req_vblank & (1 << i)) {
 301                                 rdev->pm.req_vblank &= ~(1 << i);
 302                                 drm_vblank_put(rdev->ddev, i);
 303                         }
 304                 }
 305         }
 306
 307         /* update display watermarks based on new power state */
 308         radeon_update_bandwidth_info(rdev);
 309         if (rdev->pm.active_crtc_count)
 310                 radeon_bandwidth_update(rdev);
 311
 312         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 313
 314         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 315                 if (rdev->ring[i].ring_obj)
 316                         mutex_unlock(&rdev->ring[i].mutex);
 317         }
 318         mutex_unlock(&rdev->vram_mutex);
 319         mutex_unlock(&rdev->ddev->struct_mutex);
 320 }
 321
 322 static void radeon_pm_print_states(struct radeon_device *rdev)
 323 {
 324         int i, j;
 325         struct radeon_power_state *power_state;
 326         struct radeon_pm_clock_info *clock_info;
 327
 328         DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
 329         for (i = 0; i < rdev->pm.num_power_states; i++) {
 330                 power_state = &rdev->pm.power_state[i];
 331                 DRM_DEBUG_DRIVER("State %d: %s\n", i,
 332                         radeon_pm_state_type_name[power_state->type]);
 333                 if (i == rdev->pm.default_power_state_index)
 334                         DRM_DEBUG_DRIVER("\tDefault");
 335                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 336                         DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
 337                 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 338                         DRM_DEBUG_DRIVER("\tSingle display only\n");
 339                 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
 340                 for (j = 0; j < power_state->num_clock_modes; j++) {
 341                         clock_info = &(power_state->clock_info[j]);
 342                         if (rdev->flags & RADEON_IS_IGP)
 343                                 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
 344                                         j,
 345                                         clock_info->sclk * 10,
 346                                         clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
 347                         else
 348                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
 349                                         j,
 350                                         clock_info->sclk * 10,
 351                                         clock_info->mclk * 10,
 352                                         clock_info->voltage.voltage,
 353                                         clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
 354                 }
 355         }
 356 }
 357
 358 static ssize_t radeon_get_pm_profile(struct device *dev,
 359                                      struct device_attribute *attr,
 360                                      char *buf)
 361 {
 362         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 363         struct radeon_device *rdev = ddev->dev_private;
 364         int cp = rdev->pm.profile;
 365
 366         return snprintf(buf, PAGE_SIZE, "%s\n",
 367                         (cp == PM_PROFILE_AUTO) ? "auto" :
 368                         (cp == PM_PROFILE_LOW) ? "low" :
 369                         (cp == PM_PROFILE_MID) ? "mid" :
 370                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 371 }
 372
 373 static ssize_t radeon_set_pm_profile(struct device *dev,
 374                                      struct device_attribute *attr,
 375                                      const char *buf,
 376                                      size_t count)
 377 {
 378         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 379         struct radeon_device *rdev = ddev->dev_private;
 380
 381         mutex_lock(&rdev->pm.mutex);
 382         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 383                 if (strncmp("default", buf, strlen("default")) == 0)
 384                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 385                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 386                         rdev->pm.profile = PM_PROFILE_AUTO;
 387                 else if (strncmp("low", buf, strlen("low")) == 0)
 388                         rdev->pm.profile = PM_PROFILE_LOW;
 389                 else if (strncmp("mid", buf, strlen("mid")) == 0)
 390                         rdev->pm.profile = PM_PROFILE_MID;
 391                 else if (strncmp("high", buf, strlen("high")) == 0)
 392                         rdev->pm.profile = PM_PROFILE_HIGH;
 393                 else {
 394                         count = -EINVAL;
 395                         goto fail;
 396                 }
 397                 radeon_pm_update_profile(rdev);
 398                 radeon_pm_set_clocks(rdev);
 399         } else
 400                 count = -EINVAL;
 401
 402 fail:
 403         mutex_unlock(&rdev->pm.mutex);
 404
 405         return count;
 406 }
 407
 408 static ssize_t radeon_get_pm_method(struct device *dev,
 409                                     struct device_attribute *attr,
 410                                     char *buf)
 411 {
 412         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 413         struct radeon_device *rdev = ddev->dev_private;
 414         int pm = rdev->pm.pm_method;
 415
 416         return snprintf(buf, PAGE_SIZE, "%s\n",
 417                         (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
 418 }
 419
 420 static ssize_t radeon_set_pm_method(struct device *dev,
 421                                     struct device_attribute *attr,
 422                                     const char *buf,
 423                                     size_t count)
 424 {
 425         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 426         struct radeon_device *rdev = ddev->dev_private;
 427
 428
 429         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 430                 mutex_lock(&rdev->pm.mutex);
 431                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 432                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 433                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 434                 mutex_unlock(&rdev->pm.mutex);
 435         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 436                 mutex_lock(&rdev->pm.mutex);
 437                 /* disable dynpm */
 438                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 439                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 440                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 441                 mutex_unlock(&rdev->pm.mutex);
 442                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 443         } else {
 444                 count = -EINVAL;
 445                 goto fail;
 446         }
 447         radeon_pm_compute_clocks(rdev);
 448 fail:
 449         return count;
 450 }
 451
 452 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 453 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 454
 455 static ssize_t radeon_hwmon_show_temp(struct device *dev,
 456                                       struct device_attribute *attr,
 457                                       char *buf)
 458 {
 459         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 460         struct radeon_device *rdev = ddev->dev_private;
 461         int temp;
 462
 463         switch (rdev->pm.int_thermal_type) {
 464         case THERMAL_TYPE_RV6XX:
 465                 temp = rv6xx_get_temp(rdev);
 466                 break;
 467         case THERMAL_TYPE_RV770:
 468                 temp = rv770_get_temp(rdev);
 469                 break;
 470         case THERMAL_TYPE_EVERGREEN:
 471         case THERMAL_TYPE_NI:
 472                 temp = evergreen_get_temp(rdev);
 473                 break;
 474         case THERMAL_TYPE_SUMO:
 475                 temp = sumo_get_temp(rdev);
 476                 break;
 477         case THERMAL_TYPE_SI:
 478                 temp = si_get_temp(rdev);
 479                 break;
 480         default:
 481                 temp = 0;
 482                 break;
 483         }
 484
 485         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 486 }
 487
 488 static ssize_t radeon_hwmon_show_name(struct device *dev,
 489                                       struct device_attribute *attr,
 490                                       char *buf)
 491 {
 492         return sprintf(buf, "radeon\n");
 493 }
 494
 495 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
 496 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
 497
 498 static struct attribute *hwmon_attributes[] = {
 499         &sensor_dev_attr_temp1_input.dev_attr.attr,
 500         &sensor_dev_attr_name.dev_attr.attr,
 501         NULL
 502 };
 503
 504 static const struct attribute_group hwmon_attrgroup = {
 505         .attrs = hwmon_attributes,
 506 };
 507
 508 static int radeon_hwmon_init(struct radeon_device *rdev)
 509 {
 510         int err = 0;
 511
 512         rdev->pm.int_hwmon_dev = NULL;
 513
 514         switch (rdev->pm.int_thermal_type) {
 515         case THERMAL_TYPE_RV6XX:
 516         case THERMAL_TYPE_RV770:
 517         case THERMAL_TYPE_EVERGREEN:
 518         case THERMAL_TYPE_NI:
 519         case THERMAL_TYPE_SUMO:
 520         case THERMAL_TYPE_SI:
 521                 /* No support for TN yet */
 522                 if (rdev->family == CHIP_ARUBA)
 523                         return err;
 524                 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
 525                 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
 526                         err = PTR_ERR(rdev->pm.int_hwmon_dev);
 527                         dev_err(rdev->dev,
 528                                 "Unable to register hwmon device: %d\n", err);
 529                         break;
 530                 }
 531                 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
 532                 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
 533                                          &hwmon_attrgroup);
 534                 if (err) {
 535                         dev_err(rdev->dev,
 536                                 "Unable to create hwmon sysfs file: %d\n", err);
 537                         hwmon_device_unregister(rdev->dev);
 538                 }
 539                 break;
 540         default:
 541                 break;
 542         }
 543
 544         return err;
 545 }
 546
 547 static void radeon_hwmon_fini(struct radeon_device *rdev)
 548 {
 549         if (rdev->pm.int_hwmon_dev) {
 550                 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
 551                 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
 552         }
 553 }
 554
 555 void radeon_pm_suspend(struct radeon_device *rdev)
 556 {
 557         mutex_lock(&rdev->pm.mutex);
 558         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 559                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
 560                         rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
 561         }
 562         mutex_unlock(&rdev->pm.mutex);
 563
 564         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 565 }
 566
 567 void radeon_pm_resume(struct radeon_device *rdev)
 568 {
 569         /* set up the default clocks if the MC ucode is loaded */
 570         if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
 571                 if (rdev->pm.default_vddc)
 572                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 573                                                 SET_VOLTAGE_TYPE_ASIC_VDDC);
 574                 if (rdev->pm.default_vddci)
 575                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 576                                                 SET_VOLTAGE_TYPE_ASIC_VDDCI);
 577                 if (rdev->pm.default_sclk)
 578                         radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 579                 if (rdev->pm.default_mclk)
 580                         radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 581         }
 582         /* asic init will reset the default power state */
 583         mutex_lock(&rdev->pm.mutex);
 584         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
 585         rdev->pm.current_clock_mode_index = 0;
 586         rdev->pm.current_sclk = rdev->pm.default_sclk;
 587         rdev->pm.current_mclk = rdev->pm.default_mclk;
 588         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
 589         rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
 590         if (rdev->pm.pm_method == PM_METHOD_DYNPM
 591             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
 592                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 593                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 594                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 595         }
 596         mutex_unlock(&rdev->pm.mutex);
 597         radeon_pm_compute_clocks(rdev);
 598 }
 599
 600 int radeon_pm_init(struct radeon_device *rdev)
 601 {
 602         int ret;
 603
 604         /* default to profile method */
 605         rdev->pm.pm_method = PM_METHOD_PROFILE;
 606         rdev->pm.profile = PM_PROFILE_DEFAULT;
 607         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 608         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 609         rdev->pm.dynpm_can_upclock = true;
 610         rdev->pm.dynpm_can_downclock = true;
 611         rdev->pm.default_sclk = rdev->clock.default_sclk;
 612         rdev->pm.default_mclk = rdev->clock.default_mclk;
 613         rdev->pm.current_sclk = rdev->clock.default_sclk;
 614         rdev->pm.current_mclk = rdev->clock.default_mclk;
 615         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
 616
 617         if (rdev->bios) {
 618                 if (rdev->is_atom_bios)
 619                         radeon_atombios_get_power_modes(rdev);
 620                 else
 621                         radeon_combios_get_power_modes(rdev);
 622                 radeon_pm_print_states(rdev);
 623                 radeon_pm_init_profile(rdev);
 624                 /* set up the default clocks if the MC ucode is loaded */
 625                 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
 626                         if (rdev->pm.default_vddc)
 627                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 628                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
 629                         if (rdev->pm.default_vddci)
 630                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 631                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
 632                         if (rdev->pm.default_sclk)
 633                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 634                         if (rdev->pm.default_mclk)
 635                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 636                 }
 637         }
 638
 639         /* set up the internal thermal sensor if applicable */
 640         ret = radeon_hwmon_init(rdev);
 641         if (ret)
 642                 return ret;
 643
 644         INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
 645
 646         if (rdev->pm.num_power_states > 1) {
 647                 /* where's the best place to put these? */
 648                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
 649                 if (ret)
 650                         DRM_ERROR("failed to create device file for power profile\n");
 651                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
 652                 if (ret)
 653                         DRM_ERROR("failed to create device file for power method\n");
 654
 655 #ifdef CONFIG_ACPI
 656                 rdev->acpi_nb.notifier_call = radeon_acpi_event;
 657                 register_acpi_notifier(&rdev->acpi_nb);
 658 #endif
 659                 if (radeon_debugfs_pm_init(rdev)) {
 660                         DRM_ERROR("Failed to register debugfs file for PM!\n");
 661                 }
 662
 663                 DRM_INFO("radeon: power management initialized\n");
 664         }
 665
 666         return 0;
 667 }
 668
 669 void radeon_pm_fini(struct radeon_device *rdev)
 670 {
 671         if (rdev->pm.num_power_states > 1) {
 672                 mutex_lock(&rdev->pm.mutex);
 673                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 674                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 675                         radeon_pm_update_profile(rdev);
 676                         radeon_pm_set_clocks(rdev);
 677                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 678                         /* reset default clocks */
 679                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 680                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 681                         radeon_pm_set_clocks(rdev);
 682                 }
 683                 mutex_unlock(&rdev->pm.mutex);
 684
 685                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 686
 687                 device_remove_file(rdev->dev, &dev_attr_power_profile);
 688                 device_remove_file(rdev->dev, &dev_attr_power_method);
 689 #ifdef CONFIG_ACPI
 690                 unregister_acpi_notifier(&rdev->acpi_nb);
 691 #endif
 692         }
 693
 694         if (rdev->pm.power_state)
 695                 kfree(rdev->pm.power_state);
 696
 697         radeon_hwmon_fini(rdev);
 698 }
 699
 700 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 701 {
 702         struct drm_device *ddev = rdev->ddev;
 703         struct drm_crtc *crtc;
 704         struct radeon_crtc *radeon_crtc;
 705
 706         if (rdev->pm.num_power_states < 2)
 707                 return;
 708
 709         mutex_lock(&rdev->pm.mutex);
 710
 711         rdev->pm.active_crtcs = 0;
 712         rdev->pm.active_crtc_count = 0;
 713         list_for_each_entry(crtc,
 714                 &ddev->mode_config.crtc_list, head) {
 715                 radeon_crtc = to_radeon_crtc(crtc);
 716                 if (radeon_crtc->enabled) {
 717                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 718                         rdev->pm.active_crtc_count++;
 719                 }
 720         }
 721
 722         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 723                 radeon_pm_update_profile(rdev);
 724                 radeon_pm_set_clocks(rdev);
 725         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 726                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
 727                         if (rdev->pm.active_crtc_count > 1) {
 728                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 729                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 730
 731                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 732                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 733                                         radeon_pm_get_dynpm_state(rdev);
 734                                         radeon_pm_set_clocks(rdev);
 735
 736                                         DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
 737                                 }
 738                         } else if (rdev->pm.active_crtc_count == 1) {
 739                                 /* TODO: Increase clocks if needed for current mode */
 740
 741                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
 742                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 743                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
 744                                         radeon_pm_get_dynpm_state(rdev);
 745                                         radeon_pm_set_clocks(rdev);
 746
 747                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 748                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 749                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
 750                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 751                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 752                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 753                                         DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
 754                                 }
 755                         } else { /* count == 0 */
 756                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
 757                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 758
 759                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
 760                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
 761                                         radeon_pm_get_dynpm_state(rdev);
 762                                         radeon_pm_set_clocks(rdev);
 763                                 }
 764                         }
 765                 }
 766         }
 767
 768         mutex_unlock(&rdev->pm.mutex);
 769 }
 770
 771 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
 772 {
 773         int  crtc, vpos, hpos, vbl_status;
 774         bool in_vbl = true;
 775
 776         /* Iterate over all active crtc's. All crtc's must be in vblank,
 777          * otherwise return in_vbl == false.
 778          */
 779         for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
 780                 if (rdev->pm.active_crtcs & (1 << crtc)) {
 781                         vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
 782                         if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
 783                             !(vbl_status & DRM_SCANOUTPOS_INVBL))
 784                                 in_vbl = false;
 785                 }
 786         }
 787
 788         return in_vbl;
 789 }
 790
 791 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 792 {
 793         u32 stat_crtc = 0;
 794         bool in_vbl = radeon_pm_in_vbl(rdev);
 795
 796         if (in_vbl == false)
 797                 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
 798                          finish ? "exit" : "entry");
 799         return in_vbl;
 800 }
 801
 802 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
 803 {
 804         struct radeon_device *rdev;
 805         int resched;
 806         rdev = container_of(work, struct radeon_device,
 807                                 pm.dynpm_idle_work.work);
 808
 809         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 810         mutex_lock(&rdev->pm.mutex);
 811         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 812                 int not_processed = 0;
 813                 int i;
 814
 815                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 816                         not_processed += radeon_fence_count_emitted(rdev, i);
 817                         if (not_processed >= 3)
 818                                 break;
 819                 }
 820
 821                 if (not_processed >= 3) { /* should upclock */
 822                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
 823                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 824                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 825                                    rdev->pm.dynpm_can_upclock) {
 826                                 rdev->pm.dynpm_planned_action =
 827                                         DYNPM_ACTION_UPCLOCK;
 828                                 rdev->pm.dynpm_action_timeout = jiffies +
 829                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 830                         }
 831                 } else if (not_processed == 0) { /* should downclock */
 832                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
 833                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 834                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 835                                    rdev->pm.dynpm_can_downclock) {
 836                                 rdev->pm.dynpm_planned_action =
 837                                         DYNPM_ACTION_DOWNCLOCK;
 838                                 rdev->pm.dynpm_action_timeout = jiffies +
 839                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 840                         }
 841                 }
 842
 843                 /* Note, radeon_pm_set_clocks is called with static_switch set
 844                  * to false since we want to wait for vbl to avoid flicker.
 845                  */
 846                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
 847                     jiffies > rdev->pm.dynpm_action_timeout) {
 848                         radeon_pm_get_dynpm_state(rdev);
 849                         radeon_pm_set_clocks(rdev);
 850                 }
 851
 852                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 853                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 854         }
 855         mutex_unlock(&rdev->pm.mutex);
 856         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
 857 }
 858
 859 /*
 860  * Debugfs info
 861  */
 862 #if defined(CONFIG_DEBUG_FS)
 863
 864 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 865 {
 866         struct drm_info_node *node = (struct drm_info_node *) m->private;
 867         struct drm_device *dev = node->minor->dev;
 868         struct radeon_device *rdev = dev->dev_private;
 869
 870         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
 871         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 872         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
 873         if (rdev->asic->pm.get_memory_clock)
 874                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 875         if (rdev->pm.current_vddc)
 876                 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
 877         if (rdev->asic->pm.get_pcie_lanes)
 878                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 879
 880         return 0;
 881 }
 882
 883 static struct drm_info_list radeon_pm_info_list[] = {
 884         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 885 };
 886 #endif
 887
 888 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 889 {
 890 #if defined(CONFIG_DEBUG_FS)
 891         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 892 #else
 893         return 0;
 894 #endif
 895 }