Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/radeon_legacy_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
  33 {
  34         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  35         struct drm_encoder_helper_funcs *encoder_funcs;
  36
  37         encoder_funcs = encoder->helper_private;
  38         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  39         radeon_encoder->active_device = 0;
  40 }
  41
  42 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
  43 {
  44         struct drm_device *dev = encoder->dev;
  45         struct radeon_device *rdev = dev->dev_private;
  46         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  47         uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
  48         int panel_pwr_delay = 2000;
  49         DRM_DEBUG("\n");
  50
  51         if (radeon_encoder->enc_priv) {
  52                 if (rdev->is_atom_bios) {
  53                         struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  54                         panel_pwr_delay = lvds->panel_pwr_delay;
  55                 } else {
  56                         struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  57                         panel_pwr_delay = lvds->panel_pwr_delay;
  58                 }
  59         }
  60
  61         switch (mode) {
  62         case DRM_MODE_DPMS_ON:
  63                 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
  64                 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
  65                 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
  66                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  67                 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
  68                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  69                 udelay(1000);
  70
  71                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  72                 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
  73                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  74
  75                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  76                 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
  77                 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
  78                 udelay(panel_pwr_delay * 1000);
  79                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  80                 break;
  81         case DRM_MODE_DPMS_STANDBY:
  82         case DRM_MODE_DPMS_SUSPEND:
  83         case DRM_MODE_DPMS_OFF:
  84                 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
  85                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
  86                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  87                 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
  88                 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
  89                 udelay(panel_pwr_delay * 1000);
  90                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  91                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
  92                 break;
  93         }
  94
  95         if (rdev->is_atom_bios)
  96                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  97         else
  98                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  99 }
 100
 101 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
 102 {
 103         struct radeon_device *rdev = encoder->dev->dev_private;
 104
 105         if (rdev->is_atom_bios)
 106                 radeon_atom_output_lock(encoder, true);
 107         else
 108                 radeon_combios_output_lock(encoder, true);
 109         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
 110 }
 111
 112 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
 113 {
 114         struct radeon_device *rdev = encoder->dev->dev_private;
 115
 116         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
 117         if (rdev->is_atom_bios)
 118                 radeon_atom_output_lock(encoder, false);
 119         else
 120                 radeon_combios_output_lock(encoder, false);
 121 }
 122
 123 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
 124                                         struct drm_display_mode *mode,
 125                                         struct drm_display_mode *adjusted_mode)
 126 {
 127         struct drm_device *dev = encoder->dev;
 128         struct radeon_device *rdev = dev->dev_private;
 129         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 130         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 131         uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
 132
 133         DRM_DEBUG("\n");
 134
 135         lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
 136         lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
 137
 138         lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
 139         if ((!rdev->is_atom_bios)) {
 140                 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 141                 if (lvds) {
 142                         DRM_DEBUG("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
 143                         lvds_gen_cntl = lvds->lvds_gen_cntl;
 144                         lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 145                                               (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 146                         lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 147                                              (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 148                 } else
 149                         lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 150         } else
 151                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 152         lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 153         lvds_gen_cntl &= ~(RADEON_LVDS_ON |
 154                            RADEON_LVDS_BLON |
 155                            RADEON_LVDS_EN |
 156                            RADEON_LVDS_RST_FM);
 157
 158         if (ASIC_IS_R300(rdev))
 159                 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
 160
 161         if (radeon_crtc->crtc_id == 0) {
 162                 if (ASIC_IS_R300(rdev)) {
 163                         if (radeon_encoder->rmx_type != RMX_OFF)
 164                                 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
 165                 } else
 166                         lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
 167         } else {
 168                 if (ASIC_IS_R300(rdev))
 169                         lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
 170                 else
 171                         lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
 172         }
 173
 174         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 175         WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 176         WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
 177
 178         if (rdev->family == CHIP_RV410)
 179                 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
 180
 181         if (rdev->is_atom_bios)
 182                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 183         else
 184                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 185 }
 186
 187 static bool radeon_legacy_lvds_mode_fixup(struct drm_encoder *encoder,
 188                                           struct drm_display_mode *mode,
 189                                           struct drm_display_mode *adjusted_mode)
 190 {
 191         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 192
 193         /* set the active encoder to connector routing */
 194         radeon_encoder_set_active_device(encoder);
 195         drm_mode_set_crtcinfo(adjusted_mode, 0);
 196
 197         if (radeon_encoder->rmx_type != RMX_OFF)
 198                 radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
 199
 200         return true;
 201 }
 202
 203 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
 204         .dpms = radeon_legacy_lvds_dpms,
 205         .mode_fixup = radeon_legacy_lvds_mode_fixup,
 206         .prepare = radeon_legacy_lvds_prepare,
 207         .mode_set = radeon_legacy_lvds_mode_set,
 208         .commit = radeon_legacy_lvds_commit,
 209         .disable = radeon_legacy_encoder_disable,
 210 };
 211
 212
 213 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
 214         .destroy = radeon_enc_destroy,
 215 };
 216
 217 static bool radeon_legacy_primary_dac_mode_fixup(struct drm_encoder *encoder,
 218                                                  struct drm_display_mode *mode,
 219                                                  struct drm_display_mode *adjusted_mode)
 220 {
 221         /* set the active encoder to connector routing */
 222         radeon_encoder_set_active_device(encoder);
 223         drm_mode_set_crtcinfo(adjusted_mode, 0);
 224
 225         return true;
 226 }
 227
 228 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
 229 {
 230         struct drm_device *dev = encoder->dev;
 231         struct radeon_device *rdev = dev->dev_private;
 232         uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 233         uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
 234         uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 235
 236         DRM_DEBUG("\n");
 237
 238         switch (mode) {
 239         case DRM_MODE_DPMS_ON:
 240                 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
 241                 dac_cntl &= ~RADEON_DAC_PDWN;
 242                 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
 243                                     RADEON_DAC_PDWN_G |
 244                                     RADEON_DAC_PDWN_B);
 245                 break;
 246         case DRM_MODE_DPMS_STANDBY:
 247         case DRM_MODE_DPMS_SUSPEND:
 248         case DRM_MODE_DPMS_OFF:
 249                 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
 250                 dac_cntl |= RADEON_DAC_PDWN;
 251                 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
 252                                    RADEON_DAC_PDWN_G |
 253                                    RADEON_DAC_PDWN_B);
 254                 break;
 255         }
 256
 257         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 258         WREG32(RADEON_DAC_CNTL, dac_cntl);
 259         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 260
 261         if (rdev->is_atom_bios)
 262                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 263         else
 264                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 265 }
 266
 267 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
 268 {
 269         struct radeon_device *rdev = encoder->dev->dev_private;
 270
 271         if (rdev->is_atom_bios)
 272                 radeon_atom_output_lock(encoder, true);
 273         else
 274                 radeon_combios_output_lock(encoder, true);
 275         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 276 }
 277
 278 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
 279 {
 280         struct radeon_device *rdev = encoder->dev->dev_private;
 281
 282         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 283
 284         if (rdev->is_atom_bios)
 285                 radeon_atom_output_lock(encoder, false);
 286         else
 287                 radeon_combios_output_lock(encoder, false);
 288 }
 289
 290 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
 291                                                struct drm_display_mode *mode,
 292                                                struct drm_display_mode *adjusted_mode)
 293 {
 294         struct drm_device *dev = encoder->dev;
 295         struct radeon_device *rdev = dev->dev_private;
 296         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 297         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 298         uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
 299
 300         DRM_DEBUG("\n");
 301
 302         if (radeon_crtc->crtc_id == 0) {
 303                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
 304                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
 305                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 306                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 307                 } else {
 308                         dac2_cntl = RREG32(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
 309                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 310                 }
 311         } else {
 312                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
 313                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
 314                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 315                         disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
 316                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 317                 } else {
 318                         dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
 319                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 320                 }
 321         }
 322
 323         dac_cntl = (RADEON_DAC_MASK_ALL |
 324                     RADEON_DAC_VGA_ADR_EN |
 325                     /* TODO 6-bits */
 326                     RADEON_DAC_8BIT_EN);
 327
 328         WREG32_P(RADEON_DAC_CNTL,
 329                        dac_cntl,
 330                        RADEON_DAC_RANGE_CNTL |
 331                        RADEON_DAC_BLANKING);
 332
 333         if (radeon_encoder->enc_priv) {
 334                 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
 335                 dac_macro_cntl = p_dac->ps2_pdac_adj;
 336         } else
 337                 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 338         dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
 339         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 340
 341         if (rdev->is_atom_bios)
 342                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 343         else
 344                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 345 }
 346
 347 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
 348                                                                   struct drm_connector *connector)
 349 {
 350         struct drm_device *dev = encoder->dev;
 351         struct radeon_device *rdev = dev->dev_private;
 352         uint32_t vclk_ecp_cntl, crtc_ext_cntl;
 353         uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
 354         enum drm_connector_status found = connector_status_disconnected;
 355         bool color = true;
 356
 357         /* save the regs we need */
 358         vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
 359         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 360         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
 361         dac_cntl = RREG32(RADEON_DAC_CNTL);
 362         dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 363
 364         tmp = vclk_ecp_cntl &
 365                 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
 366         WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
 367
 368         tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
 369         WREG32(RADEON_CRTC_EXT_CNTL, tmp);
 370
 371         tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
 372                 RADEON_DAC_FORCE_DATA_EN;
 373
 374         if (color)
 375                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
 376         else
 377                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
 378
 379         if (ASIC_IS_R300(rdev))
 380                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
 381         else
 382                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
 383
 384         WREG32(RADEON_DAC_EXT_CNTL, tmp);
 385
 386         tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
 387         tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
 388         WREG32(RADEON_DAC_CNTL, tmp);
 389
 390         tmp &= ~(RADEON_DAC_PDWN_R |
 391                  RADEON_DAC_PDWN_G |
 392                  RADEON_DAC_PDWN_B);
 393
 394         WREG32(RADEON_DAC_MACRO_CNTL, tmp);
 395
 396         udelay(2000);
 397
 398         if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
 399                 found = connector_status_connected;
 400
 401         /* restore the regs we used */
 402         WREG32(RADEON_DAC_CNTL, dac_cntl);
 403         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 404         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
 405         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 406         WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
 407
 408         return found;
 409 }
 410
 411 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
 412         .dpms = radeon_legacy_primary_dac_dpms,
 413         .mode_fixup = radeon_legacy_primary_dac_mode_fixup,
 414         .prepare = radeon_legacy_primary_dac_prepare,
 415         .mode_set = radeon_legacy_primary_dac_mode_set,
 416         .commit = radeon_legacy_primary_dac_commit,
 417         .detect = radeon_legacy_primary_dac_detect,
 418         .disable = radeon_legacy_encoder_disable,
 419 };
 420
 421
 422 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
 423         .destroy = radeon_enc_destroy,
 424 };
 425
 426 static bool radeon_legacy_tmds_int_mode_fixup(struct drm_encoder *encoder,
 427                                               struct drm_display_mode *mode,
 428                                               struct drm_display_mode *adjusted_mode)
 429 {
 430
 431         drm_mode_set_crtcinfo(adjusted_mode, 0);
 432
 433         return true;
 434 }
 435
 436 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
 437 {
 438         struct drm_device *dev = encoder->dev;
 439         struct radeon_device *rdev = dev->dev_private;
 440         uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
 441         DRM_DEBUG("\n");
 442
 443         switch (mode) {
 444         case DRM_MODE_DPMS_ON:
 445                 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 446                 break;
 447         case DRM_MODE_DPMS_STANDBY:
 448         case DRM_MODE_DPMS_SUSPEND:
 449         case DRM_MODE_DPMS_OFF:
 450                 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 451                 break;
 452         }
 453
 454         WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 455
 456         if (rdev->is_atom_bios)
 457                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 458         else
 459                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 460 }
 461
 462 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
 463 {
 464         struct radeon_device *rdev = encoder->dev->dev_private;
 465
 466         if (rdev->is_atom_bios)
 467                 radeon_atom_output_lock(encoder, true);
 468         else
 469                 radeon_combios_output_lock(encoder, true);
 470         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
 471 }
 472
 473 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
 474 {
 475         struct radeon_device *rdev = encoder->dev->dev_private;
 476
 477         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
 478
 479         if (rdev->is_atom_bios)
 480                 radeon_atom_output_lock(encoder, true);
 481         else
 482                 radeon_combios_output_lock(encoder, true);
 483 }
 484
 485 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
 486                                             struct drm_display_mode *mode,
 487                                             struct drm_display_mode *adjusted_mode)
 488 {
 489         struct drm_device *dev = encoder->dev;
 490         struct radeon_device *rdev = dev->dev_private;
 491         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 492         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 493         uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
 494         int i;
 495
 496         DRM_DEBUG("\n");
 497
 498         tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
 499         tmp &= 0xfffff;
 500         if (rdev->family == CHIP_RV280) {
 501                 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
 502                 tmp ^= (1 << 22);
 503                 tmds_pll_cntl ^= (1 << 22);
 504         }
 505
 506         if (radeon_encoder->enc_priv) {
 507                 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
 508
 509                 for (i = 0; i < 4; i++) {
 510                         if (tmds->tmds_pll[i].freq == 0)
 511                                 break;
 512                         if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
 513                                 tmp = tmds->tmds_pll[i].value ;
 514                                 break;
 515                         }
 516                 }
 517         }
 518
 519         if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
 520                 if (tmp & 0xfff00000)
 521                         tmds_pll_cntl = tmp;
 522                 else {
 523                         tmds_pll_cntl &= 0xfff00000;
 524                         tmds_pll_cntl |= tmp;
 525                 }
 526         } else
 527                 tmds_pll_cntl = tmp;
 528
 529         tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
 530                 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
 531
 532     if (rdev->family == CHIP_R200 ||
 533         rdev->family == CHIP_R100 ||
 534         ASIC_IS_R300(rdev))
 535             tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
 536     else /* RV chips got this bit reversed */
 537             tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
 538
 539     fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
 540                    (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
 541                     RADEON_FP_CRTC_DONT_SHADOW_HEND));
 542
 543     fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 544
 545     fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
 546                      RADEON_FP_DFP_SYNC_SEL |
 547                      RADEON_FP_CRT_SYNC_SEL |
 548                      RADEON_FP_CRTC_LOCK_8DOT |
 549                      RADEON_FP_USE_SHADOW_EN |
 550                      RADEON_FP_CRTC_USE_SHADOW_VEND |
 551                      RADEON_FP_CRT_SYNC_ALT);
 552
 553     if (1) /*  FIXME rgbBits == 8 */
 554             fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
 555     else
 556             fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
 557
 558     if (radeon_crtc->crtc_id == 0) {
 559             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
 560                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 561                     if (radeon_encoder->rmx_type != RMX_OFF)
 562                             fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
 563                     else
 564                             fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
 565             } else
 566                     fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
 567     } else {
 568             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
 569                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 570                     fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
 571             } else
 572                     fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
 573     }
 574
 575     WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
 576     WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
 577     WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 578
 579         if (rdev->is_atom_bios)
 580                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 581         else
 582                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 583 }
 584
 585 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
 586         .dpms = radeon_legacy_tmds_int_dpms,
 587         .mode_fixup = radeon_legacy_tmds_int_mode_fixup,
 588         .prepare = radeon_legacy_tmds_int_prepare,
 589         .mode_set = radeon_legacy_tmds_int_mode_set,
 590         .commit = radeon_legacy_tmds_int_commit,
 591         .disable = radeon_legacy_encoder_disable,
 592 };
 593
 594
 595 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
 596         .destroy = radeon_enc_destroy,
 597 };
 598
 599 static bool radeon_legacy_tmds_ext_mode_fixup(struct drm_encoder *encoder,
 600                                               struct drm_display_mode *mode,
 601                                               struct drm_display_mode *adjusted_mode)
 602 {
 603         /* set the active encoder to connector routing */
 604         radeon_encoder_set_active_device(encoder);
 605         drm_mode_set_crtcinfo(adjusted_mode, 0);
 606
 607         return true;
 608 }
 609
 610 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
 611 {
 612         struct drm_device *dev = encoder->dev;
 613         struct radeon_device *rdev = dev->dev_private;
 614         uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 615         DRM_DEBUG("\n");
 616
 617         switch (mode) {
 618         case DRM_MODE_DPMS_ON:
 619                 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
 620                 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 621                 break;
 622         case DRM_MODE_DPMS_STANDBY:
 623         case DRM_MODE_DPMS_SUSPEND:
 624         case DRM_MODE_DPMS_OFF:
 625                 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
 626                 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 627                 break;
 628         }
 629
 630         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 631
 632         if (rdev->is_atom_bios)
 633                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 634         else
 635                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 636 }
 637
 638 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
 639 {
 640         struct radeon_device *rdev = encoder->dev->dev_private;
 641
 642         if (rdev->is_atom_bios)
 643                 radeon_atom_output_lock(encoder, true);
 644         else
 645                 radeon_combios_output_lock(encoder, true);
 646         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
 647 }
 648
 649 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
 650 {
 651         struct radeon_device *rdev = encoder->dev->dev_private;
 652         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
 653
 654         if (rdev->is_atom_bios)
 655                 radeon_atom_output_lock(encoder, false);
 656         else
 657                 radeon_combios_output_lock(encoder, false);
 658 }
 659
 660 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
 661                                             struct drm_display_mode *mode,
 662                                             struct drm_display_mode *adjusted_mode)
 663 {
 664         struct drm_device *dev = encoder->dev;
 665         struct radeon_device *rdev = dev->dev_private;
 666         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 667         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 668         uint32_t fp2_gen_cntl;
 669
 670         DRM_DEBUG("\n");
 671
 672         if (rdev->is_atom_bios) {
 673                 radeon_encoder->pixel_clock = adjusted_mode->clock;
 674                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
 675                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 676         } else {
 677                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 678
 679                 if (1) /*  FIXME rgbBits == 8 */
 680                         fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
 681                 else
 682                         fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
 683
 684                 fp2_gen_cntl &= ~(RADEON_FP2_ON |
 685                                   RADEON_FP2_DVO_EN |
 686                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 687
 688                 /* XXX: these are oem specific */
 689                 if (ASIC_IS_R300(rdev)) {
 690                         if ((dev->pdev->device == 0x4850) &&
 691                             (dev->pdev->subsystem_vendor == 0x1028) &&
 692                             (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
 693                                 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
 694                         else
 695                                 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
 696
 697                         /*if (mode->clock > 165000)
 698                           fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
 699                 }
 700                 if (!radeon_combios_external_tmds_setup(encoder))
 701                         radeon_external_tmds_setup(encoder);
 702         }
 703
 704         if (radeon_crtc->crtc_id == 0) {
 705                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
 706                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 707                         if (radeon_encoder->rmx_type != RMX_OFF)
 708                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
 709                         else
 710                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
 711                 } else
 712                         fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
 713         } else {
 714                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
 715                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 716                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 717                 } else
 718                         fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
 719         }
 720
 721         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 722
 723         if (rdev->is_atom_bios)
 724                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 725         else
 726                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 727 }
 728
 729 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
 730 {
 731         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 732         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
 733         if (tmds) {
 734                 if (tmds->i2c_bus)
 735                         radeon_i2c_destroy(tmds->i2c_bus);
 736         }
 737         kfree(radeon_encoder->enc_priv);
 738         drm_encoder_cleanup(encoder);
 739         kfree(radeon_encoder);
 740 }
 741
 742 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
 743         .dpms = radeon_legacy_tmds_ext_dpms,
 744         .mode_fixup = radeon_legacy_tmds_ext_mode_fixup,
 745         .prepare = radeon_legacy_tmds_ext_prepare,
 746         .mode_set = radeon_legacy_tmds_ext_mode_set,
 747         .commit = radeon_legacy_tmds_ext_commit,
 748         .disable = radeon_legacy_encoder_disable,
 749 };
 750
 751
 752 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
 753         .destroy = radeon_ext_tmds_enc_destroy,
 754 };
 755
 756 static bool radeon_legacy_tv_dac_mode_fixup(struct drm_encoder *encoder,
 757                                             struct drm_display_mode *mode,
 758                                             struct drm_display_mode *adjusted_mode)
 759 {
 760         /* set the active encoder to connector routing */
 761         radeon_encoder_set_active_device(encoder);
 762         drm_mode_set_crtcinfo(adjusted_mode, 0);
 763
 764         return true;
 765 }
 766
 767 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
 768 {
 769         struct drm_device *dev = encoder->dev;
 770         struct radeon_device *rdev = dev->dev_private;
 771         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 772         uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
 773         uint32_t tv_master_cntl = 0;
 774         bool is_tv;
 775         DRM_DEBUG("\n");
 776
 777         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
 778
 779         if (rdev->family == CHIP_R200)
 780                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 781         else {
 782                 if (is_tv)
 783                         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
 784                 else
 785                         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 786                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 787         }
 788
 789         switch (mode) {
 790         case DRM_MODE_DPMS_ON:
 791                 if (rdev->family == CHIP_R200) {
 792                         fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 793                 } else {
 794                         if (is_tv)
 795                                 tv_master_cntl |= RADEON_TV_ON;
 796                         else
 797                                 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
 798
 799                         if (rdev->family == CHIP_R420 ||
 800                             rdev->family == CHIP_R423 ||
 801                             rdev->family == CHIP_RV410)
 802                                 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
 803                                                  R420_TV_DAC_GDACPD |
 804                                                  R420_TV_DAC_BDACPD |
 805                                                  RADEON_TV_DAC_BGSLEEP);
 806                         else
 807                                 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
 808                                                  RADEON_TV_DAC_GDACPD |
 809                                                  RADEON_TV_DAC_BDACPD |
 810                                                  RADEON_TV_DAC_BGSLEEP);
 811                 }
 812                 break;
 813         case DRM_MODE_DPMS_STANDBY:
 814         case DRM_MODE_DPMS_SUSPEND:
 815         case DRM_MODE_DPMS_OFF:
 816                 if (rdev->family == CHIP_R200)
 817                         fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 818                 else {
 819                         if (is_tv)
 820                                 tv_master_cntl &= ~RADEON_TV_ON;
 821                         else
 822                                 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
 823
 824                         if (rdev->family == CHIP_R420 ||
 825                                         rdev->family == CHIP_R423 ||
 826                                         rdev->family == CHIP_RV410)
 827                                 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
 828                                                 R420_TV_DAC_GDACPD |
 829                                                 R420_TV_DAC_BDACPD |
 830                                                 RADEON_TV_DAC_BGSLEEP);
 831                         else
 832                                 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
 833                                                 RADEON_TV_DAC_GDACPD |
 834                                                 RADEON_TV_DAC_BDACPD |
 835                                                 RADEON_TV_DAC_BGSLEEP);
 836                 }
 837                 break;
 838         }
 839
 840         if (rdev->family == CHIP_R200) {
 841                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 842         } else {
 843                 if (is_tv)
 844                         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
 845                 else
 846                         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 847                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 848         }
 849
 850         if (rdev->is_atom_bios)
 851                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 852         else
 853                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 854 }
 855
 856 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
 857 {
 858         struct radeon_device *rdev = encoder->dev->dev_private;
 859
 860         if (rdev->is_atom_bios)
 861                 radeon_atom_output_lock(encoder, true);
 862         else
 863                 radeon_combios_output_lock(encoder, true);
 864         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 865 }
 866
 867 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
 868 {
 869         struct radeon_device *rdev = encoder->dev->dev_private;
 870
 871         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 872
 873         if (rdev->is_atom_bios)
 874                 radeon_atom_output_lock(encoder, true);
 875         else
 876                 radeon_combios_output_lock(encoder, true);
 877 }
 878
 879 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
 880                 struct drm_display_mode *mode,
 881                 struct drm_display_mode *adjusted_mode)
 882 {
 883         struct drm_device *dev = encoder->dev;
 884         struct radeon_device *rdev = dev->dev_private;
 885         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 886         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 887         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
 888         uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
 889         uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
 890         bool is_tv = false;
 891
 892         DRM_DEBUG("\n");
 893
 894         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
 895
 896         if (rdev->family != CHIP_R200) {
 897                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 898                 if (rdev->family == CHIP_R420 ||
 899                                 rdev->family == CHIP_R423 ||
 900                                 rdev->family == CHIP_RV410) {
 901                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
 902                                         RADEON_TV_DAC_BGADJ_MASK |
 903                                         R420_TV_DAC_DACADJ_MASK |
 904                                         R420_TV_DAC_RDACPD |
 905                                         R420_TV_DAC_GDACPD |
 906                                         R420_TV_DAC_BDACPD |
 907                                         R420_TV_DAC_TVENABLE);
 908                 } else {
 909                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
 910                                         RADEON_TV_DAC_BGADJ_MASK |
 911                                         RADEON_TV_DAC_DACADJ_MASK |
 912                                         RADEON_TV_DAC_RDACPD |
 913                                         RADEON_TV_DAC_GDACPD |
 914                                         RADEON_TV_DAC_BDACPD);
 915                 }
 916
 917                 /*  FIXME TV */
 918                 if (tv_dac) {
 919                         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
 920                         tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
 921                                         RADEON_TV_DAC_NHOLD |
 922                                         RADEON_TV_DAC_STD_PS2 |
 923                                         tv_dac->ps2_tvdac_adj);
 924                 } else
 925                         tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
 926                                         RADEON_TV_DAC_NHOLD |
 927                                         RADEON_TV_DAC_STD_PS2);
 928
 929                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 930         }
 931
 932         if (ASIC_IS_R300(rdev)) {
 933                 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
 934                 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
 935         }
 936
 937         if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev))
 938                 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
 939         else
 940                 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
 941
 942         if (rdev->family == CHIP_R200)
 943                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 944
 945         if (is_tv) {
 946                 uint32_t dac_cntl;
 947
 948                 dac_cntl = RREG32(RADEON_DAC_CNTL);
 949                 dac_cntl &= ~RADEON_DAC_TVO_EN;
 950                 WREG32(RADEON_DAC_CNTL, dac_cntl);
 951
 952                 if (ASIC_IS_R300(rdev))
 953                         gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
 954
 955                 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
 956                 if (radeon_crtc->crtc_id == 0) {
 957                         if (ASIC_IS_R300(rdev)) {
 958                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 959                                 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
 960                                                      RADEON_DISP_TV_SOURCE_CRTC);
 961                         }
 962                         if (rdev->family >= CHIP_R200) {
 963                                 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
 964                         } else {
 965                                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 966                         }
 967                 } else {
 968                         if (ASIC_IS_R300(rdev)) {
 969                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 970                                 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
 971                         }
 972                         if (rdev->family >= CHIP_R200) {
 973                                 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
 974                         } else {
 975                                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
 976                         }
 977                 }
 978                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 979         } else {
 980
 981                 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
 982
 983                 if (radeon_crtc->crtc_id == 0) {
 984                         if (ASIC_IS_R300(rdev)) {
 985                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 986                                 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
 987                         } else if (rdev->family == CHIP_R200) {
 988                                 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
 989                                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 990                         } else
 991                                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 992                 } else {
 993                         if (ASIC_IS_R300(rdev)) {
 994                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 995                                 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
 996                         } else if (rdev->family == CHIP_R200) {
 997                                 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
 998                                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 999                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1000                         } else
1001                                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1002                 }
1003                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1004         }
1005
1006         if (ASIC_IS_R300(rdev)) {
1007                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1008                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1009         }
1010
1011         if (rdev->family >= CHIP_R200)
1012                 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1013         else
1014                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1015
1016         if (rdev->family == CHIP_R200)
1017                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1018
1019         if (is_tv)
1020                 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1021
1022         if (rdev->is_atom_bios)
1023                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1024         else
1025                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1026
1027 }
1028
1029 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1030                                   struct drm_connector *connector)
1031 {
1032         struct drm_device *dev = encoder->dev;
1033         struct radeon_device *rdev = dev->dev_private;
1034         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1035         uint32_t disp_output_cntl, gpiopad_a, tmp;
1036         bool found = false;
1037
1038         /* save regs needed */
1039         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1040         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1041         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1042         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1043         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1044         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1045
1046         WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1047
1048         WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1049
1050         WREG32(RADEON_CRTC2_GEN_CNTL,
1051                RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1052
1053         tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1054         tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1055         WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1056
1057         WREG32(RADEON_DAC_EXT_CNTL,
1058                RADEON_DAC2_FORCE_BLANK_OFF_EN |
1059                RADEON_DAC2_FORCE_DATA_EN |
1060                RADEON_DAC_FORCE_DATA_SEL_RGB |
1061                (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1062
1063         WREG32(RADEON_TV_DAC_CNTL,
1064                RADEON_TV_DAC_STD_NTSC |
1065                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1066                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1067
1068         RREG32(RADEON_TV_DAC_CNTL);
1069         mdelay(4);
1070
1071         WREG32(RADEON_TV_DAC_CNTL,
1072                RADEON_TV_DAC_NBLANK |
1073                RADEON_TV_DAC_NHOLD |
1074                RADEON_TV_MONITOR_DETECT_EN |
1075                RADEON_TV_DAC_STD_NTSC |
1076                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1077                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1078
1079         RREG32(RADEON_TV_DAC_CNTL);
1080         mdelay(6);
1081
1082         tmp = RREG32(RADEON_TV_DAC_CNTL);
1083         if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1084                 found = true;
1085                 DRM_DEBUG("S-video TV connection detected\n");
1086         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1087                 found = true;
1088                 DRM_DEBUG("Composite TV connection detected\n");
1089         }
1090
1091         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1092         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1093         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1094         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1095         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1096         WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1097         return found;
1098 }
1099
1100 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1101                                     struct drm_connector *connector)
1102 {
1103         struct drm_device *dev = encoder->dev;
1104         struct radeon_device *rdev = dev->dev_private;
1105         uint32_t tv_dac_cntl, dac_cntl2;
1106         uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1107         bool found = false;
1108
1109         if (ASIC_IS_R300(rdev))
1110                 return r300_legacy_tv_detect(encoder, connector);
1111
1112         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1113         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1114         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1115         config_cntl = RREG32(RADEON_CONFIG_CNTL);
1116         tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1117
1118         tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1119         WREG32(RADEON_DAC_CNTL2, tmp);
1120
1121         tmp = tv_master_cntl | RADEON_TV_ON;
1122         tmp &= ~(RADEON_TV_ASYNC_RST |
1123                  RADEON_RESTART_PHASE_FIX |
1124                  RADEON_CRT_FIFO_CE_EN |
1125                  RADEON_TV_FIFO_CE_EN |
1126                  RADEON_RE_SYNC_NOW_SEL_MASK);
1127         tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1128         WREG32(RADEON_TV_MASTER_CNTL, tmp);
1129
1130         tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1131                 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1132                 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1133
1134         if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1135                 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1136         else
1137                 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1138         WREG32(RADEON_TV_DAC_CNTL, tmp);
1139
1140         tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1141                 RADEON_RED_MX_FORCE_DAC_DATA |
1142                 RADEON_GRN_MX_FORCE_DAC_DATA |
1143                 RADEON_BLU_MX_FORCE_DAC_DATA |
1144                 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1145         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1146
1147         mdelay(3);
1148         tmp = RREG32(RADEON_TV_DAC_CNTL);
1149         if (tmp & RADEON_TV_DAC_GDACDET) {
1150                 found = true;
1151                 DRM_DEBUG("S-video TV connection detected\n");
1152         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1153                 found = true;
1154                 DRM_DEBUG("Composite TV connection detected\n");
1155         }
1156
1157         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1158         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1159         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1160         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1161         return found;
1162 }
1163
1164 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1165                                                              struct drm_connector *connector)
1166 {
1167         struct drm_device *dev = encoder->dev;
1168         struct radeon_device *rdev = dev->dev_private;
1169         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1170         uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
1171         enum drm_connector_status found = connector_status_disconnected;
1172         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1173         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1174         bool color = true;
1175
1176         if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1177             connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1178             connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1179                 bool tv_detect;
1180
1181                 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1182                         return connector_status_disconnected;
1183
1184                 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1185                 if (tv_detect && tv_dac)
1186                         found = connector_status_connected;
1187                 return found;
1188         }
1189
1190         /* don't probe if the encoder is being used for something else not CRT related */
1191         if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1192                 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1193                 return connector_status_disconnected;
1194         }
1195
1196         /* save the regs we need */
1197         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1198         gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
1199         disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
1200         disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
1201         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1202         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1203         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1204         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1205
1206         tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1207                                | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1208         WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1209
1210         if (ASIC_IS_R300(rdev))
1211                 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1212
1213         tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1214         tmp |= RADEON_CRTC2_CRT2_ON |
1215                 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1216
1217         WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1218
1219         if (ASIC_IS_R300(rdev)) {
1220                 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1221                 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1222                 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1223         } else {
1224                 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1225                 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1226         }
1227
1228         tmp = RADEON_TV_DAC_NBLANK |
1229                 RADEON_TV_DAC_NHOLD |
1230                 RADEON_TV_MONITOR_DETECT_EN |
1231                 RADEON_TV_DAC_STD_PS2;
1232
1233         WREG32(RADEON_TV_DAC_CNTL, tmp);
1234
1235         tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1236                 RADEON_DAC2_FORCE_DATA_EN;
1237
1238         if (color)
1239                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1240         else
1241                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1242
1243         if (ASIC_IS_R300(rdev))
1244                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1245         else
1246                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1247
1248         WREG32(RADEON_DAC_EXT_CNTL, tmp);
1249
1250         tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1251         WREG32(RADEON_DAC_CNTL2, tmp);
1252
1253         udelay(10000);
1254
1255         if (ASIC_IS_R300(rdev)) {
1256                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1257                         found = connector_status_connected;
1258         } else {
1259                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1260                         found = connector_status_connected;
1261         }
1262
1263         /* restore regs we used */
1264         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1265         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1266         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1267         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1268
1269         if (ASIC_IS_R300(rdev)) {
1270                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1271                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1272         } else {
1273                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1274         }
1275         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1276
1277         return found;
1278
1279 }
1280
1281 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1282         .dpms = radeon_legacy_tv_dac_dpms,
1283         .mode_fixup = radeon_legacy_tv_dac_mode_fixup,
1284         .prepare = radeon_legacy_tv_dac_prepare,
1285         .mode_set = radeon_legacy_tv_dac_mode_set,
1286         .commit = radeon_legacy_tv_dac_commit,
1287         .detect = radeon_legacy_tv_dac_detect,
1288         .disable = radeon_legacy_encoder_disable,
1289 };
1290
1291
1292 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1293         .destroy = radeon_enc_destroy,
1294 };
1295
1296
1297 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1298 {
1299         struct drm_device *dev = encoder->base.dev;
1300         struct radeon_device *rdev = dev->dev_private;
1301         struct radeon_encoder_int_tmds *tmds = NULL;
1302         bool ret;
1303
1304         tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1305
1306         if (!tmds)
1307                 return NULL;
1308
1309         if (rdev->is_atom_bios)
1310                 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1311         else
1312                 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1313
1314         if (ret == false)
1315                 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1316
1317         return tmds;
1318 }
1319
1320 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1321 {
1322         struct drm_device *dev = encoder->base.dev;
1323         struct radeon_device *rdev = dev->dev_private;
1324         struct radeon_encoder_ext_tmds *tmds = NULL;
1325         bool ret;
1326
1327         if (rdev->is_atom_bios)
1328                 return NULL;
1329
1330         tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1331
1332         if (!tmds)
1333                 return NULL;
1334
1335         ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1336
1337         if (ret == false)
1338                 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1339
1340         return tmds;
1341 }
1342
1343 void
1344 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1345 {
1346         struct radeon_device *rdev = dev->dev_private;
1347         struct drm_encoder *encoder;
1348         struct radeon_encoder *radeon_encoder;
1349
1350         /* see if we already added it */
1351         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1352                 radeon_encoder = to_radeon_encoder(encoder);
1353                 if (radeon_encoder->encoder_id == encoder_id) {
1354                         radeon_encoder->devices |= supported_device;
1355                         return;
1356                 }
1357
1358         }
1359
1360         /* add a new one */
1361         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1362         if (!radeon_encoder)
1363                 return;
1364
1365         encoder = &radeon_encoder->base;
1366         if (rdev->flags & RADEON_SINGLE_CRTC)
1367                 encoder->possible_crtcs = 0x1;
1368         else
1369                 encoder->possible_crtcs = 0x3;
1370         encoder->possible_clones = 0;
1371
1372         radeon_encoder->enc_priv = NULL;
1373
1374         radeon_encoder->encoder_id = encoder_id;
1375         radeon_encoder->devices = supported_device;
1376         radeon_encoder->rmx_type = RMX_OFF;
1377
1378         switch (radeon_encoder->encoder_id) {
1379         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1380                 encoder->possible_crtcs = 0x1;
1381                 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1382                 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1383                 if (rdev->is_atom_bios)
1384                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1385                 else
1386                         radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1387                 radeon_encoder->rmx_type = RMX_FULL;
1388                 break;
1389         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1390                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1391                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1392                 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1393                 break;
1394         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1395                 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
1396                 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1397                 if (rdev->is_atom_bios)
1398                         radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1399                 else
1400                         radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1401                 break;
1402         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1403                 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1404                 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1405                 if (rdev->is_atom_bios)
1406                         radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1407                 else
1408                         radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1409                 break;
1410         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1411                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
1412                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1413                 if (!rdev->is_atom_bios)
1414                         radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1415                 break;
1416         }
1417 }