Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/radeon_legacy_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
  33 {
  34         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  35         struct drm_encoder_helper_funcs *encoder_funcs;
  36
  37         encoder_funcs = encoder->helper_private;
  38         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  39         radeon_encoder->active_device = 0;
  40 }
  41
  42 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
  43 {
  44         struct drm_device *dev = encoder->dev;
  45         struct radeon_device *rdev = dev->dev_private;
  46         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  47         uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
  48         int panel_pwr_delay = 2000;
  49         DRM_DEBUG("\n");
  50
  51         if (radeon_encoder->enc_priv) {
  52                 if (rdev->is_atom_bios) {
  53                         struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  54                         panel_pwr_delay = lvds->panel_pwr_delay;
  55                 } else {
  56                         struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  57                         panel_pwr_delay = lvds->panel_pwr_delay;
  58                 }
  59         }
  60
  61         switch (mode) {
  62         case DRM_MODE_DPMS_ON:
  63                 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
  64                 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
  65                 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
  66                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  67                 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
  68                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  69                 udelay(1000);
  70
  71                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  72                 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
  73                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  74
  75                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  76                 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
  77                 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
  78                 udelay(panel_pwr_delay * 1000);
  79                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  80                 break;
  81         case DRM_MODE_DPMS_STANDBY:
  82         case DRM_MODE_DPMS_SUSPEND:
  83         case DRM_MODE_DPMS_OFF:
  84                 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
  85                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
  86                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  87                 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
  88                 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
  89                 udelay(panel_pwr_delay * 1000);
  90                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  91                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
  92                 break;
  93         }
  94
  95         if (rdev->is_atom_bios)
  96                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  97         else
  98                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  99 }
 100
 101 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
 102 {
 103         struct radeon_device *rdev = encoder->dev->dev_private;
 104
 105         if (rdev->is_atom_bios)
 106                 radeon_atom_output_lock(encoder, true);
 107         else
 108                 radeon_combios_output_lock(encoder, true);
 109         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
 110 }
 111
 112 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
 113 {
 114         struct radeon_device *rdev = encoder->dev->dev_private;
 115
 116         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
 117         if (rdev->is_atom_bios)
 118                 radeon_atom_output_lock(encoder, false);
 119         else
 120                 radeon_combios_output_lock(encoder, false);
 121 }
 122
 123 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
 124                                         struct drm_display_mode *mode,
 125                                         struct drm_display_mode *adjusted_mode)
 126 {
 127         struct drm_device *dev = encoder->dev;
 128         struct radeon_device *rdev = dev->dev_private;
 129         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 130         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 131         uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
 132
 133         DRM_DEBUG("\n");
 134
 135         lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
 136         lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
 137
 138         lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
 139         if ((!rdev->is_atom_bios)) {
 140                 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 141                 if (lvds) {
 142                         DRM_DEBUG("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
 143                         lvds_gen_cntl = lvds->lvds_gen_cntl;
 144                         lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 145                                               (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 146                         lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 147                                              (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 148                 } else
 149                         lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 150         } else
 151                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 152         lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 153         lvds_gen_cntl &= ~(RADEON_LVDS_ON |
 154                            RADEON_LVDS_BLON |
 155                            RADEON_LVDS_EN |
 156                            RADEON_LVDS_RST_FM);
 157
 158         if (ASIC_IS_R300(rdev))
 159                 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
 160
 161         if (radeon_crtc->crtc_id == 0) {
 162                 if (ASIC_IS_R300(rdev)) {
 163                         if (radeon_encoder->rmx_type != RMX_OFF)
 164                                 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
 165                 } else
 166                         lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
 167         } else {
 168                 if (ASIC_IS_R300(rdev))
 169                         lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
 170                 else
 171                         lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
 172         }
 173
 174         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 175         WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 176         WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
 177
 178         if (rdev->family == CHIP_RV410)
 179                 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
 180
 181         if (rdev->is_atom_bios)
 182                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 183         else
 184                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 185 }
 186
 187 static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
 188                                      struct drm_display_mode *mode,
 189                                      struct drm_display_mode *adjusted_mode)
 190 {
 191         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 192
 193         /* set the active encoder to connector routing */
 194         radeon_encoder_set_active_device(encoder);
 195         drm_mode_set_crtcinfo(adjusted_mode, 0);
 196
 197         /* get the native mode for LVDS */
 198         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 199                 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 200                 int mode_id = adjusted_mode->base.id;
 201                 *adjusted_mode = *native_mode;
 202                 adjusted_mode->hdisplay = mode->hdisplay;
 203                 adjusted_mode->vdisplay = mode->vdisplay;
 204                 adjusted_mode->base.id = mode_id;
 205         }
 206
 207         return true;
 208 }
 209
 210 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
 211         .dpms = radeon_legacy_lvds_dpms,
 212         .mode_fixup = radeon_legacy_mode_fixup,
 213         .prepare = radeon_legacy_lvds_prepare,
 214         .mode_set = radeon_legacy_lvds_mode_set,
 215         .commit = radeon_legacy_lvds_commit,
 216         .disable = radeon_legacy_encoder_disable,
 217 };
 218
 219
 220 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
 221         .destroy = radeon_enc_destroy,
 222 };
 223
 224 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
 225 {
 226         struct drm_device *dev = encoder->dev;
 227         struct radeon_device *rdev = dev->dev_private;
 228         uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 229         uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
 230         uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 231
 232         DRM_DEBUG("\n");
 233
 234         switch (mode) {
 235         case DRM_MODE_DPMS_ON:
 236                 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
 237                 dac_cntl &= ~RADEON_DAC_PDWN;
 238                 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
 239                                     RADEON_DAC_PDWN_G |
 240                                     RADEON_DAC_PDWN_B);
 241                 break;
 242         case DRM_MODE_DPMS_STANDBY:
 243         case DRM_MODE_DPMS_SUSPEND:
 244         case DRM_MODE_DPMS_OFF:
 245                 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
 246                 dac_cntl |= RADEON_DAC_PDWN;
 247                 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
 248                                    RADEON_DAC_PDWN_G |
 249                                    RADEON_DAC_PDWN_B);
 250                 break;
 251         }
 252
 253         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 254         WREG32(RADEON_DAC_CNTL, dac_cntl);
 255         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 256
 257         if (rdev->is_atom_bios)
 258                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 259         else
 260                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 261 }
 262
 263 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
 264 {
 265         struct radeon_device *rdev = encoder->dev->dev_private;
 266
 267         if (rdev->is_atom_bios)
 268                 radeon_atom_output_lock(encoder, true);
 269         else
 270                 radeon_combios_output_lock(encoder, true);
 271         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 272 }
 273
 274 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
 275 {
 276         struct radeon_device *rdev = encoder->dev->dev_private;
 277
 278         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 279
 280         if (rdev->is_atom_bios)
 281                 radeon_atom_output_lock(encoder, false);
 282         else
 283                 radeon_combios_output_lock(encoder, false);
 284 }
 285
 286 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
 287                                                struct drm_display_mode *mode,
 288                                                struct drm_display_mode *adjusted_mode)
 289 {
 290         struct drm_device *dev = encoder->dev;
 291         struct radeon_device *rdev = dev->dev_private;
 292         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 293         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 294         uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
 295
 296         DRM_DEBUG("\n");
 297
 298         if (radeon_crtc->crtc_id == 0) {
 299                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
 300                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
 301                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 302                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 303                 } else {
 304                         dac2_cntl = RREG32(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
 305                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 306                 }
 307         } else {
 308                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
 309                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
 310                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 311                         disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
 312                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 313                 } else {
 314                         dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
 315                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 316                 }
 317         }
 318
 319         dac_cntl = (RADEON_DAC_MASK_ALL |
 320                     RADEON_DAC_VGA_ADR_EN |
 321                     /* TODO 6-bits */
 322                     RADEON_DAC_8BIT_EN);
 323
 324         WREG32_P(RADEON_DAC_CNTL,
 325                        dac_cntl,
 326                        RADEON_DAC_RANGE_CNTL |
 327                        RADEON_DAC_BLANKING);
 328
 329         if (radeon_encoder->enc_priv) {
 330                 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
 331                 dac_macro_cntl = p_dac->ps2_pdac_adj;
 332         } else
 333                 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 334         dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
 335         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 336
 337         if (rdev->is_atom_bios)
 338                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 339         else
 340                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 341 }
 342
 343 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
 344                                                                   struct drm_connector *connector)
 345 {
 346         struct drm_device *dev = encoder->dev;
 347         struct radeon_device *rdev = dev->dev_private;
 348         uint32_t vclk_ecp_cntl, crtc_ext_cntl;
 349         uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
 350         enum drm_connector_status found = connector_status_disconnected;
 351         bool color = true;
 352
 353         /* save the regs we need */
 354         vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
 355         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 356         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
 357         dac_cntl = RREG32(RADEON_DAC_CNTL);
 358         dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 359
 360         tmp = vclk_ecp_cntl &
 361                 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
 362         WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
 363
 364         tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
 365         WREG32(RADEON_CRTC_EXT_CNTL, tmp);
 366
 367         tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
 368                 RADEON_DAC_FORCE_DATA_EN;
 369
 370         if (color)
 371                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
 372         else
 373                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
 374
 375         if (ASIC_IS_R300(rdev))
 376                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
 377         else
 378                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
 379
 380         WREG32(RADEON_DAC_EXT_CNTL, tmp);
 381
 382         tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
 383         tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
 384         WREG32(RADEON_DAC_CNTL, tmp);
 385
 386         tmp &= ~(RADEON_DAC_PDWN_R |
 387                  RADEON_DAC_PDWN_G |
 388                  RADEON_DAC_PDWN_B);
 389
 390         WREG32(RADEON_DAC_MACRO_CNTL, tmp);
 391
 392         udelay(2000);
 393
 394         if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
 395                 found = connector_status_connected;
 396
 397         /* restore the regs we used */
 398         WREG32(RADEON_DAC_CNTL, dac_cntl);
 399         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 400         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
 401         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 402         WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
 403
 404         return found;
 405 }
 406
 407 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
 408         .dpms = radeon_legacy_primary_dac_dpms,
 409         .mode_fixup = radeon_legacy_mode_fixup,
 410         .prepare = radeon_legacy_primary_dac_prepare,
 411         .mode_set = radeon_legacy_primary_dac_mode_set,
 412         .commit = radeon_legacy_primary_dac_commit,
 413         .detect = radeon_legacy_primary_dac_detect,
 414         .disable = radeon_legacy_encoder_disable,
 415 };
 416
 417
 418 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
 419         .destroy = radeon_enc_destroy,
 420 };
 421
 422 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
 423 {
 424         struct drm_device *dev = encoder->dev;
 425         struct radeon_device *rdev = dev->dev_private;
 426         uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
 427         DRM_DEBUG("\n");
 428
 429         switch (mode) {
 430         case DRM_MODE_DPMS_ON:
 431                 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 432                 break;
 433         case DRM_MODE_DPMS_STANDBY:
 434         case DRM_MODE_DPMS_SUSPEND:
 435         case DRM_MODE_DPMS_OFF:
 436                 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 437                 break;
 438         }
 439
 440         WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 441
 442         if (rdev->is_atom_bios)
 443                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 444         else
 445                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 446 }
 447
 448 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
 449 {
 450         struct radeon_device *rdev = encoder->dev->dev_private;
 451
 452         if (rdev->is_atom_bios)
 453                 radeon_atom_output_lock(encoder, true);
 454         else
 455                 radeon_combios_output_lock(encoder, true);
 456         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
 457 }
 458
 459 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
 460 {
 461         struct radeon_device *rdev = encoder->dev->dev_private;
 462
 463         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
 464
 465         if (rdev->is_atom_bios)
 466                 radeon_atom_output_lock(encoder, true);
 467         else
 468                 radeon_combios_output_lock(encoder, true);
 469 }
 470
 471 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
 472                                             struct drm_display_mode *mode,
 473                                             struct drm_display_mode *adjusted_mode)
 474 {
 475         struct drm_device *dev = encoder->dev;
 476         struct radeon_device *rdev = dev->dev_private;
 477         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 478         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 479         uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
 480         int i;
 481
 482         DRM_DEBUG("\n");
 483
 484         tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
 485         tmp &= 0xfffff;
 486         if (rdev->family == CHIP_RV280) {
 487                 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
 488                 tmp ^= (1 << 22);
 489                 tmds_pll_cntl ^= (1 << 22);
 490         }
 491
 492         if (radeon_encoder->enc_priv) {
 493                 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
 494
 495                 for (i = 0; i < 4; i++) {
 496                         if (tmds->tmds_pll[i].freq == 0)
 497                                 break;
 498                         if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
 499                                 tmp = tmds->tmds_pll[i].value ;
 500                                 break;
 501                         }
 502                 }
 503         }
 504
 505         if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
 506                 if (tmp & 0xfff00000)
 507                         tmds_pll_cntl = tmp;
 508                 else {
 509                         tmds_pll_cntl &= 0xfff00000;
 510                         tmds_pll_cntl |= tmp;
 511                 }
 512         } else
 513                 tmds_pll_cntl = tmp;
 514
 515         tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
 516                 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
 517
 518     if (rdev->family == CHIP_R200 ||
 519         rdev->family == CHIP_R100 ||
 520         ASIC_IS_R300(rdev))
 521             tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
 522     else /* RV chips got this bit reversed */
 523             tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
 524
 525     fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
 526                    (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
 527                     RADEON_FP_CRTC_DONT_SHADOW_HEND));
 528
 529     fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 530
 531     fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
 532                      RADEON_FP_DFP_SYNC_SEL |
 533                      RADEON_FP_CRT_SYNC_SEL |
 534                      RADEON_FP_CRTC_LOCK_8DOT |
 535                      RADEON_FP_USE_SHADOW_EN |
 536                      RADEON_FP_CRTC_USE_SHADOW_VEND |
 537                      RADEON_FP_CRT_SYNC_ALT);
 538
 539     if (1) /*  FIXME rgbBits == 8 */
 540             fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
 541     else
 542             fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
 543
 544     if (radeon_crtc->crtc_id == 0) {
 545             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
 546                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 547                     if (radeon_encoder->rmx_type != RMX_OFF)
 548                             fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
 549                     else
 550                             fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
 551             } else
 552                     fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
 553     } else {
 554             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
 555                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 556                     fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
 557             } else
 558                     fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
 559     }
 560
 561     WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
 562     WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
 563     WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 564
 565         if (rdev->is_atom_bios)
 566                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 567         else
 568                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 569 }
 570
 571 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
 572         .dpms = radeon_legacy_tmds_int_dpms,
 573         .mode_fixup = radeon_legacy_mode_fixup,
 574         .prepare = radeon_legacy_tmds_int_prepare,
 575         .mode_set = radeon_legacy_tmds_int_mode_set,
 576         .commit = radeon_legacy_tmds_int_commit,
 577         .disable = radeon_legacy_encoder_disable,
 578 };
 579
 580
 581 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
 582         .destroy = radeon_enc_destroy,
 583 };
 584
 585 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
 586 {
 587         struct drm_device *dev = encoder->dev;
 588         struct radeon_device *rdev = dev->dev_private;
 589         uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 590         DRM_DEBUG("\n");
 591
 592         switch (mode) {
 593         case DRM_MODE_DPMS_ON:
 594                 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
 595                 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 596                 break;
 597         case DRM_MODE_DPMS_STANDBY:
 598         case DRM_MODE_DPMS_SUSPEND:
 599         case DRM_MODE_DPMS_OFF:
 600                 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
 601                 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 602                 break;
 603         }
 604
 605         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 606
 607         if (rdev->is_atom_bios)
 608                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 609         else
 610                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 611 }
 612
 613 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
 614 {
 615         struct radeon_device *rdev = encoder->dev->dev_private;
 616
 617         if (rdev->is_atom_bios)
 618                 radeon_atom_output_lock(encoder, true);
 619         else
 620                 radeon_combios_output_lock(encoder, true);
 621         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
 622 }
 623
 624 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
 625 {
 626         struct radeon_device *rdev = encoder->dev->dev_private;
 627         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
 628
 629         if (rdev->is_atom_bios)
 630                 radeon_atom_output_lock(encoder, false);
 631         else
 632                 radeon_combios_output_lock(encoder, false);
 633 }
 634
 635 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
 636                                             struct drm_display_mode *mode,
 637                                             struct drm_display_mode *adjusted_mode)
 638 {
 639         struct drm_device *dev = encoder->dev;
 640         struct radeon_device *rdev = dev->dev_private;
 641         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 642         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 643         uint32_t fp2_gen_cntl;
 644
 645         DRM_DEBUG("\n");
 646
 647         if (rdev->is_atom_bios) {
 648                 radeon_encoder->pixel_clock = adjusted_mode->clock;
 649                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
 650                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 651         } else {
 652                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 653
 654                 if (1) /*  FIXME rgbBits == 8 */
 655                         fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
 656                 else
 657                         fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
 658
 659                 fp2_gen_cntl &= ~(RADEON_FP2_ON |
 660                                   RADEON_FP2_DVO_EN |
 661                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 662
 663                 /* XXX: these are oem specific */
 664                 if (ASIC_IS_R300(rdev)) {
 665                         if ((dev->pdev->device == 0x4850) &&
 666                             (dev->pdev->subsystem_vendor == 0x1028) &&
 667                             (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
 668                                 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
 669                         else
 670                                 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
 671
 672                         /*if (mode->clock > 165000)
 673                           fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
 674                 }
 675                 if (!radeon_combios_external_tmds_setup(encoder))
 676                         radeon_external_tmds_setup(encoder);
 677         }
 678
 679         if (radeon_crtc->crtc_id == 0) {
 680                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
 681                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 682                         if (radeon_encoder->rmx_type != RMX_OFF)
 683                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
 684                         else
 685                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
 686                 } else
 687                         fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
 688         } else {
 689                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
 690                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 691                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 692                 } else
 693                         fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
 694         }
 695
 696         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 697
 698         if (rdev->is_atom_bios)
 699                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 700         else
 701                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 702 }
 703
 704 static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
 705 {
 706         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 707         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
 708         if (tmds) {
 709                 if (tmds->i2c_bus)
 710                         radeon_i2c_destroy(tmds->i2c_bus);
 711         }
 712         kfree(radeon_encoder->enc_priv);
 713         drm_encoder_cleanup(encoder);
 714         kfree(radeon_encoder);
 715 }
 716
 717 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
 718         .dpms = radeon_legacy_tmds_ext_dpms,
 719         .mode_fixup = radeon_legacy_mode_fixup,
 720         .prepare = radeon_legacy_tmds_ext_prepare,
 721         .mode_set = radeon_legacy_tmds_ext_mode_set,
 722         .commit = radeon_legacy_tmds_ext_commit,
 723         .disable = radeon_legacy_encoder_disable,
 724 };
 725
 726
 727 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
 728         .destroy = radeon_ext_tmds_enc_destroy,
 729 };
 730
 731 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
 732 {
 733         struct drm_device *dev = encoder->dev;
 734         struct radeon_device *rdev = dev->dev_private;
 735         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 736         uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
 737         uint32_t tv_master_cntl = 0;
 738         bool is_tv;
 739         DRM_DEBUG("\n");
 740
 741         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
 742
 743         if (rdev->family == CHIP_R200)
 744                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 745         else {
 746                 if (is_tv)
 747                         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
 748                 else
 749                         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 750                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 751         }
 752
 753         switch (mode) {
 754         case DRM_MODE_DPMS_ON:
 755                 if (rdev->family == CHIP_R200) {
 756                         fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 757                 } else {
 758                         if (is_tv)
 759                                 tv_master_cntl |= RADEON_TV_ON;
 760                         else
 761                                 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
 762
 763                         if (rdev->family == CHIP_R420 ||
 764                             rdev->family == CHIP_R423 ||
 765                             rdev->family == CHIP_RV410)
 766                                 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
 767                                                  R420_TV_DAC_GDACPD |
 768                                                  R420_TV_DAC_BDACPD |
 769                                                  RADEON_TV_DAC_BGSLEEP);
 770                         else
 771                                 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
 772                                                  RADEON_TV_DAC_GDACPD |
 773                                                  RADEON_TV_DAC_BDACPD |
 774                                                  RADEON_TV_DAC_BGSLEEP);
 775                 }
 776                 break;
 777         case DRM_MODE_DPMS_STANDBY:
 778         case DRM_MODE_DPMS_SUSPEND:
 779         case DRM_MODE_DPMS_OFF:
 780                 if (rdev->family == CHIP_R200)
 781                         fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 782                 else {
 783                         if (is_tv)
 784                                 tv_master_cntl &= ~RADEON_TV_ON;
 785                         else
 786                                 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
 787
 788                         if (rdev->family == CHIP_R420 ||
 789                                         rdev->family == CHIP_R423 ||
 790                                         rdev->family == CHIP_RV410)
 791                                 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
 792                                                 R420_TV_DAC_GDACPD |
 793                                                 R420_TV_DAC_BDACPD |
 794                                                 RADEON_TV_DAC_BGSLEEP);
 795                         else
 796                                 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
 797                                                 RADEON_TV_DAC_GDACPD |
 798                                                 RADEON_TV_DAC_BDACPD |
 799                                                 RADEON_TV_DAC_BGSLEEP);
 800                 }
 801                 break;
 802         }
 803
 804         if (rdev->family == CHIP_R200) {
 805                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 806         } else {
 807                 if (is_tv)
 808                         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
 809                 else
 810                         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 811                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 812         }
 813
 814         if (rdev->is_atom_bios)
 815                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 816         else
 817                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 818 }
 819
 820 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
 821 {
 822         struct radeon_device *rdev = encoder->dev->dev_private;
 823
 824         if (rdev->is_atom_bios)
 825                 radeon_atom_output_lock(encoder, true);
 826         else
 827                 radeon_combios_output_lock(encoder, true);
 828         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 829 }
 830
 831 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
 832 {
 833         struct radeon_device *rdev = encoder->dev->dev_private;
 834
 835         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 836
 837         if (rdev->is_atom_bios)
 838                 radeon_atom_output_lock(encoder, true);
 839         else
 840                 radeon_combios_output_lock(encoder, true);
 841 }
 842
 843 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
 844                 struct drm_display_mode *mode,
 845                 struct drm_display_mode *adjusted_mode)
 846 {
 847         struct drm_device *dev = encoder->dev;
 848         struct radeon_device *rdev = dev->dev_private;
 849         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 850         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 851         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
 852         uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
 853         uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
 854         bool is_tv = false;
 855
 856         DRM_DEBUG("\n");
 857
 858         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
 859
 860         if (rdev->family != CHIP_R200) {
 861                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
 862                 if (rdev->family == CHIP_R420 ||
 863                                 rdev->family == CHIP_R423 ||
 864                                 rdev->family == CHIP_RV410) {
 865                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
 866                                         RADEON_TV_DAC_BGADJ_MASK |
 867                                         R420_TV_DAC_DACADJ_MASK |
 868                                         R420_TV_DAC_RDACPD |
 869                                         R420_TV_DAC_GDACPD |
 870                                         R420_TV_DAC_BDACPD |
 871                                         R420_TV_DAC_TVENABLE);
 872                 } else {
 873                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
 874                                         RADEON_TV_DAC_BGADJ_MASK |
 875                                         RADEON_TV_DAC_DACADJ_MASK |
 876                                         RADEON_TV_DAC_RDACPD |
 877                                         RADEON_TV_DAC_GDACPD |
 878                                         RADEON_TV_DAC_BDACPD);
 879                 }
 880
 881                 /*  FIXME TV */
 882                 if (tv_dac) {
 883                         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
 884                         tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
 885                                         RADEON_TV_DAC_NHOLD |
 886                                         RADEON_TV_DAC_STD_PS2 |
 887                                         tv_dac->ps2_tvdac_adj);
 888                 } else
 889                         tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
 890                                         RADEON_TV_DAC_NHOLD |
 891                                         RADEON_TV_DAC_STD_PS2);
 892
 893                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 894         }
 895
 896         if (ASIC_IS_R300(rdev)) {
 897                 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
 898                 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
 899         }
 900
 901         if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev))
 902                 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
 903         else
 904                 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
 905
 906         if (rdev->family == CHIP_R200)
 907                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 908
 909         if (is_tv) {
 910                 uint32_t dac_cntl;
 911
 912                 dac_cntl = RREG32(RADEON_DAC_CNTL);
 913                 dac_cntl &= ~RADEON_DAC_TVO_EN;
 914                 WREG32(RADEON_DAC_CNTL, dac_cntl);
 915
 916                 if (ASIC_IS_R300(rdev))
 917                         gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
 918
 919                 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
 920                 if (radeon_crtc->crtc_id == 0) {
 921                         if (ASIC_IS_R300(rdev)) {
 922                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 923                                 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
 924                                                      RADEON_DISP_TV_SOURCE_CRTC);
 925                         }
 926                         if (rdev->family >= CHIP_R200) {
 927                                 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
 928                         } else {
 929                                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 930                         }
 931                 } else {
 932                         if (ASIC_IS_R300(rdev)) {
 933                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 934                                 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
 935                         }
 936                         if (rdev->family >= CHIP_R200) {
 937                                 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
 938                         } else {
 939                                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
 940                         }
 941                 }
 942                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 943         } else {
 944
 945                 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
 946
 947                 if (radeon_crtc->crtc_id == 0) {
 948                         if (ASIC_IS_R300(rdev)) {
 949                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 950                                 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
 951                         } else if (rdev->family == CHIP_R200) {
 952                                 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
 953                                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 954                         } else
 955                                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 956                 } else {
 957                         if (ASIC_IS_R300(rdev)) {
 958                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
 959                                 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
 960                         } else if (rdev->family == CHIP_R200) {
 961                                 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
 962                                                   RADEON_FP2_DVO_RATE_SEL_SDR);
 963                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 964                         } else
 965                                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
 966                 }
 967                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 968         }
 969
 970         if (ASIC_IS_R300(rdev)) {
 971                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
 972                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 973         }
 974
 975         if (rdev->family >= CHIP_R200)
 976                 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
 977         else
 978                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
 979
 980         if (rdev->family == CHIP_R200)
 981                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 982
 983         if (is_tv)
 984                 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
 985
 986         if (rdev->is_atom_bios)
 987                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 988         else
 989                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 990
 991 }
 992
 993 static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
 994                                   struct drm_connector *connector)
 995 {
 996         struct drm_device *dev = encoder->dev;
 997         struct radeon_device *rdev = dev->dev_private;
 998         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
 999         uint32_t disp_output_cntl, gpiopad_a, tmp;
1000         bool found = false;
1001
1002         /* save regs needed */
1003         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1004         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1005         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1006         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1007         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1008         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1009
1010         WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1011
1012         WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1013
1014         WREG32(RADEON_CRTC2_GEN_CNTL,
1015                RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1016
1017         tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1018         tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1019         WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1020
1021         WREG32(RADEON_DAC_EXT_CNTL,
1022                RADEON_DAC2_FORCE_BLANK_OFF_EN |
1023                RADEON_DAC2_FORCE_DATA_EN |
1024                RADEON_DAC_FORCE_DATA_SEL_RGB |
1025                (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1026
1027         WREG32(RADEON_TV_DAC_CNTL,
1028                RADEON_TV_DAC_STD_NTSC |
1029                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1030                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1031
1032         RREG32(RADEON_TV_DAC_CNTL);
1033         mdelay(4);
1034
1035         WREG32(RADEON_TV_DAC_CNTL,
1036                RADEON_TV_DAC_NBLANK |
1037                RADEON_TV_DAC_NHOLD |
1038                RADEON_TV_MONITOR_DETECT_EN |
1039                RADEON_TV_DAC_STD_NTSC |
1040                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1041                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1042
1043         RREG32(RADEON_TV_DAC_CNTL);
1044         mdelay(6);
1045
1046         tmp = RREG32(RADEON_TV_DAC_CNTL);
1047         if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1048                 found = true;
1049                 DRM_DEBUG("S-video TV connection detected\n");
1050         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1051                 found = true;
1052                 DRM_DEBUG("Composite TV connection detected\n");
1053         }
1054
1055         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1056         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1057         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1058         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1059         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1060         WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1061         return found;
1062 }
1063
1064 static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1065                                     struct drm_connector *connector)
1066 {
1067         struct drm_device *dev = encoder->dev;
1068         struct radeon_device *rdev = dev->dev_private;
1069         uint32_t tv_dac_cntl, dac_cntl2;
1070         uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1071         bool found = false;
1072
1073         if (ASIC_IS_R300(rdev))
1074                 return r300_legacy_tv_detect(encoder, connector);
1075
1076         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1077         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1078         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1079         config_cntl = RREG32(RADEON_CONFIG_CNTL);
1080         tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1081
1082         tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1083         WREG32(RADEON_DAC_CNTL2, tmp);
1084
1085         tmp = tv_master_cntl | RADEON_TV_ON;
1086         tmp &= ~(RADEON_TV_ASYNC_RST |
1087                  RADEON_RESTART_PHASE_FIX |
1088                  RADEON_CRT_FIFO_CE_EN |
1089                  RADEON_TV_FIFO_CE_EN |
1090                  RADEON_RE_SYNC_NOW_SEL_MASK);
1091         tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1092         WREG32(RADEON_TV_MASTER_CNTL, tmp);
1093
1094         tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1095                 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1096                 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
1097
1098         if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1099                 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1100         else
1101                 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1102         WREG32(RADEON_TV_DAC_CNTL, tmp);
1103
1104         tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1105                 RADEON_RED_MX_FORCE_DAC_DATA |
1106                 RADEON_GRN_MX_FORCE_DAC_DATA |
1107                 RADEON_BLU_MX_FORCE_DAC_DATA |
1108                 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1109         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1110
1111         mdelay(3);
1112         tmp = RREG32(RADEON_TV_DAC_CNTL);
1113         if (tmp & RADEON_TV_DAC_GDACDET) {
1114                 found = true;
1115                 DRM_DEBUG("S-video TV connection detected\n");
1116         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1117                 found = true;
1118                 DRM_DEBUG("Composite TV connection detected\n");
1119         }
1120
1121         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1122         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1123         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1124         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1125         return found;
1126 }
1127
1128 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1129                                                              struct drm_connector *connector)
1130 {
1131         struct drm_device *dev = encoder->dev;
1132         struct radeon_device *rdev = dev->dev_private;
1133         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1134         uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
1135         enum drm_connector_status found = connector_status_disconnected;
1136         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1137         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1138         bool color = true;
1139
1140         if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1141             connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1142             connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1143                 bool tv_detect;
1144
1145                 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1146                         return connector_status_disconnected;
1147
1148                 tv_detect = radeon_legacy_tv_detect(encoder, connector);
1149                 if (tv_detect && tv_dac)
1150                         found = connector_status_connected;
1151                 return found;
1152         }
1153
1154         /* don't probe if the encoder is being used for something else not CRT related */
1155         if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1156                 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1157                 return connector_status_disconnected;
1158         }
1159
1160         /* save the regs we need */
1161         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1162         gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
1163         disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
1164         disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
1165         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1166         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1167         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1168         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1169
1170         tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1171                                | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1172         WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1173
1174         if (ASIC_IS_R300(rdev))
1175                 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1176
1177         tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1178         tmp |= RADEON_CRTC2_CRT2_ON |
1179                 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1180
1181         WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1182
1183         if (ASIC_IS_R300(rdev)) {
1184                 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1185                 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1186                 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1187         } else {
1188                 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1189                 WREG32(RADEON_DISP_HW_DEBUG, tmp);
1190         }
1191
1192         tmp = RADEON_TV_DAC_NBLANK |
1193                 RADEON_TV_DAC_NHOLD |
1194                 RADEON_TV_MONITOR_DETECT_EN |
1195                 RADEON_TV_DAC_STD_PS2;
1196
1197         WREG32(RADEON_TV_DAC_CNTL, tmp);
1198
1199         tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1200                 RADEON_DAC2_FORCE_DATA_EN;
1201
1202         if (color)
1203                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1204         else
1205                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1206
1207         if (ASIC_IS_R300(rdev))
1208                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1209         else
1210                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1211
1212         WREG32(RADEON_DAC_EXT_CNTL, tmp);
1213
1214         tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1215         WREG32(RADEON_DAC_CNTL2, tmp);
1216
1217         udelay(10000);
1218
1219         if (ASIC_IS_R300(rdev)) {
1220                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1221                         found = connector_status_connected;
1222         } else {
1223                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1224                         found = connector_status_connected;
1225         }
1226
1227         /* restore regs we used */
1228         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1229         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1230         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1231         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1232
1233         if (ASIC_IS_R300(rdev)) {
1234                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1235                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1236         } else {
1237                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1238         }
1239         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1240
1241         return found;
1242
1243 }
1244
1245 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1246         .dpms = radeon_legacy_tv_dac_dpms,
1247         .mode_fixup = radeon_legacy_mode_fixup,
1248         .prepare = radeon_legacy_tv_dac_prepare,
1249         .mode_set = radeon_legacy_tv_dac_mode_set,
1250         .commit = radeon_legacy_tv_dac_commit,
1251         .detect = radeon_legacy_tv_dac_detect,
1252         .disable = radeon_legacy_encoder_disable,
1253 };
1254
1255
1256 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1257         .destroy = radeon_enc_destroy,
1258 };
1259
1260
1261 static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1262 {
1263         struct drm_device *dev = encoder->base.dev;
1264         struct radeon_device *rdev = dev->dev_private;
1265         struct radeon_encoder_int_tmds *tmds = NULL;
1266         bool ret;
1267
1268         tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1269
1270         if (!tmds)
1271                 return NULL;
1272
1273         if (rdev->is_atom_bios)
1274                 ret = radeon_atombios_get_tmds_info(encoder, tmds);
1275         else
1276                 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1277
1278         if (ret == false)
1279                 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1280
1281         return tmds;
1282 }
1283
1284 static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1285 {
1286         struct drm_device *dev = encoder->base.dev;
1287         struct radeon_device *rdev = dev->dev_private;
1288         struct radeon_encoder_ext_tmds *tmds = NULL;
1289         bool ret;
1290
1291         if (rdev->is_atom_bios)
1292                 return NULL;
1293
1294         tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1295
1296         if (!tmds)
1297                 return NULL;
1298
1299         ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1300
1301         if (ret == false)
1302                 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1303
1304         return tmds;
1305 }
1306
1307 void
1308 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1309 {
1310         struct radeon_device *rdev = dev->dev_private;
1311         struct drm_encoder *encoder;
1312         struct radeon_encoder *radeon_encoder;
1313
1314         /* see if we already added it */
1315         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1316                 radeon_encoder = to_radeon_encoder(encoder);
1317                 if (radeon_encoder->encoder_id == encoder_id) {
1318                         radeon_encoder->devices |= supported_device;
1319                         return;
1320                 }
1321
1322         }
1323
1324         /* add a new one */
1325         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1326         if (!radeon_encoder)
1327                 return;
1328
1329         encoder = &radeon_encoder->base;
1330         if (rdev->flags & RADEON_SINGLE_CRTC)
1331                 encoder->possible_crtcs = 0x1;
1332         else
1333                 encoder->possible_crtcs = 0x3;
1334         encoder->possible_clones = 0;
1335
1336         radeon_encoder->enc_priv = NULL;
1337
1338         radeon_encoder->encoder_id = encoder_id;
1339         radeon_encoder->devices = supported_device;
1340         radeon_encoder->rmx_type = RMX_OFF;
1341
1342         switch (radeon_encoder->encoder_id) {
1343         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1344                 encoder->possible_crtcs = 0x1;
1345                 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1346                 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1347                 if (rdev->is_atom_bios)
1348                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1349                 else
1350                         radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1351                 radeon_encoder->rmx_type = RMX_FULL;
1352                 break;
1353         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1354                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1355                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1356                 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1357                 break;
1358         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1359                 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
1360                 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1361                 if (rdev->is_atom_bios)
1362                         radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1363                 else
1364                         radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1365                 break;
1366         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1367                 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1368                 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1369                 if (rdev->is_atom_bios)
1370                         radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1371                 else
1372                         radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1373                 break;
1374         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1375                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
1376                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1377                 if (!rdev->is_atom_bios)
1378                         radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1379                 break;
1380         }
1381 }