Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/radeon_legacy_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon_fixed.h"
  30 #include "radeon.h"
  31 #include "atom.h"
  32
  33 static void radeon_overscan_setup(struct drm_crtc *crtc,
  34                                   struct drm_display_mode *mode)
  35 {
  36         struct drm_device *dev = crtc->dev;
  37         struct radeon_device *rdev = dev->dev_private;
  38         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  39
  40         WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
  41         WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
  42         WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
  43 }
  44
  45 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
  46                                        struct drm_display_mode *mode)
  47 {
  48         struct drm_device *dev = crtc->dev;
  49         struct radeon_device *rdev = dev->dev_private;
  50         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  51         int xres = mode->hdisplay;
  52         int yres = mode->vdisplay;
  53         bool hscale = true, vscale = true;
  54         int hsync_wid;
  55         int vsync_wid;
  56         int hsync_start;
  57         int blank_width;
  58         u32 scale, inc, crtc_more_cntl;
  59         u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
  60         u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
  61         u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
  62         struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
  63
  64         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
  65                 (RADEON_VERT_STRETCH_RESERVED |
  66                  RADEON_VERT_AUTO_RATIO_INC);
  67         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
  68                 (RADEON_HORZ_FP_LOOP_STRETCH |
  69                  RADEON_HORZ_AUTO_RATIO_INC);
  70
  71         crtc_more_cntl = 0;
  72         if ((rdev->family == CHIP_RS100) ||
  73             (rdev->family == CHIP_RS200)) {
  74                 /* This is to workaround the asic bug for RMX, some versions
  75                    of BIOS dosen't have this register initialized correctly. */
  76                 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
  77         }
  78
  79
  80         fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
  81                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
  82
  83         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
  84         if (!hsync_wid)
  85                 hsync_wid = 1;
  86         hsync_start = mode->crtc_hsync_start - 8;
  87
  88         fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
  89                               | ((hsync_wid & 0x3f) << 16)
  90                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
  91                                  ? RADEON_CRTC_H_SYNC_POL
  92                                  : 0));
  93
  94         fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
  95                                 | ((mode->crtc_vdisplay - 1) << 16));
  96
  97         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
  98         if (!vsync_wid)
  99                 vsync_wid = 1;
 100
 101         fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 102                               | ((vsync_wid & 0x1f) << 16)
 103                               | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 104                                  ? RADEON_CRTC_V_SYNC_POL
 105                                  : 0));
 106
 107         fp_horz_vert_active = 0;
 108
 109         if (native_mode->hdisplay == 0 ||
 110             native_mode->vdisplay == 0) {
 111                 hscale = false;
 112                 vscale = false;
 113         } else {
 114                 if (xres > native_mode->hdisplay)
 115                         xres = native_mode->hdisplay;
 116                 if (yres > native_mode->vdisplay)
 117                         yres = native_mode->vdisplay;
 118
 119                 if (xres == native_mode->hdisplay)
 120                         hscale = false;
 121                 if (yres == native_mode->vdisplay)
 122                         vscale = false;
 123         }
 124
 125         switch (radeon_crtc->rmx_type) {
 126         case RMX_FULL:
 127         case RMX_ASPECT:
 128                 if (!hscale)
 129                         fp_horz_stretch |= ((xres/8-1) << 16);
 130                 else {
 131                         inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
 132                         scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
 133                                 / native_mode->hdisplay + 1;
 134                         fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
 135                                         RADEON_HORZ_STRETCH_BLEND |
 136                                         RADEON_HORZ_STRETCH_ENABLE |
 137                                         ((native_mode->hdisplay/8-1) << 16));
 138                 }
 139
 140                 if (!vscale)
 141                         fp_vert_stretch |= ((yres-1) << 12);
 142                 else {
 143                         inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
 144                         scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
 145                                 / native_mode->vdisplay + 1;
 146                         fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
 147                                         RADEON_VERT_STRETCH_ENABLE |
 148                                         RADEON_VERT_STRETCH_BLEND |
 149                                         ((native_mode->vdisplay-1) << 12));
 150                 }
 151                 break;
 152         case RMX_CENTER:
 153                 fp_horz_stretch |= ((xres/8-1) << 16);
 154                 fp_vert_stretch |= ((yres-1) << 12);
 155
 156                 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
 157                                 RADEON_CRTC_AUTO_VERT_CENTER_EN);
 158
 159                 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
 160                 if (blank_width > 110)
 161                         blank_width = 110;
 162
 163                 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
 164                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 165
 166                 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 167                 if (!hsync_wid)
 168                         hsync_wid = 1;
 169
 170                 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
 171                                 | ((hsync_wid & 0x3f) << 16)
 172                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 173                                         ? RADEON_CRTC_H_SYNC_POL
 174                                         : 0));
 175
 176                 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
 177                                 | ((mode->crtc_vdisplay - 1) << 16));
 178
 179                 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 180                 if (!vsync_wid)
 181                         vsync_wid = 1;
 182
 183                 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
 184                                         | ((vsync_wid & 0x1f) << 16)
 185                                         | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 186                                                 ? RADEON_CRTC_V_SYNC_POL
 187                                                 : 0)));
 188
 189                 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
 190                                 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
 191                 break;
 192         case RMX_OFF:
 193         default:
 194                 fp_horz_stretch |= ((xres/8-1) << 16);
 195                 fp_vert_stretch |= ((yres-1) << 12);
 196                 break;
 197         }
 198
 199         WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
 200         WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
 201         WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
 202         WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
 203         WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
 204         WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
 205         WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
 206         WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
 207 }
 208
 209 void radeon_restore_common_regs(struct drm_device *dev)
 210 {
 211         /* don't need this yet */
 212 }
 213
 214 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
 215 {
 216         struct radeon_device *rdev = dev->dev_private;
 217         int i = 0;
 218
 219         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 220            the cause yet, but this workaround will mask the problem for now.
 221            Other chips usually will pass at the very first test, so the
 222            workaround shouldn't have any effect on them. */
 223         for (i = 0;
 224              (i < 10000 &&
 225               RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 226              i++);
 227 }
 228
 229 static void radeon_pll_write_update(struct drm_device *dev)
 230 {
 231         struct radeon_device *rdev = dev->dev_private;
 232
 233         while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
 234
 235         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 236                            RADEON_PPLL_ATOMIC_UPDATE_W,
 237                            ~(RADEON_PPLL_ATOMIC_UPDATE_W));
 238 }
 239
 240 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
 241 {
 242         struct radeon_device *rdev = dev->dev_private;
 243         int i = 0;
 244
 245
 246         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 247            the cause yet, but this workaround will mask the problem for now.
 248            Other chips usually will pass at the very first test, so the
 249            workaround shouldn't have any effect on them. */
 250         for (i = 0;
 251              (i < 10000 &&
 252               RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 253              i++);
 254 }
 255
 256 static void radeon_pll2_write_update(struct drm_device *dev)
 257 {
 258         struct radeon_device *rdev = dev->dev_private;
 259
 260         while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
 261
 262         WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 263                            RADEON_P2PLL_ATOMIC_UPDATE_W,
 264                            ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
 265 }
 266
 267 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
 268                                        uint16_t fb_div)
 269 {
 270         unsigned int vcoFreq;
 271
 272         if (!ref_div)
 273                 return 1;
 274
 275         vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
 276
 277         /*
 278          * This is horribly crude: the VCO frequency range is divided into
 279          * 3 parts, each part having a fixed PLL gain value.
 280          */
 281         if (vcoFreq >= 30000)
 282                 /*
 283                  * [300..max] MHz : 7
 284                  */
 285                 return 7;
 286         else if (vcoFreq >= 18000)
 287                 /*
 288                  * [180..300) MHz : 4
 289                  */
 290                 return 4;
 291         else
 292                 /*
 293                  * [0..180) MHz : 1
 294                  */
 295                 return 1;
 296 }
 297
 298 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 299 {
 300         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 301         struct drm_device *dev = crtc->dev;
 302         struct radeon_device *rdev = dev->dev_private;
 303         uint32_t mask;
 304
 305         if (radeon_crtc->crtc_id)
 306                 mask = (RADEON_CRTC2_DISP_DIS |
 307                         RADEON_CRTC2_VSYNC_DIS |
 308                         RADEON_CRTC2_HSYNC_DIS |
 309                         RADEON_CRTC2_DISP_REQ_EN_B);
 310         else
 311                 mask = (RADEON_CRTC_DISPLAY_DIS |
 312                         RADEON_CRTC_VSYNC_DIS |
 313                         RADEON_CRTC_HSYNC_DIS);
 314
 315         switch (mode) {
 316         case DRM_MODE_DPMS_ON:
 317                 if (radeon_crtc->crtc_id)
 318                         WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
 319                 else {
 320                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
 321                                                                          RADEON_CRTC_DISP_REQ_EN_B));
 322                         WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
 323                 }
 324                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 325                 radeon_crtc_load_lut(crtc);
 326                 break;
 327         case DRM_MODE_DPMS_STANDBY:
 328         case DRM_MODE_DPMS_SUSPEND:
 329         case DRM_MODE_DPMS_OFF:
 330                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 331                 if (radeon_crtc->crtc_id)
 332                         WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
 333                 else {
 334                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
 335                                                                                     RADEON_CRTC_DISP_REQ_EN_B));
 336                         WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
 337                 }
 338                 break;
 339         }
 340 }
 341
 342 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 343                          struct drm_framebuffer *old_fb)
 344 {
 345         struct drm_device *dev = crtc->dev;
 346         struct radeon_device *rdev = dev->dev_private;
 347         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 348         struct radeon_framebuffer *radeon_fb;
 349         struct drm_gem_object *obj;
 350         struct radeon_bo *rbo;
 351         uint64_t base;
 352         uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
 353         uint32_t crtc_pitch, pitch_pixels;
 354         uint32_t tiling_flags;
 355         int format;
 356         uint32_t gen_cntl_reg, gen_cntl_val;
 357         int r;
 358
 359         DRM_DEBUG("\n");
 360         /* no fb bound */
 361         if (!crtc->fb) {
 362                 DRM_DEBUG("No FB bound\n");
 363                 return 0;
 364         }
 365
 366         radeon_fb = to_radeon_framebuffer(crtc->fb);
 367
 368         switch (crtc->fb->bits_per_pixel) {
 369         case 8:
 370                 format = 2;
 371                 break;
 372         case 15:      /*  555 */
 373                 format = 3;
 374                 break;
 375         case 16:      /*  565 */
 376                 format = 4;
 377                 break;
 378         case 24:      /*  RGB */
 379                 format = 5;
 380                 break;
 381         case 32:      /* xRGB */
 382                 format = 6;
 383                 break;
 384         default:
 385                 return false;
 386         }
 387
 388         /* Pin framebuffer & get tilling informations */
 389         obj = radeon_fb->obj;
 390         rbo = obj->driver_private;
 391         r = radeon_bo_reserve(rbo, false);
 392         if (unlikely(r != 0))
 393                 return r;
 394         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
 395         if (unlikely(r != 0)) {
 396                 radeon_bo_unreserve(rbo);
 397                 return -EINVAL;
 398         }
 399         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 400         radeon_bo_unreserve(rbo);
 401         if (tiling_flags & RADEON_TILING_MICRO)
 402                 DRM_ERROR("trying to scanout microtiled buffer\n");
 403
 404         /* if scanout was in GTT this really wouldn't work */
 405         /* crtc offset is from display base addr not FB location */
 406         radeon_crtc->legacy_display_base_addr = rdev->mc.vram_start;
 407
 408         base -= radeon_crtc->legacy_display_base_addr;
 409
 410         crtc_offset_cntl = 0;
 411
 412         pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
 413         crtc_pitch  = (((pitch_pixels * crtc->fb->bits_per_pixel) +
 414                         ((crtc->fb->bits_per_pixel * 8) - 1)) /
 415                        (crtc->fb->bits_per_pixel * 8));
 416         crtc_pitch |= crtc_pitch << 16;
 417
 418
 419         if (tiling_flags & RADEON_TILING_MACRO) {
 420                 if (ASIC_IS_R300(rdev))
 421                         crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 422                                              R300_CRTC_MICRO_TILE_BUFFER_DIS |
 423                                              R300_CRTC_MACRO_TILE_EN);
 424                 else
 425                         crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
 426         } else {
 427                 if (ASIC_IS_R300(rdev))
 428                         crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 429                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 430                                               R300_CRTC_MACRO_TILE_EN);
 431                 else
 432                         crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 433         }
 434
 435         if (tiling_flags & RADEON_TILING_MACRO) {
 436                 if (ASIC_IS_R300(rdev)) {
 437                         crtc_tile_x0_y0 = x | (y << 16);
 438                         base &= ~0x7ff;
 439                 } else {
 440                         int byteshift = crtc->fb->bits_per_pixel >> 4;
 441                         int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
 442                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 443                         crtc_offset_cntl |= (y % 16);
 444                 }
 445         } else {
 446                 int offset = y * pitch_pixels + x;
 447                 switch (crtc->fb->bits_per_pixel) {
 448                 case 8:
 449                         offset *= 1;
 450                         break;
 451                 case 15:
 452                 case 16:
 453                         offset *= 2;
 454                         break;
 455                 case 24:
 456                         offset *= 3;
 457                         break;
 458                 case 32:
 459                         offset *= 4;
 460                         break;
 461                 default:
 462                         return false;
 463                 }
 464                 base += offset;
 465         }
 466
 467         base &= ~7;
 468
 469         if (radeon_crtc->crtc_id == 1)
 470                 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
 471         else
 472                 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
 473
 474         gen_cntl_val = RREG32(gen_cntl_reg);
 475         gen_cntl_val &= ~(0xf << 8);
 476         gen_cntl_val |= (format << 8);
 477         WREG32(gen_cntl_reg, gen_cntl_val);
 478
 479         crtc_offset = (u32)base;
 480
 481         WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
 482
 483         if (ASIC_IS_R300(rdev)) {
 484                 if (radeon_crtc->crtc_id)
 485                         WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
 486                 else
 487                         WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
 488         }
 489         WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
 490         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
 491         WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
 492
 493         if (old_fb && old_fb != crtc->fb) {
 494                 radeon_fb = to_radeon_framebuffer(old_fb);
 495                 rbo = radeon_fb->obj->driver_private;
 496                 r = radeon_bo_reserve(rbo, false);
 497                 if (unlikely(r != 0))
 498                         return r;
 499                 radeon_bo_unpin(rbo);
 500                 radeon_bo_unreserve(rbo);
 501         }
 502
 503         /* Bytes per pixel may have changed */
 504         radeon_bandwidth_update(rdev);
 505
 506         return 0;
 507 }
 508
 509 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 510 {
 511         struct drm_device *dev = crtc->dev;
 512         struct radeon_device *rdev = dev->dev_private;
 513         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 514         struct drm_encoder *encoder;
 515         int format;
 516         int hsync_start;
 517         int hsync_wid;
 518         int vsync_wid;
 519         uint32_t crtc_h_total_disp;
 520         uint32_t crtc_h_sync_strt_wid;
 521         uint32_t crtc_v_total_disp;
 522         uint32_t crtc_v_sync_strt_wid;
 523         bool is_tv = false;
 524
 525         DRM_DEBUG("\n");
 526         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 527                 if (encoder->crtc == crtc) {
 528                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 529                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 530                                 is_tv = true;
 531                                 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
 532                                 break;
 533                         }
 534                 }
 535         }
 536
 537         switch (crtc->fb->bits_per_pixel) {
 538         case 8:
 539                 format = 2;
 540                 break;
 541         case 15:      /*  555 */
 542                 format = 3;
 543                 break;
 544         case 16:      /*  565 */
 545                 format = 4;
 546                 break;
 547         case 24:      /*  RGB */
 548                 format = 5;
 549                 break;
 550         case 32:      /* xRGB */
 551                 format = 6;
 552                 break;
 553         default:
 554                 return false;
 555         }
 556
 557         crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 558                              | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 559
 560         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 561         if (!hsync_wid)
 562                 hsync_wid = 1;
 563         hsync_start = mode->crtc_hsync_start - 8;
 564
 565         crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
 566                                 | ((hsync_wid & 0x3f) << 16)
 567                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 568                                    ? RADEON_CRTC_H_SYNC_POL
 569                                    : 0));
 570
 571         /* This works for double scan mode. */
 572         crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 573                              | ((mode->crtc_vdisplay - 1) << 16));
 574
 575         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 576         if (!vsync_wid)
 577                 vsync_wid = 1;
 578
 579         crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 580                                 | ((vsync_wid & 0x1f) << 16)
 581                                 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 582                                    ? RADEON_CRTC_V_SYNC_POL
 583                                    : 0));
 584
 585         if (radeon_crtc->crtc_id) {
 586                 uint32_t crtc2_gen_cntl;
 587                 uint32_t disp2_merge_cntl;
 588
 589                 /* if TV DAC is enabled for another crtc and keep it enabled */
 590                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
 591                 crtc2_gen_cntl |= ((format << 8)
 592                                    | RADEON_CRTC2_VSYNC_DIS
 593                                    | RADEON_CRTC2_HSYNC_DIS
 594                                    | RADEON_CRTC2_DISP_DIS
 595                                    | RADEON_CRTC2_DISP_REQ_EN_B
 596                                    | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 597                                       ? RADEON_CRTC2_DBL_SCAN_EN
 598                                       : 0)
 599                                    | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 600                                       ? RADEON_CRTC2_CSYNC_EN
 601                                       : 0)
 602                                    | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 603                                       ? RADEON_CRTC2_INTERLACE_EN
 604                                       : 0));
 605
 606                 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
 607                 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 608
 609                 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
 610                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 611
 612                 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
 613                 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
 614         } else {
 615                 uint32_t crtc_gen_cntl;
 616                 uint32_t crtc_ext_cntl;
 617                 uint32_t disp_merge_cntl;
 618
 619                 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
 620                 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
 621                                  | (format << 8)
 622                                  | RADEON_CRTC_DISP_REQ_EN_B
 623                                  | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 624                                     ? RADEON_CRTC_DBL_SCAN_EN
 625                                     : 0)
 626                                  | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 627                                     ? RADEON_CRTC_CSYNC_EN
 628                                     : 0)
 629                                  | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 630                                     ? RADEON_CRTC_INTERLACE_EN
 631                                     : 0));
 632
 633                 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 634                 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
 635                                   RADEON_CRTC_VSYNC_DIS |
 636                                   RADEON_CRTC_HSYNC_DIS |
 637                                   RADEON_CRTC_DISPLAY_DIS);
 638
 639                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
 640                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 641
 642                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 643                 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 644                 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 645         }
 646
 647         if (is_tv)
 648                 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
 649                                                  &crtc_h_sync_strt_wid, &crtc_v_total_disp,
 650                                                  &crtc_v_sync_strt_wid);
 651
 652         WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
 653         WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
 654         WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
 655         WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
 656
 657         return true;
 658 }
 659
 660 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 661 {
 662         struct drm_device *dev = crtc->dev;
 663         struct radeon_device *rdev = dev->dev_private;
 664         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 665         struct drm_encoder *encoder;
 666         uint32_t feedback_div = 0;
 667         uint32_t frac_fb_div = 0;
 668         uint32_t reference_div = 0;
 669         uint32_t post_divider = 0;
 670         uint32_t freq = 0;
 671         uint8_t pll_gain;
 672         bool use_bios_divs = false;
 673         /* PLL registers */
 674         uint32_t pll_ref_div = 0;
 675         uint32_t pll_fb_post_div = 0;
 676         uint32_t htotal_cntl = 0;
 677         bool is_tv = false;
 678         struct radeon_pll *pll;
 679
 680         struct {
 681                 int divider;
 682                 int bitvalue;
 683         } *post_div, post_divs[]   = {
 684                 /* From RAGE 128 VR/RAGE 128 GL Register
 685                  * Reference Manual (Technical Reference
 686                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 687                  * 3-17 (PLL_DIV_[3:0]).
 688                  */
 689                 {  1, 0 },              /* VCLK_SRC                 */
 690                 {  2, 1 },              /* VCLK_SRC/2               */
 691                 {  4, 2 },              /* VCLK_SRC/4               */
 692                 {  8, 3 },              /* VCLK_SRC/8               */
 693                 {  3, 4 },              /* VCLK_SRC/3               */
 694                 { 16, 5 },              /* VCLK_SRC/16              */
 695                 {  6, 6 },              /* VCLK_SRC/6               */
 696                 { 12, 7 },              /* VCLK_SRC/12              */
 697                 {  0, 0 }
 698         };
 699
 700         if (radeon_crtc->crtc_id)
 701                 pll = &rdev->clock.p2pll;
 702         else
 703                 pll = &rdev->clock.p1pll;
 704
 705         pll->flags = RADEON_PLL_LEGACY;
 706         if (radeon_new_pll == 1)
 707                 pll->algo = PLL_ALGO_NEW;
 708         else
 709                 pll->algo = PLL_ALGO_LEGACY;
 710
 711         if (mode->clock > 200000) /* range limits??? */
 712                 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 713         else
 714                 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 715
 716         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 717                 if (encoder->crtc == crtc) {
 718                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 719
 720                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 721                                 is_tv = true;
 722                                 break;
 723                         }
 724
 725                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 726                                 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
 727                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
 728                                 if (!rdev->is_atom_bios) {
 729                                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 730                                         struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 731                                         if (lvds) {
 732                                                 if (lvds->use_bios_dividers) {
 733                                                         pll_ref_div = lvds->panel_ref_divider;
 734                                                         pll_fb_post_div   = (lvds->panel_fb_divider |
 735                                                                              (lvds->panel_post_divider << 16));
 736                                                         htotal_cntl  = 0;
 737                                                         use_bios_divs = true;
 738                                                 }
 739                                         }
 740                                 }
 741                                 pll->flags |= RADEON_PLL_USE_REF_DIV;
 742                         }
 743                 }
 744         }
 745
 746         DRM_DEBUG("\n");
 747
 748         if (!use_bios_divs) {
 749                 radeon_compute_pll(pll, mode->clock,
 750                                    &freq, &feedback_div, &frac_fb_div,
 751                                    &reference_div, &post_divider);
 752
 753                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 754                         if (post_div->divider == post_divider)
 755                                 break;
 756                 }
 757
 758                 if (!post_div->divider)
 759                         post_div = &post_divs[0];
 760
 761                 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
 762                           (unsigned)freq,
 763                           feedback_div,
 764                           reference_div,
 765                           post_divider);
 766
 767                 pll_ref_div   = reference_div;
 768 #if defined(__powerpc__) && (0) /* TODO */
 769                 /* apparently programming this otherwise causes a hang??? */
 770                 if (info->MacModel == RADEON_MAC_IBOOK)
 771                         pll_fb_post_div = 0x000600ad;
 772                 else
 773 #endif
 774                         pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
 775
 776                 htotal_cntl    = mode->htotal & 0x7;
 777
 778         }
 779
 780         pll_gain = radeon_compute_pll_gain(pll->reference_freq,
 781                                            pll_ref_div & 0x3ff,
 782                                            pll_fb_post_div & 0x7ff);
 783
 784         if (radeon_crtc->crtc_id) {
 785                 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
 786                                           ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
 787                                          RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 788
 789                 if (is_tv) {
 790                         radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
 791                                                      &pll_ref_div, &pll_fb_post_div,
 792                                                      &pixclks_cntl);
 793                 }
 794
 795                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 796                              RADEON_PIX2CLK_SRC_SEL_CPUCLK,
 797                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 798
 799                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 800                              RADEON_P2PLL_RESET
 801                              | RADEON_P2PLL_ATOMIC_UPDATE_EN
 802                              | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
 803                              ~(RADEON_P2PLL_RESET
 804                                | RADEON_P2PLL_ATOMIC_UPDATE_EN
 805                                | RADEON_P2PLL_PVG_MASK));
 806
 807                 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
 808                              pll_ref_div,
 809                              ~RADEON_P2PLL_REF_DIV_MASK);
 810
 811                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 812                              pll_fb_post_div,
 813                              ~RADEON_P2PLL_FB0_DIV_MASK);
 814
 815                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
 816                              pll_fb_post_div,
 817                              ~RADEON_P2PLL_POST0_DIV_MASK);
 818
 819                 radeon_pll2_write_update(dev);
 820                 radeon_pll2_wait_for_read_update_complete(dev);
 821
 822                 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
 823
 824                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
 825                              0,
 826                              ~(RADEON_P2PLL_RESET
 827                                | RADEON_P2PLL_SLEEP
 828                                | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 829
 830                 DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 831                           (unsigned)pll_ref_div,
 832                           (unsigned)pll_fb_post_div,
 833                           (unsigned)htotal_cntl,
 834                           RREG32_PLL(RADEON_P2PLL_CNTL));
 835                 DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
 836                           (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 837                           (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
 838                           (unsigned)((pll_fb_post_div &
 839                                       RADEON_P2PLL_POST0_DIV_MASK) >> 16));
 840
 841                 mdelay(50); /* Let the clock to lock */
 842
 843                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
 844                              RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
 845                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 846
 847                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 848         } else {
 849                 uint32_t pixclks_cntl;
 850
 851
 852                 if (is_tv) {
 853                         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
 854                         radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
 855                                                      &pll_fb_post_div, &pixclks_cntl);
 856                 }
 857
 858                 if (rdev->flags & RADEON_IS_MOBILITY) {
 859                         /* A temporal workaround for the occational blanking on certain laptop panels.
 860                            This appears to related to the PLL divider registers (fail to lock?).
 861                            It occurs even when all dividers are the same with their old settings.
 862                            In this case we really don't need to fiddle with PLL registers.
 863                            By doing this we can avoid the blanking problem with some panels.
 864                         */
 865                         if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
 866                             (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
 867                                                  (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
 868                                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 869                                          RADEON_PLL_DIV_SEL,
 870                                          ~(RADEON_PLL_DIV_SEL));
 871                                 r100_pll_errata_after_index(rdev);
 872                                 return;
 873                         }
 874                 }
 875
 876                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
 877                              RADEON_VCLK_SRC_SEL_CPUCLK,
 878                              ~(RADEON_VCLK_SRC_SEL_MASK));
 879                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 880                              RADEON_PPLL_RESET
 881                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 882                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 883                              | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
 884                              ~(RADEON_PPLL_RESET
 885                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 886                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 887                                | RADEON_PPLL_PVG_MASK));
 888
 889                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
 890                          RADEON_PLL_DIV_SEL,
 891                          ~(RADEON_PLL_DIV_SEL));
 892                 r100_pll_errata_after_index(rdev);
 893
 894                 if (ASIC_IS_R300(rdev) ||
 895                     (rdev->family == CHIP_RS300) ||
 896                     (rdev->family == CHIP_RS400) ||
 897                     (rdev->family == CHIP_RS480)) {
 898                         if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
 899                                 /* When restoring console mode, use saved PPLL_REF_DIV
 900                                  * setting.
 901                                  */
 902                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 903                                              pll_ref_div,
 904                                              0);
 905                         } else {
 906                                 /* R300 uses ref_div_acc field as real ref divider */
 907                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 908                                              (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
 909                                              ~R300_PPLL_REF_DIV_ACC_MASK);
 910                         }
 911                 } else
 912                         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
 913                                      pll_ref_div,
 914                                      ~RADEON_PPLL_REF_DIV_MASK);
 915
 916                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 917                              pll_fb_post_div,
 918                              ~RADEON_PPLL_FB3_DIV_MASK);
 919
 920                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
 921                              pll_fb_post_div,
 922                              ~RADEON_PPLL_POST3_DIV_MASK);
 923
 924                 radeon_pll_write_update(dev);
 925                 radeon_pll_wait_for_read_update_complete(dev);
 926
 927                 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
 928
 929                 WREG32_PLL_P(RADEON_PPLL_CNTL,
 930                              0,
 931                              ~(RADEON_PPLL_RESET
 932                                | RADEON_PPLL_SLEEP
 933                                | RADEON_PPLL_ATOMIC_UPDATE_EN
 934                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
 935
 936                 DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 937                           pll_ref_div,
 938                           pll_fb_post_div,
 939                           (unsigned)htotal_cntl,
 940                           RREG32_PLL(RADEON_PPLL_CNTL));
 941                 DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
 942                           pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
 943                           pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
 944                           (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
 945
 946                 mdelay(50); /* Let the clock to lock */
 947
 948                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
 949                              RADEON_VCLK_SRC_SEL_PPLLCLK,
 950                              ~(RADEON_VCLK_SRC_SEL_MASK));
 951
 952                 if (is_tv)
 953                         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 954         }
 955 }
 956
 957 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
 958                                    struct drm_display_mode *mode,
 959                                    struct drm_display_mode *adjusted_mode)
 960 {
 961         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
 962                 return false;
 963         return true;
 964 }
 965
 966 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
 967                                  struct drm_display_mode *mode,
 968                                  struct drm_display_mode *adjusted_mode,
 969                                  int x, int y, struct drm_framebuffer *old_fb)
 970 {
 971         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 972
 973         /* TODO TV */
 974         radeon_crtc_set_base(crtc, x, y, old_fb);
 975         radeon_set_crtc_timing(crtc, adjusted_mode);
 976         radeon_set_pll(crtc, adjusted_mode);
 977         radeon_overscan_setup(crtc, adjusted_mode);
 978         if (radeon_crtc->crtc_id == 0) {
 979                 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
 980         } else {
 981                 if (radeon_crtc->rmx_type != RMX_OFF) {
 982                         /* FIXME: only first crtc has rmx what should we
 983                          * do ?
 984                          */
 985                         DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
 986                 }
 987         }
 988         return 0;
 989 }
 990
 991 static void radeon_crtc_prepare(struct drm_crtc *crtc)
 992 {
 993         struct drm_device *dev = crtc->dev;
 994         struct drm_crtc *crtci;
 995
 996         /*
 997         * The hardware wedges sometimes if you reconfigure one CRTC
 998         * whilst another is running (see fdo bug #24611).
 999         */
1000         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1001                 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1002 }
1003
1004 static void radeon_crtc_commit(struct drm_crtc *crtc)
1005 {
1006         struct drm_device *dev = crtc->dev;
1007         struct drm_crtc *crtci;
1008
1009         /*
1010         * Reenable the CRTCs that should be running.
1011         */
1012         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1013                 if (crtci->enabled)
1014                         radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1015         }
1016 }
1017
1018 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1019         .dpms = radeon_crtc_dpms,
1020         .mode_fixup = radeon_crtc_mode_fixup,
1021         .mode_set = radeon_crtc_mode_set,
1022         .mode_set_base = radeon_crtc_set_base,
1023         .prepare = radeon_crtc_prepare,
1024         .commit = radeon_crtc_commit,
1025         .load_lut = radeon_crtc_load_lut,
1026 };
1027
1028
1029 void radeon_legacy_init_crtc(struct drm_device *dev,
1030                                struct radeon_crtc *radeon_crtc)
1031 {
1032         if (radeon_crtc->crtc_id == 1)
1033                 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1034         drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1035 }