Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/radeon_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 extern int atom_debug;
  33
  34 /* evil but including atombios.h is much worse */
  35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  36                                 struct drm_display_mode *mode);
  37
  38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
  39 {
  40         struct drm_device *dev = encoder->dev;
  41         struct radeon_device *rdev = dev->dev_private;
  42         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  43         struct drm_encoder *clone_encoder;
  44         uint32_t index_mask = 0;
  45         int count;
  46
  47         /* DIG routing gets problematic */
  48         if (rdev->family >= CHIP_R600)
  49                 return index_mask;
  50         /* LVDS/TV are too wacky */
  51         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  52                 return index_mask;
  53         /* DVO requires 2x ppll clocks depending on tmds chip */
  54         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
  55                 return index_mask;
  56
  57         count = -1;
  58         list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
  59                 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
  60                 count++;
  61
  62                 if (clone_encoder == encoder)
  63                         continue;
  64                 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
  65                         continue;
  66                 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
  67                         continue;
  68                 else
  69                         index_mask |= (1 << count);
  70         }
  71         return index_mask;
  72 }
  73
  74 void radeon_setup_encoder_clones(struct drm_device *dev)
  75 {
  76         struct drm_encoder *encoder;
  77
  78         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  79                 encoder->possible_clones = radeon_encoder_clones(encoder);
  80         }
  81 }
  82
  83 uint32_t
  84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
  85 {
  86         struct radeon_device *rdev = dev->dev_private;
  87         uint32_t ret = 0;
  88
  89         switch (supported_device) {
  90         case ATOM_DEVICE_CRT1_SUPPORT:
  91         case ATOM_DEVICE_TV1_SUPPORT:
  92         case ATOM_DEVICE_TV2_SUPPORT:
  93         case ATOM_DEVICE_CRT2_SUPPORT:
  94         case ATOM_DEVICE_CV_SUPPORT:
  95                 switch (dac) {
  96                 case 1: /* dac a */
  97                         if ((rdev->family == CHIP_RS300) ||
  98                             (rdev->family == CHIP_RS400) ||
  99                             (rdev->family == CHIP_RS480))
 100                                 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
 101                         else if (ASIC_IS_AVIVO(rdev))
 102                                 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
 103                         else
 104                                 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
 105                         break;
 106                 case 2: /* dac b */
 107                         if (ASIC_IS_AVIVO(rdev))
 108                                 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
 109                         else {
 110                                 /*if (rdev->family == CHIP_R200)
 111                                   ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 112                                   else*/
 113                                 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
 114                         }
 115                         break;
 116                 case 3: /* external dac */
 117                         if (ASIC_IS_AVIVO(rdev))
 118                                 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
 119                         else
 120                                 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 121                         break;
 122                 }
 123                 break;
 124         case ATOM_DEVICE_LCD1_SUPPORT:
 125                 if (ASIC_IS_AVIVO(rdev))
 126                         ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
 127                 else
 128                         ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
 129                 break;
 130         case ATOM_DEVICE_DFP1_SUPPORT:
 131                 if ((rdev->family == CHIP_RS300) ||
 132                     (rdev->family == CHIP_RS400) ||
 133                     (rdev->family == CHIP_RS480))
 134                         ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 135                 else if (ASIC_IS_AVIVO(rdev))
 136                         ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
 137                 else
 138                         ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
 139                 break;
 140         case ATOM_DEVICE_LCD2_SUPPORT:
 141         case ATOM_DEVICE_DFP2_SUPPORT:
 142                 if ((rdev->family == CHIP_RS600) ||
 143                     (rdev->family == CHIP_RS690) ||
 144                     (rdev->family == CHIP_RS740))
 145                         ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
 146                 else if (ASIC_IS_AVIVO(rdev))
 147                         ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
 148                 else
 149                         ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
 150                 break;
 151         case ATOM_DEVICE_DFP3_SUPPORT:
 152                 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
 153                 break;
 154         }
 155
 156         return ret;
 157 }
 158
 159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 160 {
 161         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 162         switch (radeon_encoder->encoder_id) {
 163         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 164         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 165         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 166         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 167         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 168         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 169         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 170         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 171         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 172         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 173         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 174                 return true;
 175         default:
 176                 return false;
 177         }
 178 }
 179
 180 void
 181 radeon_link_encoder_connector(struct drm_device *dev)
 182 {
 183         struct drm_connector *connector;
 184         struct radeon_connector *radeon_connector;
 185         struct drm_encoder *encoder;
 186         struct radeon_encoder *radeon_encoder;
 187
 188         /* walk the list and link encoders to connectors */
 189         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 190                 radeon_connector = to_radeon_connector(connector);
 191                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 192                         radeon_encoder = to_radeon_encoder(encoder);
 193                         if (radeon_encoder->devices & radeon_connector->devices)
 194                                 drm_mode_connector_attach_encoder(connector, encoder);
 195                 }
 196         }
 197 }
 198
 199 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
 200 {
 201         struct drm_device *dev = encoder->dev;
 202         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 203         struct drm_connector *connector;
 204
 205         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 206                 if (connector->encoder == encoder) {
 207                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 208                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
 209                         DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
 210                                   radeon_encoder->active_device, radeon_encoder->devices,
 211                                   radeon_connector->devices, encoder->encoder_type);
 212                 }
 213         }
 214 }
 215
 216 struct drm_connector *
 217 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
 218 {
 219         struct drm_device *dev = encoder->dev;
 220         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 221         struct drm_connector *connector;
 222         struct radeon_connector *radeon_connector;
 223
 224         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 225                 radeon_connector = to_radeon_connector(connector);
 226                 if (radeon_encoder->active_device & radeon_connector->devices)
 227                         return connector;
 228         }
 229         return NULL;
 230 }
 231
 232 struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
 233 {
 234         struct drm_device *dev = encoder->dev;
 235         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 236         struct drm_encoder *other_encoder;
 237         struct radeon_encoder *other_radeon_encoder;
 238
 239         if (radeon_encoder->is_ext_encoder)
 240                 return NULL;
 241
 242         list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
 243                 if (other_encoder == encoder)
 244                         continue;
 245                 other_radeon_encoder = to_radeon_encoder(other_encoder);
 246                 if (other_radeon_encoder->is_ext_encoder &&
 247                     (radeon_encoder->devices & other_radeon_encoder->devices))
 248                         return other_encoder;
 249         }
 250         return NULL;
 251 }
 252
 253 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
 254                              struct drm_display_mode *adjusted_mode)
 255 {
 256         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 257         struct drm_device *dev = encoder->dev;
 258         struct radeon_device *rdev = dev->dev_private;
 259         struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
 260         unsigned hblank = native_mode->htotal - native_mode->hdisplay;
 261         unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
 262         unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
 263         unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
 264         unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
 265         unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
 266
 267         adjusted_mode->clock = native_mode->clock;
 268         adjusted_mode->flags = native_mode->flags;
 269
 270         if (ASIC_IS_AVIVO(rdev)) {
 271                 adjusted_mode->hdisplay = native_mode->hdisplay;
 272                 adjusted_mode->vdisplay = native_mode->vdisplay;
 273         }
 274
 275         adjusted_mode->htotal = native_mode->hdisplay + hblank;
 276         adjusted_mode->hsync_start = native_mode->hdisplay + hover;
 277         adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
 278
 279         adjusted_mode->vtotal = native_mode->vdisplay + vblank;
 280         adjusted_mode->vsync_start = native_mode->vdisplay + vover;
 281         adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
 282
 283         drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
 284
 285         if (ASIC_IS_AVIVO(rdev)) {
 286                 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
 287                 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
 288         }
 289
 290         adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
 291         adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
 292         adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
 293
 294         adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
 295         adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
 296         adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
 297
 298 }
 299
 300 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 301                                    struct drm_display_mode *mode,
 302                                    struct drm_display_mode *adjusted_mode)
 303 {
 304         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 305         struct drm_device *dev = encoder->dev;
 306         struct radeon_device *rdev = dev->dev_private;
 307
 308         /* set the active encoder to connector routing */
 309         radeon_encoder_set_active_device(encoder);
 310         drm_mode_set_crtcinfo(adjusted_mode, 0);
 311
 312         /* hw bug */
 313         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 314             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 315                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 316
 317         /* get the native mode for LVDS */
 318         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
 319                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 320
 321         /* get the native mode for TV */
 322         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 323                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 324                 if (tv_dac) {
 325                         if (tv_dac->tv_std == TV_STD_NTSC ||
 326                             tv_dac->tv_std == TV_STD_NTSC_J ||
 327                             tv_dac->tv_std == TV_STD_PAL_M)
 328                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 329                         else
 330                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 331                 }
 332         }
 333
 334         if (ASIC_IS_DCE3(rdev) &&
 335             (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
 336                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 337                 radeon_dp_set_link_config(connector, mode);
 338         }
 339
 340         return true;
 341 }
 342
 343 static void
 344 atombios_dac_setup(struct drm_encoder *encoder, int action)
 345 {
 346         struct drm_device *dev = encoder->dev;
 347         struct radeon_device *rdev = dev->dev_private;
 348         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 349         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 350         int index = 0;
 351         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 352
 353         memset(&args, 0, sizeof(args));
 354
 355         switch (radeon_encoder->encoder_id) {
 356         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 357         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 358                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 359                 break;
 360         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 361         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 362                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 363                 break;
 364         }
 365
 366         args.ucAction = action;
 367
 368         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 369                 args.ucDacStandard = ATOM_DAC1_PS2;
 370         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 371                 args.ucDacStandard = ATOM_DAC1_CV;
 372         else {
 373                 switch (dac_info->tv_std) {
 374                 case TV_STD_PAL:
 375                 case TV_STD_PAL_M:
 376                 case TV_STD_SCART_PAL:
 377                 case TV_STD_SECAM:
 378                 case TV_STD_PAL_CN:
 379                         args.ucDacStandard = ATOM_DAC1_PAL;
 380                         break;
 381                 case TV_STD_NTSC:
 382                 case TV_STD_NTSC_J:
 383                 case TV_STD_PAL_60:
 384                 default:
 385                         args.ucDacStandard = ATOM_DAC1_NTSC;
 386                         break;
 387                 }
 388         }
 389         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 390
 391         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 392
 393 }
 394
 395 static void
 396 atombios_tv_setup(struct drm_encoder *encoder, int action)
 397 {
 398         struct drm_device *dev = encoder->dev;
 399         struct radeon_device *rdev = dev->dev_private;
 400         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 401         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 402         int index = 0;
 403         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 404
 405         memset(&args, 0, sizeof(args));
 406
 407         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 408
 409         args.sTVEncoder.ucAction = action;
 410
 411         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 412                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 413         else {
 414                 switch (dac_info->tv_std) {
 415                 case TV_STD_NTSC:
 416                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 417                         break;
 418                 case TV_STD_PAL:
 419                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 420                         break;
 421                 case TV_STD_PAL_M:
 422                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 423                         break;
 424                 case TV_STD_PAL_60:
 425                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 426                         break;
 427                 case TV_STD_NTSC_J:
 428                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 429                         break;
 430                 case TV_STD_SCART_PAL:
 431                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 432                         break;
 433                 case TV_STD_SECAM:
 434                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 435                         break;
 436                 case TV_STD_PAL_CN:
 437                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 438                         break;
 439                 default:
 440                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 441                         break;
 442                 }
 443         }
 444
 445         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 446
 447         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 448
 449 }
 450
 451 union dvo_encoder_control {
 452         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 453         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 454         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 455 };
 456
 457 void
 458 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 459 {
 460         struct drm_device *dev = encoder->dev;
 461         struct radeon_device *rdev = dev->dev_private;
 462         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 463         union dvo_encoder_control args;
 464         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 465
 466         memset(&args, 0, sizeof(args));
 467
 468         if (ASIC_IS_DCE3(rdev)) {
 469                 /* DCE3+ */
 470                 args.dvo_v3.ucAction = action;
 471                 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 472                 args.dvo_v3.ucDVOConfig = 0; /* XXX */
 473         } else if (ASIC_IS_DCE2(rdev)) {
 474                 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
 475                 args.dvo.sDVOEncoder.ucAction = action;
 476                 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 477                 /* DFP1, CRT1, TV1 depending on the type of port */
 478                 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 479
 480                 if (radeon_encoder->pixel_clock > 165000)
 481                         args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 482         } else {
 483                 /* R4xx, R5xx */
 484                 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 485
 486                 if (radeon_encoder->pixel_clock > 165000)
 487                         args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 488
 489                 /*if (pScrn->rgbBits == 8)*/
 490                 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 491         }
 492
 493         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 494 }
 495
 496 union lvds_encoder_control {
 497         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 498         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 499 };
 500
 501 void
 502 atombios_digital_setup(struct drm_encoder *encoder, int action)
 503 {
 504         struct drm_device *dev = encoder->dev;
 505         struct radeon_device *rdev = dev->dev_private;
 506         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 507         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 508         union lvds_encoder_control args;
 509         int index = 0;
 510         int hdmi_detected = 0;
 511         uint8_t frev, crev;
 512
 513         if (!dig)
 514                 return;
 515
 516         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 517                 hdmi_detected = 1;
 518
 519         memset(&args, 0, sizeof(args));
 520
 521         switch (radeon_encoder->encoder_id) {
 522         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 523                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 524                 break;
 525         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 526         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 527                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 528                 break;
 529         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 530                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 531                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 532                 else
 533                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 534                 break;
 535         }
 536
 537         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 538                 return;
 539
 540         switch (frev) {
 541         case 1:
 542         case 2:
 543                 switch (crev) {
 544                 case 1:
 545                         args.v1.ucMisc = 0;
 546                         args.v1.ucAction = action;
 547                         if (hdmi_detected)
 548                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 549                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 550                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 551                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 552                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 553                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 554                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 555                         } else {
 556                                 if (dig->linkb)
 557                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 558                                 if (radeon_encoder->pixel_clock > 165000)
 559                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 560                                 /*if (pScrn->rgbBits == 8) */
 561                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 562                         }
 563                         break;
 564                 case 2:
 565                 case 3:
 566                         args.v2.ucMisc = 0;
 567                         args.v2.ucAction = action;
 568                         if (crev == 3) {
 569                                 if (dig->coherent_mode)
 570                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 571                         }
 572                         if (hdmi_detected)
 573                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 574                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 575                         args.v2.ucTruncate = 0;
 576                         args.v2.ucSpatial = 0;
 577                         args.v2.ucTemporal = 0;
 578                         args.v2.ucFRC = 0;
 579                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 580                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 581                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 582                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 583                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 584                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 585                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 586                                 }
 587                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 588                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 589                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 590                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 591                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 592                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 593                                 }
 594                         } else {
 595                                 if (dig->linkb)
 596                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 597                                 if (radeon_encoder->pixel_clock > 165000)
 598                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 599                         }
 600                         break;
 601                 default:
 602                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 603                         break;
 604                 }
 605                 break;
 606         default:
 607                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 608                 break;
 609         }
 610
 611         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 612 }
 613
 614 int
 615 atombios_get_encoder_mode(struct drm_encoder *encoder)
 616 {
 617         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 618         struct drm_device *dev = encoder->dev;
 619         struct radeon_device *rdev = dev->dev_private;
 620         struct drm_connector *connector;
 621         struct radeon_connector *radeon_connector;
 622         struct radeon_connector_atom_dig *dig_connector;
 623
 624         connector = radeon_get_connector_for_encoder(encoder);
 625         if (!connector) {
 626                 switch (radeon_encoder->encoder_id) {
 627                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 628                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 629                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 630                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 631                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 632                         return ATOM_ENCODER_MODE_DVI;
 633                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 634                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 635                 default:
 636                         return ATOM_ENCODER_MODE_CRT;
 637                 }
 638         }
 639         radeon_connector = to_radeon_connector(connector);
 640
 641         switch (connector->connector_type) {
 642         case DRM_MODE_CONNECTOR_DVII:
 643         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 644                 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
 645                         /* fix me */
 646                         if (ASIC_IS_DCE4(rdev))
 647                                 return ATOM_ENCODER_MODE_DVI;
 648                         else
 649                                 return ATOM_ENCODER_MODE_HDMI;
 650                 } else if (radeon_connector->use_digital)
 651                         return ATOM_ENCODER_MODE_DVI;
 652                 else
 653                         return ATOM_ENCODER_MODE_CRT;
 654                 break;
 655         case DRM_MODE_CONNECTOR_DVID:
 656         case DRM_MODE_CONNECTOR_HDMIA:
 657         default:
 658                 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
 659                         /* fix me */
 660                         if (ASIC_IS_DCE4(rdev))
 661                                 return ATOM_ENCODER_MODE_DVI;
 662                         else
 663                                 return ATOM_ENCODER_MODE_HDMI;
 664                 } else
 665                         return ATOM_ENCODER_MODE_DVI;
 666                 break;
 667         case DRM_MODE_CONNECTOR_LVDS:
 668                 return ATOM_ENCODER_MODE_LVDS;
 669                 break;
 670         case DRM_MODE_CONNECTOR_DisplayPort:
 671         case DRM_MODE_CONNECTOR_eDP:
 672                 dig_connector = radeon_connector->con_priv;
 673                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 674                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 675                         return ATOM_ENCODER_MODE_DP;
 676                 else if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
 677                         /* fix me */
 678                         if (ASIC_IS_DCE4(rdev))
 679                                 return ATOM_ENCODER_MODE_DVI;
 680                         else
 681                                 return ATOM_ENCODER_MODE_HDMI;
 682                 } else
 683                         return ATOM_ENCODER_MODE_DVI;
 684                 break;
 685         case DRM_MODE_CONNECTOR_DVIA:
 686         case DRM_MODE_CONNECTOR_VGA:
 687                 return ATOM_ENCODER_MODE_CRT;
 688                 break;
 689         case DRM_MODE_CONNECTOR_Composite:
 690         case DRM_MODE_CONNECTOR_SVIDEO:
 691         case DRM_MODE_CONNECTOR_9PinDIN:
 692                 /* fix me */
 693                 return ATOM_ENCODER_MODE_TV;
 694                 /*return ATOM_ENCODER_MODE_CV;*/
 695                 break;
 696         }
 697 }
 698
 699 /*
 700  * DIG Encoder/Transmitter Setup
 701  *
 702  * DCE 3.0/3.1
 703  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 704  * Supports up to 3 digital outputs
 705  * - 2 DIG encoder blocks.
 706  * DIG1 can drive UNIPHY link A or link B
 707  * DIG2 can drive UNIPHY link B or LVTMA
 708  *
 709  * DCE 3.2
 710  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 711  * Supports up to 5 digital outputs
 712  * - 2 DIG encoder blocks.
 713  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 714  *
 715  * DCE 4.0
 716  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 717  * Supports up to 6 digital outputs
 718  * - 6 DIG encoder blocks.
 719  * - DIG to PHY mapping is hardcoded
 720  * DIG1 drives UNIPHY0 link A, A+B
 721  * DIG2 drives UNIPHY0 link B
 722  * DIG3 drives UNIPHY1 link A, A+B
 723  * DIG4 drives UNIPHY1 link B
 724  * DIG5 drives UNIPHY2 link A, A+B
 725  * DIG6 drives UNIPHY2 link B
 726  *
 727  * DCE 4.1
 728  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 729  * Supports up to 6 digital outputs
 730  * - 2 DIG encoder blocks.
 731  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 732  *
 733  * Routing
 734  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 735  * Examples:
 736  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 737  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 738  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 739  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 740  */
 741
 742 union dig_encoder_control {
 743         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 744         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 745         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 746 };
 747
 748 void
 749 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
 750 {
 751         struct drm_device *dev = encoder->dev;
 752         struct radeon_device *rdev = dev->dev_private;
 753         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 754         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 755         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 756         union dig_encoder_control args;
 757         int index = 0;
 758         uint8_t frev, crev;
 759         int dp_clock = 0;
 760         int dp_lane_count = 0;
 761
 762         if (connector) {
 763                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 764                 struct radeon_connector_atom_dig *dig_connector =
 765                         radeon_connector->con_priv;
 766
 767                 dp_clock = dig_connector->dp_clock;
 768                 dp_lane_count = dig_connector->dp_lane_count;
 769         }
 770
 771         /* no dig encoder assigned */
 772         if (dig->dig_encoder == -1)
 773                 return;
 774
 775         memset(&args, 0, sizeof(args));
 776
 777         if (ASIC_IS_DCE4(rdev))
 778                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 779         else {
 780                 if (dig->dig_encoder)
 781                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 782                 else
 783                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 784         }
 785
 786         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 787                 return;
 788
 789         args.v1.ucAction = action;
 790         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 791         args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 792
 793         if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
 794                 if (dp_clock == 270000)
 795                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 796                 args.v1.ucLaneNum = dp_lane_count;
 797         } else if (radeon_encoder->pixel_clock > 165000)
 798                 args.v1.ucLaneNum = 8;
 799         else
 800                 args.v1.ucLaneNum = 4;
 801
 802         if (ASIC_IS_DCE4(rdev)) {
 803                 args.v3.acConfig.ucDigSel = dig->dig_encoder;
 804                 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
 805         } else {
 806                 switch (radeon_encoder->encoder_id) {
 807                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 808                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 809                         break;
 810                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 811                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 812                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 813                         break;
 814                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 815                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 816                         break;
 817                 }
 818                 if (dig->linkb)
 819                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 820                 else
 821                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 822         }
 823
 824         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 825
 826 }
 827
 828 union dig_transmitter_control {
 829         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 830         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 831         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 832 };
 833
 834 void
 835 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 836 {
 837         struct drm_device *dev = encoder->dev;
 838         struct radeon_device *rdev = dev->dev_private;
 839         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 840         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 841         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 842         union dig_transmitter_control args;
 843         int index = 0;
 844         uint8_t frev, crev;
 845         bool is_dp = false;
 846         int pll_id = 0;
 847         int dp_clock = 0;
 848         int dp_lane_count = 0;
 849         int connector_object_id = 0;
 850         int igp_lane_info = 0;
 851
 852         if (connector) {
 853                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 854                 struct radeon_connector_atom_dig *dig_connector =
 855                         radeon_connector->con_priv;
 856
 857                 dp_clock = dig_connector->dp_clock;
 858                 dp_lane_count = dig_connector->dp_lane_count;
 859                 connector_object_id =
 860                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 861                 igp_lane_info = dig_connector->igp_lane_info;
 862         }
 863
 864         /* no dig encoder assigned */
 865         if (dig->dig_encoder == -1)
 866                 return;
 867
 868         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
 869                 is_dp = true;
 870
 871         memset(&args, 0, sizeof(args));
 872
 873         switch (radeon_encoder->encoder_id) {
 874         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 875                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
 876                 break;
 877         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 878         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 879         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 880                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
 881                 break;
 882         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 883                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
 884                 break;
 885         }
 886
 887         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 888                 return;
 889
 890         args.v1.ucAction = action;
 891         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 892                 args.v1.usInitInfo = connector_object_id;
 893         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
 894                 args.v1.asMode.ucLaneSel = lane_num;
 895                 args.v1.asMode.ucLaneSet = lane_set;
 896         } else {
 897                 if (is_dp)
 898                         args.v1.usPixelClock =
 899                                 cpu_to_le16(dp_clock / 10);
 900                 else if (radeon_encoder->pixel_clock > 165000)
 901                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
 902                 else
 903                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 904         }
 905         if (ASIC_IS_DCE4(rdev)) {
 906                 if (is_dp)
 907                         args.v3.ucLaneNum = dp_lane_count;
 908                 else if (radeon_encoder->pixel_clock > 165000)
 909                         args.v3.ucLaneNum = 8;
 910                 else
 911                         args.v3.ucLaneNum = 4;
 912
 913                 if (dig->linkb) {
 914                         args.v3.acConfig.ucLinkSel = 1;
 915                         args.v3.acConfig.ucEncoderSel = 1;
 916                 }
 917
 918                 /* Select the PLL for the PHY
 919                  * DP PHY should be clocked from external src if there is
 920                  * one.
 921                  */
 922                 if (encoder->crtc) {
 923                         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 924                         pll_id = radeon_crtc->pll_id;
 925                 }
 926                 if (is_dp && rdev->clock.dp_extclk)
 927                         args.v3.acConfig.ucRefClkSource = 2; /* external src */
 928                 else
 929                         args.v3.acConfig.ucRefClkSource = pll_id;
 930
 931                 switch (radeon_encoder->encoder_id) {
 932                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 933                         args.v3.acConfig.ucTransmitterSel = 0;
 934                         break;
 935                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 936                         args.v3.acConfig.ucTransmitterSel = 1;
 937                         break;
 938                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 939                         args.v3.acConfig.ucTransmitterSel = 2;
 940                         break;
 941                 }
 942
 943                 if (is_dp)
 944                         args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
 945                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 946                         if (dig->coherent_mode)
 947                                 args.v3.acConfig.fCoherentMode = 1;
 948                         if (radeon_encoder->pixel_clock > 165000)
 949                                 args.v3.acConfig.fDualLinkConnector = 1;
 950                 }
 951         } else if (ASIC_IS_DCE32(rdev)) {
 952                 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
 953                 if (dig->linkb)
 954                         args.v2.acConfig.ucLinkSel = 1;
 955
 956                 switch (radeon_encoder->encoder_id) {
 957                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 958                         args.v2.acConfig.ucTransmitterSel = 0;
 959                         break;
 960                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 961                         args.v2.acConfig.ucTransmitterSel = 1;
 962                         break;
 963                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 964                         args.v2.acConfig.ucTransmitterSel = 2;
 965                         break;
 966                 }
 967
 968                 if (is_dp)
 969                         args.v2.acConfig.fCoherentMode = 1;
 970                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 971                         if (dig->coherent_mode)
 972                                 args.v2.acConfig.fCoherentMode = 1;
 973                         if (radeon_encoder->pixel_clock > 165000)
 974                                 args.v2.acConfig.fDualLinkConnector = 1;
 975                 }
 976         } else {
 977                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
 978
 979                 if (dig->dig_encoder)
 980                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
 981                 else
 982                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
 983
 984                 if ((rdev->flags & RADEON_IS_IGP) &&
 985                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
 986                         if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
 987                                 if (igp_lane_info & 0x1)
 988                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
 989                                 else if (igp_lane_info & 0x2)
 990                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
 991                                 else if (igp_lane_info & 0x4)
 992                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
 993                                 else if (igp_lane_info & 0x8)
 994                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
 995                         } else {
 996                                 if (igp_lane_info & 0x3)
 997                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
 998                                 else if (igp_lane_info & 0xc)
 999                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1000                         }
1001                 }
1002
1003                 if (dig->linkb)
1004                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1005                 else
1006                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1007
1008                 if (is_dp)
1009                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1010                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1011                         if (dig->coherent_mode)
1012                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1013                         if (radeon_encoder->pixel_clock > 165000)
1014                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1015                 }
1016         }
1017
1018         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1019 }
1020
1021 void
1022 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1023 {
1024         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1025         struct drm_device *dev = radeon_connector->base.dev;
1026         struct radeon_device *rdev = dev->dev_private;
1027         union dig_transmitter_control args;
1028         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1029         uint8_t frev, crev;
1030
1031         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1032                 return;
1033
1034         if (!ASIC_IS_DCE4(rdev))
1035                 return;
1036
1037         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) ||
1038             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1039                 return;
1040
1041         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1042                 return;
1043
1044         memset(&args, 0, sizeof(args));
1045
1046         args.v1.ucAction = action;
1047
1048         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1049 }
1050
1051 union external_encoder_control {
1052         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1053         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1054 };
1055
1056 static void
1057 atombios_external_encoder_setup(struct drm_encoder *encoder,
1058                                 struct drm_encoder *ext_encoder,
1059                                 int action)
1060 {
1061         struct drm_device *dev = encoder->dev;
1062         struct radeon_device *rdev = dev->dev_private;
1063         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1064         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1065         union external_encoder_control args;
1066         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1067         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1068         u8 frev, crev;
1069         int dp_clock = 0;
1070         int dp_lane_count = 0;
1071         int connector_object_id = 0;
1072         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1073
1074         if (connector) {
1075                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1076                 struct radeon_connector_atom_dig *dig_connector =
1077                         radeon_connector->con_priv;
1078
1079                 dp_clock = dig_connector->dp_clock;
1080                 dp_lane_count = dig_connector->dp_lane_count;
1081                 connector_object_id =
1082                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1083         }
1084
1085         memset(&args, 0, sizeof(args));
1086
1087         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1088                 return;
1089
1090         switch (frev) {
1091         case 1:
1092                 /* no params on frev 1 */
1093                 break;
1094         case 2:
1095                 switch (crev) {
1096                 case 1:
1097                 case 2:
1098                         args.v1.sDigEncoder.ucAction = action;
1099                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1100                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1101
1102                         if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1103                                 if (dp_clock == 270000)
1104                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1105                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1106                         } else if (radeon_encoder->pixel_clock > 165000)
1107                                 args.v1.sDigEncoder.ucLaneNum = 8;
1108                         else
1109                                 args.v1.sDigEncoder.ucLaneNum = 4;
1110                         break;
1111                 case 3:
1112                         args.v3.sExtEncoder.ucAction = action;
1113                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1114                                 args.v3.sExtEncoder.usConnectorId = connector_object_id;
1115                         else
1116                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1117                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1118
1119                         if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1120                                 if (dp_clock == 270000)
1121                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1122                                 else if (dp_clock == 540000)
1123                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1124                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1125                         } else if (radeon_encoder->pixel_clock > 165000)
1126                                 args.v3.sExtEncoder.ucLaneNum = 8;
1127                         else
1128                                 args.v3.sExtEncoder.ucLaneNum = 4;
1129                         switch (ext_enum) {
1130                         case GRAPH_OBJECT_ENUM_ID1:
1131                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1132                                 break;
1133                         case GRAPH_OBJECT_ENUM_ID2:
1134                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1135                                 break;
1136                         case GRAPH_OBJECT_ENUM_ID3:
1137                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1138                                 break;
1139                         }
1140                         args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1141                         break;
1142                 default:
1143                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1144                         return;
1145                 }
1146                 break;
1147         default:
1148                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1149                 return;
1150         }
1151         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1152 }
1153
1154 static void
1155 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1156 {
1157         struct drm_device *dev = encoder->dev;
1158         struct radeon_device *rdev = dev->dev_private;
1159         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1160         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1161         ENABLE_YUV_PS_ALLOCATION args;
1162         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1163         uint32_t temp, reg;
1164
1165         memset(&args, 0, sizeof(args));
1166
1167         if (rdev->family >= CHIP_R600)
1168                 reg = R600_BIOS_3_SCRATCH;
1169         else
1170                 reg = RADEON_BIOS_3_SCRATCH;
1171
1172         /* XXX: fix up scratch reg handling */
1173         temp = RREG32(reg);
1174         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1175                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1176                              (radeon_crtc->crtc_id << 18)));
1177         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1178                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1179         else
1180                 WREG32(reg, 0);
1181
1182         if (enable)
1183                 args.ucEnable = ATOM_ENABLE;
1184         args.ucCRTC = radeon_crtc->crtc_id;
1185
1186         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1187
1188         WREG32(reg, temp);
1189 }
1190
1191 static void
1192 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1193 {
1194         struct drm_device *dev = encoder->dev;
1195         struct radeon_device *rdev = dev->dev_private;
1196         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1197         struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1198         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1199         int index = 0;
1200         bool is_dig = false;
1201
1202         memset(&args, 0, sizeof(args));
1203
1204         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1205                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1206                   radeon_encoder->active_device);
1207         switch (radeon_encoder->encoder_id) {
1208         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1209         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1210                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1211                 break;
1212         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1213         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1214         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1215         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1216                 is_dig = true;
1217                 break;
1218         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1219         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1220                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1221                 break;
1222         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1223                 if (ASIC_IS_DCE3(rdev))
1224                         is_dig = true;
1225                 else
1226                         index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1227                 break;
1228         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1229                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1230                 break;
1231         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1232                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1233                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1234                 else
1235                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1236                 break;
1237         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1238         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1239                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1240                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1241                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1242                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1243                 else
1244                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1245                 break;
1246         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1247         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1248                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1249                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1250                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1251                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1252                 else
1253                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1254                 break;
1255         }
1256
1257         if (is_dig) {
1258                 switch (mode) {
1259                 case DRM_MODE_DPMS_ON:
1260                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1261                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1262                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1263
1264                                 if (connector &&
1265                                     (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1266                                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1267                                         struct radeon_connector_atom_dig *radeon_dig_connector =
1268                                                 radeon_connector->con_priv;
1269                                         atombios_set_edp_panel_power(connector,
1270                                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1271                                         radeon_dig_connector->edp_on = true;
1272                                 }
1273                                 dp_link_train(encoder, connector);
1274                                 if (ASIC_IS_DCE4(rdev))
1275                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1276                         }
1277                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1278                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1279                         break;
1280                 case DRM_MODE_DPMS_STANDBY:
1281                 case DRM_MODE_DPMS_SUSPEND:
1282                 case DRM_MODE_DPMS_OFF:
1283                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1284                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1285                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1286
1287                                 if (ASIC_IS_DCE4(rdev))
1288                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1289                                 if (connector &&
1290                                     (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1291                                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1292                                         struct radeon_connector_atom_dig *radeon_dig_connector =
1293                                                 radeon_connector->con_priv;
1294                                         atombios_set_edp_panel_power(connector,
1295                                                                      ATOM_TRANSMITTER_ACTION_POWER_OFF);
1296                                         radeon_dig_connector->edp_on = false;
1297                                 }
1298                         }
1299                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1300                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1301                         break;
1302                 }
1303         } else {
1304                 switch (mode) {
1305                 case DRM_MODE_DPMS_ON:
1306                         args.ucAction = ATOM_ENABLE;
1307                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1308                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1309                                 args.ucAction = ATOM_LCD_BLON;
1310                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1311                         }
1312                         break;
1313                 case DRM_MODE_DPMS_STANDBY:
1314                 case DRM_MODE_DPMS_SUSPEND:
1315                 case DRM_MODE_DPMS_OFF:
1316                         args.ucAction = ATOM_DISABLE;
1317                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1318                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1319                                 args.ucAction = ATOM_LCD_BLOFF;
1320                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1321                         }
1322                         break;
1323                 }
1324         }
1325
1326         if (ext_encoder) {
1327                 int action;
1328
1329                 switch (mode) {
1330                 case DRM_MODE_DPMS_ON:
1331                 default:
1332                         if (ASIC_IS_DCE41(rdev) && (rdev->flags & RADEON_IS_IGP))
1333                                 action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT;
1334                         else
1335                                 action = ATOM_ENABLE;
1336                         break;
1337                 case DRM_MODE_DPMS_STANDBY:
1338                 case DRM_MODE_DPMS_SUSPEND:
1339                 case DRM_MODE_DPMS_OFF:
1340                         if (ASIC_IS_DCE41(rdev) && (rdev->flags & RADEON_IS_IGP))
1341                                 action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT;
1342                         else
1343                                 action = ATOM_DISABLE;
1344                         break;
1345                 }
1346                 atombios_external_encoder_setup(encoder, ext_encoder, action);
1347         }
1348
1349         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1350
1351 }
1352
1353 union crtc_source_param {
1354         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1355         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1356 };
1357
1358 static void
1359 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1360 {
1361         struct drm_device *dev = encoder->dev;
1362         struct radeon_device *rdev = dev->dev_private;
1363         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1364         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1365         union crtc_source_param args;
1366         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1367         uint8_t frev, crev;
1368         struct radeon_encoder_atom_dig *dig;
1369
1370         memset(&args, 0, sizeof(args));
1371
1372         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1373                 return;
1374
1375         switch (frev) {
1376         case 1:
1377                 switch (crev) {
1378                 case 1:
1379                 default:
1380                         if (ASIC_IS_AVIVO(rdev))
1381                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1382                         else {
1383                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1384                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1385                                 } else {
1386                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1387                                 }
1388                         }
1389                         switch (radeon_encoder->encoder_id) {
1390                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1391                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1392                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1393                                 break;
1394                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1395                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1396                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1397                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1398                                 else
1399                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1400                                 break;
1401                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1402                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1403                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1404                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1405                                 break;
1406                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1407                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1408                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1409                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1410                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1411                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1412                                 else
1413                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1414                                 break;
1415                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1416                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1417                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1418                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1419                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1420                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1421                                 else
1422                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1423                                 break;
1424                         }
1425                         break;
1426                 case 2:
1427                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1428                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1429                         switch (radeon_encoder->encoder_id) {
1430                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1431                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1432                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1433                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1434                                 dig = radeon_encoder->enc_priv;
1435                                 switch (dig->dig_encoder) {
1436                                 case 0:
1437                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1438                                         break;
1439                                 case 1:
1440                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1441                                         break;
1442                                 case 2:
1443                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1444                                         break;
1445                                 case 3:
1446                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1447                                         break;
1448                                 case 4:
1449                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1450                                         break;
1451                                 case 5:
1452                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1453                                         break;
1454                                 }
1455                                 break;
1456                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1457                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1458                                 break;
1459                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1460                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1461                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1462                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1463                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1464                                 else
1465                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1466                                 break;
1467                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1468                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1469                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1470                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1471                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1472                                 else
1473                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1474                                 break;
1475                         }
1476                         break;
1477                 }
1478                 break;
1479         default:
1480                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1481                 return;
1482         }
1483
1484         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1485
1486         /* update scratch regs with new routing */
1487         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1488 }
1489
1490 static void
1491 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1492                               struct drm_display_mode *mode)
1493 {
1494         struct drm_device *dev = encoder->dev;
1495         struct radeon_device *rdev = dev->dev_private;
1496         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1497         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1498
1499         /* Funky macbooks */
1500         if ((dev->pdev->device == 0x71C5) &&
1501             (dev->pdev->subsystem_vendor == 0x106b) &&
1502             (dev->pdev->subsystem_device == 0x0080)) {
1503                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1504                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1505
1506                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1507                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1508
1509                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1510                 }
1511         }
1512
1513         /* set scaler clears this on some chips */
1514         /* XXX check DCE4 */
1515         if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1516                 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1517                         WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1518                                AVIVO_D1MODE_INTERLEAVE_EN);
1519         }
1520 }
1521
1522 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1523 {
1524         struct drm_device *dev = encoder->dev;
1525         struct radeon_device *rdev = dev->dev_private;
1526         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1527         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1528         struct drm_encoder *test_encoder;
1529         struct radeon_encoder_atom_dig *dig;
1530         uint32_t dig_enc_in_use = 0;
1531
1532         if (ASIC_IS_DCE4(rdev)) {
1533                 dig = radeon_encoder->enc_priv;
1534                 if (ASIC_IS_DCE41(rdev)) {
1535                         if (dig->linkb)
1536                                 return 1;
1537                         else
1538                                 return 0;
1539                 } else {
1540                         switch (radeon_encoder->encoder_id) {
1541                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1542                                 if (dig->linkb)
1543                                         return 1;
1544                                 else
1545                                         return 0;
1546                                 break;
1547                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1548                                 if (dig->linkb)
1549                                         return 3;
1550                                 else
1551                                         return 2;
1552                                 break;
1553                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1554                                 if (dig->linkb)
1555                                         return 5;
1556                                 else
1557                                         return 4;
1558                                 break;
1559                         }
1560                 }
1561         }
1562
1563         /* on DCE32 and encoder can driver any block so just crtc id */
1564         if (ASIC_IS_DCE32(rdev)) {
1565                 return radeon_crtc->crtc_id;
1566         }
1567
1568         /* on DCE3 - LVTMA can only be driven by DIGB */
1569         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1570                 struct radeon_encoder *radeon_test_encoder;
1571
1572                 if (encoder == test_encoder)
1573                         continue;
1574
1575                 if (!radeon_encoder_is_digital(test_encoder))
1576                         continue;
1577
1578                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1579                 dig = radeon_test_encoder->enc_priv;
1580
1581                 if (dig->dig_encoder >= 0)
1582                         dig_enc_in_use |= (1 << dig->dig_encoder);
1583         }
1584
1585         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1586                 if (dig_enc_in_use & 0x2)
1587                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1588                 return 1;
1589         }
1590         if (!(dig_enc_in_use & 1))
1591                 return 0;
1592         return 1;
1593 }
1594
1595 static void
1596 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1597                              struct drm_display_mode *mode,
1598                              struct drm_display_mode *adjusted_mode)
1599 {
1600         struct drm_device *dev = encoder->dev;
1601         struct radeon_device *rdev = dev->dev_private;
1602         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1603         struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1604
1605         radeon_encoder->pixel_clock = adjusted_mode->clock;
1606
1607         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1608                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1609                         atombios_yuv_setup(encoder, true);
1610                 else
1611                         atombios_yuv_setup(encoder, false);
1612         }
1613
1614         switch (radeon_encoder->encoder_id) {
1615         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1616         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1617         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1618         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1619                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1620                 break;
1621         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1622         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1623         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1624         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1625                 if (ASIC_IS_DCE4(rdev)) {
1626                         /* disable the transmitter */
1627                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1628                         /* setup and enable the encoder */
1629                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1630
1631                         /* init and enable the transmitter */
1632                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1633                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1634                 } else {
1635                         /* disable the encoder and transmitter */
1636                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1637                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1638
1639                         /* setup and enable the encoder and transmitter */
1640                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1641                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1642                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1643                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1644                 }
1645                 break;
1646         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1647         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1648         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1649                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1650                 break;
1651         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1652         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1653         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1654         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1655                 atombios_dac_setup(encoder, ATOM_ENABLE);
1656                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1657                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1658                                 atombios_tv_setup(encoder, ATOM_ENABLE);
1659                         else
1660                                 atombios_tv_setup(encoder, ATOM_DISABLE);
1661                 }
1662                 break;
1663         }
1664
1665         if (ext_encoder) {
1666                 if (ASIC_IS_DCE41(rdev) && (rdev->flags & RADEON_IS_IGP)) {
1667                         atombios_external_encoder_setup(encoder, ext_encoder,
1668                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1669                         atombios_external_encoder_setup(encoder, ext_encoder,
1670                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1671                 } else
1672                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1673         }
1674
1675         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1676
1677         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1678                 r600_hdmi_enable(encoder);
1679                 r600_hdmi_setmode(encoder, adjusted_mode);
1680         }
1681 }
1682
1683 static bool
1684 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1685 {
1686         struct drm_device *dev = encoder->dev;
1687         struct radeon_device *rdev = dev->dev_private;
1688         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1689         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1690
1691         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1692                                        ATOM_DEVICE_CV_SUPPORT |
1693                                        ATOM_DEVICE_CRT_SUPPORT)) {
1694                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1695                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1696                 uint8_t frev, crev;
1697
1698                 memset(&args, 0, sizeof(args));
1699
1700                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1701                         return false;
1702
1703                 args.sDacload.ucMisc = 0;
1704
1705                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1706                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1707                         args.sDacload.ucDacType = ATOM_DAC_A;
1708                 else
1709                         args.sDacload.ucDacType = ATOM_DAC_B;
1710
1711                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1712                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1713                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1714                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1715                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1716                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1717                         if (crev >= 3)
1718                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1719                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1720                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1721                         if (crev >= 3)
1722                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1723                 }
1724
1725                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1726
1727                 return true;
1728         } else
1729                 return false;
1730 }
1731
1732 static enum drm_connector_status
1733 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1734 {
1735         struct drm_device *dev = encoder->dev;
1736         struct radeon_device *rdev = dev->dev_private;
1737         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1738         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1739         uint32_t bios_0_scratch;
1740
1741         if (!atombios_dac_load_detect(encoder, connector)) {
1742                 DRM_DEBUG_KMS("detect returned false \n");
1743                 return connector_status_unknown;
1744         }
1745
1746         if (rdev->family >= CHIP_R600)
1747                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1748         else
1749                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1750
1751         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1752         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1753                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1754                         return connector_status_connected;
1755         }
1756         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1757                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1758                         return connector_status_connected;
1759         }
1760         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1761                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1762                         return connector_status_connected;
1763         }
1764         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1765                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1766                         return connector_status_connected; /* CTV */
1767                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1768                         return connector_status_connected; /* STV */
1769         }
1770         return connector_status_disconnected;
1771 }
1772
1773 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1774 {
1775         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1776         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1777
1778         if (radeon_encoder->active_device &
1779             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1780                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1781                 if (dig)
1782                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1783         }
1784
1785         radeon_atom_output_lock(encoder, true);
1786         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1787
1788         /* select the clock/data port if it uses a router */
1789         if (connector) {
1790                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1791                 if (radeon_connector->router.cd_valid)
1792                         radeon_router_select_cd_port(radeon_connector);
1793         }
1794
1795         /* this is needed for the pll/ss setup to work correctly in some cases */
1796         atombios_set_encoder_crtc_source(encoder);
1797 }
1798
1799 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1800 {
1801         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1802         radeon_atom_output_lock(encoder, false);
1803 }
1804
1805 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1806 {
1807         struct drm_device *dev = encoder->dev;
1808         struct radeon_device *rdev = dev->dev_private;
1809         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1810         struct radeon_encoder_atom_dig *dig;
1811
1812         /* check for pre-DCE3 cards with shared encoders;
1813          * can't really use the links individually, so don't disable
1814          * the encoder if it's in use by another connector
1815          */
1816         if (!ASIC_IS_DCE3(rdev)) {
1817                 struct drm_encoder *other_encoder;
1818                 struct radeon_encoder *other_radeon_encoder;
1819
1820                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
1821                         other_radeon_encoder = to_radeon_encoder(other_encoder);
1822                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
1823                             drm_helper_encoder_in_use(other_encoder))
1824                                 goto disable_done;
1825                 }
1826         }
1827
1828         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1829
1830         switch (radeon_encoder->encoder_id) {
1831         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1832         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1833         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1834         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1835                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1836                 break;
1837         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1838         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1839         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1840         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1841                 if (ASIC_IS_DCE4(rdev))
1842                         /* disable the transmitter */
1843                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1844                 else {
1845                         /* disable the encoder and transmitter */
1846                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1847                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1848                 }
1849                 break;
1850         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1851         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1852         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1853                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1854                 break;
1855         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1856         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1857         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1858         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1859                 atombios_dac_setup(encoder, ATOM_DISABLE);
1860                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1861                         atombios_tv_setup(encoder, ATOM_DISABLE);
1862                 break;
1863         }
1864
1865 disable_done:
1866         if (radeon_encoder_is_digital(encoder)) {
1867                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1868                         r600_hdmi_disable(encoder);
1869                 dig = radeon_encoder->enc_priv;
1870                 dig->dig_encoder = -1;
1871         }
1872         radeon_encoder->active_device = 0;
1873 }
1874
1875 /* these are handled by the primary encoders */
1876 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
1877 {
1878
1879 }
1880
1881 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
1882 {
1883
1884 }
1885
1886 static void
1887 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
1888                          struct drm_display_mode *mode,
1889                          struct drm_display_mode *adjusted_mode)
1890 {
1891
1892 }
1893
1894 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
1895 {
1896
1897 }
1898
1899 static void
1900 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
1901 {
1902
1903 }
1904
1905 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
1906                                        struct drm_display_mode *mode,
1907                                        struct drm_display_mode *adjusted_mode)
1908 {
1909         return true;
1910 }
1911
1912 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
1913         .dpms = radeon_atom_ext_dpms,
1914         .mode_fixup = radeon_atom_ext_mode_fixup,
1915         .prepare = radeon_atom_ext_prepare,
1916         .mode_set = radeon_atom_ext_mode_set,
1917         .commit = radeon_atom_ext_commit,
1918         .disable = radeon_atom_ext_disable,
1919         /* no detect for TMDS/LVDS yet */
1920 };
1921
1922 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1923         .dpms = radeon_atom_encoder_dpms,
1924         .mode_fixup = radeon_atom_mode_fixup,
1925         .prepare = radeon_atom_encoder_prepare,
1926         .mode_set = radeon_atom_encoder_mode_set,
1927         .commit = radeon_atom_encoder_commit,
1928         .disable = radeon_atom_encoder_disable,
1929         /* no detect for TMDS/LVDS yet */
1930 };
1931
1932 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1933         .dpms = radeon_atom_encoder_dpms,
1934         .mode_fixup = radeon_atom_mode_fixup,
1935         .prepare = radeon_atom_encoder_prepare,
1936         .mode_set = radeon_atom_encoder_mode_set,
1937         .commit = radeon_atom_encoder_commit,
1938         .detect = radeon_atom_dac_detect,
1939 };
1940
1941 void radeon_enc_destroy(struct drm_encoder *encoder)
1942 {
1943         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1944         kfree(radeon_encoder->enc_priv);
1945         drm_encoder_cleanup(encoder);
1946         kfree(radeon_encoder);
1947 }
1948
1949 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1950         .destroy = radeon_enc_destroy,
1951 };
1952
1953 struct radeon_encoder_atom_dac *
1954 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1955 {
1956         struct drm_device *dev = radeon_encoder->base.dev;
1957         struct radeon_device *rdev = dev->dev_private;
1958         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1959
1960         if (!dac)
1961                 return NULL;
1962
1963         dac->tv_std = radeon_atombios_get_tv_info(rdev);
1964         return dac;
1965 }
1966
1967 struct radeon_encoder_atom_dig *
1968 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1969 {
1970         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1971         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1972
1973         if (!dig)
1974                 return NULL;
1975
1976         /* coherent mode by default */
1977         dig->coherent_mode = true;
1978         dig->dig_encoder = -1;
1979
1980         if (encoder_enum == 2)
1981                 dig->linkb = true;
1982         else
1983                 dig->linkb = false;
1984
1985         return dig;
1986 }
1987
1988 void
1989 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1990 {
1991         struct radeon_device *rdev = dev->dev_private;
1992         struct drm_encoder *encoder;
1993         struct radeon_encoder *radeon_encoder;
1994
1995         /* see if we already added it */
1996         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1997                 radeon_encoder = to_radeon_encoder(encoder);
1998                 if (radeon_encoder->encoder_enum == encoder_enum) {
1999                         radeon_encoder->devices |= supported_device;
2000                         return;
2001                 }
2002
2003         }
2004
2005         /* add a new one */
2006         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2007         if (!radeon_encoder)
2008                 return;
2009
2010         encoder = &radeon_encoder->base;
2011         switch (rdev->num_crtc) {
2012         case 1:
2013                 encoder->possible_crtcs = 0x1;
2014                 break;
2015         case 2:
2016         default:
2017                 encoder->possible_crtcs = 0x3;
2018                 break;
2019         case 6:
2020                 encoder->possible_crtcs = 0x3f;
2021                 break;
2022         }
2023
2024         radeon_encoder->enc_priv = NULL;
2025
2026         radeon_encoder->encoder_enum = encoder_enum;
2027         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2028         radeon_encoder->devices = supported_device;
2029         radeon_encoder->rmx_type = RMX_OFF;
2030         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2031         radeon_encoder->is_ext_encoder = false;
2032
2033         switch (radeon_encoder->encoder_id) {
2034         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2035         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2036         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2037         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2038                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2039                         radeon_encoder->rmx_type = RMX_FULL;
2040                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2041                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2042                 } else {
2043                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2044                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2045                         if (ASIC_IS_AVIVO(rdev))
2046                                 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
2047                 }
2048                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2049                 break;
2050         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2051                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2052                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2053                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2054                 break;
2055         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2056         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2057         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2058                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2059                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2060                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2061                 break;
2062         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2063         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2064         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2065         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2066         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2067         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2068         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2069                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2070                         radeon_encoder->rmx_type = RMX_FULL;
2071                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2072                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2073                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2074                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2075                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2076                 } else {
2077                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2078                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2079                         if (ASIC_IS_AVIVO(rdev))
2080                                 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
2081                 }
2082                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2083                 break;
2084         case ENCODER_OBJECT_ID_SI170B:
2085         case ENCODER_OBJECT_ID_CH7303:
2086         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2087         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2088         case ENCODER_OBJECT_ID_TITFP513:
2089         case ENCODER_OBJECT_ID_VT1623:
2090         case ENCODER_OBJECT_ID_HDMI_SI1930:
2091         case ENCODER_OBJECT_ID_TRAVIS:
2092         case ENCODER_OBJECT_ID_NUTMEG:
2093                 /* these are handled by the primary encoders */
2094                 radeon_encoder->is_ext_encoder = true;
2095                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2096                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2097                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2098                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2099                 else
2100                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2101                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2102                 break;
2103         }
2104 }