Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35
  36 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  37 {
  38         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  39         struct drm_device *dev = crtc->dev;
  40         struct radeon_device *rdev = dev->dev_private;
  41         int i;
  42
  43         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  44         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  45
  46         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  47         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  48         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  49
  50         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  51         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  52         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  53
  54         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  55         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  56         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  57
  58         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  59         for (i = 0; i < 256; i++) {
  60                 WREG32(AVIVO_DC_LUT_30_COLOR,
  61                              (radeon_crtc->lut_r[i] << 20) |
  62                              (radeon_crtc->lut_g[i] << 10) |
  63                              (radeon_crtc->lut_b[i] << 0));
  64         }
  65
  66         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  67 }
  68
  69 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  70 {
  71         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  72         struct drm_device *dev = crtc->dev;
  73         struct radeon_device *rdev = dev->dev_private;
  74         int i;
  75
  76         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  77         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  78
  79         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  80         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  81         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  82
  83         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  84         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  85         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  86
  87         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  88         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  89
  90         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  91         for (i = 0; i < 256; i++) {
  92                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  93                        (radeon_crtc->lut_r[i] << 20) |
  94                        (radeon_crtc->lut_g[i] << 10) |
  95                        (radeon_crtc->lut_b[i] << 0));
  96         }
  97 }
  98
  99 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 100 {
 101         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 102         struct drm_device *dev = crtc->dev;
 103         struct radeon_device *rdev = dev->dev_private;
 104         int i;
 105
 106         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 107
 108         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 109                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 110                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 111         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 112                NI_GRPH_PRESCALE_BYPASS);
 113         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 114                NI_OVL_PRESCALE_BYPASS);
 115         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 116                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 117                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 118
 119         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 120
 121         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 122         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 123         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 124
 125         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 126         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 127         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 128
 129         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 130         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 131
 132         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 133         for (i = 0; i < 256; i++) {
 134                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 135                        (radeon_crtc->lut_r[i] << 20) |
 136                        (radeon_crtc->lut_g[i] << 10) |
 137                        (radeon_crtc->lut_b[i] << 0));
 138         }
 139
 140         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 141                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 142                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 143                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 144                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 145         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 146                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 147                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 148         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 149                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 150                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 151         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 152                (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
 153                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 154         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 155         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 156         if (ASIC_IS_DCE8(rdev)) {
 157                 /* XXX this only needs to be programmed once per crtc at startup,
 158                  * not sure where the best place for it is
 159                  */
 160                 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
 161                        CIK_CURSOR_ALPHA_BLND_ENA);
 162         }
 163 }
 164
 165 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 166 {
 167         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 168         struct drm_device *dev = crtc->dev;
 169         struct radeon_device *rdev = dev->dev_private;
 170         int i;
 171         uint32_t dac2_cntl;
 172
 173         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 174         if (radeon_crtc->crtc_id == 0)
 175                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 176         else
 177                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 178         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 179
 180         WREG8(RADEON_PALETTE_INDEX, 0);
 181         for (i = 0; i < 256; i++) {
 182                 WREG32(RADEON_PALETTE_30_DATA,
 183                              (radeon_crtc->lut_r[i] << 20) |
 184                              (radeon_crtc->lut_g[i] << 10) |
 185                              (radeon_crtc->lut_b[i] << 0));
 186         }
 187 }
 188
 189 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 190 {
 191         struct drm_device *dev = crtc->dev;
 192         struct radeon_device *rdev = dev->dev_private;
 193
 194         if (!crtc->enabled)
 195                 return;
 196
 197         if (ASIC_IS_DCE5(rdev))
 198                 dce5_crtc_load_lut(crtc);
 199         else if (ASIC_IS_DCE4(rdev))
 200                 dce4_crtc_load_lut(crtc);
 201         else if (ASIC_IS_AVIVO(rdev))
 202                 avivo_crtc_load_lut(crtc);
 203         else
 204                 legacy_crtc_load_lut(crtc);
 205 }
 206
 207 /** Sets the color ramps on behalf of fbcon */
 208 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 209                               u16 blue, int regno)
 210 {
 211         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 212
 213         radeon_crtc->lut_r[regno] = red >> 6;
 214         radeon_crtc->lut_g[regno] = green >> 6;
 215         radeon_crtc->lut_b[regno] = blue >> 6;
 216 }
 217
 218 /** Gets the color ramps on behalf of fbcon */
 219 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 220                               u16 *blue, int regno)
 221 {
 222         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 223
 224         *red = radeon_crtc->lut_r[regno] << 6;
 225         *green = radeon_crtc->lut_g[regno] << 6;
 226         *blue = radeon_crtc->lut_b[regno] << 6;
 227 }
 228
 229 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 230                                   u16 *blue, uint32_t start, uint32_t size)
 231 {
 232         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 233         int end = (start + size > 256) ? 256 : start + size, i;
 234
 235         /* userspace palettes are always correct as is */
 236         for (i = start; i < end; i++) {
 237                 radeon_crtc->lut_r[i] = red[i] >> 6;
 238                 radeon_crtc->lut_g[i] = green[i] >> 6;
 239                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 240         }
 241         radeon_crtc_load_lut(crtc);
 242 }
 243
 244 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 245 {
 246         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 247
 248         drm_crtc_cleanup(crtc);
 249         kfree(radeon_crtc);
 250 }
 251
 252 /*
 253  * Handle unpin events outside the interrupt handler proper.
 254  */
 255 static void radeon_unpin_work_func(struct work_struct *__work)
 256 {
 257         struct radeon_unpin_work *work =
 258                 container_of(__work, struct radeon_unpin_work, work);
 259         int r;
 260
 261         /* unpin of the old buffer */
 262         r = radeon_bo_reserve(work->old_rbo, false);
 263         if (likely(r == 0)) {
 264                 r = radeon_bo_unpin(work->old_rbo);
 265                 if (unlikely(r != 0)) {
 266                         DRM_ERROR("failed to unpin buffer after flip\n");
 267                 }
 268                 radeon_bo_unreserve(work->old_rbo);
 269         } else
 270                 DRM_ERROR("failed to reserve buffer after flip\n");
 271
 272         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 273         kfree(work);
 274 }
 275
 276 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 277 {
 278         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 279         struct radeon_unpin_work *work;
 280         unsigned long flags;
 281         u32 update_pending;
 282         int vpos, hpos;
 283
 284         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 285         work = radeon_crtc->unpin_work;
 286         if (work == NULL ||
 287             (work->fence && !radeon_fence_signaled(work->fence))) {
 288                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 289                 return;
 290         }
 291         /* New pageflip, or just completion of a previous one? */
 292         if (!radeon_crtc->deferred_flip_completion) {
 293                 /* do the flip (mmio) */
 294                 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
 295         } else {
 296                 /* This is just a completion of a flip queued in crtc
 297                  * at last invocation. Make sure we go directly to
 298                  * completion routine.
 299                  */
 300                 update_pending = 0;
 301                 radeon_crtc->deferred_flip_completion = 0;
 302         }
 303
 304         /* Has the pageflip already completed in crtc, or is it certain
 305          * to complete in this vblank?
 306          */
 307         if (update_pending &&
 308             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
 309                                                                &vpos, &hpos)) &&
 310             ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
 311              (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
 312                 /* crtc didn't flip in this target vblank interval,
 313                  * but flip is pending in crtc. Based on the current
 314                  * scanout position we know that the current frame is
 315                  * (nearly) complete and the flip will (likely)
 316                  * complete before the start of the next frame.
 317                  */
 318                 update_pending = 0;
 319         }
 320         if (update_pending) {
 321                 /* crtc didn't flip in this target vblank interval,
 322                  * but flip is pending in crtc. It will complete it
 323                  * in next vblank interval, so complete the flip at
 324                  * next vblank irq.
 325                  */
 326                 radeon_crtc->deferred_flip_completion = 1;
 327                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 328                 return;
 329         }
 330
 331         /* Pageflip (will be) certainly completed in this vblank. Clean up. */
 332         radeon_crtc->unpin_work = NULL;
 333
 334         /* wakeup userspace */
 335         if (work->event)
 336                 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
 337
 338         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 339
 340         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
 341         radeon_fence_unref(&work->fence);
 342         radeon_post_page_flip(work->rdev, work->crtc_id);
 343         schedule_work(&work->work);
 344 }
 345
 346 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 347                                  struct drm_framebuffer *fb,
 348                                  struct drm_pending_vblank_event *event)
 349 {
 350         struct drm_device *dev = crtc->dev;
 351         struct radeon_device *rdev = dev->dev_private;
 352         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 353         struct radeon_framebuffer *old_radeon_fb;
 354         struct radeon_framebuffer *new_radeon_fb;
 355         struct drm_gem_object *obj;
 356         struct radeon_bo *rbo;
 357         struct radeon_unpin_work *work;
 358         unsigned long flags;
 359         u32 tiling_flags, pitch_pixels;
 360         u64 base;
 361         int r;
 362
 363         work = kzalloc(sizeof *work, GFP_KERNEL);
 364         if (work == NULL)
 365                 return -ENOMEM;
 366
 367         work->event = event;
 368         work->rdev = rdev;
 369         work->crtc_id = radeon_crtc->crtc_id;
 370         old_radeon_fb = to_radeon_framebuffer(crtc->fb);
 371         new_radeon_fb = to_radeon_framebuffer(fb);
 372         /* schedule unpin of the old buffer */
 373         obj = old_radeon_fb->obj;
 374         /* take a reference to the old object */
 375         drm_gem_object_reference(obj);
 376         rbo = gem_to_radeon_bo(obj);
 377         work->old_rbo = rbo;
 378         obj = new_radeon_fb->obj;
 379         rbo = gem_to_radeon_bo(obj);
 380
 381         spin_lock(&rbo->tbo.bdev->fence_lock);
 382         if (rbo->tbo.sync_obj)
 383                 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
 384         spin_unlock(&rbo->tbo.bdev->fence_lock);
 385
 386         INIT_WORK(&work->work, radeon_unpin_work_func);
 387
 388         /* We borrow the event spin lock for protecting unpin_work */
 389         spin_lock_irqsave(&dev->event_lock, flags);
 390         if (radeon_crtc->unpin_work) {
 391                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 392                 r = -EBUSY;
 393                 goto unlock_free;
 394         }
 395         radeon_crtc->unpin_work = work;
 396         radeon_crtc->deferred_flip_completion = 0;
 397         spin_unlock_irqrestore(&dev->event_lock, flags);
 398
 399         /* pin the new buffer */
 400         DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
 401                          work->old_rbo, rbo);
 402
 403         r = radeon_bo_reserve(rbo, false);
 404         if (unlikely(r != 0)) {
 405                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 406                 goto pflip_cleanup;
 407         }
 408         /* Only 27 bit offset for legacy CRTC */
 409         r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
 410                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 411         if (unlikely(r != 0)) {
 412                 radeon_bo_unreserve(rbo);
 413                 r = -EINVAL;
 414                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 415                 goto pflip_cleanup;
 416         }
 417         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 418         radeon_bo_unreserve(rbo);
 419
 420         if (!ASIC_IS_AVIVO(rdev)) {
 421                 /* crtc offset is from display base addr not FB location */
 422                 base -= radeon_crtc->legacy_display_base_addr;
 423                 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 424
 425                 if (tiling_flags & RADEON_TILING_MACRO) {
 426                         if (ASIC_IS_R300(rdev)) {
 427                                 base &= ~0x7ff;
 428                         } else {
 429                                 int byteshift = fb->bits_per_pixel >> 4;
 430                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 431                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 432                         }
 433                 } else {
 434                         int offset = crtc->y * pitch_pixels + crtc->x;
 435                         switch (fb->bits_per_pixel) {
 436                         case 8:
 437                         default:
 438                                 offset *= 1;
 439                                 break;
 440                         case 15:
 441                         case 16:
 442                                 offset *= 2;
 443                                 break;
 444                         case 24:
 445                                 offset *= 3;
 446                                 break;
 447                         case 32:
 448                                 offset *= 4;
 449                                 break;
 450                         }
 451                         base += offset;
 452                 }
 453                 base &= ~7;
 454         }
 455
 456         spin_lock_irqsave(&dev->event_lock, flags);
 457         work->new_crtc_base = base;
 458         spin_unlock_irqrestore(&dev->event_lock, flags);
 459
 460         /* update crtc fb */
 461         crtc->fb = fb;
 462
 463         r = drm_vblank_get(dev, radeon_crtc->crtc_id);
 464         if (r) {
 465                 DRM_ERROR("failed to get vblank before flip\n");
 466                 goto pflip_cleanup1;
 467         }
 468
 469         /* set the proper interrupt */
 470         radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
 471
 472         return 0;
 473
 474 pflip_cleanup1:
 475         if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
 476                 DRM_ERROR("failed to reserve new rbo in error path\n");
 477                 goto pflip_cleanup;
 478         }
 479         if (unlikely(radeon_bo_unpin(rbo) != 0)) {
 480                 DRM_ERROR("failed to unpin new rbo in error path\n");
 481         }
 482         radeon_bo_unreserve(rbo);
 483
 484 pflip_cleanup:
 485         spin_lock_irqsave(&dev->event_lock, flags);
 486         radeon_crtc->unpin_work = NULL;
 487 unlock_free:
 488         spin_unlock_irqrestore(&dev->event_lock, flags);
 489         drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
 490         radeon_fence_unref(&work->fence);
 491         kfree(work);
 492
 493         return r;
 494 }
 495
 496 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 497         .cursor_set = radeon_crtc_cursor_set,
 498         .cursor_move = radeon_crtc_cursor_move,
 499         .gamma_set = radeon_crtc_gamma_set,
 500         .set_config = drm_crtc_helper_set_config,
 501         .destroy = radeon_crtc_destroy,
 502         .page_flip = radeon_crtc_page_flip,
 503 };
 504
 505 static void radeon_crtc_init(struct drm_device *dev, int index)
 506 {
 507         struct radeon_device *rdev = dev->dev_private;
 508         struct radeon_crtc *radeon_crtc;
 509         int i;
 510
 511         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 512         if (radeon_crtc == NULL)
 513                 return;
 514
 515         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 516
 517         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 518         radeon_crtc->crtc_id = index;
 519         rdev->mode_info.crtcs[index] = radeon_crtc;
 520
 521         if (rdev->family >= CHIP_BONAIRE) {
 522                 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
 523                 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
 524         } else {
 525                 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
 526                 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
 527         }
 528
 529 #if 0
 530         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 531         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 532         radeon_crtc->mode_set.num_connectors = 0;
 533 #endif
 534
 535         for (i = 0; i < 256; i++) {
 536                 radeon_crtc->lut_r[i] = i << 2;
 537                 radeon_crtc->lut_g[i] = i << 2;
 538                 radeon_crtc->lut_b[i] = i << 2;
 539         }
 540
 541         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 542                 radeon_atombios_init_crtc(dev, radeon_crtc);
 543         else
 544                 radeon_legacy_init_crtc(dev, radeon_crtc);
 545 }
 546
 547 static const char *encoder_names[38] = {
 548         "NONE",
 549         "INTERNAL_LVDS",
 550         "INTERNAL_TMDS1",
 551         "INTERNAL_TMDS2",
 552         "INTERNAL_DAC1",
 553         "INTERNAL_DAC2",
 554         "INTERNAL_SDVOA",
 555         "INTERNAL_SDVOB",
 556         "SI170B",
 557         "CH7303",
 558         "CH7301",
 559         "INTERNAL_DVO1",
 560         "EXTERNAL_SDVOA",
 561         "EXTERNAL_SDVOB",
 562         "TITFP513",
 563         "INTERNAL_LVTM1",
 564         "VT1623",
 565         "HDMI_SI1930",
 566         "HDMI_INTERNAL",
 567         "INTERNAL_KLDSCP_TMDS1",
 568         "INTERNAL_KLDSCP_DVO1",
 569         "INTERNAL_KLDSCP_DAC1",
 570         "INTERNAL_KLDSCP_DAC2",
 571         "SI178",
 572         "MVPU_FPGA",
 573         "INTERNAL_DDI",
 574         "VT1625",
 575         "HDMI_SI1932",
 576         "DP_AN9801",
 577         "DP_DP501",
 578         "INTERNAL_UNIPHY",
 579         "INTERNAL_KLDSCP_LVTMA",
 580         "INTERNAL_UNIPHY1",
 581         "INTERNAL_UNIPHY2",
 582         "NUTMEG",
 583         "TRAVIS",
 584         "INTERNAL_VCE",
 585         "INTERNAL_UNIPHY3",
 586 };
 587
 588 static const char *hpd_names[6] = {
 589         "HPD1",
 590         "HPD2",
 591         "HPD3",
 592         "HPD4",
 593         "HPD5",
 594         "HPD6",
 595 };
 596
 597 static void radeon_print_display_setup(struct drm_device *dev)
 598 {
 599         struct drm_connector *connector;
 600         struct radeon_connector *radeon_connector;
 601         struct drm_encoder *encoder;
 602         struct radeon_encoder *radeon_encoder;
 603         uint32_t devices;
 604         int i = 0;
 605
 606         DRM_INFO("Radeon Display Connectors\n");
 607         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 608                 radeon_connector = to_radeon_connector(connector);
 609                 DRM_INFO("Connector %d:\n", i);
 610                 DRM_INFO("  %s\n", drm_get_connector_name(connector));
 611                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 612                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 613                 if (radeon_connector->ddc_bus) {
 614                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 615                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 616                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 617                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 618                                  radeon_connector->ddc_bus->rec.a_data_reg,
 619                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 620                                  radeon_connector->ddc_bus->rec.en_data_reg,
 621                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 622                                  radeon_connector->ddc_bus->rec.y_data_reg);
 623                         if (radeon_connector->router.ddc_valid)
 624                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 625                                          radeon_connector->router.ddc_mux_control_pin,
 626                                          radeon_connector->router.ddc_mux_state);
 627                         if (radeon_connector->router.cd_valid)
 628                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 629                                          radeon_connector->router.cd_mux_control_pin,
 630                                          radeon_connector->router.cd_mux_state);
 631                 } else {
 632                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 633                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 634                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 635                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 636                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 637                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 638                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 639                 }
 640                 DRM_INFO("  Encoders:\n");
 641                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 642                         radeon_encoder = to_radeon_encoder(encoder);
 643                         devices = radeon_encoder->devices & radeon_connector->devices;
 644                         if (devices) {
 645                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 646                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 647                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 648                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 649                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 650                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 651                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 652                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 653                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 654                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 655                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 656                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 657                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 658                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 659                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 660                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 661                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 662                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 663                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 664                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 665                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 666                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 667                         }
 668                 }
 669                 i++;
 670         }
 671 }
 672
 673 static bool radeon_setup_enc_conn(struct drm_device *dev)
 674 {
 675         struct radeon_device *rdev = dev->dev_private;
 676         bool ret = false;
 677
 678         if (rdev->bios) {
 679                 if (rdev->is_atom_bios) {
 680                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 681                         if (ret == false)
 682                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 683                 } else {
 684                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 685                         if (ret == false)
 686                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 687                 }
 688         } else {
 689                 if (!ASIC_IS_AVIVO(rdev))
 690                         ret = radeon_get_legacy_connector_info_from_table(dev);
 691         }
 692         if (ret) {
 693                 radeon_setup_encoder_clones(dev);
 694                 radeon_print_display_setup(dev);
 695         }
 696
 697         return ret;
 698 }
 699
 700 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 701 {
 702         struct drm_device *dev = radeon_connector->base.dev;
 703         struct radeon_device *rdev = dev->dev_private;
 704         int ret = 0;
 705
 706         /* on hw with routers, select right port */
 707         if (radeon_connector->router.ddc_valid)
 708                 radeon_router_select_ddc_port(radeon_connector);
 709
 710         if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
 711             ENCODER_OBJECT_ID_NONE) {
 712                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 713
 714                 if (dig->dp_i2c_bus)
 715                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 716                                                               &dig->dp_i2c_bus->adapter);
 717         } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 718                    (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 719                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 720
 721                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 722                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
 723                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 724                                                               &dig->dp_i2c_bus->adapter);
 725                 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
 726                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 727                                                               &radeon_connector->ddc_bus->adapter);
 728         } else {
 729                 if (radeon_connector->ddc_bus && !radeon_connector->edid)
 730                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 731                                                               &radeon_connector->ddc_bus->adapter);
 732         }
 733
 734         if (!radeon_connector->edid) {
 735                 if (rdev->is_atom_bios) {
 736                         /* some laptops provide a hardcoded edid in rom for LCDs */
 737                         if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 738                              (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
 739                                 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 740                 } else
 741                         /* some servers provide a hardcoded edid in rom for KVMs */
 742                         radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 743         }
 744         if (radeon_connector->edid) {
 745                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 746                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 747                 return ret;
 748         }
 749         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 750         return 0;
 751 }
 752
 753 /* avivo */
 754 static void avivo_get_fb_div(struct radeon_pll *pll,
 755                              u32 target_clock,
 756                              u32 post_div,
 757                              u32 ref_div,
 758                              u32 *fb_div,
 759                              u32 *frac_fb_div)
 760 {
 761         u32 tmp = post_div * ref_div;
 762
 763         tmp *= target_clock;
 764         *fb_div = tmp / pll->reference_freq;
 765         *frac_fb_div = tmp % pll->reference_freq;
 766
 767         if (*fb_div > pll->max_feedback_div)
 768                 *fb_div = pll->max_feedback_div;
 769         else if (*fb_div < pll->min_feedback_div)
 770                 *fb_div = pll->min_feedback_div;
 771 }
 772
 773 static u32 avivo_get_post_div(struct radeon_pll *pll,
 774                               u32 target_clock)
 775 {
 776         u32 vco, post_div, tmp;
 777
 778         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 779                 return pll->post_div;
 780
 781         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
 782                 if (pll->flags & RADEON_PLL_IS_LCD)
 783                         vco = pll->lcd_pll_out_min;
 784                 else
 785                         vco = pll->pll_out_min;
 786         } else {
 787                 if (pll->flags & RADEON_PLL_IS_LCD)
 788                         vco = pll->lcd_pll_out_max;
 789                 else
 790                         vco = pll->pll_out_max;
 791         }
 792
 793         post_div = vco / target_clock;
 794         tmp = vco % target_clock;
 795
 796         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
 797                 if (tmp)
 798                         post_div++;
 799         } else {
 800                 if (!tmp)
 801                         post_div--;
 802         }
 803
 804         if (post_div > pll->max_post_div)
 805                 post_div = pll->max_post_div;
 806         else if (post_div < pll->min_post_div)
 807                 post_div = pll->min_post_div;
 808
 809         return post_div;
 810 }
 811
 812 #define MAX_TOLERANCE 10
 813
 814 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 815                               u32 freq,
 816                               u32 *dot_clock_p,
 817                               u32 *fb_div_p,
 818                               u32 *frac_fb_div_p,
 819                               u32 *ref_div_p,
 820                               u32 *post_div_p)
 821 {
 822         u32 target_clock = freq / 10;
 823         u32 post_div = avivo_get_post_div(pll, target_clock);
 824         u32 ref_div = pll->min_ref_div;
 825         u32 fb_div = 0, frac_fb_div = 0, tmp;
 826
 827         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 828                 ref_div = pll->reference_div;
 829
 830         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 831                 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
 832                 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
 833                 if (frac_fb_div >= 5) {
 834                         frac_fb_div -= 5;
 835                         frac_fb_div = frac_fb_div / 10;
 836                         frac_fb_div++;
 837                 }
 838                 if (frac_fb_div >= 10) {
 839                         fb_div++;
 840                         frac_fb_div = 0;
 841                 }
 842         } else {
 843                 while (ref_div <= pll->max_ref_div) {
 844                         avivo_get_fb_div(pll, target_clock, post_div, ref_div,
 845                                          &fb_div, &frac_fb_div);
 846                         if (frac_fb_div >= (pll->reference_freq / 2))
 847                                 fb_div++;
 848                         frac_fb_div = 0;
 849                         tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
 850                         tmp = (tmp * 10000) / target_clock;
 851
 852                         if (tmp > (10000 + MAX_TOLERANCE))
 853                                 ref_div++;
 854                         else if (tmp >= (10000 - MAX_TOLERANCE))
 855                                 break;
 856                         else
 857                                 ref_div++;
 858                 }
 859         }
 860
 861         *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
 862                 (ref_div * post_div * 10);
 863         *fb_div_p = fb_div;
 864         *frac_fb_div_p = frac_fb_div;
 865         *ref_div_p = ref_div;
 866         *post_div_p = post_div;
 867         DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
 868                       *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
 869 }
 870
 871 /* pre-avivo */
 872 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
 873 {
 874         uint64_t mod;
 875
 876         n += d / 2;
 877
 878         mod = do_div(n, d);
 879         return n;
 880 }
 881
 882 void radeon_compute_pll_legacy(struct radeon_pll *pll,
 883                                uint64_t freq,
 884                                uint32_t *dot_clock_p,
 885                                uint32_t *fb_div_p,
 886                                uint32_t *frac_fb_div_p,
 887                                uint32_t *ref_div_p,
 888                                uint32_t *post_div_p)
 889 {
 890         uint32_t min_ref_div = pll->min_ref_div;
 891         uint32_t max_ref_div = pll->max_ref_div;
 892         uint32_t min_post_div = pll->min_post_div;
 893         uint32_t max_post_div = pll->max_post_div;
 894         uint32_t min_fractional_feed_div = 0;
 895         uint32_t max_fractional_feed_div = 0;
 896         uint32_t best_vco = pll->best_vco;
 897         uint32_t best_post_div = 1;
 898         uint32_t best_ref_div = 1;
 899         uint32_t best_feedback_div = 1;
 900         uint32_t best_frac_feedback_div = 0;
 901         uint32_t best_freq = -1;
 902         uint32_t best_error = 0xffffffff;
 903         uint32_t best_vco_diff = 1;
 904         uint32_t post_div;
 905         u32 pll_out_min, pll_out_max;
 906
 907         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
 908         freq = freq * 1000;
 909
 910         if (pll->flags & RADEON_PLL_IS_LCD) {
 911                 pll_out_min = pll->lcd_pll_out_min;
 912                 pll_out_max = pll->lcd_pll_out_max;
 913         } else {
 914                 pll_out_min = pll->pll_out_min;
 915                 pll_out_max = pll->pll_out_max;
 916         }
 917
 918         if (pll_out_min > 64800)
 919                 pll_out_min = 64800;
 920
 921         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 922                 min_ref_div = max_ref_div = pll->reference_div;
 923         else {
 924                 while (min_ref_div < max_ref_div-1) {
 925                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
 926                         uint32_t pll_in = pll->reference_freq / mid;
 927                         if (pll_in < pll->pll_in_min)
 928                                 max_ref_div = mid;
 929                         else if (pll_in > pll->pll_in_max)
 930                                 min_ref_div = mid;
 931                         else
 932                                 break;
 933                 }
 934         }
 935
 936         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 937                 min_post_div = max_post_div = pll->post_div;
 938
 939         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 940                 min_fractional_feed_div = pll->min_frac_feedback_div;
 941                 max_fractional_feed_div = pll->max_frac_feedback_div;
 942         }
 943
 944         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
 945                 uint32_t ref_div;
 946
 947                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
 948                         continue;
 949
 950                 /* legacy radeons only have a few post_divs */
 951                 if (pll->flags & RADEON_PLL_LEGACY) {
 952                         if ((post_div == 5) ||
 953                             (post_div == 7) ||
 954                             (post_div == 9) ||
 955                             (post_div == 10) ||
 956                             (post_div == 11) ||
 957                             (post_div == 13) ||
 958                             (post_div == 14) ||
 959                             (post_div == 15))
 960                                 continue;
 961                 }
 962
 963                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
 964                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
 965                         uint32_t pll_in = pll->reference_freq / ref_div;
 966                         uint32_t min_feed_div = pll->min_feedback_div;
 967                         uint32_t max_feed_div = pll->max_feedback_div + 1;
 968
 969                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
 970                                 continue;
 971
 972                         while (min_feed_div < max_feed_div) {
 973                                 uint32_t vco;
 974                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
 975                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
 976                                 uint32_t frac_feedback_div;
 977                                 uint64_t tmp;
 978
 979                                 feedback_div = (min_feed_div + max_feed_div) / 2;
 980
 981                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
 982                                 vco = radeon_div(tmp, ref_div);
 983
 984                                 if (vco < pll_out_min) {
 985                                         min_feed_div = feedback_div + 1;
 986                                         continue;
 987                                 } else if (vco > pll_out_max) {
 988                                         max_feed_div = feedback_div;
 989                                         continue;
 990                                 }
 991
 992                                 while (min_frac_feed_div < max_frac_feed_div) {
 993                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
 994                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
 995                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
 996                                         current_freq = radeon_div(tmp, ref_div * post_div);
 997
 998                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
 999                                                 if (freq < current_freq)
1000                                                         error = 0xffffffff;
1001                                                 else
1002                                                         error = freq - current_freq;
1003                                         } else
1004                                                 error = abs(current_freq - freq);
1005                                         vco_diff = abs(vco - best_vco);
1006
1007                                         if ((best_vco == 0 && error < best_error) ||
1008                                             (best_vco != 0 &&
1009                                              ((best_error > 100 && error < best_error - 100) ||
1010                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1011                                                 best_post_div = post_div;
1012                                                 best_ref_div = ref_div;
1013                                                 best_feedback_div = feedback_div;
1014                                                 best_frac_feedback_div = frac_feedback_div;
1015                                                 best_freq = current_freq;
1016                                                 best_error = error;
1017                                                 best_vco_diff = vco_diff;
1018                                         } else if (current_freq == freq) {
1019                                                 if (best_freq == -1) {
1020                                                         best_post_div = post_div;
1021                                                         best_ref_div = ref_div;
1022                                                         best_feedback_div = feedback_div;
1023                                                         best_frac_feedback_div = frac_feedback_div;
1024                                                         best_freq = current_freq;
1025                                                         best_error = error;
1026                                                         best_vco_diff = vco_diff;
1027                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1028                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1029                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1030                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1031                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1032                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1033                                                         best_post_div = post_div;
1034                                                         best_ref_div = ref_div;
1035                                                         best_feedback_div = feedback_div;
1036                                                         best_frac_feedback_div = frac_feedback_div;
1037                                                         best_freq = current_freq;
1038                                                         best_error = error;
1039                                                         best_vco_diff = vco_diff;
1040                                                 }
1041                                         }
1042                                         if (current_freq < freq)
1043                                                 min_frac_feed_div = frac_feedback_div + 1;
1044                                         else
1045                                                 max_frac_feed_div = frac_feedback_div;
1046                                 }
1047                                 if (current_freq < freq)
1048                                         min_feed_div = feedback_div + 1;
1049                                 else
1050                                         max_feed_div = feedback_div;
1051                         }
1052                 }
1053         }
1054
1055         *dot_clock_p = best_freq / 10000;
1056         *fb_div_p = best_feedback_div;
1057         *frac_fb_div_p = best_frac_feedback_div;
1058         *ref_div_p = best_ref_div;
1059         *post_div_p = best_post_div;
1060         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1061                       (long long)freq,
1062                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1063                       best_ref_div, best_post_div);
1064
1065 }
1066
1067 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1068 {
1069         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1070
1071         if (radeon_fb->obj) {
1072                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1073         }
1074         drm_framebuffer_cleanup(fb);
1075         kfree(radeon_fb);
1076 }
1077
1078 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1079                                                   struct drm_file *file_priv,
1080                                                   unsigned int *handle)
1081 {
1082         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1083
1084         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1085 }
1086
1087 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1088         .destroy = radeon_user_framebuffer_destroy,
1089         .create_handle = radeon_user_framebuffer_create_handle,
1090 };
1091
1092 int
1093 radeon_framebuffer_init(struct drm_device *dev,
1094                         struct radeon_framebuffer *rfb,
1095                         struct drm_mode_fb_cmd2 *mode_cmd,
1096                         struct drm_gem_object *obj)
1097 {
1098         int ret;
1099         rfb->obj = obj;
1100         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1101         ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1102         if (ret) {
1103                 rfb->obj = NULL;
1104                 return ret;
1105         }
1106         return 0;
1107 }
1108
1109 static struct drm_framebuffer *
1110 radeon_user_framebuffer_create(struct drm_device *dev,
1111                                struct drm_file *file_priv,
1112                                struct drm_mode_fb_cmd2 *mode_cmd)
1113 {
1114         struct drm_gem_object *obj;
1115         struct radeon_framebuffer *radeon_fb;
1116         int ret;
1117
1118         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1119         if (obj ==  NULL) {
1120                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1121                         "can't create framebuffer\n", mode_cmd->handles[0]);
1122                 return ERR_PTR(-ENOENT);
1123         }
1124
1125         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1126         if (radeon_fb == NULL) {
1127                 drm_gem_object_unreference_unlocked(obj);
1128                 return ERR_PTR(-ENOMEM);
1129         }
1130
1131         ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1132         if (ret) {
1133                 kfree(radeon_fb);
1134                 drm_gem_object_unreference_unlocked(obj);
1135                 return ERR_PTR(ret);
1136         }
1137
1138         return &radeon_fb->base;
1139 }
1140
1141 static void radeon_output_poll_changed(struct drm_device *dev)
1142 {
1143         struct radeon_device *rdev = dev->dev_private;
1144         radeon_fb_output_poll_changed(rdev);
1145 }
1146
1147 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1148         .fb_create = radeon_user_framebuffer_create,
1149         .output_poll_changed = radeon_output_poll_changed
1150 };
1151
1152 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1153 {       { 0, "driver" },
1154         { 1, "bios" },
1155 };
1156
1157 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1158 {       { TV_STD_NTSC, "ntsc" },
1159         { TV_STD_PAL, "pal" },
1160         { TV_STD_PAL_M, "pal-m" },
1161         { TV_STD_PAL_60, "pal-60" },
1162         { TV_STD_NTSC_J, "ntsc-j" },
1163         { TV_STD_SCART_PAL, "scart-pal" },
1164         { TV_STD_PAL_CN, "pal-cn" },
1165         { TV_STD_SECAM, "secam" },
1166 };
1167
1168 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1169 {       { UNDERSCAN_OFF, "off" },
1170         { UNDERSCAN_ON, "on" },
1171         { UNDERSCAN_AUTO, "auto" },
1172 };
1173
1174 static int radeon_modeset_create_props(struct radeon_device *rdev)
1175 {
1176         int sz;
1177
1178         if (rdev->is_atom_bios) {
1179                 rdev->mode_info.coherent_mode_property =
1180                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1181                 if (!rdev->mode_info.coherent_mode_property)
1182                         return -ENOMEM;
1183         }
1184
1185         if (!ASIC_IS_AVIVO(rdev)) {
1186                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1187                 rdev->mode_info.tmds_pll_property =
1188                         drm_property_create_enum(rdev->ddev, 0,
1189                                             "tmds_pll",
1190                                             radeon_tmds_pll_enum_list, sz);
1191         }
1192
1193         rdev->mode_info.load_detect_property =
1194                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1195         if (!rdev->mode_info.load_detect_property)
1196                 return -ENOMEM;
1197
1198         drm_mode_create_scaling_mode_property(rdev->ddev);
1199
1200         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1201         rdev->mode_info.tv_std_property =
1202                 drm_property_create_enum(rdev->ddev, 0,
1203                                     "tv standard",
1204                                     radeon_tv_std_enum_list, sz);
1205
1206         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1207         rdev->mode_info.underscan_property =
1208                 drm_property_create_enum(rdev->ddev, 0,
1209                                     "underscan",
1210                                     radeon_underscan_enum_list, sz);
1211
1212         rdev->mode_info.underscan_hborder_property =
1213                 drm_property_create_range(rdev->ddev, 0,
1214                                         "underscan hborder", 0, 128);
1215         if (!rdev->mode_info.underscan_hborder_property)
1216                 return -ENOMEM;
1217
1218         rdev->mode_info.underscan_vborder_property =
1219                 drm_property_create_range(rdev->ddev, 0,
1220                                         "underscan vborder", 0, 128);
1221         if (!rdev->mode_info.underscan_vborder_property)
1222                 return -ENOMEM;
1223
1224         return 0;
1225 }
1226
1227 void radeon_update_display_priority(struct radeon_device *rdev)
1228 {
1229         /* adjustment options for the display watermarks */
1230         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1231                 /* set display priority to high for r3xx, rv515 chips
1232                  * this avoids flickering due to underflow to the
1233                  * display controllers during heavy acceleration.
1234                  * Don't force high on rs4xx igp chips as it seems to
1235                  * affect the sound card.  See kernel bug 15982.
1236                  */
1237                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1238                     !(rdev->flags & RADEON_IS_IGP))
1239                         rdev->disp_priority = 2;
1240                 else
1241                         rdev->disp_priority = 0;
1242         } else
1243                 rdev->disp_priority = radeon_disp_priority;
1244
1245 }
1246
1247 /*
1248  * Allocate hdmi structs and determine register offsets
1249  */
1250 static void radeon_afmt_init(struct radeon_device *rdev)
1251 {
1252         int i;
1253
1254         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1255                 rdev->mode_info.afmt[i] = NULL;
1256
1257         if (ASIC_IS_DCE6(rdev)) {
1258                 /* todo */
1259         } else if (ASIC_IS_DCE4(rdev)) {
1260                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1261                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1262                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1263                 if (rdev->mode_info.afmt[0]) {
1264                         rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1265                         rdev->mode_info.afmt[0]->id = 0;
1266                 }
1267                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1268                 if (rdev->mode_info.afmt[1]) {
1269                         rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1270                         rdev->mode_info.afmt[1]->id = 1;
1271                 }
1272                 if (!ASIC_IS_DCE41(rdev)) {
1273                         rdev->mode_info.afmt[2] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1274                         if (rdev->mode_info.afmt[2]) {
1275                                 rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1276                                 rdev->mode_info.afmt[2]->id = 2;
1277                         }
1278                         rdev->mode_info.afmt[3] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1279                         if (rdev->mode_info.afmt[3]) {
1280                                 rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1281                                 rdev->mode_info.afmt[3]->id = 3;
1282                         }
1283                         rdev->mode_info.afmt[4] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1284                         if (rdev->mode_info.afmt[4]) {
1285                                 rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1286                                 rdev->mode_info.afmt[4]->id = 4;
1287                         }
1288                         rdev->mode_info.afmt[5] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1289                         if (rdev->mode_info.afmt[5]) {
1290                                 rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1291                                 rdev->mode_info.afmt[5]->id = 5;
1292                         }
1293                 }
1294         } else if (ASIC_IS_DCE3(rdev)) {
1295                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1296                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1297                 if (rdev->mode_info.afmt[0]) {
1298                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1299                         rdev->mode_info.afmt[0]->id = 0;
1300                 }
1301                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1302                 if (rdev->mode_info.afmt[1]) {
1303                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1304                         rdev->mode_info.afmt[1]->id = 1;
1305                 }
1306         } else if (ASIC_IS_DCE2(rdev)) {
1307                 /* DCE2 has at least 1 routable audio block */
1308                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1309                 if (rdev->mode_info.afmt[0]) {
1310                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1311                         rdev->mode_info.afmt[0]->id = 0;
1312                 }
1313                 /* r6xx has 2 routable audio blocks */
1314                 if (rdev->family >= CHIP_R600) {
1315                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1316                         if (rdev->mode_info.afmt[1]) {
1317                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1318                                 rdev->mode_info.afmt[1]->id = 1;
1319                         }
1320                 }
1321         }
1322 }
1323
1324 static void radeon_afmt_fini(struct radeon_device *rdev)
1325 {
1326         int i;
1327
1328         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1329                 kfree(rdev->mode_info.afmt[i]);
1330                 rdev->mode_info.afmt[i] = NULL;
1331         }
1332 }
1333
1334 int radeon_modeset_init(struct radeon_device *rdev)
1335 {
1336         int i;
1337         int ret;
1338
1339         drm_mode_config_init(rdev->ddev);
1340         rdev->mode_info.mode_config_initialized = true;
1341
1342         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1343
1344         if (ASIC_IS_DCE5(rdev)) {
1345                 rdev->ddev->mode_config.max_width = 16384;
1346                 rdev->ddev->mode_config.max_height = 16384;
1347         } else if (ASIC_IS_AVIVO(rdev)) {
1348                 rdev->ddev->mode_config.max_width = 8192;
1349                 rdev->ddev->mode_config.max_height = 8192;
1350         } else {
1351                 rdev->ddev->mode_config.max_width = 4096;
1352                 rdev->ddev->mode_config.max_height = 4096;
1353         }
1354
1355         rdev->ddev->mode_config.preferred_depth = 24;
1356         rdev->ddev->mode_config.prefer_shadow = 1;
1357
1358         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1359
1360         ret = radeon_modeset_create_props(rdev);
1361         if (ret) {
1362                 return ret;
1363         }
1364
1365         /* init i2c buses */
1366         radeon_i2c_init(rdev);
1367
1368         /* check combios for a valid hardcoded EDID - Sun servers */
1369         if (!rdev->is_atom_bios) {
1370                 /* check for hardcoded EDID in BIOS */
1371                 radeon_combios_check_hardcoded_edid(rdev);
1372         }
1373
1374         /* allocate crtcs */
1375         for (i = 0; i < rdev->num_crtc; i++) {
1376                 radeon_crtc_init(rdev->ddev, i);
1377         }
1378
1379         /* okay we should have all the bios connectors */
1380         ret = radeon_setup_enc_conn(rdev->ddev);
1381         if (!ret) {
1382                 return ret;
1383         }
1384
1385         /* init dig PHYs, disp eng pll */
1386         if (rdev->is_atom_bios) {
1387                 radeon_atom_encoder_init(rdev);
1388                 radeon_atom_disp_eng_pll_init(rdev);
1389         }
1390
1391         /* initialize hpd */
1392         radeon_hpd_init(rdev);
1393
1394         /* setup afmt */
1395         radeon_afmt_init(rdev);
1396
1397         /* Initialize power management */
1398         radeon_pm_init(rdev);
1399
1400         radeon_fbdev_init(rdev);
1401         drm_kms_helper_poll_init(rdev->ddev);
1402
1403         return 0;
1404 }
1405
1406 void radeon_modeset_fini(struct radeon_device *rdev)
1407 {
1408         radeon_fbdev_fini(rdev);
1409         kfree(rdev->mode_info.bios_hardcoded_edid);
1410         radeon_pm_fini(rdev);
1411
1412         if (rdev->mode_info.mode_config_initialized) {
1413                 radeon_afmt_fini(rdev);
1414                 drm_kms_helper_poll_fini(rdev->ddev);
1415                 radeon_hpd_fini(rdev);
1416                 drm_mode_config_cleanup(rdev->ddev);
1417                 rdev->mode_info.mode_config_initialized = false;
1418         }
1419         /* free i2c buses */
1420         radeon_i2c_fini(rdev);
1421 }
1422
1423 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1424 {
1425         /* try and guess if this is a tv or a monitor */
1426         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1427             (mode->vdisplay == 576) || /* 576p */
1428             (mode->vdisplay == 720) || /* 720p */
1429             (mode->vdisplay == 1080)) /* 1080p */
1430                 return true;
1431         else
1432                 return false;
1433 }
1434
1435 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1436                                 const struct drm_display_mode *mode,
1437                                 struct drm_display_mode *adjusted_mode)
1438 {
1439         struct drm_device *dev = crtc->dev;
1440         struct radeon_device *rdev = dev->dev_private;
1441         struct drm_encoder *encoder;
1442         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1443         struct radeon_encoder *radeon_encoder;
1444         struct drm_connector *connector;
1445         struct radeon_connector *radeon_connector;
1446         bool first = true;
1447         u32 src_v = 1, dst_v = 1;
1448         u32 src_h = 1, dst_h = 1;
1449
1450         radeon_crtc->h_border = 0;
1451         radeon_crtc->v_border = 0;
1452
1453         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1454                 if (encoder->crtc != crtc)
1455                         continue;
1456                 radeon_encoder = to_radeon_encoder(encoder);
1457                 connector = radeon_get_connector_for_encoder(encoder);
1458                 radeon_connector = to_radeon_connector(connector);
1459
1460                 if (first) {
1461                         /* set scaling */
1462                         if (radeon_encoder->rmx_type == RMX_OFF)
1463                                 radeon_crtc->rmx_type = RMX_OFF;
1464                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1465                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1466                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1467                         else
1468                                 radeon_crtc->rmx_type = RMX_OFF;
1469                         /* copy native mode */
1470                         memcpy(&radeon_crtc->native_mode,
1471                                &radeon_encoder->native_mode,
1472                                 sizeof(struct drm_display_mode));
1473                         src_v = crtc->mode.vdisplay;
1474                         dst_v = radeon_crtc->native_mode.vdisplay;
1475                         src_h = crtc->mode.hdisplay;
1476                         dst_h = radeon_crtc->native_mode.hdisplay;
1477
1478                         /* fix up for overscan on hdmi */
1479                         if (ASIC_IS_AVIVO(rdev) &&
1480                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1481                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1482                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1483                               drm_detect_hdmi_monitor(radeon_connector->edid) &&
1484                               is_hdtv_mode(mode)))) {
1485                                 if (radeon_encoder->underscan_hborder != 0)
1486                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1487                                 else
1488                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1489                                 if (radeon_encoder->underscan_vborder != 0)
1490                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1491                                 else
1492                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1493                                 radeon_crtc->rmx_type = RMX_FULL;
1494                                 src_v = crtc->mode.vdisplay;
1495                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1496                                 src_h = crtc->mode.hdisplay;
1497                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1498                         }
1499                         first = false;
1500                 } else {
1501                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1502                                 /* WARNING: Right now this can't happen but
1503                                  * in the future we need to check that scaling
1504                                  * are consistent across different encoder
1505                                  * (ie all encoder can work with the same
1506                                  *  scaling).
1507                                  */
1508                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1509                                 return false;
1510                         }
1511                 }
1512         }
1513         if (radeon_crtc->rmx_type != RMX_OFF) {
1514                 fixed20_12 a, b;
1515                 a.full = dfixed_const(src_v);
1516                 b.full = dfixed_const(dst_v);
1517                 radeon_crtc->vsc.full = dfixed_div(a, b);
1518                 a.full = dfixed_const(src_h);
1519                 b.full = dfixed_const(dst_h);
1520                 radeon_crtc->hsc.full = dfixed_div(a, b);
1521         } else {
1522                 radeon_crtc->vsc.full = dfixed_const(1);
1523                 radeon_crtc->hsc.full = dfixed_const(1);
1524         }
1525         return true;
1526 }
1527
1528 /*
1529  * Retrieve current video scanout position of crtc on a given gpu.
1530  *
1531  * \param dev Device to query.
1532  * \param crtc Crtc to query.
1533  * \param *vpos Location where vertical scanout position should be stored.
1534  * \param *hpos Location where horizontal scanout position should go.
1535  *
1536  * Returns vpos as a positive number while in active scanout area.
1537  * Returns vpos as a negative number inside vblank, counting the number
1538  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1539  * until start of active scanout / end of vblank."
1540  *
1541  * \return Flags, or'ed together as follows:
1542  *
1543  * DRM_SCANOUTPOS_VALID = Query successful.
1544  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1545  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1546  * this flag means that returned position may be offset by a constant but
1547  * unknown small number of scanlines wrt. real scanout position.
1548  *
1549  */
1550 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
1551 {
1552         u32 stat_crtc = 0, vbl = 0, position = 0;
1553         int vbl_start, vbl_end, vtotal, ret = 0;
1554         bool in_vbl = true;
1555
1556         struct radeon_device *rdev = dev->dev_private;
1557
1558         if (ASIC_IS_DCE4(rdev)) {
1559                 if (crtc == 0) {
1560                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1561                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1562                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1563                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1564                         ret |= DRM_SCANOUTPOS_VALID;
1565                 }
1566                 if (crtc == 1) {
1567                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1568                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1569                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1570                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1571                         ret |= DRM_SCANOUTPOS_VALID;
1572                 }
1573                 if (crtc == 2) {
1574                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1575                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1576                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1577                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1578                         ret |= DRM_SCANOUTPOS_VALID;
1579                 }
1580                 if (crtc == 3) {
1581                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1582                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1583                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1584                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1585                         ret |= DRM_SCANOUTPOS_VALID;
1586                 }
1587                 if (crtc == 4) {
1588                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1589                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1590                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1591                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1592                         ret |= DRM_SCANOUTPOS_VALID;
1593                 }
1594                 if (crtc == 5) {
1595                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1596                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1597                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1598                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1599                         ret |= DRM_SCANOUTPOS_VALID;
1600                 }
1601         } else if (ASIC_IS_AVIVO(rdev)) {
1602                 if (crtc == 0) {
1603                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1604                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1605                         ret |= DRM_SCANOUTPOS_VALID;
1606                 }
1607                 if (crtc == 1) {
1608                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1609                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1610                         ret |= DRM_SCANOUTPOS_VALID;
1611                 }
1612         } else {
1613                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1614                 if (crtc == 0) {
1615                         /* Assume vbl_end == 0, get vbl_start from
1616                          * upper 16 bits.
1617                          */
1618                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1619                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1620                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1621                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1622                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1623                         if (!(stat_crtc & 1))
1624                                 in_vbl = false;
1625
1626                         ret |= DRM_SCANOUTPOS_VALID;
1627                 }
1628                 if (crtc == 1) {
1629                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1630                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1631                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1632                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1633                         if (!(stat_crtc & 1))
1634                                 in_vbl = false;
1635
1636                         ret |= DRM_SCANOUTPOS_VALID;
1637                 }
1638         }
1639
1640         /* Decode into vertical and horizontal scanout position. */
1641         *vpos = position & 0x1fff;
1642         *hpos = (position >> 16) & 0x1fff;
1643
1644         /* Valid vblank area boundaries from gpu retrieved? */
1645         if (vbl > 0) {
1646                 /* Yes: Decode. */
1647                 ret |= DRM_SCANOUTPOS_ACCURATE;
1648                 vbl_start = vbl & 0x1fff;
1649                 vbl_end = (vbl >> 16) & 0x1fff;
1650         }
1651         else {
1652                 /* No: Fake something reasonable which gives at least ok results. */
1653                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1654                 vbl_end = 0;
1655         }
1656
1657         /* Test scanout position against vblank region. */
1658         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1659                 in_vbl = false;
1660
1661         /* Check if inside vblank area and apply corrective offsets:
1662          * vpos will then be >=0 in video scanout area, but negative
1663          * within vblank area, counting down the number of lines until
1664          * start of scanout.
1665          */
1666
1667         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1668         if (in_vbl && (*vpos >= vbl_start)) {
1669                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1670                 *vpos = *vpos - vtotal;
1671         }
1672
1673         /* Correct for shifted end of vbl at vbl_end. */
1674         *vpos = *vpos - vbl_end;
1675
1676         /* In vblank? */
1677         if (in_vbl)
1678                 ret |= DRM_SCANOUTPOS_INVBL;
1679
1680         return ret;
1681 }