Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include "drm_crtc_helper.h"
  34 #include "drm_edid.h"
  35
  36 static int radeon_ddc_dump(struct drm_connector *connector);
  37
  38 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  39 {
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         struct drm_device *dev = crtc->dev;
  42         struct radeon_device *rdev = dev->dev_private;
  43         int i;
  44
  45         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  46         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  47
  48         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  49         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  51
  52         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  53         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  55
  56         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  57         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  58         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  59
  60         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  61         for (i = 0; i < 256; i++) {
  62                 WREG32(AVIVO_DC_LUT_30_COLOR,
  63                              (radeon_crtc->lut_r[i] << 20) |
  64                              (radeon_crtc->lut_g[i] << 10) |
  65                              (radeon_crtc->lut_b[i] << 0));
  66         }
  67
  68         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  69 }
  70
  71 static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
  72 {
  73         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  74         struct drm_device *dev = crtc->dev;
  75         struct radeon_device *rdev = dev->dev_private;
  76         int i;
  77
  78         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  79         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  80
  81         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  82         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  83         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  84
  85         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  86         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  87         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  88
  89         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  90         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  91
  92         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  93         for (i = 0; i < 256; i++) {
  94                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  95                        (radeon_crtc->lut_r[i] << 20) |
  96                        (radeon_crtc->lut_g[i] << 10) |
  97                        (radeon_crtc->lut_b[i] << 0));
  98         }
  99 }
 100
 101 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 102 {
 103         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 104         struct drm_device *dev = crtc->dev;
 105         struct radeon_device *rdev = dev->dev_private;
 106         int i;
 107         uint32_t dac2_cntl;
 108
 109         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 110         if (radeon_crtc->crtc_id == 0)
 111                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 112         else
 113                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 114         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 115
 116         WREG8(RADEON_PALETTE_INDEX, 0);
 117         for (i = 0; i < 256; i++) {
 118                 WREG32(RADEON_PALETTE_30_DATA,
 119                              (radeon_crtc->lut_r[i] << 20) |
 120                              (radeon_crtc->lut_g[i] << 10) |
 121                              (radeon_crtc->lut_b[i] << 0));
 122         }
 123 }
 124
 125 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 126 {
 127         struct drm_device *dev = crtc->dev;
 128         struct radeon_device *rdev = dev->dev_private;
 129
 130         if (!crtc->enabled)
 131                 return;
 132
 133         if (ASIC_IS_DCE4(rdev))
 134                 evergreen_crtc_load_lut(crtc);
 135         else if (ASIC_IS_AVIVO(rdev))
 136                 avivo_crtc_load_lut(crtc);
 137         else
 138                 legacy_crtc_load_lut(crtc);
 139 }
 140
 141 /** Sets the color ramps on behalf of fbcon */
 142 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 143                               u16 blue, int regno)
 144 {
 145         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 146
 147         radeon_crtc->lut_r[regno] = red >> 6;
 148         radeon_crtc->lut_g[regno] = green >> 6;
 149         radeon_crtc->lut_b[regno] = blue >> 6;
 150 }
 151
 152 /** Gets the color ramps on behalf of fbcon */
 153 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 154                               u16 *blue, int regno)
 155 {
 156         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 157
 158         *red = radeon_crtc->lut_r[regno] << 6;
 159         *green = radeon_crtc->lut_g[regno] << 6;
 160         *blue = radeon_crtc->lut_b[regno] << 6;
 161 }
 162
 163 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 164                                   u16 *blue, uint32_t start, uint32_t size)
 165 {
 166         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 167         int end = (start + size > 256) ? 256 : start + size, i;
 168
 169         /* userspace palettes are always correct as is */
 170         for (i = start; i < end; i++) {
 171                 radeon_crtc->lut_r[i] = red[i] >> 6;
 172                 radeon_crtc->lut_g[i] = green[i] >> 6;
 173                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 174         }
 175         radeon_crtc_load_lut(crtc);
 176 }
 177
 178 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 179 {
 180         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 181
 182         drm_crtc_cleanup(crtc);
 183         kfree(radeon_crtc);
 184 }
 185
 186 /*
 187  * Handle unpin events outside the interrupt handler proper.
 188  */
 189 static void radeon_unpin_work_func(struct work_struct *__work)
 190 {
 191         struct radeon_unpin_work *work =
 192                 container_of(__work, struct radeon_unpin_work, work);
 193         int r;
 194
 195         /* unpin of the old buffer */
 196         r = radeon_bo_reserve(work->old_rbo, false);
 197         if (likely(r == 0)) {
 198                 r = radeon_bo_unpin(work->old_rbo);
 199                 if (unlikely(r != 0)) {
 200                         DRM_ERROR("failed to unpin buffer after flip\n");
 201                 }
 202                 radeon_bo_unreserve(work->old_rbo);
 203         } else
 204                 DRM_ERROR("failed to reserve buffer after flip\n");
 205         kfree(work);
 206 }
 207
 208 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 209 {
 210         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 211         struct radeon_unpin_work *work;
 212         struct drm_pending_vblank_event *e;
 213         struct timeval now;
 214         unsigned long flags;
 215         u32 update_pending;
 216         int vpos, hpos;
 217
 218         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 219         work = radeon_crtc->unpin_work;
 220         if (work == NULL ||
 221             !radeon_fence_signaled(work->fence)) {
 222                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 223                 return;
 224         }
 225         /* New pageflip, or just completion of a previous one? */
 226         if (!radeon_crtc->deferred_flip_completion) {
 227                 /* do the flip (mmio) */
 228                 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
 229         } else {
 230                 /* This is just a completion of a flip queued in crtc
 231                  * at last invocation. Make sure we go directly to
 232                  * completion routine.
 233                  */
 234                 update_pending = 0;
 235                 radeon_crtc->deferred_flip_completion = 0;
 236         }
 237
 238         /* Has the pageflip already completed in crtc, or is it certain
 239          * to complete in this vblank?
 240          */
 241         if (update_pending &&
 242             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
 243                                                                &vpos, &hpos)) &&
 244             (vpos >=0) &&
 245             (vpos < (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100)) {
 246                 /* crtc didn't flip in this target vblank interval,
 247                  * but flip is pending in crtc. It will complete it
 248                  * in next vblank interval, so complete the flip at
 249                  * next vblank irq.
 250                  */
 251                 radeon_crtc->deferred_flip_completion = 1;
 252                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 253                 return;
 254         }
 255
 256         /* Pageflip (will be) certainly completed in this vblank. Clean up. */
 257         radeon_crtc->unpin_work = NULL;
 258
 259         /* wakeup userspace */
 260         if (work->event) {
 261                 e = work->event;
 262                 e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
 263                 e->event.tv_sec = now.tv_sec;
 264                 e->event.tv_usec = now.tv_usec;
 265                 list_add_tail(&e->base.link, &e->base.file_priv->event_list);
 266                 wake_up_interruptible(&e->base.file_priv->event_wait);
 267         }
 268         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 269
 270         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
 271         radeon_fence_unref(&work->fence);
 272         radeon_post_page_flip(work->rdev, work->crtc_id);
 273         schedule_work(&work->work);
 274 }
 275
 276 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 277                                  struct drm_framebuffer *fb,
 278                                  struct drm_pending_vblank_event *event)
 279 {
 280         struct drm_device *dev = crtc->dev;
 281         struct radeon_device *rdev = dev->dev_private;
 282         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 283         struct radeon_framebuffer *old_radeon_fb;
 284         struct radeon_framebuffer *new_radeon_fb;
 285         struct drm_gem_object *obj;
 286         struct radeon_bo *rbo;
 287         struct radeon_fence *fence;
 288         struct radeon_unpin_work *work;
 289         unsigned long flags;
 290         u32 tiling_flags, pitch_pixels;
 291         u64 base;
 292         int r;
 293
 294         work = kzalloc(sizeof *work, GFP_KERNEL);
 295         if (work == NULL)
 296                 return -ENOMEM;
 297
 298         r = radeon_fence_create(rdev, &fence);
 299         if (unlikely(r != 0)) {
 300                 kfree(work);
 301                 DRM_ERROR("flip queue: failed to create fence.\n");
 302                 return -ENOMEM;
 303         }
 304         work->event = event;
 305         work->rdev = rdev;
 306         work->crtc_id = radeon_crtc->crtc_id;
 307         work->fence = radeon_fence_ref(fence);
 308         old_radeon_fb = to_radeon_framebuffer(crtc->fb);
 309         new_radeon_fb = to_radeon_framebuffer(fb);
 310         /* schedule unpin of the old buffer */
 311         obj = old_radeon_fb->obj;
 312         rbo = obj->driver_private;
 313         work->old_rbo = rbo;
 314         INIT_WORK(&work->work, radeon_unpin_work_func);
 315
 316         /* We borrow the event spin lock for protecting unpin_work */
 317         spin_lock_irqsave(&dev->event_lock, flags);
 318         if (radeon_crtc->unpin_work) {
 319                 spin_unlock_irqrestore(&dev->event_lock, flags);
 320                 kfree(work);
 321                 radeon_fence_unref(&fence);
 322
 323                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 324                 return -EBUSY;
 325         }
 326         radeon_crtc->unpin_work = work;
 327         radeon_crtc->deferred_flip_completion = 0;
 328         spin_unlock_irqrestore(&dev->event_lock, flags);
 329
 330         /* pin the new buffer */
 331         obj = new_radeon_fb->obj;
 332         rbo = obj->driver_private;
 333
 334         DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
 335                          work->old_rbo, rbo);
 336
 337         r = radeon_bo_reserve(rbo, false);
 338         if (unlikely(r != 0)) {
 339                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 340                 goto pflip_cleanup;
 341         }
 342         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
 343         if (unlikely(r != 0)) {
 344                 radeon_bo_unreserve(rbo);
 345                 r = -EINVAL;
 346                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 347                 goto pflip_cleanup;
 348         }
 349         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 350         radeon_bo_unreserve(rbo);
 351
 352         if (!ASIC_IS_AVIVO(rdev)) {
 353                 /* crtc offset is from display base addr not FB location */
 354                 base -= radeon_crtc->legacy_display_base_addr;
 355                 pitch_pixels = fb->pitch / (fb->bits_per_pixel / 8);
 356
 357                 if (tiling_flags & RADEON_TILING_MACRO) {
 358                         if (ASIC_IS_R300(rdev)) {
 359                                 base &= ~0x7ff;
 360                         } else {
 361                                 int byteshift = fb->bits_per_pixel >> 4;
 362                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 363                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 364                         }
 365                 } else {
 366                         int offset = crtc->y * pitch_pixels + crtc->x;
 367                         switch (fb->bits_per_pixel) {
 368                         case 8:
 369                         default:
 370                                 offset *= 1;
 371                                 break;
 372                         case 15:
 373                         case 16:
 374                                 offset *= 2;
 375                                 break;
 376                         case 24:
 377                                 offset *= 3;
 378                                 break;
 379                         case 32:
 380                                 offset *= 4;
 381                                 break;
 382                         }
 383                         base += offset;
 384                 }
 385                 base &= ~7;
 386         }
 387
 388         spin_lock_irqsave(&dev->event_lock, flags);
 389         work->new_crtc_base = base;
 390         spin_unlock_irqrestore(&dev->event_lock, flags);
 391
 392         /* update crtc fb */
 393         crtc->fb = fb;
 394
 395         r = drm_vblank_get(dev, radeon_crtc->crtc_id);
 396         if (r) {
 397                 DRM_ERROR("failed to get vblank before flip\n");
 398                 goto pflip_cleanup1;
 399         }
 400
 401         /* 32 ought to cover us */
 402         r = radeon_ring_lock(rdev, 32);
 403         if (r) {
 404                 DRM_ERROR("failed to lock the ring before flip\n");
 405                 goto pflip_cleanup2;
 406         }
 407
 408         /* emit the fence */
 409         radeon_fence_emit(rdev, fence);
 410         /* set the proper interrupt */
 411         radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
 412         /* fire the ring */
 413         radeon_ring_unlock_commit(rdev);
 414
 415         return 0;
 416
 417 pflip_cleanup2:
 418         drm_vblank_put(dev, radeon_crtc->crtc_id);
 419
 420 pflip_cleanup1:
 421         r = radeon_bo_reserve(rbo, false);
 422         if (unlikely(r != 0)) {
 423                 DRM_ERROR("failed to reserve new rbo in error path\n");
 424                 goto pflip_cleanup;
 425         }
 426         r = radeon_bo_unpin(rbo);
 427         if (unlikely(r != 0)) {
 428                 radeon_bo_unreserve(rbo);
 429                 r = -EINVAL;
 430                 DRM_ERROR("failed to unpin new rbo in error path\n");
 431                 goto pflip_cleanup;
 432         }
 433         radeon_bo_unreserve(rbo);
 434
 435 pflip_cleanup:
 436         spin_lock_irqsave(&dev->event_lock, flags);
 437         radeon_crtc->unpin_work = NULL;
 438         spin_unlock_irqrestore(&dev->event_lock, flags);
 439         radeon_fence_unref(&fence);
 440         kfree(work);
 441
 442         return r;
 443 }
 444
 445 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 446         .cursor_set = radeon_crtc_cursor_set,
 447         .cursor_move = radeon_crtc_cursor_move,
 448         .gamma_set = radeon_crtc_gamma_set,
 449         .set_config = drm_crtc_helper_set_config,
 450         .destroy = radeon_crtc_destroy,
 451         .page_flip = radeon_crtc_page_flip,
 452 };
 453
 454 static void radeon_crtc_init(struct drm_device *dev, int index)
 455 {
 456         struct radeon_device *rdev = dev->dev_private;
 457         struct radeon_crtc *radeon_crtc;
 458         int i;
 459
 460         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 461         if (radeon_crtc == NULL)
 462                 return;
 463
 464         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 465
 466         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 467         radeon_crtc->crtc_id = index;
 468         rdev->mode_info.crtcs[index] = radeon_crtc;
 469
 470 #if 0
 471         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 472         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 473         radeon_crtc->mode_set.num_connectors = 0;
 474 #endif
 475
 476         for (i = 0; i < 256; i++) {
 477                 radeon_crtc->lut_r[i] = i << 2;
 478                 radeon_crtc->lut_g[i] = i << 2;
 479                 radeon_crtc->lut_b[i] = i << 2;
 480         }
 481
 482         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 483                 radeon_atombios_init_crtc(dev, radeon_crtc);
 484         else
 485                 radeon_legacy_init_crtc(dev, radeon_crtc);
 486 }
 487
 488 static const char *encoder_names[36] = {
 489         "NONE",
 490         "INTERNAL_LVDS",
 491         "INTERNAL_TMDS1",
 492         "INTERNAL_TMDS2",
 493         "INTERNAL_DAC1",
 494         "INTERNAL_DAC2",
 495         "INTERNAL_SDVOA",
 496         "INTERNAL_SDVOB",
 497         "SI170B",
 498         "CH7303",
 499         "CH7301",
 500         "INTERNAL_DVO1",
 501         "EXTERNAL_SDVOA",
 502         "EXTERNAL_SDVOB",
 503         "TITFP513",
 504         "INTERNAL_LVTM1",
 505         "VT1623",
 506         "HDMI_SI1930",
 507         "HDMI_INTERNAL",
 508         "INTERNAL_KLDSCP_TMDS1",
 509         "INTERNAL_KLDSCP_DVO1",
 510         "INTERNAL_KLDSCP_DAC1",
 511         "INTERNAL_KLDSCP_DAC2",
 512         "SI178",
 513         "MVPU_FPGA",
 514         "INTERNAL_DDI",
 515         "VT1625",
 516         "HDMI_SI1932",
 517         "DP_AN9801",
 518         "DP_DP501",
 519         "INTERNAL_UNIPHY",
 520         "INTERNAL_KLDSCP_LVTMA",
 521         "INTERNAL_UNIPHY1",
 522         "INTERNAL_UNIPHY2",
 523         "NUTMEG",
 524         "TRAVIS",
 525 };
 526
 527 static const char *connector_names[15] = {
 528         "Unknown",
 529         "VGA",
 530         "DVI-I",
 531         "DVI-D",
 532         "DVI-A",
 533         "Composite",
 534         "S-video",
 535         "LVDS",
 536         "Component",
 537         "DIN",
 538         "DisplayPort",
 539         "HDMI-A",
 540         "HDMI-B",
 541         "TV",
 542         "eDP",
 543 };
 544
 545 static const char *hpd_names[6] = {
 546         "HPD1",
 547         "HPD2",
 548         "HPD3",
 549         "HPD4",
 550         "HPD5",
 551         "HPD6",
 552 };
 553
 554 static void radeon_print_display_setup(struct drm_device *dev)
 555 {
 556         struct drm_connector *connector;
 557         struct radeon_connector *radeon_connector;
 558         struct drm_encoder *encoder;
 559         struct radeon_encoder *radeon_encoder;
 560         uint32_t devices;
 561         int i = 0;
 562
 563         DRM_INFO("Radeon Display Connectors\n");
 564         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 565                 radeon_connector = to_radeon_connector(connector);
 566                 DRM_INFO("Connector %d:\n", i);
 567                 DRM_INFO("  %s\n", connector_names[connector->connector_type]);
 568                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 569                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 570                 if (radeon_connector->ddc_bus) {
 571                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 572                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 573                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 574                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 575                                  radeon_connector->ddc_bus->rec.a_data_reg,
 576                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 577                                  radeon_connector->ddc_bus->rec.en_data_reg,
 578                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 579                                  radeon_connector->ddc_bus->rec.y_data_reg);
 580                         if (radeon_connector->router.ddc_valid)
 581                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 582                                          radeon_connector->router.ddc_mux_control_pin,
 583                                          radeon_connector->router.ddc_mux_state);
 584                         if (radeon_connector->router.cd_valid)
 585                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 586                                          radeon_connector->router.cd_mux_control_pin,
 587                                          radeon_connector->router.cd_mux_state);
 588                 } else {
 589                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 590                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 591                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 592                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 593                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 594                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 595                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 596                 }
 597                 DRM_INFO("  Encoders:\n");
 598                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 599                         radeon_encoder = to_radeon_encoder(encoder);
 600                         devices = radeon_encoder->devices & radeon_connector->devices;
 601                         if (devices) {
 602                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 603                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 604                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 605                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 606                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 607                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 608                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 609                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 610                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 611                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 612                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 613                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 614                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 615                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 616                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 617                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 618                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 619                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 620                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 621                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 622                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 623                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 624                         }
 625                 }
 626                 i++;
 627         }
 628 }
 629
 630 static bool radeon_setup_enc_conn(struct drm_device *dev)
 631 {
 632         struct radeon_device *rdev = dev->dev_private;
 633         struct drm_connector *drm_connector;
 634         bool ret = false;
 635
 636         if (rdev->bios) {
 637                 if (rdev->is_atom_bios) {
 638                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 639                         if (ret == false)
 640                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 641                 } else {
 642                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 643                         if (ret == false)
 644                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 645                 }
 646         } else {
 647                 if (!ASIC_IS_AVIVO(rdev))
 648                         ret = radeon_get_legacy_connector_info_from_table(dev);
 649         }
 650         if (ret) {
 651                 radeon_setup_encoder_clones(dev);
 652                 radeon_print_display_setup(dev);
 653                 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
 654                         radeon_ddc_dump(drm_connector);
 655         }
 656
 657         return ret;
 658 }
 659
 660 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 661 {
 662         struct drm_device *dev = radeon_connector->base.dev;
 663         struct radeon_device *rdev = dev->dev_private;
 664         int ret = 0;
 665
 666         /* on hw with routers, select right port */
 667         if (radeon_connector->router.ddc_valid)
 668                 radeon_router_select_ddc_port(radeon_connector);
 669
 670         if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 671             (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 672                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 673                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 674                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
 675                         radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
 676         }
 677         if (!radeon_connector->ddc_bus)
 678                 return -1;
 679         if (!radeon_connector->edid) {
 680                 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
 681         }
 682
 683         if (!radeon_connector->edid) {
 684                 if (rdev->is_atom_bios) {
 685                         /* some laptops provide a hardcoded edid in rom for LCDs */
 686                         if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 687                              (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
 688                                 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 689                 } else
 690                         /* some servers provide a hardcoded edid in rom for KVMs */
 691                         radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 692         }
 693         if (radeon_connector->edid) {
 694                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 695                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 696                 return ret;
 697         }
 698         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 699         return 0;
 700 }
 701
 702 static int radeon_ddc_dump(struct drm_connector *connector)
 703 {
 704         struct edid *edid;
 705         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 706         int ret = 0;
 707
 708         /* on hw with routers, select right port */
 709         if (radeon_connector->router.ddc_valid)
 710                 radeon_router_select_ddc_port(radeon_connector);
 711
 712         if (!radeon_connector->ddc_bus)
 713                 return -1;
 714         edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
 715         if (edid) {
 716                 kfree(edid);
 717         }
 718         return ret;
 719 }
 720
 721 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
 722 {
 723         uint64_t mod;
 724
 725         n += d / 2;
 726
 727         mod = do_div(n, d);
 728         return n;
 729 }
 730
 731 void radeon_compute_pll(struct radeon_pll *pll,
 732                         uint64_t freq,
 733                         uint32_t *dot_clock_p,
 734                         uint32_t *fb_div_p,
 735                         uint32_t *frac_fb_div_p,
 736                         uint32_t *ref_div_p,
 737                         uint32_t *post_div_p)
 738 {
 739         uint32_t min_ref_div = pll->min_ref_div;
 740         uint32_t max_ref_div = pll->max_ref_div;
 741         uint32_t min_post_div = pll->min_post_div;
 742         uint32_t max_post_div = pll->max_post_div;
 743         uint32_t min_fractional_feed_div = 0;
 744         uint32_t max_fractional_feed_div = 0;
 745         uint32_t best_vco = pll->best_vco;
 746         uint32_t best_post_div = 1;
 747         uint32_t best_ref_div = 1;
 748         uint32_t best_feedback_div = 1;
 749         uint32_t best_frac_feedback_div = 0;
 750         uint32_t best_freq = -1;
 751         uint32_t best_error = 0xffffffff;
 752         uint32_t best_vco_diff = 1;
 753         uint32_t post_div;
 754         u32 pll_out_min, pll_out_max;
 755
 756         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
 757         freq = freq * 1000;
 758
 759         if (pll->flags & RADEON_PLL_IS_LCD) {
 760                 pll_out_min = pll->lcd_pll_out_min;
 761                 pll_out_max = pll->lcd_pll_out_max;
 762         } else {
 763                 pll_out_min = pll->pll_out_min;
 764                 pll_out_max = pll->pll_out_max;
 765         }
 766
 767         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 768                 min_ref_div = max_ref_div = pll->reference_div;
 769         else {
 770                 while (min_ref_div < max_ref_div-1) {
 771                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
 772                         uint32_t pll_in = pll->reference_freq / mid;
 773                         if (pll_in < pll->pll_in_min)
 774                                 max_ref_div = mid;
 775                         else if (pll_in > pll->pll_in_max)
 776                                 min_ref_div = mid;
 777                         else
 778                                 break;
 779                 }
 780         }
 781
 782         if (pll->flags & RADEON_PLL_USE_POST_DIV)
 783                 min_post_div = max_post_div = pll->post_div;
 784
 785         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 786                 min_fractional_feed_div = pll->min_frac_feedback_div;
 787                 max_fractional_feed_div = pll->max_frac_feedback_div;
 788         }
 789
 790         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
 791                 uint32_t ref_div;
 792
 793                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
 794                         continue;
 795
 796                 /* legacy radeons only have a few post_divs */
 797                 if (pll->flags & RADEON_PLL_LEGACY) {
 798                         if ((post_div == 5) ||
 799                             (post_div == 7) ||
 800                             (post_div == 9) ||
 801                             (post_div == 10) ||
 802                             (post_div == 11) ||
 803                             (post_div == 13) ||
 804                             (post_div == 14) ||
 805                             (post_div == 15))
 806                                 continue;
 807                 }
 808
 809                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
 810                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
 811                         uint32_t pll_in = pll->reference_freq / ref_div;
 812                         uint32_t min_feed_div = pll->min_feedback_div;
 813                         uint32_t max_feed_div = pll->max_feedback_div + 1;
 814
 815                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
 816                                 continue;
 817
 818                         while (min_feed_div < max_feed_div) {
 819                                 uint32_t vco;
 820                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
 821                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
 822                                 uint32_t frac_feedback_div;
 823                                 uint64_t tmp;
 824
 825                                 feedback_div = (min_feed_div + max_feed_div) / 2;
 826
 827                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
 828                                 vco = radeon_div(tmp, ref_div);
 829
 830                                 if (vco < pll_out_min) {
 831                                         min_feed_div = feedback_div + 1;
 832                                         continue;
 833                                 } else if (vco > pll_out_max) {
 834                                         max_feed_div = feedback_div;
 835                                         continue;
 836                                 }
 837
 838                                 while (min_frac_feed_div < max_frac_feed_div) {
 839                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
 840                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
 841                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
 842                                         current_freq = radeon_div(tmp, ref_div * post_div);
 843
 844                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
 845                                                 if (freq < current_freq)
 846                                                         error = 0xffffffff;
 847                                                 else
 848                                                         error = freq - current_freq;
 849                                         } else
 850                                                 error = abs(current_freq - freq);
 851                                         vco_diff = abs(vco - best_vco);
 852
 853                                         if ((best_vco == 0 && error < best_error) ||
 854                                             (best_vco != 0 &&
 855                                              ((best_error > 100 && error < best_error - 100) ||
 856                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
 857                                                 best_post_div = post_div;
 858                                                 best_ref_div = ref_div;
 859                                                 best_feedback_div = feedback_div;
 860                                                 best_frac_feedback_div = frac_feedback_div;
 861                                                 best_freq = current_freq;
 862                                                 best_error = error;
 863                                                 best_vco_diff = vco_diff;
 864                                         } else if (current_freq == freq) {
 865                                                 if (best_freq == -1) {
 866                                                         best_post_div = post_div;
 867                                                         best_ref_div = ref_div;
 868                                                         best_feedback_div = feedback_div;
 869                                                         best_frac_feedback_div = frac_feedback_div;
 870                                                         best_freq = current_freq;
 871                                                         best_error = error;
 872                                                         best_vco_diff = vco_diff;
 873                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
 874                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
 875                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
 876                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
 877                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
 878                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
 879                                                         best_post_div = post_div;
 880                                                         best_ref_div = ref_div;
 881                                                         best_feedback_div = feedback_div;
 882                                                         best_frac_feedback_div = frac_feedback_div;
 883                                                         best_freq = current_freq;
 884                                                         best_error = error;
 885                                                         best_vco_diff = vco_diff;
 886                                                 }
 887                                         }
 888                                         if (current_freq < freq)
 889                                                 min_frac_feed_div = frac_feedback_div + 1;
 890                                         else
 891                                                 max_frac_feed_div = frac_feedback_div;
 892                                 }
 893                                 if (current_freq < freq)
 894                                         min_feed_div = feedback_div + 1;
 895                                 else
 896                                         max_feed_div = feedback_div;
 897                         }
 898                 }
 899         }
 900
 901         *dot_clock_p = best_freq / 10000;
 902         *fb_div_p = best_feedback_div;
 903         *frac_fb_div_p = best_frac_feedback_div;
 904         *ref_div_p = best_ref_div;
 905         *post_div_p = best_post_div;
 906 }
 907
 908 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
 909 {
 910         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
 911
 912         if (radeon_fb->obj) {
 913                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
 914         }
 915         drm_framebuffer_cleanup(fb);
 916         kfree(radeon_fb);
 917 }
 918
 919 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
 920                                                   struct drm_file *file_priv,
 921                                                   unsigned int *handle)
 922 {
 923         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
 924
 925         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
 926 }
 927
 928 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
 929         .destroy = radeon_user_framebuffer_destroy,
 930         .create_handle = radeon_user_framebuffer_create_handle,
 931 };
 932
 933 void
 934 radeon_framebuffer_init(struct drm_device *dev,
 935                         struct radeon_framebuffer *rfb,
 936                         struct drm_mode_fb_cmd *mode_cmd,
 937                         struct drm_gem_object *obj)
 938 {
 939         rfb->obj = obj;
 940         drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
 941         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
 942 }
 943
 944 static struct drm_framebuffer *
 945 radeon_user_framebuffer_create(struct drm_device *dev,
 946                                struct drm_file *file_priv,
 947                                struct drm_mode_fb_cmd *mode_cmd)
 948 {
 949         struct drm_gem_object *obj;
 950         struct radeon_framebuffer *radeon_fb;
 951
 952         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
 953         if (obj ==  NULL) {
 954                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
 955                         "can't create framebuffer\n", mode_cmd->handle);
 956                 return ERR_PTR(-ENOENT);
 957         }
 958
 959         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
 960         if (radeon_fb == NULL)
 961                 return ERR_PTR(-ENOMEM);
 962
 963         radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
 964
 965         return &radeon_fb->base;
 966 }
 967
 968 static void radeon_output_poll_changed(struct drm_device *dev)
 969 {
 970         struct radeon_device *rdev = dev->dev_private;
 971         radeon_fb_output_poll_changed(rdev);
 972 }
 973
 974 static const struct drm_mode_config_funcs radeon_mode_funcs = {
 975         .fb_create = radeon_user_framebuffer_create,
 976         .output_poll_changed = radeon_output_poll_changed
 977 };
 978
 979 struct drm_prop_enum_list {
 980         int type;
 981         char *name;
 982 };
 983
 984 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
 985 {       { 0, "driver" },
 986         { 1, "bios" },
 987 };
 988
 989 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
 990 {       { TV_STD_NTSC, "ntsc" },
 991         { TV_STD_PAL, "pal" },
 992         { TV_STD_PAL_M, "pal-m" },
 993         { TV_STD_PAL_60, "pal-60" },
 994         { TV_STD_NTSC_J, "ntsc-j" },
 995         { TV_STD_SCART_PAL, "scart-pal" },
 996         { TV_STD_PAL_CN, "pal-cn" },
 997         { TV_STD_SECAM, "secam" },
 998 };
 999
1000 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1001 {       { UNDERSCAN_OFF, "off" },
1002         { UNDERSCAN_ON, "on" },
1003         { UNDERSCAN_AUTO, "auto" },
1004 };
1005
1006 static int radeon_modeset_create_props(struct radeon_device *rdev)
1007 {
1008         int i, sz;
1009
1010         if (rdev->is_atom_bios) {
1011                 rdev->mode_info.coherent_mode_property =
1012                         drm_property_create(rdev->ddev,
1013                                             DRM_MODE_PROP_RANGE,
1014                                             "coherent", 2);
1015                 if (!rdev->mode_info.coherent_mode_property)
1016                         return -ENOMEM;
1017
1018                 rdev->mode_info.coherent_mode_property->values[0] = 0;
1019                 rdev->mode_info.coherent_mode_property->values[1] = 1;
1020         }
1021
1022         if (!ASIC_IS_AVIVO(rdev)) {
1023                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1024                 rdev->mode_info.tmds_pll_property =
1025                         drm_property_create(rdev->ddev,
1026                                             DRM_MODE_PROP_ENUM,
1027                                             "tmds_pll", sz);
1028                 for (i = 0; i < sz; i++) {
1029                         drm_property_add_enum(rdev->mode_info.tmds_pll_property,
1030                                               i,
1031                                               radeon_tmds_pll_enum_list[i].type,
1032                                               radeon_tmds_pll_enum_list[i].name);
1033                 }
1034         }
1035
1036         rdev->mode_info.load_detect_property =
1037                 drm_property_create(rdev->ddev,
1038                                     DRM_MODE_PROP_RANGE,
1039                                     "load detection", 2);
1040         if (!rdev->mode_info.load_detect_property)
1041                 return -ENOMEM;
1042         rdev->mode_info.load_detect_property->values[0] = 0;
1043         rdev->mode_info.load_detect_property->values[1] = 1;
1044
1045         drm_mode_create_scaling_mode_property(rdev->ddev);
1046
1047         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1048         rdev->mode_info.tv_std_property =
1049                 drm_property_create(rdev->ddev,
1050                                     DRM_MODE_PROP_ENUM,
1051                                     "tv standard", sz);
1052         for (i = 0; i < sz; i++) {
1053                 drm_property_add_enum(rdev->mode_info.tv_std_property,
1054                                       i,
1055                                       radeon_tv_std_enum_list[i].type,
1056                                       radeon_tv_std_enum_list[i].name);
1057         }
1058
1059         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1060         rdev->mode_info.underscan_property =
1061                 drm_property_create(rdev->ddev,
1062                                     DRM_MODE_PROP_ENUM,
1063                                     "underscan", sz);
1064         for (i = 0; i < sz; i++) {
1065                 drm_property_add_enum(rdev->mode_info.underscan_property,
1066                                       i,
1067                                       radeon_underscan_enum_list[i].type,
1068                                       radeon_underscan_enum_list[i].name);
1069         }
1070
1071         rdev->mode_info.underscan_hborder_property =
1072                 drm_property_create(rdev->ddev,
1073                                         DRM_MODE_PROP_RANGE,
1074                                         "underscan hborder", 2);
1075         if (!rdev->mode_info.underscan_hborder_property)
1076                 return -ENOMEM;
1077         rdev->mode_info.underscan_hborder_property->values[0] = 0;
1078         rdev->mode_info.underscan_hborder_property->values[1] = 128;
1079
1080         rdev->mode_info.underscan_vborder_property =
1081                 drm_property_create(rdev->ddev,
1082                                         DRM_MODE_PROP_RANGE,
1083                                         "underscan vborder", 2);
1084         if (!rdev->mode_info.underscan_vborder_property)
1085                 return -ENOMEM;
1086         rdev->mode_info.underscan_vborder_property->values[0] = 0;
1087         rdev->mode_info.underscan_vborder_property->values[1] = 128;
1088
1089         return 0;
1090 }
1091
1092 void radeon_update_display_priority(struct radeon_device *rdev)
1093 {
1094         /* adjustment options for the display watermarks */
1095         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1096                 /* set display priority to high for r3xx, rv515 chips
1097                  * this avoids flickering due to underflow to the
1098                  * display controllers during heavy acceleration.
1099                  * Don't force high on rs4xx igp chips as it seems to
1100                  * affect the sound card.  See kernel bug 15982.
1101                  */
1102                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1103                     !(rdev->flags & RADEON_IS_IGP))
1104                         rdev->disp_priority = 2;
1105                 else
1106                         rdev->disp_priority = 0;
1107         } else
1108                 rdev->disp_priority = radeon_disp_priority;
1109
1110 }
1111
1112 int radeon_modeset_init(struct radeon_device *rdev)
1113 {
1114         int i;
1115         int ret;
1116
1117         drm_mode_config_init(rdev->ddev);
1118         rdev->mode_info.mode_config_initialized = true;
1119
1120         rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1121
1122         if (ASIC_IS_AVIVO(rdev)) {
1123                 rdev->ddev->mode_config.max_width = 8192;
1124                 rdev->ddev->mode_config.max_height = 8192;
1125         } else {
1126                 rdev->ddev->mode_config.max_width = 4096;
1127                 rdev->ddev->mode_config.max_height = 4096;
1128         }
1129
1130         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1131
1132         ret = radeon_modeset_create_props(rdev);
1133         if (ret) {
1134                 return ret;
1135         }
1136
1137         /* init i2c buses */
1138         radeon_i2c_init(rdev);
1139
1140         /* check combios for a valid hardcoded EDID - Sun servers */
1141         if (!rdev->is_atom_bios) {
1142                 /* check for hardcoded EDID in BIOS */
1143                 radeon_combios_check_hardcoded_edid(rdev);
1144         }
1145
1146         /* allocate crtcs */
1147         for (i = 0; i < rdev->num_crtc; i++) {
1148                 radeon_crtc_init(rdev->ddev, i);
1149         }
1150
1151         /* okay we should have all the bios connectors */
1152         ret = radeon_setup_enc_conn(rdev->ddev);
1153         if (!ret) {
1154                 return ret;
1155         }
1156         /* initialize hpd */
1157         radeon_hpd_init(rdev);
1158
1159         /* Initialize power management */
1160         radeon_pm_init(rdev);
1161
1162         radeon_fbdev_init(rdev);
1163         drm_kms_helper_poll_init(rdev->ddev);
1164
1165         return 0;
1166 }
1167
1168 void radeon_modeset_fini(struct radeon_device *rdev)
1169 {
1170         radeon_fbdev_fini(rdev);
1171         kfree(rdev->mode_info.bios_hardcoded_edid);
1172         radeon_pm_fini(rdev);
1173
1174         if (rdev->mode_info.mode_config_initialized) {
1175                 drm_kms_helper_poll_fini(rdev->ddev);
1176                 radeon_hpd_fini(rdev);
1177                 drm_mode_config_cleanup(rdev->ddev);
1178                 rdev->mode_info.mode_config_initialized = false;
1179         }
1180         /* free i2c buses */
1181         radeon_i2c_fini(rdev);
1182 }
1183
1184 static bool is_hdtv_mode(struct drm_display_mode *mode)
1185 {
1186         /* try and guess if this is a tv or a monitor */
1187         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1188             (mode->vdisplay == 576) || /* 576p */
1189             (mode->vdisplay == 720) || /* 720p */
1190             (mode->vdisplay == 1080)) /* 1080p */
1191                 return true;
1192         else
1193                 return false;
1194 }
1195
1196 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1197                                 struct drm_display_mode *mode,
1198                                 struct drm_display_mode *adjusted_mode)
1199 {
1200         struct drm_device *dev = crtc->dev;
1201         struct radeon_device *rdev = dev->dev_private;
1202         struct drm_encoder *encoder;
1203         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1204         struct radeon_encoder *radeon_encoder;
1205         struct drm_connector *connector;
1206         struct radeon_connector *radeon_connector;
1207         bool first = true;
1208         u32 src_v = 1, dst_v = 1;
1209         u32 src_h = 1, dst_h = 1;
1210
1211         radeon_crtc->h_border = 0;
1212         radeon_crtc->v_border = 0;
1213
1214         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1215                 if (encoder->crtc != crtc)
1216                         continue;
1217                 radeon_encoder = to_radeon_encoder(encoder);
1218                 connector = radeon_get_connector_for_encoder(encoder);
1219                 radeon_connector = to_radeon_connector(connector);
1220
1221                 if (first) {
1222                         /* set scaling */
1223                         if (radeon_encoder->rmx_type == RMX_OFF)
1224                                 radeon_crtc->rmx_type = RMX_OFF;
1225                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1226                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1227                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1228                         else
1229                                 radeon_crtc->rmx_type = RMX_OFF;
1230                         /* copy native mode */
1231                         memcpy(&radeon_crtc->native_mode,
1232                                &radeon_encoder->native_mode,
1233                                 sizeof(struct drm_display_mode));
1234                         src_v = crtc->mode.vdisplay;
1235                         dst_v = radeon_crtc->native_mode.vdisplay;
1236                         src_h = crtc->mode.hdisplay;
1237                         dst_h = radeon_crtc->native_mode.hdisplay;
1238
1239                         /* fix up for overscan on hdmi */
1240                         if (ASIC_IS_AVIVO(rdev) &&
1241                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1242                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1243                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1244                               drm_detect_hdmi_monitor(radeon_connector->edid) &&
1245                               is_hdtv_mode(mode)))) {
1246                                 if (radeon_encoder->underscan_hborder != 0)
1247                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1248                                 else
1249                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1250                                 if (radeon_encoder->underscan_vborder != 0)
1251                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1252                                 else
1253                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1254                                 radeon_crtc->rmx_type = RMX_FULL;
1255                                 src_v = crtc->mode.vdisplay;
1256                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1257                                 src_h = crtc->mode.hdisplay;
1258                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1259                         }
1260                         first = false;
1261                 } else {
1262                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1263                                 /* WARNING: Right now this can't happen but
1264                                  * in the future we need to check that scaling
1265                                  * are consistent across different encoder
1266                                  * (ie all encoder can work with the same
1267                                  *  scaling).
1268                                  */
1269                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1270                                 return false;
1271                         }
1272                 }
1273         }
1274         if (radeon_crtc->rmx_type != RMX_OFF) {
1275                 fixed20_12 a, b;
1276                 a.full = dfixed_const(src_v);
1277                 b.full = dfixed_const(dst_v);
1278                 radeon_crtc->vsc.full = dfixed_div(a, b);
1279                 a.full = dfixed_const(src_h);
1280                 b.full = dfixed_const(dst_h);
1281                 radeon_crtc->hsc.full = dfixed_div(a, b);
1282         } else {
1283                 radeon_crtc->vsc.full = dfixed_const(1);
1284                 radeon_crtc->hsc.full = dfixed_const(1);
1285         }
1286         return true;
1287 }
1288
1289 /*
1290  * Retrieve current video scanout position of crtc on a given gpu.
1291  *
1292  * \param dev Device to query.
1293  * \param crtc Crtc to query.
1294  * \param *vpos Location where vertical scanout position should be stored.
1295  * \param *hpos Location where horizontal scanout position should go.
1296  *
1297  * Returns vpos as a positive number while in active scanout area.
1298  * Returns vpos as a negative number inside vblank, counting the number
1299  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1300  * until start of active scanout / end of vblank."
1301  *
1302  * \return Flags, or'ed together as follows:
1303  *
1304  * DRM_SCANOUTPOS_VALID = Query successfull.
1305  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1306  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1307  * this flag means that returned position may be offset by a constant but
1308  * unknown small number of scanlines wrt. real scanout position.
1309  *
1310  */
1311 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
1312 {
1313         u32 stat_crtc = 0, vbl = 0, position = 0;
1314         int vbl_start, vbl_end, vtotal, ret = 0;
1315         bool in_vbl = true;
1316
1317         struct radeon_device *rdev = dev->dev_private;
1318
1319         if (ASIC_IS_DCE4(rdev)) {
1320                 if (crtc == 0) {
1321                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1322                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1323                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1324                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1325                         ret |= DRM_SCANOUTPOS_VALID;
1326                 }
1327                 if (crtc == 1) {
1328                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1329                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1330                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1331                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1332                         ret |= DRM_SCANOUTPOS_VALID;
1333                 }
1334                 if (crtc == 2) {
1335                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1336                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1337                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1338                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1339                         ret |= DRM_SCANOUTPOS_VALID;
1340                 }
1341                 if (crtc == 3) {
1342                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1343                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1344                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1345                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1346                         ret |= DRM_SCANOUTPOS_VALID;
1347                 }
1348                 if (crtc == 4) {
1349                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1350                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1351                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1352                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1353                         ret |= DRM_SCANOUTPOS_VALID;
1354                 }
1355                 if (crtc == 5) {
1356                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1357                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1358                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1359                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1360                         ret |= DRM_SCANOUTPOS_VALID;
1361                 }
1362         } else if (ASIC_IS_AVIVO(rdev)) {
1363                 if (crtc == 0) {
1364                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1365                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1366                         ret |= DRM_SCANOUTPOS_VALID;
1367                 }
1368                 if (crtc == 1) {
1369                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1370                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1371                         ret |= DRM_SCANOUTPOS_VALID;
1372                 }
1373         } else {
1374                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1375                 if (crtc == 0) {
1376                         /* Assume vbl_end == 0, get vbl_start from
1377                          * upper 16 bits.
1378                          */
1379                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1380                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1381                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1382                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1383                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1384                         if (!(stat_crtc & 1))
1385                                 in_vbl = false;
1386
1387                         ret |= DRM_SCANOUTPOS_VALID;
1388                 }
1389                 if (crtc == 1) {
1390                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1391                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1392                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1393                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1394                         if (!(stat_crtc & 1))
1395                                 in_vbl = false;
1396
1397                         ret |= DRM_SCANOUTPOS_VALID;
1398                 }
1399         }
1400
1401         /* Decode into vertical and horizontal scanout position. */
1402         *vpos = position & 0x1fff;
1403         *hpos = (position >> 16) & 0x1fff;
1404
1405         /* Valid vblank area boundaries from gpu retrieved? */
1406         if (vbl > 0) {
1407                 /* Yes: Decode. */
1408                 ret |= DRM_SCANOUTPOS_ACCURATE;
1409                 vbl_start = vbl & 0x1fff;
1410                 vbl_end = (vbl >> 16) & 0x1fff;
1411         }
1412         else {
1413                 /* No: Fake something reasonable which gives at least ok results. */
1414                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1415                 vbl_end = 0;
1416         }
1417
1418         /* Test scanout position against vblank region. */
1419         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1420                 in_vbl = false;
1421
1422         /* Check if inside vblank area and apply corrective offsets:
1423          * vpos will then be >=0 in video scanout area, but negative
1424          * within vblank area, counting down the number of lines until
1425          * start of scanout.
1426          */
1427
1428         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1429         if (in_vbl && (*vpos >= vbl_start)) {
1430                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1431                 *vpos = *vpos - vtotal;
1432         }
1433
1434         /* Correct for shifted end of vbl at vbl_end. */
1435         *vpos = *vpos - vbl_end;
1436
1437         /* In vblank? */
1438         if (in_vbl)
1439                 ret |= DRM_SCANOUTPOS_INVBL;
1440
1441         return ret;
1442 }