Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_encoder.c */
  41 extern uint32_t
  42 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  43                       uint8_t dac);
  44 extern void radeon_link_encoder_connector(struct drm_device *dev);
  45
  46 /* from radeon_connector.c */
  47 extern void
  48 radeon_add_legacy_connector(struct drm_device *dev,
  49                             uint32_t connector_id,
  50                             uint32_t supported_device,
  51                             int connector_type,
  52                             struct radeon_i2c_bus_rec *i2c_bus,
  53                             uint16_t connector_object_id,
  54                             struct radeon_hpd *hpd);
  55
  56 /* from radeon_legacy_encoder.c */
  57 extern void
  58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  59                           uint32_t supported_device);
  60
  61 /* old legacy ATI BIOS routines */
  62
  63 /* COMBIOS table offsets */
  64 enum radeon_combios_table_offset {
  65         /* absolute offset tables */
  66         COMBIOS_ASIC_INIT_1_TABLE,
  67         COMBIOS_BIOS_SUPPORT_TABLE,
  68         COMBIOS_DAC_PROGRAMMING_TABLE,
  69         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  70         COMBIOS_CRTC_INFO_TABLE,
  71         COMBIOS_PLL_INFO_TABLE,
  72         COMBIOS_TV_INFO_TABLE,
  73         COMBIOS_DFP_INFO_TABLE,
  74         COMBIOS_HW_CONFIG_INFO_TABLE,
  75         COMBIOS_MULTIMEDIA_INFO_TABLE,
  76         COMBIOS_TV_STD_PATCH_TABLE,
  77         COMBIOS_LCD_INFO_TABLE,
  78         COMBIOS_MOBILE_INFO_TABLE,
  79         COMBIOS_PLL_INIT_TABLE,
  80         COMBIOS_MEM_CONFIG_TABLE,
  81         COMBIOS_SAVE_MASK_TABLE,
  82         COMBIOS_HARDCODED_EDID_TABLE,
  83         COMBIOS_ASIC_INIT_2_TABLE,
  84         COMBIOS_CONNECTOR_INFO_TABLE,
  85         COMBIOS_DYN_CLK_1_TABLE,
  86         COMBIOS_RESERVED_MEM_TABLE,
  87         COMBIOS_EXT_TMDS_INFO_TABLE,
  88         COMBIOS_MEM_CLK_INFO_TABLE,
  89         COMBIOS_EXT_DAC_INFO_TABLE,
  90         COMBIOS_MISC_INFO_TABLE,
  91         COMBIOS_CRT_INFO_TABLE,
  92         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  93         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  94         COMBIOS_FAN_SPEED_INFO_TABLE,
  95         COMBIOS_OVERDRIVE_INFO_TABLE,
  96         COMBIOS_OEM_INFO_TABLE,
  97         COMBIOS_DYN_CLK_2_TABLE,
  98         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  99         COMBIOS_I2C_INFO_TABLE,
 100         /* relative offset tables */
 101         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 102         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 103         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 104         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 105         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 106         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 107         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 108         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 109         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 110         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 111         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 112 };
 113
 114 enum radeon_combios_ddc {
 115         DDC_NONE_DETECTED,
 116         DDC_MONID,
 117         DDC_DVI,
 118         DDC_VGA,
 119         DDC_CRT2,
 120         DDC_LCD,
 121         DDC_GPIO,
 122 };
 123
 124 enum radeon_combios_connector {
 125         CONNECTOR_NONE_LEGACY,
 126         CONNECTOR_PROPRIETARY_LEGACY,
 127         CONNECTOR_CRT_LEGACY,
 128         CONNECTOR_DVI_I_LEGACY,
 129         CONNECTOR_DVI_D_LEGACY,
 130         CONNECTOR_CTV_LEGACY,
 131         CONNECTOR_STV_LEGACY,
 132         CONNECTOR_UNSUPPORTED_LEGACY
 133 };
 134
 135 const int legacy_connector_convert[] = {
 136         DRM_MODE_CONNECTOR_Unknown,
 137         DRM_MODE_CONNECTOR_DVID,
 138         DRM_MODE_CONNECTOR_VGA,
 139         DRM_MODE_CONNECTOR_DVII,
 140         DRM_MODE_CONNECTOR_DVID,
 141         DRM_MODE_CONNECTOR_Composite,
 142         DRM_MODE_CONNECTOR_SVIDEO,
 143         DRM_MODE_CONNECTOR_Unknown,
 144 };
 145
 146 static uint16_t combios_get_table_offset(struct drm_device *dev,
 147                                          enum radeon_combios_table_offset table)
 148 {
 149         struct radeon_device *rdev = dev->dev_private;
 150         int rev;
 151         uint16_t offset = 0, check_offset;
 152
 153         if (!rdev->bios)
 154                 return 0;
 155
 156         switch (table) {
 157                 /* absolute offset tables */
 158         case COMBIOS_ASIC_INIT_1_TABLE:
 159                 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
 160                 if (check_offset)
 161                         offset = check_offset;
 162                 break;
 163         case COMBIOS_BIOS_SUPPORT_TABLE:
 164                 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
 165                 if (check_offset)
 166                         offset = check_offset;
 167                 break;
 168         case COMBIOS_DAC_PROGRAMMING_TABLE:
 169                 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
 170                 if (check_offset)
 171                         offset = check_offset;
 172                 break;
 173         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 174                 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
 175                 if (check_offset)
 176                         offset = check_offset;
 177                 break;
 178         case COMBIOS_CRTC_INFO_TABLE:
 179                 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
 180                 if (check_offset)
 181                         offset = check_offset;
 182                 break;
 183         case COMBIOS_PLL_INFO_TABLE:
 184                 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
 185                 if (check_offset)
 186                         offset = check_offset;
 187                 break;
 188         case COMBIOS_TV_INFO_TABLE:
 189                 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
 190                 if (check_offset)
 191                         offset = check_offset;
 192                 break;
 193         case COMBIOS_DFP_INFO_TABLE:
 194                 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
 195                 if (check_offset)
 196                         offset = check_offset;
 197                 break;
 198         case COMBIOS_HW_CONFIG_INFO_TABLE:
 199                 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
 200                 if (check_offset)
 201                         offset = check_offset;
 202                 break;
 203         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 204                 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
 205                 if (check_offset)
 206                         offset = check_offset;
 207                 break;
 208         case COMBIOS_TV_STD_PATCH_TABLE:
 209                 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
 210                 if (check_offset)
 211                         offset = check_offset;
 212                 break;
 213         case COMBIOS_LCD_INFO_TABLE:
 214                 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
 215                 if (check_offset)
 216                         offset = check_offset;
 217                 break;
 218         case COMBIOS_MOBILE_INFO_TABLE:
 219                 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
 220                 if (check_offset)
 221                         offset = check_offset;
 222                 break;
 223         case COMBIOS_PLL_INIT_TABLE:
 224                 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
 225                 if (check_offset)
 226                         offset = check_offset;
 227                 break;
 228         case COMBIOS_MEM_CONFIG_TABLE:
 229                 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
 230                 if (check_offset)
 231                         offset = check_offset;
 232                 break;
 233         case COMBIOS_SAVE_MASK_TABLE:
 234                 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
 235                 if (check_offset)
 236                         offset = check_offset;
 237                 break;
 238         case COMBIOS_HARDCODED_EDID_TABLE:
 239                 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
 240                 if (check_offset)
 241                         offset = check_offset;
 242                 break;
 243         case COMBIOS_ASIC_INIT_2_TABLE:
 244                 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
 245                 if (check_offset)
 246                         offset = check_offset;
 247                 break;
 248         case COMBIOS_CONNECTOR_INFO_TABLE:
 249                 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
 250                 if (check_offset)
 251                         offset = check_offset;
 252                 break;
 253         case COMBIOS_DYN_CLK_1_TABLE:
 254                 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
 255                 if (check_offset)
 256                         offset = check_offset;
 257                 break;
 258         case COMBIOS_RESERVED_MEM_TABLE:
 259                 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
 260                 if (check_offset)
 261                         offset = check_offset;
 262                 break;
 263         case COMBIOS_EXT_TMDS_INFO_TABLE:
 264                 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
 265                 if (check_offset)
 266                         offset = check_offset;
 267                 break;
 268         case COMBIOS_MEM_CLK_INFO_TABLE:
 269                 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
 270                 if (check_offset)
 271                         offset = check_offset;
 272                 break;
 273         case COMBIOS_EXT_DAC_INFO_TABLE:
 274                 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
 275                 if (check_offset)
 276                         offset = check_offset;
 277                 break;
 278         case COMBIOS_MISC_INFO_TABLE:
 279                 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
 280                 if (check_offset)
 281                         offset = check_offset;
 282                 break;
 283         case COMBIOS_CRT_INFO_TABLE:
 284                 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
 285                 if (check_offset)
 286                         offset = check_offset;
 287                 break;
 288         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 289                 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
 290                 if (check_offset)
 291                         offset = check_offset;
 292                 break;
 293         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 294                 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
 295                 if (check_offset)
 296                         offset = check_offset;
 297                 break;
 298         case COMBIOS_FAN_SPEED_INFO_TABLE:
 299                 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
 300                 if (check_offset)
 301                         offset = check_offset;
 302                 break;
 303         case COMBIOS_OVERDRIVE_INFO_TABLE:
 304                 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
 305                 if (check_offset)
 306                         offset = check_offset;
 307                 break;
 308         case COMBIOS_OEM_INFO_TABLE:
 309                 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
 310                 if (check_offset)
 311                         offset = check_offset;
 312                 break;
 313         case COMBIOS_DYN_CLK_2_TABLE:
 314                 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
 315                 if (check_offset)
 316                         offset = check_offset;
 317                 break;
 318         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 319                 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
 320                 if (check_offset)
 321                         offset = check_offset;
 322                 break;
 323         case COMBIOS_I2C_INFO_TABLE:
 324                 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
 325                 if (check_offset)
 326                         offset = check_offset;
 327                 break;
 328                 /* relative offset tables */
 329         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 330                 check_offset =
 331                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 332                 if (check_offset) {
 333                         rev = RBIOS8(check_offset);
 334                         if (rev > 0) {
 335                                 check_offset = RBIOS16(check_offset + 0x3);
 336                                 if (check_offset)
 337                                         offset = check_offset;
 338                         }
 339                 }
 340                 break;
 341         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 342                 check_offset =
 343                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 344                 if (check_offset) {
 345                         rev = RBIOS8(check_offset);
 346                         if (rev > 0) {
 347                                 check_offset = RBIOS16(check_offset + 0x5);
 348                                 if (check_offset)
 349                                         offset = check_offset;
 350                         }
 351                 }
 352                 break;
 353         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 354                 check_offset =
 355                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 356                 if (check_offset) {
 357                         rev = RBIOS8(check_offset);
 358                         if (rev > 0) {
 359                                 check_offset = RBIOS16(check_offset + 0x7);
 360                                 if (check_offset)
 361                                         offset = check_offset;
 362                         }
 363                 }
 364                 break;
 365         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 366                 check_offset =
 367                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 368                 if (check_offset) {
 369                         rev = RBIOS8(check_offset);
 370                         if (rev == 2) {
 371                                 check_offset = RBIOS16(check_offset + 0x9);
 372                                 if (check_offset)
 373                                         offset = check_offset;
 374                         }
 375                 }
 376                 break;
 377         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 378                 check_offset =
 379                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 380                 if (check_offset) {
 381                         while (RBIOS8(check_offset++));
 382                         check_offset += 2;
 383                         if (check_offset)
 384                                 offset = check_offset;
 385                 }
 386                 break;
 387         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 388                 check_offset =
 389                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 390                 if (check_offset) {
 391                         check_offset = RBIOS16(check_offset + 0x11);
 392                         if (check_offset)
 393                                 offset = check_offset;
 394                 }
 395                 break;
 396         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 397                 check_offset =
 398                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 399                 if (check_offset) {
 400                         check_offset = RBIOS16(check_offset + 0x13);
 401                         if (check_offset)
 402                                 offset = check_offset;
 403                 }
 404                 break;
 405         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 406                 check_offset =
 407                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 408                 if (check_offset) {
 409                         check_offset = RBIOS16(check_offset + 0x15);
 410                         if (check_offset)
 411                                 offset = check_offset;
 412                 }
 413                 break;
 414         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 415                 check_offset =
 416                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 417                 if (check_offset) {
 418                         check_offset = RBIOS16(check_offset + 0x17);
 419                         if (check_offset)
 420                                 offset = check_offset;
 421                 }
 422                 break;
 423         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 424                 check_offset =
 425                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 426                 if (check_offset) {
 427                         check_offset = RBIOS16(check_offset + 0x2);
 428                         if (check_offset)
 429                                 offset = check_offset;
 430                 }
 431                 break;
 432         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 433                 check_offset =
 434                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 435                 if (check_offset) {
 436                         check_offset = RBIOS16(check_offset + 0x4);
 437                         if (check_offset)
 438                                 offset = check_offset;
 439                 }
 440                 break;
 441         default:
 442                 break;
 443         }
 444
 445         return offset;
 446
 447 }
 448
 449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
 450 {
 451         int edid_info;
 452         struct edid *edid;
 453         unsigned char *raw;
 454         edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
 455         if (!edid_info)
 456                 return false;
 457
 458         raw = rdev->bios + edid_info;
 459         edid = kmalloc(EDID_LENGTH * (raw[0x7e] + 1), GFP_KERNEL);
 460         if (edid == NULL)
 461                 return false;
 462
 463         memcpy((unsigned char *)edid, raw, EDID_LENGTH * (raw[0x7e] + 1));
 464
 465         if (!drm_edid_is_valid(edid)) {
 466                 kfree(edid);
 467                 return false;
 468         }
 469
 470         rdev->mode_info.bios_hardcoded_edid = edid;
 471         return true;
 472 }
 473
 474 struct edid *
 475 radeon_combios_get_hardcoded_edid(struct radeon_device *rdev)
 476 {
 477         if (rdev->mode_info.bios_hardcoded_edid)
 478                 return rdev->mode_info.bios_hardcoded_edid;
 479         return NULL;
 480 }
 481
 482 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 483                                                        int ddc_line)
 484 {
 485         struct radeon_i2c_bus_rec i2c;
 486
 487         if (ddc_line == RADEON_GPIOPAD_MASK) {
 488                 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 489                 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 490                 i2c.a_clk_reg = RADEON_GPIOPAD_A;
 491                 i2c.a_data_reg = RADEON_GPIOPAD_A;
 492                 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 493                 i2c.en_data_reg = RADEON_GPIOPAD_EN;
 494                 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 495                 i2c.y_data_reg = RADEON_GPIOPAD_Y;
 496         } else if (ddc_line == RADEON_MDGPIO_MASK) {
 497                 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 498                 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 499                 i2c.a_clk_reg = RADEON_MDGPIO_A;
 500                 i2c.a_data_reg = RADEON_MDGPIO_A;
 501                 i2c.en_clk_reg = RADEON_MDGPIO_EN;
 502                 i2c.en_data_reg = RADEON_MDGPIO_EN;
 503                 i2c.y_clk_reg = RADEON_MDGPIO_Y;
 504                 i2c.y_data_reg = RADEON_MDGPIO_Y;
 505         } else {
 506                 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
 507                 i2c.mask_data_mask = RADEON_GPIO_EN_0;
 508                 i2c.a_clk_mask = RADEON_GPIO_A_1;
 509                 i2c.a_data_mask = RADEON_GPIO_A_0;
 510                 i2c.en_clk_mask = RADEON_GPIO_EN_1;
 511                 i2c.en_data_mask = RADEON_GPIO_EN_0;
 512                 i2c.y_clk_mask = RADEON_GPIO_Y_1;
 513                 i2c.y_data_mask = RADEON_GPIO_Y_0;
 514
 515                 i2c.mask_clk_reg = ddc_line;
 516                 i2c.mask_data_reg = ddc_line;
 517                 i2c.a_clk_reg = ddc_line;
 518                 i2c.a_data_reg = ddc_line;
 519                 i2c.en_clk_reg = ddc_line;
 520                 i2c.en_data_reg = ddc_line;
 521                 i2c.y_clk_reg = ddc_line;
 522                 i2c.y_data_reg = ddc_line;
 523         }
 524
 525         switch (rdev->family) {
 526         case CHIP_R100:
 527         case CHIP_RV100:
 528         case CHIP_RS100:
 529         case CHIP_RV200:
 530         case CHIP_RS200:
 531         case CHIP_RS300:
 532                 switch (ddc_line) {
 533                 case RADEON_GPIO_DVI_DDC:
 534                         i2c.hw_capable = true;
 535                         break;
 536                 default:
 537                         i2c.hw_capable = false;
 538                         break;
 539                 }
 540                 break;
 541         case CHIP_R200:
 542                 switch (ddc_line) {
 543                 case RADEON_GPIO_DVI_DDC:
 544                 case RADEON_GPIO_MONID:
 545                         i2c.hw_capable = true;
 546                         break;
 547                 default:
 548                         i2c.hw_capable = false;
 549                         break;
 550                 }
 551                 break;
 552         case CHIP_RV250:
 553         case CHIP_RV280:
 554                 switch (ddc_line) {
 555                 case RADEON_GPIO_VGA_DDC:
 556                 case RADEON_GPIO_DVI_DDC:
 557                 case RADEON_GPIO_CRT2_DDC:
 558                         i2c.hw_capable = true;
 559                         break;
 560                 default:
 561                         i2c.hw_capable = false;
 562                         break;
 563                 }
 564                 break;
 565         case CHIP_R300:
 566         case CHIP_R350:
 567                 switch (ddc_line) {
 568                 case RADEON_GPIO_VGA_DDC:
 569                 case RADEON_GPIO_DVI_DDC:
 570                         i2c.hw_capable = true;
 571                         break;
 572                 default:
 573                         i2c.hw_capable = false;
 574                         break;
 575                 }
 576                 break;
 577         case CHIP_RV350:
 578         case CHIP_RV380:
 579         case CHIP_RS400:
 580         case CHIP_RS480:
 581                 switch (ddc_line) {
 582                 case RADEON_GPIO_VGA_DDC:
 583                 case RADEON_GPIO_DVI_DDC:
 584                         i2c.hw_capable = true;
 585                         break;
 586                 case RADEON_GPIO_MONID:
 587                         /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 588                          * reliably on some pre-r4xx hardware; not sure why.
 589                          */
 590                         i2c.hw_capable = false;
 591                         break;
 592                 default:
 593                         i2c.hw_capable = false;
 594                         break;
 595                 }
 596                 break;
 597         default:
 598                 i2c.hw_capable = false;
 599                 break;
 600         }
 601         i2c.mm_i2c = false;
 602         i2c.i2c_id = 0;
 603         i2c.hpd = RADEON_HPD_NONE;
 604
 605         if (ddc_line)
 606                 i2c.valid = true;
 607         else
 608                 i2c.valid = false;
 609
 610         return i2c;
 611 }
 612
 613 bool radeon_combios_get_clock_info(struct drm_device *dev)
 614 {
 615         struct radeon_device *rdev = dev->dev_private;
 616         uint16_t pll_info;
 617         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 618         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 619         struct radeon_pll *spll = &rdev->clock.spll;
 620         struct radeon_pll *mpll = &rdev->clock.mpll;
 621         int8_t rev;
 622         uint16_t sclk, mclk;
 623
 624         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 625         if (pll_info) {
 626                 rev = RBIOS8(pll_info);
 627
 628                 /* pixel clocks */
 629                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 630                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 631                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 632                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 633                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
 634                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
 635
 636                 if (rev > 9) {
 637                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 638                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 639                 } else {
 640                         p1pll->pll_in_min = 40;
 641                         p1pll->pll_in_max = 500;
 642                 }
 643                 *p2pll = *p1pll;
 644
 645                 /* system clock */
 646                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 647                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 648                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 649                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 650
 651                 if (rev > 10) {
 652                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 653                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 654                 } else {
 655                         /* ??? */
 656                         spll->pll_in_min = 40;
 657                         spll->pll_in_max = 500;
 658                 }
 659
 660                 /* memory clock */
 661                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 662                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 663                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 664                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 665
 666                 if (rev > 10) {
 667                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 668                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 669                 } else {
 670                         /* ??? */
 671                         mpll->pll_in_min = 40;
 672                         mpll->pll_in_max = 500;
 673                 }
 674
 675                 /* default sclk/mclk */
 676                 sclk = RBIOS16(pll_info + 0xa);
 677                 mclk = RBIOS16(pll_info + 0x8);
 678                 if (sclk == 0)
 679                         sclk = 200 * 100;
 680                 if (mclk == 0)
 681                         mclk = 200 * 100;
 682
 683                 rdev->clock.default_sclk = sclk;
 684                 rdev->clock.default_mclk = mclk;
 685
 686                 return true;
 687         }
 688         return false;
 689 }
 690
 691 bool radeon_combios_sideport_present(struct radeon_device *rdev)
 692 {
 693         struct drm_device *dev = rdev->ddev;
 694         u16 igp_info;
 695
 696         /* sideport is AMD only */
 697         if (rdev->family == CHIP_RS400)
 698                 return false;
 699
 700         igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
 701
 702         if (igp_info) {
 703                 if (RBIOS16(igp_info + 0x4))
 704                         return true;
 705         }
 706         return false;
 707 }
 708
 709 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
 710         0x00000808,             /* r100  */
 711         0x00000808,             /* rv100 */
 712         0x00000808,             /* rs100 */
 713         0x00000808,             /* rv200 */
 714         0x00000808,             /* rs200 */
 715         0x00000808,             /* r200  */
 716         0x00000808,             /* rv250 */
 717         0x00000000,             /* rs300 */
 718         0x00000808,             /* rv280 */
 719         0x00000808,             /* r300  */
 720         0x00000808,             /* r350  */
 721         0x00000808,             /* rv350 */
 722         0x00000808,             /* rv380 */
 723         0x00000808,             /* r420  */
 724         0x00000808,             /* r423  */
 725         0x00000808,             /* rv410 */
 726         0x00000000,             /* rs400 */
 727         0x00000000,             /* rs480 */
 728 };
 729
 730 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
 731                                                           struct radeon_encoder_primary_dac *p_dac)
 732 {
 733         p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
 734         return;
 735 }
 736
 737 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 738                                                                        radeon_encoder
 739                                                                        *encoder)
 740 {
 741         struct drm_device *dev = encoder->base.dev;
 742         struct radeon_device *rdev = dev->dev_private;
 743         uint16_t dac_info;
 744         uint8_t rev, bg, dac;
 745         struct radeon_encoder_primary_dac *p_dac = NULL;
 746         int found = 0;
 747
 748         p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
 749                         GFP_KERNEL);
 750
 751         if (!p_dac)
 752                 return NULL;
 753
 754         /* check CRT table */
 755         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 756         if (dac_info) {
 757                 rev = RBIOS8(dac_info) & 0x3;
 758                 if (rev < 2) {
 759                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 760                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 761                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 762                 } else {
 763                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 764                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 765                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 766                 }
 767                 /* if the values are all zeros, use the table */
 768                 if (p_dac->ps2_pdac_adj)
 769                         found = 1;
 770         }
 771
 772         if (!found) /* fallback to defaults */
 773                 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
 774
 775         return p_dac;
 776 }
 777
 778 enum radeon_tv_std
 779 radeon_combios_get_tv_info(struct radeon_device *rdev)
 780 {
 781         struct drm_device *dev = rdev->ddev;
 782         uint16_t tv_info;
 783         enum radeon_tv_std tv_std = TV_STD_NTSC;
 784
 785         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 786         if (tv_info) {
 787                 if (RBIOS8(tv_info + 6) == 'T') {
 788                         switch (RBIOS8(tv_info + 7) & 0xf) {
 789                         case 1:
 790                                 tv_std = TV_STD_NTSC;
 791                                 DRM_INFO("Default TV standard: NTSC\n");
 792                                 break;
 793                         case 2:
 794                                 tv_std = TV_STD_PAL;
 795                                 DRM_INFO("Default TV standard: PAL\n");
 796                                 break;
 797                         case 3:
 798                                 tv_std = TV_STD_PAL_M;
 799                                 DRM_INFO("Default TV standard: PAL-M\n");
 800                                 break;
 801                         case 4:
 802                                 tv_std = TV_STD_PAL_60;
 803                                 DRM_INFO("Default TV standard: PAL-60\n");
 804                                 break;
 805                         case 5:
 806                                 tv_std = TV_STD_NTSC_J;
 807                                 DRM_INFO("Default TV standard: NTSC-J\n");
 808                                 break;
 809                         case 6:
 810                                 tv_std = TV_STD_SCART_PAL;
 811                                 DRM_INFO("Default TV standard: SCART-PAL\n");
 812                                 break;
 813                         default:
 814                                 tv_std = TV_STD_NTSC;
 815                                 DRM_INFO
 816                                     ("Unknown TV standard; defaulting to NTSC\n");
 817                                 break;
 818                         }
 819
 820                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
 821                         case 0:
 822                                 DRM_INFO("29.498928713 MHz TV ref clk\n");
 823                                 break;
 824                         case 1:
 825                                 DRM_INFO("28.636360000 MHz TV ref clk\n");
 826                                 break;
 827                         case 2:
 828                                 DRM_INFO("14.318180000 MHz TV ref clk\n");
 829                                 break;
 830                         case 3:
 831                                 DRM_INFO("27.000000000 MHz TV ref clk\n");
 832                                 break;
 833                         default:
 834                                 break;
 835                         }
 836                 }
 837         }
 838         return tv_std;
 839 }
 840
 841 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
 842         0x00000000,             /* r100  */
 843         0x00280000,             /* rv100 */
 844         0x00000000,             /* rs100 */
 845         0x00880000,             /* rv200 */
 846         0x00000000,             /* rs200 */
 847         0x00000000,             /* r200  */
 848         0x00770000,             /* rv250 */
 849         0x00290000,             /* rs300 */
 850         0x00560000,             /* rv280 */
 851         0x00780000,             /* r300  */
 852         0x00770000,             /* r350  */
 853         0x00780000,             /* rv350 */
 854         0x00780000,             /* rv380 */
 855         0x01080000,             /* r420  */
 856         0x01080000,             /* r423  */
 857         0x01080000,             /* rv410 */
 858         0x00780000,             /* rs400 */
 859         0x00780000,             /* rs480 */
 860 };
 861
 862 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
 863                                                      struct radeon_encoder_tv_dac *tv_dac)
 864 {
 865         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
 866         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
 867                 tv_dac->ps2_tvdac_adj = 0x00880000;
 868         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 869         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 870         return;
 871 }
 872
 873 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
 874                                                              radeon_encoder
 875                                                              *encoder)
 876 {
 877         struct drm_device *dev = encoder->base.dev;
 878         struct radeon_device *rdev = dev->dev_private;
 879         uint16_t dac_info;
 880         uint8_t rev, bg, dac;
 881         struct radeon_encoder_tv_dac *tv_dac = NULL;
 882         int found = 0;
 883
 884         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
 885         if (!tv_dac)
 886                 return NULL;
 887
 888         /* first check TV table */
 889         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 890         if (dac_info) {
 891                 rev = RBIOS8(dac_info + 0x3);
 892                 if (rev > 4) {
 893                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 894                         dac = RBIOS8(dac_info + 0xd) & 0xf;
 895                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 896
 897                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 898                         dac = RBIOS8(dac_info + 0xf) & 0xf;
 899                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 900
 901                         bg = RBIOS8(dac_info + 0x10) & 0xf;
 902                         dac = RBIOS8(dac_info + 0x11) & 0xf;
 903                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 904                         /* if the values are all zeros, use the table */
 905                         if (tv_dac->ps2_tvdac_adj)
 906                                 found = 1;
 907                 } else if (rev > 1) {
 908                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 909                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
 910                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 911
 912                         bg = RBIOS8(dac_info + 0xd) & 0xf;
 913                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
 914                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 915
 916                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 917                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
 918                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 919                         /* if the values are all zeros, use the table */
 920                         if (tv_dac->ps2_tvdac_adj)
 921                                 found = 1;
 922                 }
 923                 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
 924         }
 925         if (!found) {
 926                 /* then check CRT table */
 927                 dac_info =
 928                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 929                 if (dac_info) {
 930                         rev = RBIOS8(dac_info) & 0x3;
 931                         if (rev < 2) {
 932                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
 933                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
 934                                 tv_dac->ps2_tvdac_adj =
 935                                     (bg << 16) | (dac << 20);
 936                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 937                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 938                                 /* if the values are all zeros, use the table */
 939                                 if (tv_dac->ps2_tvdac_adj)
 940                                         found = 1;
 941                         } else {
 942                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
 943                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
 944                                 tv_dac->ps2_tvdac_adj =
 945                                     (bg << 16) | (dac << 20);
 946                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 947                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 948                                 /* if the values are all zeros, use the table */
 949                                 if (tv_dac->ps2_tvdac_adj)
 950                                         found = 1;
 951                         }
 952                 } else {
 953                         DRM_INFO("No TV DAC info found in BIOS\n");
 954                 }
 955         }
 956
 957         if (!found) /* fallback to defaults */
 958                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
 959
 960         return tv_dac;
 961 }
 962
 963 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
 964                                                                          radeon_device
 965                                                                          *rdev)
 966 {
 967         struct radeon_encoder_lvds *lvds = NULL;
 968         uint32_t fp_vert_stretch, fp_horz_stretch;
 969         uint32_t ppll_div_sel, ppll_val;
 970         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
 971
 972         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
 973
 974         if (!lvds)
 975                 return NULL;
 976
 977         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
 978         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
 979
 980         /* These should be fail-safe defaults, fingers crossed */
 981         lvds->panel_pwr_delay = 200;
 982         lvds->panel_vcc_delay = 2000;
 983
 984         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 985         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
 986         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
 987
 988         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
 989                 lvds->native_mode.vdisplay =
 990                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
 991                      RADEON_VERT_PANEL_SHIFT) + 1;
 992         else
 993                 lvds->native_mode.vdisplay =
 994                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
 995
 996         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
 997                 lvds->native_mode.hdisplay =
 998                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
 999                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1000         else
1001                 lvds->native_mode.hdisplay =
1002                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1003
1004         if ((lvds->native_mode.hdisplay < 640) ||
1005             (lvds->native_mode.vdisplay < 480)) {
1006                 lvds->native_mode.hdisplay = 640;
1007                 lvds->native_mode.vdisplay = 480;
1008         }
1009
1010         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1011         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1012         if ((ppll_val & 0x000707ff) == 0x1bb)
1013                 lvds->use_bios_dividers = false;
1014         else {
1015                 lvds->panel_ref_divider =
1016                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1017                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1018                 lvds->panel_fb_divider = ppll_val & 0x7ff;
1019
1020                 if ((lvds->panel_ref_divider != 0) &&
1021                     (lvds->panel_fb_divider > 3))
1022                         lvds->use_bios_dividers = true;
1023         }
1024         lvds->panel_vcc_delay = 200;
1025
1026         DRM_INFO("Panel info derived from registers\n");
1027         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1028                  lvds->native_mode.vdisplay);
1029
1030         return lvds;
1031 }
1032
1033 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1034                                                          *encoder)
1035 {
1036         struct drm_device *dev = encoder->base.dev;
1037         struct radeon_device *rdev = dev->dev_private;
1038         uint16_t lcd_info;
1039         uint32_t panel_setup;
1040         char stmp[30];
1041         int tmp, i;
1042         struct radeon_encoder_lvds *lvds = NULL;
1043
1044         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1045
1046         if (lcd_info) {
1047                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1048
1049                 if (!lvds)
1050                         return NULL;
1051
1052                 for (i = 0; i < 24; i++)
1053                         stmp[i] = RBIOS8(lcd_info + i + 1);
1054                 stmp[24] = 0;
1055
1056                 DRM_INFO("Panel ID String: %s\n", stmp);
1057
1058                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1059                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1060
1061                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1062                          lvds->native_mode.vdisplay);
1063
1064                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1065                 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1066
1067                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1068                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1069                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1070
1071                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1072                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1073                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1074                 if ((lvds->panel_ref_divider != 0) &&
1075                     (lvds->panel_fb_divider > 3))
1076                         lvds->use_bios_dividers = true;
1077
1078                 panel_setup = RBIOS32(lcd_info + 0x39);
1079                 lvds->lvds_gen_cntl = 0xff00;
1080                 if (panel_setup & 0x1)
1081                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1082
1083                 if ((panel_setup >> 4) & 0x1)
1084                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1085
1086                 switch ((panel_setup >> 8) & 0x7) {
1087                 case 0:
1088                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1089                         break;
1090                 case 1:
1091                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1092                         break;
1093                 case 2:
1094                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1095                         break;
1096                 default:
1097                         break;
1098                 }
1099
1100                 if ((panel_setup >> 16) & 0x1)
1101                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1102
1103                 if ((panel_setup >> 17) & 0x1)
1104                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1105
1106                 if ((panel_setup >> 18) & 0x1)
1107                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1108
1109                 if ((panel_setup >> 23) & 0x1)
1110                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1111
1112                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1113
1114                 for (i = 0; i < 32; i++) {
1115                         tmp = RBIOS16(lcd_info + 64 + i * 2);
1116                         if (tmp == 0)
1117                                 break;
1118
1119                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1120                             (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1121                                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1122                                         (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1123                                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1124                                         (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1125                                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1126                                         (RBIOS8(tmp + 23) * 8);
1127
1128                                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1129                                         (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1130                                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1131                                         ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1132                                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1133                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1134
1135                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1136                                 lvds->native_mode.flags = 0;
1137                                 /* set crtc values */
1138                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1139
1140                         }
1141                 }
1142         } else {
1143                 DRM_INFO("No panel info found in BIOS\n");
1144                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1145         }
1146
1147         if (lvds)
1148                 encoder->native_mode = lvds->native_mode;
1149         return lvds;
1150 }
1151
1152 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1153         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1154         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1155         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1156         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1157         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1158         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1159         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1160         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1161         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1162         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1163         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1164         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1165         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1166         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1167         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1168         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1169         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1170         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1171 };
1172
1173 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1174                                             struct radeon_encoder_int_tmds *tmds)
1175 {
1176         struct drm_device *dev = encoder->base.dev;
1177         struct radeon_device *rdev = dev->dev_private;
1178         int i;
1179
1180         for (i = 0; i < 4; i++) {
1181                 tmds->tmds_pll[i].value =
1182                         default_tmds_pll[rdev->family][i].value;
1183                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1184         }
1185
1186         return true;
1187 }
1188
1189 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1190                                               struct radeon_encoder_int_tmds *tmds)
1191 {
1192         struct drm_device *dev = encoder->base.dev;
1193         struct radeon_device *rdev = dev->dev_private;
1194         uint16_t tmds_info;
1195         int i, n;
1196         uint8_t ver;
1197
1198         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1199
1200         if (tmds_info) {
1201                 ver = RBIOS8(tmds_info);
1202                 DRM_INFO("DFP table revision: %d\n", ver);
1203                 if (ver == 3) {
1204                         n = RBIOS8(tmds_info + 5) + 1;
1205                         if (n > 4)
1206                                 n = 4;
1207                         for (i = 0; i < n; i++) {
1208                                 tmds->tmds_pll[i].value =
1209                                     RBIOS32(tmds_info + i * 10 + 0x08);
1210                                 tmds->tmds_pll[i].freq =
1211                                     RBIOS16(tmds_info + i * 10 + 0x10);
1212                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1213                                           tmds->tmds_pll[i].freq,
1214                                           tmds->tmds_pll[i].value);
1215                         }
1216                 } else if (ver == 4) {
1217                         int stride = 0;
1218                         n = RBIOS8(tmds_info + 5) + 1;
1219                         if (n > 4)
1220                                 n = 4;
1221                         for (i = 0; i < n; i++) {
1222                                 tmds->tmds_pll[i].value =
1223                                     RBIOS32(tmds_info + stride + 0x08);
1224                                 tmds->tmds_pll[i].freq =
1225                                     RBIOS16(tmds_info + stride + 0x10);
1226                                 if (i == 0)
1227                                         stride += 10;
1228                                 else
1229                                         stride += 6;
1230                                 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1231                                           tmds->tmds_pll[i].freq,
1232                                           tmds->tmds_pll[i].value);
1233                         }
1234                 }
1235         } else {
1236                 DRM_INFO("No TMDS info found in BIOS\n");
1237                 return false;
1238         }
1239         return true;
1240 }
1241
1242 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1243                                                 struct radeon_encoder_ext_tmds *tmds)
1244 {
1245         struct drm_device *dev = encoder->base.dev;
1246         struct radeon_device *rdev = dev->dev_private;
1247         struct radeon_i2c_bus_rec i2c_bus;
1248
1249         /* default for macs */
1250         i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1251         tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1252
1253         /* XXX some macs have duallink chips */
1254         switch (rdev->mode_info.connector_table) {
1255         case CT_POWERBOOK_EXTERNAL:
1256         case CT_MINI_EXTERNAL:
1257         default:
1258                 tmds->dvo_chip = DVO_SIL164;
1259                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1260                 break;
1261         }
1262
1263         return true;
1264 }
1265
1266 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1267                                                   struct radeon_encoder_ext_tmds *tmds)
1268 {
1269         struct drm_device *dev = encoder->base.dev;
1270         struct radeon_device *rdev = dev->dev_private;
1271         uint16_t offset;
1272         uint8_t ver, id, blocks, clk, data;
1273         int i;
1274         enum radeon_combios_ddc gpio;
1275         struct radeon_i2c_bus_rec i2c_bus;
1276
1277         tmds->i2c_bus = NULL;
1278         if (rdev->flags & RADEON_IS_IGP) {
1279                 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1280                 if (offset) {
1281                         ver = RBIOS8(offset);
1282                         DRM_INFO("GPIO Table revision: %d\n", ver);
1283                         blocks = RBIOS8(offset + 2);
1284                         for (i = 0; i < blocks; i++) {
1285                                 id = RBIOS8(offset + 3 + (i * 5) + 0);
1286                                 if (id == 136) {
1287                                         clk = RBIOS8(offset + 3 + (i * 5) + 3);
1288                                         data = RBIOS8(offset + 3 + (i * 5) + 4);
1289                                         i2c_bus.valid = true;
1290                                         i2c_bus.mask_clk_mask = (1 << clk);
1291                                         i2c_bus.mask_data_mask = (1 << data);
1292                                         i2c_bus.a_clk_mask = (1 << clk);
1293                                         i2c_bus.a_data_mask = (1 << data);
1294                                         i2c_bus.en_clk_mask = (1 << clk);
1295                                         i2c_bus.en_data_mask = (1 << data);
1296                                         i2c_bus.y_clk_mask = (1 << clk);
1297                                         i2c_bus.y_data_mask = (1 << data);
1298                                         i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1299                                         i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1300                                         i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1301                                         i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1302                                         i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1303                                         i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1304                                         i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1305                                         i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1306                                         tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1307                                         tmds->dvo_chip = DVO_SIL164;
1308                                         tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1309                                         break;
1310                                 }
1311                         }
1312                 }
1313         } else {
1314                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1315                 if (offset) {
1316                         ver = RBIOS8(offset);
1317                         DRM_INFO("External TMDS Table revision: %d\n", ver);
1318                         tmds->slave_addr = RBIOS8(offset + 4 + 2);
1319                         tmds->slave_addr >>= 1; /* 7 bit addressing */
1320                         gpio = RBIOS8(offset + 4 + 3);
1321                         switch (gpio) {
1322                         case DDC_MONID:
1323                                 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1324                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1325                                 break;
1326                         case DDC_DVI:
1327                                 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1328                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1329                                 break;
1330                         case DDC_VGA:
1331                                 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1332                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1333                                 break;
1334                         case DDC_CRT2:
1335                                 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1336                                 if (rdev->family >= CHIP_R300)
1337                                         i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1338                                 else
1339                                         i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1340                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1341                                 break;
1342                         case DDC_LCD: /* MM i2c */
1343                                 i2c_bus.valid = true;
1344                                 i2c_bus.hw_capable = true;
1345                                 i2c_bus.mm_i2c = true;
1346                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1347                                 break;
1348                         default:
1349                                 DRM_ERROR("Unsupported gpio %d\n", gpio);
1350                                 break;
1351                         }
1352                 }
1353         }
1354
1355         if (!tmds->i2c_bus) {
1356                 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1357                 return false;
1358         }
1359
1360         return true;
1361 }
1362
1363 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1364 {
1365         struct radeon_device *rdev = dev->dev_private;
1366         struct radeon_i2c_bus_rec ddc_i2c;
1367         struct radeon_hpd hpd;
1368
1369         rdev->mode_info.connector_table = radeon_connector_table;
1370         if (rdev->mode_info.connector_table == CT_NONE) {
1371 #ifdef CONFIG_PPC_PMAC
1372                 if (of_machine_is_compatible("PowerBook3,3")) {
1373                         /* powerbook with VGA */
1374                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1375                 } else if (of_machine_is_compatible("PowerBook3,4") ||
1376                            of_machine_is_compatible("PowerBook3,5")) {
1377                         /* powerbook with internal tmds */
1378                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1379                 } else if (of_machine_is_compatible("PowerBook5,1") ||
1380                            of_machine_is_compatible("PowerBook5,2") ||
1381                            of_machine_is_compatible("PowerBook5,3") ||
1382                            of_machine_is_compatible("PowerBook5,4") ||
1383                            of_machine_is_compatible("PowerBook5,5")) {
1384                         /* powerbook with external single link tmds (sil164) */
1385                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1386                 } else if (of_machine_is_compatible("PowerBook5,6")) {
1387                         /* powerbook with external dual or single link tmds */
1388                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1389                 } else if (of_machine_is_compatible("PowerBook5,7") ||
1390                            of_machine_is_compatible("PowerBook5,8") ||
1391                            of_machine_is_compatible("PowerBook5,9")) {
1392                         /* PowerBook6,2 ? */
1393                         /* powerbook with external dual link tmds (sil1178?) */
1394                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1395                 } else if (of_machine_is_compatible("PowerBook4,1") ||
1396                            of_machine_is_compatible("PowerBook4,2") ||
1397                            of_machine_is_compatible("PowerBook4,3") ||
1398                            of_machine_is_compatible("PowerBook6,3") ||
1399                            of_machine_is_compatible("PowerBook6,5") ||
1400                            of_machine_is_compatible("PowerBook6,7")) {
1401                         /* ibook */
1402                         rdev->mode_info.connector_table = CT_IBOOK;
1403                 } else if (of_machine_is_compatible("PowerMac4,4")) {
1404                         /* emac */
1405                         rdev->mode_info.connector_table = CT_EMAC;
1406                 } else if (of_machine_is_compatible("PowerMac10,1")) {
1407                         /* mini with internal tmds */
1408                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1409                 } else if (of_machine_is_compatible("PowerMac10,2")) {
1410                         /* mini with external tmds */
1411                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1412                 } else if (of_machine_is_compatible("PowerMac12,1")) {
1413                         /* PowerMac8,1 ? */
1414                         /* imac g5 isight */
1415                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1416                 } else
1417 #endif /* CONFIG_PPC_PMAC */
1418 #ifdef CONFIG_PPC64
1419                 if (ASIC_IS_RN50(rdev))
1420                         rdev->mode_info.connector_table = CT_RN50_POWER;
1421                 else
1422 #endif
1423                         rdev->mode_info.connector_table = CT_GENERIC;
1424         }
1425
1426         switch (rdev->mode_info.connector_table) {
1427         case CT_GENERIC:
1428                 DRM_INFO("Connector Table: %d (generic)\n",
1429                          rdev->mode_info.connector_table);
1430                 /* these are the most common settings */
1431                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1432                         /* VGA - primary dac */
1433                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1434                         hpd.hpd = RADEON_HPD_NONE;
1435                         radeon_add_legacy_encoder(dev,
1436                                                   radeon_get_encoder_id(dev,
1437                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1438                                                                         1),
1439                                                   ATOM_DEVICE_CRT1_SUPPORT);
1440                         radeon_add_legacy_connector(dev, 0,
1441                                                     ATOM_DEVICE_CRT1_SUPPORT,
1442                                                     DRM_MODE_CONNECTOR_VGA,
1443                                                     &ddc_i2c,
1444                                                     CONNECTOR_OBJECT_ID_VGA,
1445                                                     &hpd);
1446                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1447                         /* LVDS */
1448                         ddc_i2c = combios_setup_i2c_bus(rdev, 0);
1449                         hpd.hpd = RADEON_HPD_NONE;
1450                         radeon_add_legacy_encoder(dev,
1451                                                   radeon_get_encoder_id(dev,
1452                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1453                                                                         0),
1454                                                   ATOM_DEVICE_LCD1_SUPPORT);
1455                         radeon_add_legacy_connector(dev, 0,
1456                                                     ATOM_DEVICE_LCD1_SUPPORT,
1457                                                     DRM_MODE_CONNECTOR_LVDS,
1458                                                     &ddc_i2c,
1459                                                     CONNECTOR_OBJECT_ID_LVDS,
1460                                                     &hpd);
1461
1462                         /* VGA - primary dac */
1463                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1464                         hpd.hpd = RADEON_HPD_NONE;
1465                         radeon_add_legacy_encoder(dev,
1466                                                   radeon_get_encoder_id(dev,
1467                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1468                                                                         1),
1469                                                   ATOM_DEVICE_CRT1_SUPPORT);
1470                         radeon_add_legacy_connector(dev, 1,
1471                                                     ATOM_DEVICE_CRT1_SUPPORT,
1472                                                     DRM_MODE_CONNECTOR_VGA,
1473                                                     &ddc_i2c,
1474                                                     CONNECTOR_OBJECT_ID_VGA,
1475                                                     &hpd);
1476                 } else {
1477                         /* DVI-I - tv dac, int tmds */
1478                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1479                         hpd.hpd = RADEON_HPD_1;
1480                         radeon_add_legacy_encoder(dev,
1481                                                   radeon_get_encoder_id(dev,
1482                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1483                                                                         0),
1484                                                   ATOM_DEVICE_DFP1_SUPPORT);
1485                         radeon_add_legacy_encoder(dev,
1486                                                   radeon_get_encoder_id(dev,
1487                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1488                                                                         2),
1489                                                   ATOM_DEVICE_CRT2_SUPPORT);
1490                         radeon_add_legacy_connector(dev, 0,
1491                                                     ATOM_DEVICE_DFP1_SUPPORT |
1492                                                     ATOM_DEVICE_CRT2_SUPPORT,
1493                                                     DRM_MODE_CONNECTOR_DVII,
1494                                                     &ddc_i2c,
1495                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1496                                                     &hpd);
1497
1498                         /* VGA - primary dac */
1499                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1500                         hpd.hpd = RADEON_HPD_NONE;
1501                         radeon_add_legacy_encoder(dev,
1502                                                   radeon_get_encoder_id(dev,
1503                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1504                                                                         1),
1505                                                   ATOM_DEVICE_CRT1_SUPPORT);
1506                         radeon_add_legacy_connector(dev, 1,
1507                                                     ATOM_DEVICE_CRT1_SUPPORT,
1508                                                     DRM_MODE_CONNECTOR_VGA,
1509                                                     &ddc_i2c,
1510                                                     CONNECTOR_OBJECT_ID_VGA,
1511                                                     &hpd);
1512                 }
1513
1514                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1515                         /* TV - tv dac */
1516                         ddc_i2c.valid = false;
1517                         hpd.hpd = RADEON_HPD_NONE;
1518                         radeon_add_legacy_encoder(dev,
1519                                                   radeon_get_encoder_id(dev,
1520                                                                         ATOM_DEVICE_TV1_SUPPORT,
1521                                                                         2),
1522                                                   ATOM_DEVICE_TV1_SUPPORT);
1523                         radeon_add_legacy_connector(dev, 2,
1524                                                     ATOM_DEVICE_TV1_SUPPORT,
1525                                                     DRM_MODE_CONNECTOR_SVIDEO,
1526                                                     &ddc_i2c,
1527                                                     CONNECTOR_OBJECT_ID_SVIDEO,
1528                                                     &hpd);
1529                 }
1530                 break;
1531         case CT_IBOOK:
1532                 DRM_INFO("Connector Table: %d (ibook)\n",
1533                          rdev->mode_info.connector_table);
1534                 /* LVDS */
1535                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1536                 hpd.hpd = RADEON_HPD_NONE;
1537                 radeon_add_legacy_encoder(dev,
1538                                           radeon_get_encoder_id(dev,
1539                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1540                                                                 0),
1541                                           ATOM_DEVICE_LCD1_SUPPORT);
1542                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1543                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1544                                             CONNECTOR_OBJECT_ID_LVDS,
1545                                             &hpd);
1546                 /* VGA - TV DAC */
1547                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1548                 hpd.hpd = RADEON_HPD_NONE;
1549                 radeon_add_legacy_encoder(dev,
1550                                           radeon_get_encoder_id(dev,
1551                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1552                                                                 2),
1553                                           ATOM_DEVICE_CRT2_SUPPORT);
1554                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1555                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1556                                             CONNECTOR_OBJECT_ID_VGA,
1557                                             &hpd);
1558                 /* TV - TV DAC */
1559                 ddc_i2c.valid = false;
1560                 hpd.hpd = RADEON_HPD_NONE;
1561                 radeon_add_legacy_encoder(dev,
1562                                           radeon_get_encoder_id(dev,
1563                                                                 ATOM_DEVICE_TV1_SUPPORT,
1564                                                                 2),
1565                                           ATOM_DEVICE_TV1_SUPPORT);
1566                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1567                                             DRM_MODE_CONNECTOR_SVIDEO,
1568                                             &ddc_i2c,
1569                                             CONNECTOR_OBJECT_ID_SVIDEO,
1570                                             &hpd);
1571                 break;
1572         case CT_POWERBOOK_EXTERNAL:
1573                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1574                          rdev->mode_info.connector_table);
1575                 /* LVDS */
1576                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1577                 hpd.hpd = RADEON_HPD_NONE;
1578                 radeon_add_legacy_encoder(dev,
1579                                           radeon_get_encoder_id(dev,
1580                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1581                                                                 0),
1582                                           ATOM_DEVICE_LCD1_SUPPORT);
1583                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1584                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1585                                             CONNECTOR_OBJECT_ID_LVDS,
1586                                             &hpd);
1587                 /* DVI-I - primary dac, ext tmds */
1588                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1589                 hpd.hpd = RADEON_HPD_2; /* ??? */
1590                 radeon_add_legacy_encoder(dev,
1591                                           radeon_get_encoder_id(dev,
1592                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1593                                                                 0),
1594                                           ATOM_DEVICE_DFP2_SUPPORT);
1595                 radeon_add_legacy_encoder(dev,
1596                                           radeon_get_encoder_id(dev,
1597                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1598                                                                 1),
1599                                           ATOM_DEVICE_CRT1_SUPPORT);
1600                 /* XXX some are SL */
1601                 radeon_add_legacy_connector(dev, 1,
1602                                             ATOM_DEVICE_DFP2_SUPPORT |
1603                                             ATOM_DEVICE_CRT1_SUPPORT,
1604                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1605                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1606                                             &hpd);
1607                 /* TV - TV DAC */
1608                 ddc_i2c.valid = false;
1609                 hpd.hpd = RADEON_HPD_NONE;
1610                 radeon_add_legacy_encoder(dev,
1611                                           radeon_get_encoder_id(dev,
1612                                                                 ATOM_DEVICE_TV1_SUPPORT,
1613                                                                 2),
1614                                           ATOM_DEVICE_TV1_SUPPORT);
1615                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1616                                             DRM_MODE_CONNECTOR_SVIDEO,
1617                                             &ddc_i2c,
1618                                             CONNECTOR_OBJECT_ID_SVIDEO,
1619                                             &hpd);
1620                 break;
1621         case CT_POWERBOOK_INTERNAL:
1622                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1623                          rdev->mode_info.connector_table);
1624                 /* LVDS */
1625                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1626                 hpd.hpd = RADEON_HPD_NONE;
1627                 radeon_add_legacy_encoder(dev,
1628                                           radeon_get_encoder_id(dev,
1629                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1630                                                                 0),
1631                                           ATOM_DEVICE_LCD1_SUPPORT);
1632                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1633                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1634                                             CONNECTOR_OBJECT_ID_LVDS,
1635                                             &hpd);
1636                 /* DVI-I - primary dac, int tmds */
1637                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1638                 hpd.hpd = RADEON_HPD_1; /* ??? */
1639                 radeon_add_legacy_encoder(dev,
1640                                           radeon_get_encoder_id(dev,
1641                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1642                                                                 0),
1643                                           ATOM_DEVICE_DFP1_SUPPORT);
1644                 radeon_add_legacy_encoder(dev,
1645                                           radeon_get_encoder_id(dev,
1646                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1647                                                                 1),
1648                                           ATOM_DEVICE_CRT1_SUPPORT);
1649                 radeon_add_legacy_connector(dev, 1,
1650                                             ATOM_DEVICE_DFP1_SUPPORT |
1651                                             ATOM_DEVICE_CRT1_SUPPORT,
1652                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1653                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1654                                             &hpd);
1655                 /* TV - TV DAC */
1656                 ddc_i2c.valid = false;
1657                 hpd.hpd = RADEON_HPD_NONE;
1658                 radeon_add_legacy_encoder(dev,
1659                                           radeon_get_encoder_id(dev,
1660                                                                 ATOM_DEVICE_TV1_SUPPORT,
1661                                                                 2),
1662                                           ATOM_DEVICE_TV1_SUPPORT);
1663                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1664                                             DRM_MODE_CONNECTOR_SVIDEO,
1665                                             &ddc_i2c,
1666                                             CONNECTOR_OBJECT_ID_SVIDEO,
1667                                             &hpd);
1668                 break;
1669         case CT_POWERBOOK_VGA:
1670                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1671                          rdev->mode_info.connector_table);
1672                 /* LVDS */
1673                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1674                 hpd.hpd = RADEON_HPD_NONE;
1675                 radeon_add_legacy_encoder(dev,
1676                                           radeon_get_encoder_id(dev,
1677                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1678                                                                 0),
1679                                           ATOM_DEVICE_LCD1_SUPPORT);
1680                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1681                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1682                                             CONNECTOR_OBJECT_ID_LVDS,
1683                                             &hpd);
1684                 /* VGA - primary dac */
1685                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1686                 hpd.hpd = RADEON_HPD_NONE;
1687                 radeon_add_legacy_encoder(dev,
1688                                           radeon_get_encoder_id(dev,
1689                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1690                                                                 1),
1691                                           ATOM_DEVICE_CRT1_SUPPORT);
1692                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1693                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1694                                             CONNECTOR_OBJECT_ID_VGA,
1695                                             &hpd);
1696                 /* TV - TV DAC */
1697                 ddc_i2c.valid = false;
1698                 hpd.hpd = RADEON_HPD_NONE;
1699                 radeon_add_legacy_encoder(dev,
1700                                           radeon_get_encoder_id(dev,
1701                                                                 ATOM_DEVICE_TV1_SUPPORT,
1702                                                                 2),
1703                                           ATOM_DEVICE_TV1_SUPPORT);
1704                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1705                                             DRM_MODE_CONNECTOR_SVIDEO,
1706                                             &ddc_i2c,
1707                                             CONNECTOR_OBJECT_ID_SVIDEO,
1708                                             &hpd);
1709                 break;
1710         case CT_MINI_EXTERNAL:
1711                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1712                          rdev->mode_info.connector_table);
1713                 /* DVI-I - tv dac, ext tmds */
1714                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1715                 hpd.hpd = RADEON_HPD_2; /* ??? */
1716                 radeon_add_legacy_encoder(dev,
1717                                           radeon_get_encoder_id(dev,
1718                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1719                                                                 0),
1720                                           ATOM_DEVICE_DFP2_SUPPORT);
1721                 radeon_add_legacy_encoder(dev,
1722                                           radeon_get_encoder_id(dev,
1723                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1724                                                                 2),
1725                                           ATOM_DEVICE_CRT2_SUPPORT);
1726                 /* XXX are any DL? */
1727                 radeon_add_legacy_connector(dev, 0,
1728                                             ATOM_DEVICE_DFP2_SUPPORT |
1729                                             ATOM_DEVICE_CRT2_SUPPORT,
1730                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1731                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1732                                             &hpd);
1733                 /* TV - TV DAC */
1734                 ddc_i2c.valid = false;
1735                 hpd.hpd = RADEON_HPD_NONE;
1736                 radeon_add_legacy_encoder(dev,
1737                                           radeon_get_encoder_id(dev,
1738                                                                 ATOM_DEVICE_TV1_SUPPORT,
1739                                                                 2),
1740                                           ATOM_DEVICE_TV1_SUPPORT);
1741                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1742                                             DRM_MODE_CONNECTOR_SVIDEO,
1743                                             &ddc_i2c,
1744                                             CONNECTOR_OBJECT_ID_SVIDEO,
1745                                             &hpd);
1746                 break;
1747         case CT_MINI_INTERNAL:
1748                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1749                          rdev->mode_info.connector_table);
1750                 /* DVI-I - tv dac, int tmds */
1751                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1752                 hpd.hpd = RADEON_HPD_1; /* ??? */
1753                 radeon_add_legacy_encoder(dev,
1754                                           radeon_get_encoder_id(dev,
1755                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1756                                                                 0),
1757                                           ATOM_DEVICE_DFP1_SUPPORT);
1758                 radeon_add_legacy_encoder(dev,
1759                                           radeon_get_encoder_id(dev,
1760                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1761                                                                 2),
1762                                           ATOM_DEVICE_CRT2_SUPPORT);
1763                 radeon_add_legacy_connector(dev, 0,
1764                                             ATOM_DEVICE_DFP1_SUPPORT |
1765                                             ATOM_DEVICE_CRT2_SUPPORT,
1766                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1767                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1768                                             &hpd);
1769                 /* TV - TV DAC */
1770                 ddc_i2c.valid = false;
1771                 hpd.hpd = RADEON_HPD_NONE;
1772                 radeon_add_legacy_encoder(dev,
1773                                           radeon_get_encoder_id(dev,
1774                                                                 ATOM_DEVICE_TV1_SUPPORT,
1775                                                                 2),
1776                                           ATOM_DEVICE_TV1_SUPPORT);
1777                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1778                                             DRM_MODE_CONNECTOR_SVIDEO,
1779                                             &ddc_i2c,
1780                                             CONNECTOR_OBJECT_ID_SVIDEO,
1781                                             &hpd);
1782                 break;
1783         case CT_IMAC_G5_ISIGHT:
1784                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1785                          rdev->mode_info.connector_table);
1786                 /* DVI-D - int tmds */
1787                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1788                 hpd.hpd = RADEON_HPD_1; /* ??? */
1789                 radeon_add_legacy_encoder(dev,
1790                                           radeon_get_encoder_id(dev,
1791                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1792                                                                 0),
1793                                           ATOM_DEVICE_DFP1_SUPPORT);
1794                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1795                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1796                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1797                                             &hpd);
1798                 /* VGA - tv dac */
1799                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1800                 hpd.hpd = RADEON_HPD_NONE;
1801                 radeon_add_legacy_encoder(dev,
1802                                           radeon_get_encoder_id(dev,
1803                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1804                                                                 2),
1805                                           ATOM_DEVICE_CRT2_SUPPORT);
1806                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1807                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1808                                             CONNECTOR_OBJECT_ID_VGA,
1809                                             &hpd);
1810                 /* TV - TV DAC */
1811                 ddc_i2c.valid = false;
1812                 hpd.hpd = RADEON_HPD_NONE;
1813                 radeon_add_legacy_encoder(dev,
1814                                           radeon_get_encoder_id(dev,
1815                                                                 ATOM_DEVICE_TV1_SUPPORT,
1816                                                                 2),
1817                                           ATOM_DEVICE_TV1_SUPPORT);
1818                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1819                                             DRM_MODE_CONNECTOR_SVIDEO,
1820                                             &ddc_i2c,
1821                                             CONNECTOR_OBJECT_ID_SVIDEO,
1822                                             &hpd);
1823                 break;
1824         case CT_EMAC:
1825                 DRM_INFO("Connector Table: %d (emac)\n",
1826                          rdev->mode_info.connector_table);
1827                 /* VGA - primary dac */
1828                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1829                 hpd.hpd = RADEON_HPD_NONE;
1830                 radeon_add_legacy_encoder(dev,
1831                                           radeon_get_encoder_id(dev,
1832                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1833                                                                 1),
1834                                           ATOM_DEVICE_CRT1_SUPPORT);
1835                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1836                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1837                                             CONNECTOR_OBJECT_ID_VGA,
1838                                             &hpd);
1839                 /* VGA - tv dac */
1840                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1841                 hpd.hpd = RADEON_HPD_NONE;
1842                 radeon_add_legacy_encoder(dev,
1843                                           radeon_get_encoder_id(dev,
1844                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1845                                                                 2),
1846                                           ATOM_DEVICE_CRT2_SUPPORT);
1847                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1848                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1849                                             CONNECTOR_OBJECT_ID_VGA,
1850                                             &hpd);
1851                 /* TV - TV DAC */
1852                 ddc_i2c.valid = false;
1853                 hpd.hpd = RADEON_HPD_NONE;
1854                 radeon_add_legacy_encoder(dev,
1855                                           radeon_get_encoder_id(dev,
1856                                                                 ATOM_DEVICE_TV1_SUPPORT,
1857                                                                 2),
1858                                           ATOM_DEVICE_TV1_SUPPORT);
1859                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1860                                             DRM_MODE_CONNECTOR_SVIDEO,
1861                                             &ddc_i2c,
1862                                             CONNECTOR_OBJECT_ID_SVIDEO,
1863                                             &hpd);
1864                 break;
1865         case CT_RN50_POWER:
1866                 DRM_INFO("Connector Table: %d (rn50-power)\n",
1867                          rdev->mode_info.connector_table);
1868                 /* VGA - primary dac */
1869                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1870                 hpd.hpd = RADEON_HPD_NONE;
1871                 radeon_add_legacy_encoder(dev,
1872                                           radeon_get_encoder_id(dev,
1873                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1874                                                                 1),
1875                                           ATOM_DEVICE_CRT1_SUPPORT);
1876                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1877                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1878                                             CONNECTOR_OBJECT_ID_VGA,
1879                                             &hpd);
1880                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1881                 hpd.hpd = RADEON_HPD_NONE;
1882                 radeon_add_legacy_encoder(dev,
1883                                           radeon_get_encoder_id(dev,
1884                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1885                                                                 2),
1886                                           ATOM_DEVICE_CRT2_SUPPORT);
1887                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1888                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1889                                             CONNECTOR_OBJECT_ID_VGA,
1890                                             &hpd);
1891                 break;
1892         default:
1893                 DRM_INFO("Connector table: %d (invalid)\n",
1894                          rdev->mode_info.connector_table);
1895                 return false;
1896         }
1897
1898         radeon_link_encoder_connector(dev);
1899
1900         return true;
1901 }
1902
1903 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1904                                        int bios_index,
1905                                        enum radeon_combios_connector
1906                                        *legacy_connector,
1907                                        struct radeon_i2c_bus_rec *ddc_i2c,
1908                                        struct radeon_hpd *hpd)
1909 {
1910         struct radeon_device *rdev = dev->dev_private;
1911
1912         /* XPRESS DDC quirks */
1913         if ((rdev->family == CHIP_RS400 ||
1914              rdev->family == CHIP_RS480) &&
1915             ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1916                 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1917         else if ((rdev->family == CHIP_RS400 ||
1918                   rdev->family == CHIP_RS480) &&
1919                  ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1920                 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
1921                 ddc_i2c->mask_clk_mask = (0x20 << 8);
1922                 ddc_i2c->mask_data_mask = 0x80;
1923                 ddc_i2c->a_clk_mask = (0x20 << 8);
1924                 ddc_i2c->a_data_mask = 0x80;
1925                 ddc_i2c->en_clk_mask = (0x20 << 8);
1926                 ddc_i2c->en_data_mask = 0x80;
1927                 ddc_i2c->y_clk_mask = (0x20 << 8);
1928                 ddc_i2c->y_data_mask = 0x80;
1929         }
1930
1931         /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1932         if ((rdev->family >= CHIP_R300) &&
1933             ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1934                 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1935
1936         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1937            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1938         if (dev->pdev->device == 0x515e &&
1939             dev->pdev->subsystem_vendor == 0x1014) {
1940                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1941                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1942                         return false;
1943         }
1944
1945         /* X300 card with extra non-existent DVI port */
1946         if (dev->pdev->device == 0x5B60 &&
1947             dev->pdev->subsystem_vendor == 0x17af &&
1948             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1949                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1950                         return false;
1951         }
1952
1953         return true;
1954 }
1955
1956 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1957 {
1958         /* Acer 5102 has non-existent TV port */
1959         if (dev->pdev->device == 0x5975 &&
1960             dev->pdev->subsystem_vendor == 0x1025 &&
1961             dev->pdev->subsystem_device == 0x009f)
1962                 return false;
1963
1964         /* HP dc5750 has non-existent TV port */
1965         if (dev->pdev->device == 0x5974 &&
1966             dev->pdev->subsystem_vendor == 0x103c &&
1967             dev->pdev->subsystem_device == 0x280a)
1968                 return false;
1969
1970         /* MSI S270 has non-existent TV port */
1971         if (dev->pdev->device == 0x5955 &&
1972             dev->pdev->subsystem_vendor == 0x1462 &&
1973             dev->pdev->subsystem_device == 0x0131)
1974                 return false;
1975
1976         return true;
1977 }
1978
1979 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1980 {
1981         struct radeon_device *rdev = dev->dev_private;
1982         uint32_t ext_tmds_info;
1983
1984         if (rdev->flags & RADEON_IS_IGP) {
1985                 if (is_dvi_d)
1986                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1987                 else
1988                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1989         }
1990         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1991         if (ext_tmds_info) {
1992                 uint8_t rev = RBIOS8(ext_tmds_info);
1993                 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1994                 if (rev >= 3) {
1995                         if (is_dvi_d)
1996                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1997                         else
1998                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1999                 } else {
2000                         if (flags & 1) {
2001                                 if (is_dvi_d)
2002                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2003                                 else
2004                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2005                         }
2006                 }
2007         }
2008         if (is_dvi_d)
2009                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2010         else
2011                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2012 }
2013
2014 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2015 {
2016         struct radeon_device *rdev = dev->dev_private;
2017         uint32_t conn_info, entry, devices;
2018         uint16_t tmp, connector_object_id;
2019         enum radeon_combios_ddc ddc_type;
2020         enum radeon_combios_connector connector;
2021         int i = 0;
2022         struct radeon_i2c_bus_rec ddc_i2c;
2023         struct radeon_hpd hpd;
2024
2025         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2026         if (conn_info) {
2027                 for (i = 0; i < 4; i++) {
2028                         entry = conn_info + 2 + i * 2;
2029
2030                         if (!RBIOS16(entry))
2031                                 break;
2032
2033                         tmp = RBIOS16(entry);
2034
2035                         connector = (tmp >> 12) & 0xf;
2036
2037                         ddc_type = (tmp >> 8) & 0xf;
2038                         switch (ddc_type) {
2039                         case DDC_MONID:
2040                                 ddc_i2c =
2041                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
2042                                 break;
2043                         case DDC_DVI:
2044                                 ddc_i2c =
2045                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2046                                 break;
2047                         case DDC_VGA:
2048                                 ddc_i2c =
2049                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2050                                 break;
2051                         case DDC_CRT2:
2052                                 ddc_i2c =
2053                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
2054                                 break;
2055                         default:
2056                                 ddc_i2c.valid = false;
2057                                 break;
2058                         }
2059
2060                         switch (connector) {
2061                         case CONNECTOR_PROPRIETARY_LEGACY:
2062                         case CONNECTOR_DVI_I_LEGACY:
2063                         case CONNECTOR_DVI_D_LEGACY:
2064                                 if ((tmp >> 4) & 0x1)
2065                                         hpd.hpd = RADEON_HPD_2;
2066                                 else
2067                                         hpd.hpd = RADEON_HPD_1;
2068                                 break;
2069                         default:
2070                                 hpd.hpd = RADEON_HPD_NONE;
2071                                 break;
2072                         }
2073
2074                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
2075                                                         &ddc_i2c, &hpd))
2076                                 continue;
2077
2078                         switch (connector) {
2079                         case CONNECTOR_PROPRIETARY_LEGACY:
2080                                 if ((tmp >> 4) & 0x1)
2081                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2082                                 else
2083                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2084                                 radeon_add_legacy_encoder(dev,
2085                                                           radeon_get_encoder_id
2086                                                           (dev, devices, 0),
2087                                                           devices);
2088                                 radeon_add_legacy_connector(dev, i, devices,
2089                                                             legacy_connector_convert
2090                                                             [connector],
2091                                                             &ddc_i2c,
2092                                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2093                                                             &hpd);
2094                                 break;
2095                         case CONNECTOR_CRT_LEGACY:
2096                                 if (tmp & 0x1) {
2097                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
2098                                         radeon_add_legacy_encoder(dev,
2099                                                                   radeon_get_encoder_id
2100                                                                   (dev,
2101                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2102                                                                    2),
2103                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2104                                 } else {
2105                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
2106                                         radeon_add_legacy_encoder(dev,
2107                                                                   radeon_get_encoder_id
2108                                                                   (dev,
2109                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2110                                                                    1),
2111                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2112                                 }
2113                                 radeon_add_legacy_connector(dev,
2114                                                             i,
2115                                                             devices,
2116                                                             legacy_connector_convert
2117                                                             [connector],
2118                                                             &ddc_i2c,
2119                                                             CONNECTOR_OBJECT_ID_VGA,
2120                                                             &hpd);
2121                                 break;
2122                         case CONNECTOR_DVI_I_LEGACY:
2123                                 devices = 0;
2124                                 if (tmp & 0x1) {
2125                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
2126                                         radeon_add_legacy_encoder(dev,
2127                                                                   radeon_get_encoder_id
2128                                                                   (dev,
2129                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2130                                                                    2),
2131                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2132                                 } else {
2133                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
2134                                         radeon_add_legacy_encoder(dev,
2135                                                                   radeon_get_encoder_id
2136                                                                   (dev,
2137                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2138                                                                    1),
2139                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2140                                 }
2141                                 if ((tmp >> 4) & 0x1) {
2142                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
2143                                         radeon_add_legacy_encoder(dev,
2144                                                                   radeon_get_encoder_id
2145                                                                   (dev,
2146                                                                    ATOM_DEVICE_DFP2_SUPPORT,
2147                                                                    0),
2148                                                                   ATOM_DEVICE_DFP2_SUPPORT);
2149                                         connector_object_id = combios_check_dl_dvi(dev, 0);
2150                                 } else {
2151                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
2152                                         radeon_add_legacy_encoder(dev,
2153                                                                   radeon_get_encoder_id
2154                                                                   (dev,
2155                                                                    ATOM_DEVICE_DFP1_SUPPORT,
2156                                                                    0),
2157                                                                   ATOM_DEVICE_DFP1_SUPPORT);
2158                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2159                                 }
2160                                 radeon_add_legacy_connector(dev,
2161                                                             i,
2162                                                             devices,
2163                                                             legacy_connector_convert
2164                                                             [connector],
2165                                                             &ddc_i2c,
2166                                                             connector_object_id,
2167                                                             &hpd);
2168                                 break;
2169                         case CONNECTOR_DVI_D_LEGACY:
2170                                 if ((tmp >> 4) & 0x1) {
2171                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2172                                         connector_object_id = combios_check_dl_dvi(dev, 1);
2173                                 } else {
2174                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2175                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2176                                 }
2177                                 radeon_add_legacy_encoder(dev,
2178                                                           radeon_get_encoder_id
2179                                                           (dev, devices, 0),
2180                                                           devices);
2181                                 radeon_add_legacy_connector(dev, i, devices,
2182                                                             legacy_connector_convert
2183                                                             [connector],
2184                                                             &ddc_i2c,
2185                                                             connector_object_id,
2186                                                             &hpd);
2187                                 break;
2188                         case CONNECTOR_CTV_LEGACY:
2189                         case CONNECTOR_STV_LEGACY:
2190                                 radeon_add_legacy_encoder(dev,
2191                                                           radeon_get_encoder_id
2192                                                           (dev,
2193                                                            ATOM_DEVICE_TV1_SUPPORT,
2194                                                            2),
2195                                                           ATOM_DEVICE_TV1_SUPPORT);
2196                                 radeon_add_legacy_connector(dev, i,
2197                                                             ATOM_DEVICE_TV1_SUPPORT,
2198                                                             legacy_connector_convert
2199                                                             [connector],
2200                                                             &ddc_i2c,
2201                                                             CONNECTOR_OBJECT_ID_SVIDEO,
2202                                                             &hpd);
2203                                 break;
2204                         default:
2205                                 DRM_ERROR("Unknown connector type: %d\n",
2206                                           connector);
2207                                 continue;
2208                         }
2209
2210                 }
2211         } else {
2212                 uint16_t tmds_info =
2213                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2214                 if (tmds_info) {
2215                         DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2216
2217                         radeon_add_legacy_encoder(dev,
2218                                                   radeon_get_encoder_id(dev,
2219                                                                         ATOM_DEVICE_CRT1_SUPPORT,
2220                                                                         1),
2221                                                   ATOM_DEVICE_CRT1_SUPPORT);
2222                         radeon_add_legacy_encoder(dev,
2223                                                   radeon_get_encoder_id(dev,
2224                                                                         ATOM_DEVICE_DFP1_SUPPORT,
2225                                                                         0),
2226                                                   ATOM_DEVICE_DFP1_SUPPORT);
2227
2228                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2229                         hpd.hpd = RADEON_HPD_1;
2230                         radeon_add_legacy_connector(dev,
2231                                                     0,
2232                                                     ATOM_DEVICE_CRT1_SUPPORT |
2233                                                     ATOM_DEVICE_DFP1_SUPPORT,
2234                                                     DRM_MODE_CONNECTOR_DVII,
2235                                                     &ddc_i2c,
2236                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2237                                                     &hpd);
2238                 } else {
2239                         uint16_t crt_info =
2240                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2241                         DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2242                         if (crt_info) {
2243                                 radeon_add_legacy_encoder(dev,
2244                                                           radeon_get_encoder_id(dev,
2245                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2246                                                                                 1),
2247                                                           ATOM_DEVICE_CRT1_SUPPORT);
2248                                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2249                                 hpd.hpd = RADEON_HPD_NONE;
2250                                 radeon_add_legacy_connector(dev,
2251                                                             0,
2252                                                             ATOM_DEVICE_CRT1_SUPPORT,
2253                                                             DRM_MODE_CONNECTOR_VGA,
2254                                                             &ddc_i2c,
2255                                                             CONNECTOR_OBJECT_ID_VGA,
2256                                                             &hpd);
2257                         } else {
2258                                 DRM_DEBUG_KMS("No connector info found\n");
2259                                 return false;
2260                         }
2261                 }
2262         }
2263
2264         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2265                 uint16_t lcd_info =
2266                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2267                 if (lcd_info) {
2268                         uint16_t lcd_ddc_info =
2269                             combios_get_table_offset(dev,
2270                                                      COMBIOS_LCD_DDC_INFO_TABLE);
2271
2272                         radeon_add_legacy_encoder(dev,
2273                                                   radeon_get_encoder_id(dev,
2274                                                                         ATOM_DEVICE_LCD1_SUPPORT,
2275                                                                         0),
2276                                                   ATOM_DEVICE_LCD1_SUPPORT);
2277
2278                         if (lcd_ddc_info) {
2279                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
2280                                 switch (ddc_type) {
2281                                 case DDC_MONID:
2282                                         ddc_i2c =
2283                                             combios_setup_i2c_bus
2284                                                 (rdev, RADEON_GPIO_MONID);
2285                                         break;
2286                                 case DDC_DVI:
2287                                         ddc_i2c =
2288                                             combios_setup_i2c_bus
2289                                                 (rdev, RADEON_GPIO_DVI_DDC);
2290                                         break;
2291                                 case DDC_VGA:
2292                                         ddc_i2c =
2293                                             combios_setup_i2c_bus
2294                                                 (rdev, RADEON_GPIO_VGA_DDC);
2295                                         break;
2296                                 case DDC_CRT2:
2297                                         ddc_i2c =
2298                                             combios_setup_i2c_bus
2299                                                 (rdev, RADEON_GPIO_CRT2_DDC);
2300                                         break;
2301                                 case DDC_LCD:
2302                                         ddc_i2c =
2303                                             combios_setup_i2c_bus
2304                                                 (rdev, RADEON_GPIOPAD_MASK);
2305                                         ddc_i2c.mask_clk_mask =
2306                                             RBIOS32(lcd_ddc_info + 3);
2307                                         ddc_i2c.mask_data_mask =
2308                                             RBIOS32(lcd_ddc_info + 7);
2309                                         ddc_i2c.a_clk_mask =
2310                                             RBIOS32(lcd_ddc_info + 3);
2311                                         ddc_i2c.a_data_mask =
2312                                             RBIOS32(lcd_ddc_info + 7);
2313                                         ddc_i2c.en_clk_mask =
2314                                             RBIOS32(lcd_ddc_info + 3);
2315                                         ddc_i2c.en_data_mask =
2316                                             RBIOS32(lcd_ddc_info + 7);
2317                                         ddc_i2c.y_clk_mask =
2318                                             RBIOS32(lcd_ddc_info + 3);
2319                                         ddc_i2c.y_data_mask =
2320                                             RBIOS32(lcd_ddc_info + 7);
2321                                         break;
2322                                 case DDC_GPIO:
2323                                         ddc_i2c =
2324                                             combios_setup_i2c_bus
2325                                                 (rdev, RADEON_MDGPIO_MASK);
2326                                         ddc_i2c.mask_clk_mask =
2327                                             RBIOS32(lcd_ddc_info + 3);
2328                                         ddc_i2c.mask_data_mask =
2329                                             RBIOS32(lcd_ddc_info + 7);
2330                                         ddc_i2c.a_clk_mask =
2331                                             RBIOS32(lcd_ddc_info + 3);
2332                                         ddc_i2c.a_data_mask =
2333                                             RBIOS32(lcd_ddc_info + 7);
2334                                         ddc_i2c.en_clk_mask =
2335                                             RBIOS32(lcd_ddc_info + 3);
2336                                         ddc_i2c.en_data_mask =
2337                                             RBIOS32(lcd_ddc_info + 7);
2338                                         ddc_i2c.y_clk_mask =
2339                                             RBIOS32(lcd_ddc_info + 3);
2340                                         ddc_i2c.y_data_mask =
2341                                             RBIOS32(lcd_ddc_info + 7);
2342                                         break;
2343                                 default:
2344                                         ddc_i2c.valid = false;
2345                                         break;
2346                                 }
2347                                 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2348                         } else
2349                                 ddc_i2c.valid = false;
2350
2351                         hpd.hpd = RADEON_HPD_NONE;
2352                         radeon_add_legacy_connector(dev,
2353                                                     5,
2354                                                     ATOM_DEVICE_LCD1_SUPPORT,
2355                                                     DRM_MODE_CONNECTOR_LVDS,
2356                                                     &ddc_i2c,
2357                                                     CONNECTOR_OBJECT_ID_LVDS,
2358                                                     &hpd);
2359                 }
2360         }
2361
2362         /* check TV table */
2363         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2364                 uint32_t tv_info =
2365                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2366                 if (tv_info) {
2367                         if (RBIOS8(tv_info + 6) == 'T') {
2368                                 if (radeon_apply_legacy_tv_quirks(dev)) {
2369                                         hpd.hpd = RADEON_HPD_NONE;
2370                                         ddc_i2c.valid = false;
2371                                         radeon_add_legacy_encoder(dev,
2372                                                                   radeon_get_encoder_id
2373                                                                   (dev,
2374                                                                    ATOM_DEVICE_TV1_SUPPORT,
2375                                                                    2),
2376                                                                   ATOM_DEVICE_TV1_SUPPORT);
2377                                         radeon_add_legacy_connector(dev, 6,
2378                                                                     ATOM_DEVICE_TV1_SUPPORT,
2379                                                                     DRM_MODE_CONNECTOR_SVIDEO,
2380                                                                     &ddc_i2c,
2381                                                                     CONNECTOR_OBJECT_ID_SVIDEO,
2382                                                                     &hpd);
2383                                 }
2384                         }
2385                 }
2386         }
2387
2388         radeon_link_encoder_connector(dev);
2389
2390         return true;
2391 }
2392
2393 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2394 {
2395         struct drm_device *dev = rdev->ddev;
2396         u16 offset, misc, misc2 = 0;
2397         u8 rev, blocks, tmp;
2398         int state_index = 0;
2399
2400         rdev->pm.default_power_state_index = -1;
2401
2402         if (rdev->flags & RADEON_IS_MOBILITY) {
2403                 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2404                 if (offset) {
2405                         rev = RBIOS8(offset);
2406                         blocks = RBIOS8(offset + 0x2);
2407                         /* power mode 0 tends to be the only valid one */
2408                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2409                         rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2410                         rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2411                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2412                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2413                                 goto default_mode;
2414                         rdev->pm.power_state[state_index].type =
2415                                 POWER_STATE_TYPE_BATTERY;
2416                         misc = RBIOS16(offset + 0x5 + 0x0);
2417                         if (rev > 4)
2418                                 misc2 = RBIOS16(offset + 0x5 + 0xe);
2419                         rdev->pm.power_state[state_index].misc = misc;
2420                         rdev->pm.power_state[state_index].misc2 = misc2;
2421                         if (misc & 0x4) {
2422                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2423                                 if (misc & 0x8)
2424                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2425                                                 true;
2426                                 else
2427                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2428                                                 false;
2429                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2430                                 if (rev < 6) {
2431                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2432                                                 RBIOS16(offset + 0x5 + 0xb) * 4;
2433                                         tmp = RBIOS8(offset + 0x5 + 0xd);
2434                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2435                                 } else {
2436                                         u8 entries = RBIOS8(offset + 0x5 + 0xb);
2437                                         u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2438                                         if (entries && voltage_table_offset) {
2439                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2440                                                         RBIOS16(voltage_table_offset) * 4;
2441                                                 tmp = RBIOS8(voltage_table_offset + 0x2);
2442                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2443                                         } else
2444                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2445                                 }
2446                                 switch ((misc2 & 0x700) >> 8) {
2447                                 case 0:
2448                                 default:
2449                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2450                                         break;
2451                                 case 1:
2452                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2453                                         break;
2454                                 case 2:
2455                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2456                                         break;
2457                                 case 3:
2458                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2459                                         break;
2460                                 case 4:
2461                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2462                                         break;
2463                                 }
2464                         } else
2465                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2466                         if (rev > 6)
2467                                 rdev->pm.power_state[state_index].pcie_lanes =
2468                                         RBIOS8(offset + 0x5 + 0x10);
2469                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2470                         state_index++;
2471                 } else {
2472                         /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2473                 }
2474         } else {
2475                 /* XXX figure out some good default low power mode for desktop cards */
2476         }
2477
2478 default_mode:
2479         /* add the default mode */
2480         rdev->pm.power_state[state_index].type =
2481                 POWER_STATE_TYPE_DEFAULT;
2482         rdev->pm.power_state[state_index].num_clock_modes = 1;
2483         rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2484         rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2485         rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2486         if ((state_index > 0) &&
2487             (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2488                 rdev->pm.power_state[state_index].clock_info[0].voltage =
2489                         rdev->pm.power_state[0].clock_info[0].voltage;
2490         else
2491                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2492         rdev->pm.power_state[state_index].pcie_lanes = 16;
2493         rdev->pm.power_state[state_index].flags = 0;
2494         rdev->pm.default_power_state_index = state_index;
2495         rdev->pm.num_power_states = state_index + 1;
2496
2497         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2498         rdev->pm.current_clock_mode_index = 0;
2499 }
2500
2501 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2502 {
2503         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2504         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2505
2506         if (!tmds)
2507                 return;
2508
2509         switch (tmds->dvo_chip) {
2510         case DVO_SIL164:
2511                 /* sil 164 */
2512                 radeon_i2c_put_byte(tmds->i2c_bus,
2513                                     tmds->slave_addr,
2514                                     0x08, 0x30);
2515                 radeon_i2c_put_byte(tmds->i2c_bus,
2516                                        tmds->slave_addr,
2517                                        0x09, 0x00);
2518                 radeon_i2c_put_byte(tmds->i2c_bus,
2519                                     tmds->slave_addr,
2520                                     0x0a, 0x90);
2521                 radeon_i2c_put_byte(tmds->i2c_bus,
2522                                     tmds->slave_addr,
2523                                     0x0c, 0x89);
2524                 radeon_i2c_put_byte(tmds->i2c_bus,
2525                                        tmds->slave_addr,
2526                                        0x08, 0x3b);
2527                 break;
2528         case DVO_SIL1178:
2529                 /* sil 1178 - untested */
2530                 /*
2531                  * 0x0f, 0x44
2532                  * 0x0f, 0x4c
2533                  * 0x0e, 0x01
2534                  * 0x0a, 0x80
2535                  * 0x09, 0x30
2536                  * 0x0c, 0xc9
2537                  * 0x0d, 0x70
2538                  * 0x08, 0x32
2539                  * 0x08, 0x33
2540                  */
2541                 break;
2542         default:
2543                 break;
2544         }
2545
2546 }
2547
2548 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2549 {
2550         struct drm_device *dev = encoder->dev;
2551         struct radeon_device *rdev = dev->dev_private;
2552         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2553         uint16_t offset;
2554         uint8_t blocks, slave_addr, rev;
2555         uint32_t index, id;
2556         uint32_t reg, val, and_mask, or_mask;
2557         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2558
2559         if (!tmds)
2560                 return false;
2561
2562         if (rdev->flags & RADEON_IS_IGP) {
2563                 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2564                 rev = RBIOS8(offset);
2565                 if (offset) {
2566                         rev = RBIOS8(offset);
2567                         if (rev > 1) {
2568                                 blocks = RBIOS8(offset + 3);
2569                                 index = offset + 4;
2570                                 while (blocks > 0) {
2571                                         id = RBIOS16(index);
2572                                         index += 2;
2573                                         switch (id >> 13) {
2574                                         case 0:
2575                                                 reg = (id & 0x1fff) * 4;
2576                                                 val = RBIOS32(index);
2577                                                 index += 4;
2578                                                 WREG32(reg, val);
2579                                                 break;
2580                                         case 2:
2581                                                 reg = (id & 0x1fff) * 4;
2582                                                 and_mask = RBIOS32(index);
2583                                                 index += 4;
2584                                                 or_mask = RBIOS32(index);
2585                                                 index += 4;
2586                                                 val = RREG32(reg);
2587                                                 val = (val & and_mask) | or_mask;
2588                                                 WREG32(reg, val);
2589                                                 break;
2590                                         case 3:
2591                                                 val = RBIOS16(index);
2592                                                 index += 2;
2593                                                 udelay(val);
2594                                                 break;
2595                                         case 4:
2596                                                 val = RBIOS16(index);
2597                                                 index += 2;
2598                                                 udelay(val * 1000);
2599                                                 break;
2600                                         case 6:
2601                                                 slave_addr = id & 0xff;
2602                                                 slave_addr >>= 1; /* 7 bit addressing */
2603                                                 index++;
2604                                                 reg = RBIOS8(index);
2605                                                 index++;
2606                                                 val = RBIOS8(index);
2607                                                 index++;
2608                                                 radeon_i2c_put_byte(tmds->i2c_bus,
2609                                                                     slave_addr,
2610                                                                     reg, val);
2611                                                 break;
2612                                         default:
2613                                                 DRM_ERROR("Unknown id %d\n", id >> 13);
2614                                                 break;
2615                                         }
2616                                         blocks--;
2617                                 }
2618                                 return true;
2619                         }
2620                 }
2621         } else {
2622                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2623                 if (offset) {
2624                         index = offset + 10;
2625                         id = RBIOS16(index);
2626                         while (id != 0xffff) {
2627                                 index += 2;
2628                                 switch (id >> 13) {
2629                                 case 0:
2630                                         reg = (id & 0x1fff) * 4;
2631                                         val = RBIOS32(index);
2632                                         WREG32(reg, val);
2633                                         break;
2634                                 case 2:
2635                                         reg = (id & 0x1fff) * 4;
2636                                         and_mask = RBIOS32(index);
2637                                         index += 4;
2638                                         or_mask = RBIOS32(index);
2639                                         index += 4;
2640                                         val = RREG32(reg);
2641                                         val = (val & and_mask) | or_mask;
2642                                         WREG32(reg, val);
2643                                         break;
2644                                 case 4:
2645                                         val = RBIOS16(index);
2646                                         index += 2;
2647                                         udelay(val);
2648                                         break;
2649                                 case 5:
2650                                         reg = id & 0x1fff;
2651                                         and_mask = RBIOS32(index);
2652                                         index += 4;
2653                                         or_mask = RBIOS32(index);
2654                                         index += 4;
2655                                         val = RREG32_PLL(reg);
2656                                         val = (val & and_mask) | or_mask;
2657                                         WREG32_PLL(reg, val);
2658                                         break;
2659                                 case 6:
2660                                         reg = id & 0x1fff;
2661                                         val = RBIOS8(index);
2662                                         index += 1;
2663                                         radeon_i2c_put_byte(tmds->i2c_bus,
2664                                                             tmds->slave_addr,
2665                                                             reg, val);
2666                                         break;
2667                                 default:
2668                                         DRM_ERROR("Unknown id %d\n", id >> 13);
2669                                         break;
2670                                 }
2671                                 id = RBIOS16(index);
2672                         }
2673                         return true;
2674                 }
2675         }
2676         return false;
2677 }
2678
2679 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2680 {
2681         struct radeon_device *rdev = dev->dev_private;
2682
2683         if (offset) {
2684                 while (RBIOS16(offset)) {
2685                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2686                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
2687                         uint32_t val, and_mask, or_mask;
2688                         uint32_t tmp;
2689
2690                         offset += 2;
2691                         switch (cmd) {
2692                         case 0:
2693                                 val = RBIOS32(offset);
2694                                 offset += 4;
2695                                 WREG32(addr, val);
2696                                 break;
2697                         case 1:
2698                                 val = RBIOS32(offset);
2699                                 offset += 4;
2700                                 WREG32(addr, val);
2701                                 break;
2702                         case 2:
2703                                 and_mask = RBIOS32(offset);
2704                                 offset += 4;
2705                                 or_mask = RBIOS32(offset);
2706                                 offset += 4;
2707                                 tmp = RREG32(addr);
2708                                 tmp &= and_mask;
2709                                 tmp |= or_mask;
2710                                 WREG32(addr, tmp);
2711                                 break;
2712                         case 3:
2713                                 and_mask = RBIOS32(offset);
2714                                 offset += 4;
2715                                 or_mask = RBIOS32(offset);
2716                                 offset += 4;
2717                                 tmp = RREG32(addr);
2718                                 tmp &= and_mask;
2719                                 tmp |= or_mask;
2720                                 WREG32(addr, tmp);
2721                                 break;
2722                         case 4:
2723                                 val = RBIOS16(offset);
2724                                 offset += 2;
2725                                 udelay(val);
2726                                 break;
2727                         case 5:
2728                                 val = RBIOS16(offset);
2729                                 offset += 2;
2730                                 switch (addr) {
2731                                 case 8:
2732                                         while (val--) {
2733                                                 if (!
2734                                                     (RREG32_PLL
2735                                                      (RADEON_CLK_PWRMGT_CNTL) &
2736                                                      RADEON_MC_BUSY))
2737                                                         break;
2738                                         }
2739                                         break;
2740                                 case 9:
2741                                         while (val--) {
2742                                                 if ((RREG32(RADEON_MC_STATUS) &
2743                                                      RADEON_MC_IDLE))
2744                                                         break;
2745                                         }
2746                                         break;
2747                                 default:
2748                                         break;
2749                                 }
2750                                 break;
2751                         default:
2752                                 break;
2753                         }
2754                 }
2755         }
2756 }
2757
2758 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2759 {
2760         struct radeon_device *rdev = dev->dev_private;
2761
2762         if (offset) {
2763                 while (RBIOS8(offset)) {
2764                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2765                         uint8_t addr = (RBIOS8(offset) & 0x3f);
2766                         uint32_t val, shift, tmp;
2767                         uint32_t and_mask, or_mask;
2768
2769                         offset++;
2770                         switch (cmd) {
2771                         case 0:
2772                                 val = RBIOS32(offset);
2773                                 offset += 4;
2774                                 WREG32_PLL(addr, val);
2775                                 break;
2776                         case 1:
2777                                 shift = RBIOS8(offset) * 8;
2778                                 offset++;
2779                                 and_mask = RBIOS8(offset) << shift;
2780                                 and_mask |= ~(0xff << shift);
2781                                 offset++;
2782                                 or_mask = RBIOS8(offset) << shift;
2783                                 offset++;
2784                                 tmp = RREG32_PLL(addr);
2785                                 tmp &= and_mask;
2786                                 tmp |= or_mask;
2787                                 WREG32_PLL(addr, tmp);
2788                                 break;
2789                         case 2:
2790                         case 3:
2791                                 tmp = 1000;
2792                                 switch (addr) {
2793                                 case 1:
2794                                         udelay(150);
2795                                         break;
2796                                 case 2:
2797                                         udelay(1000);
2798                                         break;
2799                                 case 3:
2800                                         while (tmp--) {
2801                                                 if (!
2802                                                     (RREG32_PLL
2803                                                      (RADEON_CLK_PWRMGT_CNTL) &
2804                                                      RADEON_MC_BUSY))
2805                                                         break;
2806                                         }
2807                                         break;
2808                                 case 4:
2809                                         while (tmp--) {
2810                                                 if (RREG32_PLL
2811                                                     (RADEON_CLK_PWRMGT_CNTL) &
2812                                                     RADEON_DLL_READY)
2813                                                         break;
2814                                         }
2815                                         break;
2816                                 case 5:
2817                                         tmp =
2818                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2819                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
2820 #if 0
2821                                                 uint32_t mclk_cntl =
2822                                                     RREG32_PLL
2823                                                     (RADEON_MCLK_CNTL);
2824                                                 mclk_cntl &= 0xffff0000;
2825                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
2826                                                 WREG32_PLL(RADEON_MCLK_CNTL,
2827                                                            mclk_cntl);
2828                                                 udelay(10000);
2829 #endif
2830                                                 WREG32_PLL
2831                                                     (RADEON_CLK_PWRMGT_CNTL,
2832                                                      tmp &
2833                                                      ~RADEON_CG_NO1_DEBUG_0);
2834                                                 udelay(10000);
2835                                         }
2836                                         break;
2837                                 default:
2838                                         break;
2839                                 }
2840                                 break;
2841                         default:
2842                                 break;
2843                         }
2844                 }
2845         }
2846 }
2847
2848 static void combios_parse_ram_reset_table(struct drm_device *dev,
2849                                           uint16_t offset)
2850 {
2851         struct radeon_device *rdev = dev->dev_private;
2852         uint32_t tmp;
2853
2854         if (offset) {
2855                 uint8_t val = RBIOS8(offset);
2856                 while (val != 0xff) {
2857                         offset++;
2858
2859                         if (val == 0x0f) {
2860                                 uint32_t channel_complete_mask;
2861
2862                                 if (ASIC_IS_R300(rdev))
2863                                         channel_complete_mask =
2864                                             R300_MEM_PWRUP_COMPLETE;
2865                                 else
2866                                         channel_complete_mask =
2867                                             RADEON_MEM_PWRUP_COMPLETE;
2868                                 tmp = 20000;
2869                                 while (tmp--) {
2870                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
2871                                              channel_complete_mask) ==
2872                                             channel_complete_mask)
2873                                                 break;
2874                                 }
2875                         } else {
2876                                 uint32_t or_mask = RBIOS16(offset);
2877                                 offset += 2;
2878
2879                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2880                                 tmp &= RADEON_SDRAM_MODE_MASK;
2881                                 tmp |= or_mask;
2882                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2883
2884                                 or_mask = val << 24;
2885                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2886                                 tmp &= RADEON_B3MEM_RESET_MASK;
2887                                 tmp |= or_mask;
2888                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2889                         }
2890                         val = RBIOS8(offset);
2891                 }
2892         }
2893 }
2894
2895 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2896                                    int mem_addr_mapping)
2897 {
2898         struct radeon_device *rdev = dev->dev_private;
2899         uint32_t mem_cntl;
2900         uint32_t mem_size;
2901         uint32_t addr = 0;
2902
2903         mem_cntl = RREG32(RADEON_MEM_CNTL);
2904         if (mem_cntl & RV100_HALF_MODE)
2905                 ram /= 2;
2906         mem_size = ram;
2907         mem_cntl &= ~(0xff << 8);
2908         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2909         WREG32(RADEON_MEM_CNTL, mem_cntl);
2910         RREG32(RADEON_MEM_CNTL);
2911
2912         /* sdram reset ? */
2913
2914         /* something like this????  */
2915         while (ram--) {
2916                 addr = ram * 1024 * 1024;
2917                 /* write to each page */
2918                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2919                 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2920                 /* read back and verify */
2921                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2922                 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2923                         return 0;
2924         }
2925
2926         return mem_size;
2927 }
2928
2929 static void combios_write_ram_size(struct drm_device *dev)
2930 {
2931         struct radeon_device *rdev = dev->dev_private;
2932         uint8_t rev;
2933         uint16_t offset;
2934         uint32_t mem_size = 0;
2935         uint32_t mem_cntl = 0;
2936
2937         /* should do something smarter here I guess... */
2938         if (rdev->flags & RADEON_IS_IGP)
2939                 return;
2940
2941         /* first check detected mem table */
2942         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2943         if (offset) {
2944                 rev = RBIOS8(offset);
2945                 if (rev < 3) {
2946                         mem_cntl = RBIOS32(offset + 1);
2947                         mem_size = RBIOS16(offset + 5);
2948                         if ((rdev->family < CHIP_R200) &&
2949                             !ASIC_IS_RN50(rdev))
2950                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
2951                 }
2952         }
2953
2954         if (!mem_size) {
2955                 offset =
2956                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2957                 if (offset) {
2958                         rev = RBIOS8(offset - 1);
2959                         if (rev < 1) {
2960                                 if ((rdev->family < CHIP_R200)
2961                                     && !ASIC_IS_RN50(rdev)) {
2962                                         int ram = 0;
2963                                         int mem_addr_mapping = 0;
2964
2965                                         while (RBIOS8(offset)) {
2966                                                 ram = RBIOS8(offset);
2967                                                 mem_addr_mapping =
2968                                                     RBIOS8(offset + 1);
2969                                                 if (mem_addr_mapping != 0x25)
2970                                                         ram *= 2;
2971                                                 mem_size =
2972                                                     combios_detect_ram(dev, ram,
2973                                                                        mem_addr_mapping);
2974                                                 if (mem_size)
2975                                                         break;
2976                                                 offset += 2;
2977                                         }
2978                                 } else
2979                                         mem_size = RBIOS8(offset);
2980                         } else {
2981                                 mem_size = RBIOS8(offset);
2982                                 mem_size *= 2;  /* convert to MB */
2983                         }
2984                 }
2985         }
2986
2987         mem_size *= (1024 * 1024);      /* convert to bytes */
2988         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2989 }
2990
2991 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2992 {
2993         uint16_t dyn_clk_info =
2994             combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2995
2996         if (dyn_clk_info)
2997                 combios_parse_pll_table(dev, dyn_clk_info);
2998 }
2999
3000 void radeon_combios_asic_init(struct drm_device *dev)
3001 {
3002         struct radeon_device *rdev = dev->dev_private;
3003         uint16_t table;
3004
3005         /* port hardcoded mac stuff from radeonfb */
3006         if (rdev->bios == NULL)
3007                 return;
3008
3009         /* ASIC INIT 1 */
3010         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3011         if (table)
3012                 combios_parse_mmio_table(dev, table);
3013
3014         /* PLL INIT */
3015         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3016         if (table)
3017                 combios_parse_pll_table(dev, table);
3018
3019         /* ASIC INIT 2 */
3020         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3021         if (table)
3022                 combios_parse_mmio_table(dev, table);
3023
3024         if (!(rdev->flags & RADEON_IS_IGP)) {
3025                 /* ASIC INIT 4 */
3026                 table =
3027                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3028                 if (table)
3029                         combios_parse_mmio_table(dev, table);
3030
3031                 /* RAM RESET */
3032                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3033                 if (table)
3034                         combios_parse_ram_reset_table(dev, table);
3035
3036                 /* ASIC INIT 3 */
3037                 table =
3038                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3039                 if (table)
3040                         combios_parse_mmio_table(dev, table);
3041
3042                 /* write CONFIG_MEMSIZE */
3043                 combios_write_ram_size(dev);
3044         }
3045
3046         /* quirk for rs4xx HP nx6125 laptop to make it resume
3047          * - it hangs on resume inside the dynclk 1 table.
3048          */
3049         if (rdev->family == CHIP_RS480 &&
3050             rdev->pdev->subsystem_vendor == 0x103c &&
3051             rdev->pdev->subsystem_device == 0x308b)
3052                 return;
3053
3054         /* quirk for rs4xx HP dv5000 laptop to make it resume
3055          * - it hangs on resume inside the dynclk 1 table.
3056          */
3057         if (rdev->family == CHIP_RS480 &&
3058             rdev->pdev->subsystem_vendor == 0x103c &&
3059             rdev->pdev->subsystem_device == 0x30a4)
3060                 return;
3061
3062         /* DYN CLK 1 */
3063         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3064         if (table)
3065                 combios_parse_pll_table(dev, table);
3066
3067 }
3068
3069 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3070 {
3071         struct radeon_device *rdev = dev->dev_private;
3072         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3073
3074         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3075         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3076         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3077
3078         /* let the bios control the backlight */
3079         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3080
3081         /* tell the bios not to handle mode switching */
3082         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3083                            RADEON_ACC_MODE_CHANGE);
3084
3085         /* tell the bios a driver is loaded */
3086         bios_7_scratch |= RADEON_DRV_LOADED;
3087
3088         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3089         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3090         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3091 }
3092
3093 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3094 {
3095         struct drm_device *dev = encoder->dev;
3096         struct radeon_device *rdev = dev->dev_private;
3097         uint32_t bios_6_scratch;
3098
3099         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3100
3101         if (lock)
3102                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3103         else
3104                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3105
3106         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3107 }
3108
3109 void
3110 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3111                                       struct drm_encoder *encoder,
3112                                       bool connected)
3113 {
3114         struct drm_device *dev = connector->dev;
3115         struct radeon_device *rdev = dev->dev_private;
3116         struct radeon_connector *radeon_connector =
3117             to_radeon_connector(connector);
3118         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3119         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3120         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3121
3122         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3123             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3124                 if (connected) {
3125                         DRM_DEBUG_KMS("TV1 connected\n");
3126                         /* fix me */
3127                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3128                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3129                         bios_5_scratch |= RADEON_TV1_ON;
3130                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
3131                 } else {
3132                         DRM_DEBUG_KMS("TV1 disconnected\n");
3133                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3134                         bios_5_scratch &= ~RADEON_TV1_ON;
3135                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3136                 }
3137         }
3138         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3139             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3140                 if (connected) {
3141                         DRM_DEBUG_KMS("LCD1 connected\n");
3142                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
3143                         bios_5_scratch |= RADEON_LCD1_ON;
3144                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3145                 } else {
3146                         DRM_DEBUG_KMS("LCD1 disconnected\n");
3147                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3148                         bios_5_scratch &= ~RADEON_LCD1_ON;
3149                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3150                 }
3151         }
3152         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3153             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3154                 if (connected) {
3155                         DRM_DEBUG_KMS("CRT1 connected\n");
3156                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3157                         bios_5_scratch |= RADEON_CRT1_ON;
3158                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3159                 } else {
3160                         DRM_DEBUG_KMS("CRT1 disconnected\n");
3161                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3162                         bios_5_scratch &= ~RADEON_CRT1_ON;
3163                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3164                 }
3165         }
3166         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3167             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3168                 if (connected) {
3169                         DRM_DEBUG_KMS("CRT2 connected\n");
3170                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3171                         bios_5_scratch |= RADEON_CRT2_ON;
3172                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3173                 } else {
3174                         DRM_DEBUG_KMS("CRT2 disconnected\n");
3175                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3176                         bios_5_scratch &= ~RADEON_CRT2_ON;
3177                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3178                 }
3179         }
3180         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3181             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3182                 if (connected) {
3183                         DRM_DEBUG_KMS("DFP1 connected\n");
3184                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
3185                         bios_5_scratch |= RADEON_DFP1_ON;
3186                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3187                 } else {
3188                         DRM_DEBUG_KMS("DFP1 disconnected\n");
3189                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3190                         bios_5_scratch &= ~RADEON_DFP1_ON;
3191                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3192                 }
3193         }
3194         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3195             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3196                 if (connected) {
3197                         DRM_DEBUG_KMS("DFP2 connected\n");
3198                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
3199                         bios_5_scratch |= RADEON_DFP2_ON;
3200                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3201                 } else {
3202                         DRM_DEBUG_KMS("DFP2 disconnected\n");
3203                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3204                         bios_5_scratch &= ~RADEON_DFP2_ON;
3205                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3206                 }
3207         }
3208         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3209         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3210 }
3211
3212 void
3213 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3214 {
3215         struct drm_device *dev = encoder->dev;
3216         struct radeon_device *rdev = dev->dev_private;
3217         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3218         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3219
3220         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3221                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3222                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3223         }
3224         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3225                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3226                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3227         }
3228         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3229                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3230                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3231         }
3232         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3233                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3234                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3235         }
3236         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3237                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3238                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3239         }
3240         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3241                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3242                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3243         }
3244         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3245 }
3246
3247 void
3248 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3249 {
3250         struct drm_device *dev = encoder->dev;
3251         struct radeon_device *rdev = dev->dev_private;
3252         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3253         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3254
3255         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3256                 if (on)
3257                         bios_6_scratch |= RADEON_TV_DPMS_ON;
3258                 else
3259                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3260         }
3261         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3262                 if (on)
3263                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
3264                 else
3265                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3266         }
3267         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3268                 if (on)
3269                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
3270                 else
3271                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3272         }
3273         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3274                 if (on)
3275                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
3276                 else
3277                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3278         }
3279         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3280 }