Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_encoder.c */
  41 extern uint32_t
  42 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  43                       uint8_t dac);
  44 extern void radeon_link_encoder_connector(struct drm_device *dev);
  45
  46 /* from radeon_connector.c */
  47 extern void
  48 radeon_add_legacy_connector(struct drm_device *dev,
  49                             uint32_t connector_id,
  50                             uint32_t supported_device,
  51                             int connector_type,
  52                             struct radeon_i2c_bus_rec *i2c_bus,
  53                             uint16_t connector_object_id,
  54                             struct radeon_hpd *hpd);
  55
  56 /* from radeon_legacy_encoder.c */
  57 extern void
  58 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  59                           uint32_t supported_device);
  60
  61 /* old legacy ATI BIOS routines */
  62
  63 /* COMBIOS table offsets */
  64 enum radeon_combios_table_offset {
  65         /* absolute offset tables */
  66         COMBIOS_ASIC_INIT_1_TABLE,
  67         COMBIOS_BIOS_SUPPORT_TABLE,
  68         COMBIOS_DAC_PROGRAMMING_TABLE,
  69         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  70         COMBIOS_CRTC_INFO_TABLE,
  71         COMBIOS_PLL_INFO_TABLE,
  72         COMBIOS_TV_INFO_TABLE,
  73         COMBIOS_DFP_INFO_TABLE,
  74         COMBIOS_HW_CONFIG_INFO_TABLE,
  75         COMBIOS_MULTIMEDIA_INFO_TABLE,
  76         COMBIOS_TV_STD_PATCH_TABLE,
  77         COMBIOS_LCD_INFO_TABLE,
  78         COMBIOS_MOBILE_INFO_TABLE,
  79         COMBIOS_PLL_INIT_TABLE,
  80         COMBIOS_MEM_CONFIG_TABLE,
  81         COMBIOS_SAVE_MASK_TABLE,
  82         COMBIOS_HARDCODED_EDID_TABLE,
  83         COMBIOS_ASIC_INIT_2_TABLE,
  84         COMBIOS_CONNECTOR_INFO_TABLE,
  85         COMBIOS_DYN_CLK_1_TABLE,
  86         COMBIOS_RESERVED_MEM_TABLE,
  87         COMBIOS_EXT_TMDS_INFO_TABLE,
  88         COMBIOS_MEM_CLK_INFO_TABLE,
  89         COMBIOS_EXT_DAC_INFO_TABLE,
  90         COMBIOS_MISC_INFO_TABLE,
  91         COMBIOS_CRT_INFO_TABLE,
  92         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  93         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  94         COMBIOS_FAN_SPEED_INFO_TABLE,
  95         COMBIOS_OVERDRIVE_INFO_TABLE,
  96         COMBIOS_OEM_INFO_TABLE,
  97         COMBIOS_DYN_CLK_2_TABLE,
  98         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  99         COMBIOS_I2C_INFO_TABLE,
 100         /* relative offset tables */
 101         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 102         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 103         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 104         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 105         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 106         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 107         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 108         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 109         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 110         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 111         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 112 };
 113
 114 enum radeon_combios_ddc {
 115         DDC_NONE_DETECTED,
 116         DDC_MONID,
 117         DDC_DVI,
 118         DDC_VGA,
 119         DDC_CRT2,
 120         DDC_LCD,
 121         DDC_GPIO,
 122 };
 123
 124 enum radeon_combios_connector {
 125         CONNECTOR_NONE_LEGACY,
 126         CONNECTOR_PROPRIETARY_LEGACY,
 127         CONNECTOR_CRT_LEGACY,
 128         CONNECTOR_DVI_I_LEGACY,
 129         CONNECTOR_DVI_D_LEGACY,
 130         CONNECTOR_CTV_LEGACY,
 131         CONNECTOR_STV_LEGACY,
 132         CONNECTOR_UNSUPPORTED_LEGACY
 133 };
 134
 135 const int legacy_connector_convert[] = {
 136         DRM_MODE_CONNECTOR_Unknown,
 137         DRM_MODE_CONNECTOR_DVID,
 138         DRM_MODE_CONNECTOR_VGA,
 139         DRM_MODE_CONNECTOR_DVII,
 140         DRM_MODE_CONNECTOR_DVID,
 141         DRM_MODE_CONNECTOR_Composite,
 142         DRM_MODE_CONNECTOR_SVIDEO,
 143         DRM_MODE_CONNECTOR_Unknown,
 144 };
 145
 146 static uint16_t combios_get_table_offset(struct drm_device *dev,
 147                                          enum radeon_combios_table_offset table)
 148 {
 149         struct radeon_device *rdev = dev->dev_private;
 150         int rev;
 151         uint16_t offset = 0, check_offset;
 152
 153         if (!rdev->bios)
 154                 return 0;
 155
 156         switch (table) {
 157                 /* absolute offset tables */
 158         case COMBIOS_ASIC_INIT_1_TABLE:
 159                 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
 160                 if (check_offset)
 161                         offset = check_offset;
 162                 break;
 163         case COMBIOS_BIOS_SUPPORT_TABLE:
 164                 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
 165                 if (check_offset)
 166                         offset = check_offset;
 167                 break;
 168         case COMBIOS_DAC_PROGRAMMING_TABLE:
 169                 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
 170                 if (check_offset)
 171                         offset = check_offset;
 172                 break;
 173         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 174                 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
 175                 if (check_offset)
 176                         offset = check_offset;
 177                 break;
 178         case COMBIOS_CRTC_INFO_TABLE:
 179                 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
 180                 if (check_offset)
 181                         offset = check_offset;
 182                 break;
 183         case COMBIOS_PLL_INFO_TABLE:
 184                 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
 185                 if (check_offset)
 186                         offset = check_offset;
 187                 break;
 188         case COMBIOS_TV_INFO_TABLE:
 189                 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
 190                 if (check_offset)
 191                         offset = check_offset;
 192                 break;
 193         case COMBIOS_DFP_INFO_TABLE:
 194                 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
 195                 if (check_offset)
 196                         offset = check_offset;
 197                 break;
 198         case COMBIOS_HW_CONFIG_INFO_TABLE:
 199                 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
 200                 if (check_offset)
 201                         offset = check_offset;
 202                 break;
 203         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 204                 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
 205                 if (check_offset)
 206                         offset = check_offset;
 207                 break;
 208         case COMBIOS_TV_STD_PATCH_TABLE:
 209                 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
 210                 if (check_offset)
 211                         offset = check_offset;
 212                 break;
 213         case COMBIOS_LCD_INFO_TABLE:
 214                 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
 215                 if (check_offset)
 216                         offset = check_offset;
 217                 break;
 218         case COMBIOS_MOBILE_INFO_TABLE:
 219                 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
 220                 if (check_offset)
 221                         offset = check_offset;
 222                 break;
 223         case COMBIOS_PLL_INIT_TABLE:
 224                 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
 225                 if (check_offset)
 226                         offset = check_offset;
 227                 break;
 228         case COMBIOS_MEM_CONFIG_TABLE:
 229                 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
 230                 if (check_offset)
 231                         offset = check_offset;
 232                 break;
 233         case COMBIOS_SAVE_MASK_TABLE:
 234                 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
 235                 if (check_offset)
 236                         offset = check_offset;
 237                 break;
 238         case COMBIOS_HARDCODED_EDID_TABLE:
 239                 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
 240                 if (check_offset)
 241                         offset = check_offset;
 242                 break;
 243         case COMBIOS_ASIC_INIT_2_TABLE:
 244                 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
 245                 if (check_offset)
 246                         offset = check_offset;
 247                 break;
 248         case COMBIOS_CONNECTOR_INFO_TABLE:
 249                 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
 250                 if (check_offset)
 251                         offset = check_offset;
 252                 break;
 253         case COMBIOS_DYN_CLK_1_TABLE:
 254                 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
 255                 if (check_offset)
 256                         offset = check_offset;
 257                 break;
 258         case COMBIOS_RESERVED_MEM_TABLE:
 259                 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
 260                 if (check_offset)
 261                         offset = check_offset;
 262                 break;
 263         case COMBIOS_EXT_TMDS_INFO_TABLE:
 264                 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
 265                 if (check_offset)
 266                         offset = check_offset;
 267                 break;
 268         case COMBIOS_MEM_CLK_INFO_TABLE:
 269                 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
 270                 if (check_offset)
 271                         offset = check_offset;
 272                 break;
 273         case COMBIOS_EXT_DAC_INFO_TABLE:
 274                 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
 275                 if (check_offset)
 276                         offset = check_offset;
 277                 break;
 278         case COMBIOS_MISC_INFO_TABLE:
 279                 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
 280                 if (check_offset)
 281                         offset = check_offset;
 282                 break;
 283         case COMBIOS_CRT_INFO_TABLE:
 284                 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
 285                 if (check_offset)
 286                         offset = check_offset;
 287                 break;
 288         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 289                 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
 290                 if (check_offset)
 291                         offset = check_offset;
 292                 break;
 293         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 294                 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
 295                 if (check_offset)
 296                         offset = check_offset;
 297                 break;
 298         case COMBIOS_FAN_SPEED_INFO_TABLE:
 299                 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
 300                 if (check_offset)
 301                         offset = check_offset;
 302                 break;
 303         case COMBIOS_OVERDRIVE_INFO_TABLE:
 304                 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
 305                 if (check_offset)
 306                         offset = check_offset;
 307                 break;
 308         case COMBIOS_OEM_INFO_TABLE:
 309                 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
 310                 if (check_offset)
 311                         offset = check_offset;
 312                 break;
 313         case COMBIOS_DYN_CLK_2_TABLE:
 314                 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
 315                 if (check_offset)
 316                         offset = check_offset;
 317                 break;
 318         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 319                 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
 320                 if (check_offset)
 321                         offset = check_offset;
 322                 break;
 323         case COMBIOS_I2C_INFO_TABLE:
 324                 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
 325                 if (check_offset)
 326                         offset = check_offset;
 327                 break;
 328                 /* relative offset tables */
 329         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 330                 check_offset =
 331                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 332                 if (check_offset) {
 333                         rev = RBIOS8(check_offset);
 334                         if (rev > 0) {
 335                                 check_offset = RBIOS16(check_offset + 0x3);
 336                                 if (check_offset)
 337                                         offset = check_offset;
 338                         }
 339                 }
 340                 break;
 341         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 342                 check_offset =
 343                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 344                 if (check_offset) {
 345                         rev = RBIOS8(check_offset);
 346                         if (rev > 0) {
 347                                 check_offset = RBIOS16(check_offset + 0x5);
 348                                 if (check_offset)
 349                                         offset = check_offset;
 350                         }
 351                 }
 352                 break;
 353         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 354                 check_offset =
 355                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 356                 if (check_offset) {
 357                         rev = RBIOS8(check_offset);
 358                         if (rev > 0) {
 359                                 check_offset = RBIOS16(check_offset + 0x7);
 360                                 if (check_offset)
 361                                         offset = check_offset;
 362                         }
 363                 }
 364                 break;
 365         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 366                 check_offset =
 367                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 368                 if (check_offset) {
 369                         rev = RBIOS8(check_offset);
 370                         if (rev == 2) {
 371                                 check_offset = RBIOS16(check_offset + 0x9);
 372                                 if (check_offset)
 373                                         offset = check_offset;
 374                         }
 375                 }
 376                 break;
 377         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 378                 check_offset =
 379                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 380                 if (check_offset) {
 381                         while (RBIOS8(check_offset++));
 382                         check_offset += 2;
 383                         if (check_offset)
 384                                 offset = check_offset;
 385                 }
 386                 break;
 387         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 388                 check_offset =
 389                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 390                 if (check_offset) {
 391                         check_offset = RBIOS16(check_offset + 0x11);
 392                         if (check_offset)
 393                                 offset = check_offset;
 394                 }
 395                 break;
 396         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 397                 check_offset =
 398                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 399                 if (check_offset) {
 400                         check_offset = RBIOS16(check_offset + 0x13);
 401                         if (check_offset)
 402                                 offset = check_offset;
 403                 }
 404                 break;
 405         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 406                 check_offset =
 407                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 408                 if (check_offset) {
 409                         check_offset = RBIOS16(check_offset + 0x15);
 410                         if (check_offset)
 411                                 offset = check_offset;
 412                 }
 413                 break;
 414         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 415                 check_offset =
 416                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 417                 if (check_offset) {
 418                         check_offset = RBIOS16(check_offset + 0x17);
 419                         if (check_offset)
 420                                 offset = check_offset;
 421                 }
 422                 break;
 423         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 424                 check_offset =
 425                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 426                 if (check_offset) {
 427                         check_offset = RBIOS16(check_offset + 0x2);
 428                         if (check_offset)
 429                                 offset = check_offset;
 430                 }
 431                 break;
 432         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 433                 check_offset =
 434                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 435                 if (check_offset) {
 436                         check_offset = RBIOS16(check_offset + 0x4);
 437                         if (check_offset)
 438                                 offset = check_offset;
 439                 }
 440                 break;
 441         default:
 442                 break;
 443         }
 444
 445         return offset;
 446
 447 }
 448
 449 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
 450 {
 451         int edid_info;
 452         struct edid *edid;
 453         edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
 454         if (!edid_info)
 455                 return false;
 456
 457         edid = kmalloc(EDID_LENGTH * (DRM_MAX_EDID_EXT_NUM + 1),
 458                        GFP_KERNEL);
 459         if (edid == NULL)
 460                 return false;
 461
 462         memcpy((unsigned char *)edid,
 463                (unsigned char *)(rdev->bios + edid_info), EDID_LENGTH);
 464
 465         if (!drm_edid_is_valid(edid)) {
 466                 kfree(edid);
 467                 return false;
 468         }
 469
 470         rdev->mode_info.bios_hardcoded_edid = edid;
 471         return true;
 472 }
 473
 474 struct edid *
 475 radeon_combios_get_hardcoded_edid(struct radeon_device *rdev)
 476 {
 477         if (rdev->mode_info.bios_hardcoded_edid)
 478                 return rdev->mode_info.bios_hardcoded_edid;
 479         return NULL;
 480 }
 481
 482 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
 483                                                        int ddc_line)
 484 {
 485         struct radeon_i2c_bus_rec i2c;
 486
 487         if (ddc_line == RADEON_GPIOPAD_MASK) {
 488                 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
 489                 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
 490                 i2c.a_clk_reg = RADEON_GPIOPAD_A;
 491                 i2c.a_data_reg = RADEON_GPIOPAD_A;
 492                 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
 493                 i2c.en_data_reg = RADEON_GPIOPAD_EN;
 494                 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
 495                 i2c.y_data_reg = RADEON_GPIOPAD_Y;
 496         } else if (ddc_line == RADEON_MDGPIO_MASK) {
 497                 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
 498                 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
 499                 i2c.a_clk_reg = RADEON_MDGPIO_A;
 500                 i2c.a_data_reg = RADEON_MDGPIO_A;
 501                 i2c.en_clk_reg = RADEON_MDGPIO_EN;
 502                 i2c.en_data_reg = RADEON_MDGPIO_EN;
 503                 i2c.y_clk_reg = RADEON_MDGPIO_Y;
 504                 i2c.y_data_reg = RADEON_MDGPIO_Y;
 505         } else {
 506                 i2c.mask_clk_mask = RADEON_GPIO_EN_1;
 507                 i2c.mask_data_mask = RADEON_GPIO_EN_0;
 508                 i2c.a_clk_mask = RADEON_GPIO_A_1;
 509                 i2c.a_data_mask = RADEON_GPIO_A_0;
 510                 i2c.en_clk_mask = RADEON_GPIO_EN_1;
 511                 i2c.en_data_mask = RADEON_GPIO_EN_0;
 512                 i2c.y_clk_mask = RADEON_GPIO_Y_1;
 513                 i2c.y_data_mask = RADEON_GPIO_Y_0;
 514
 515                 i2c.mask_clk_reg = ddc_line;
 516                 i2c.mask_data_reg = ddc_line;
 517                 i2c.a_clk_reg = ddc_line;
 518                 i2c.a_data_reg = ddc_line;
 519                 i2c.en_clk_reg = ddc_line;
 520                 i2c.en_data_reg = ddc_line;
 521                 i2c.y_clk_reg = ddc_line;
 522                 i2c.y_data_reg = ddc_line;
 523         }
 524
 525         switch (rdev->family) {
 526         case CHIP_R100:
 527         case CHIP_RV100:
 528         case CHIP_RS100:
 529         case CHIP_RV200:
 530         case CHIP_RS200:
 531         case CHIP_RS300:
 532                 switch (ddc_line) {
 533                 case RADEON_GPIO_DVI_DDC:
 534                         /* in theory this should be hw capable,
 535                          * but it doesn't seem to work
 536                          */
 537                         i2c.hw_capable = false;
 538                         break;
 539                 default:
 540                         i2c.hw_capable = false;
 541                         break;
 542                 }
 543                 break;
 544         case CHIP_R200:
 545                 switch (ddc_line) {
 546                 case RADEON_GPIO_DVI_DDC:
 547                 case RADEON_GPIO_MONID:
 548                         i2c.hw_capable = true;
 549                         break;
 550                 default:
 551                         i2c.hw_capable = false;
 552                         break;
 553                 }
 554                 break;
 555         case CHIP_RV250:
 556         case CHIP_RV280:
 557                 switch (ddc_line) {
 558                 case RADEON_GPIO_VGA_DDC:
 559                 case RADEON_GPIO_DVI_DDC:
 560                 case RADEON_GPIO_CRT2_DDC:
 561                         i2c.hw_capable = true;
 562                         break;
 563                 default:
 564                         i2c.hw_capable = false;
 565                         break;
 566                 }
 567                 break;
 568         case CHIP_R300:
 569         case CHIP_R350:
 570                 switch (ddc_line) {
 571                 case RADEON_GPIO_VGA_DDC:
 572                 case RADEON_GPIO_DVI_DDC:
 573                         i2c.hw_capable = true;
 574                         break;
 575                 default:
 576                         i2c.hw_capable = false;
 577                         break;
 578                 }
 579                 break;
 580         case CHIP_RV350:
 581         case CHIP_RV380:
 582         case CHIP_RS400:
 583         case CHIP_RS480:
 584                 switch (ddc_line) {
 585                 case RADEON_GPIO_VGA_DDC:
 586                 case RADEON_GPIO_DVI_DDC:
 587                         i2c.hw_capable = true;
 588                         break;
 589                 case RADEON_GPIO_MONID:
 590                         /* hw i2c on RADEON_GPIO_MONID doesn't seem to work
 591                          * reliably on some pre-r4xx hardware; not sure why.
 592                          */
 593                         i2c.hw_capable = false;
 594                         break;
 595                 default:
 596                         i2c.hw_capable = false;
 597                         break;
 598                 }
 599                 break;
 600         default:
 601                 i2c.hw_capable = false;
 602                 break;
 603         }
 604         i2c.mm_i2c = false;
 605         i2c.i2c_id = 0;
 606         i2c.hpd_id = 0;
 607
 608         if (ddc_line)
 609                 i2c.valid = true;
 610         else
 611                 i2c.valid = false;
 612
 613         return i2c;
 614 }
 615
 616 bool radeon_combios_get_clock_info(struct drm_device *dev)
 617 {
 618         struct radeon_device *rdev = dev->dev_private;
 619         uint16_t pll_info;
 620         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 621         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 622         struct radeon_pll *spll = &rdev->clock.spll;
 623         struct radeon_pll *mpll = &rdev->clock.mpll;
 624         int8_t rev;
 625         uint16_t sclk, mclk;
 626
 627         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 628         if (pll_info) {
 629                 rev = RBIOS8(pll_info);
 630
 631                 /* pixel clocks */
 632                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 633                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 634                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 635                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 636
 637                 if (rev > 9) {
 638                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 639                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 640                 } else {
 641                         p1pll->pll_in_min = 40;
 642                         p1pll->pll_in_max = 500;
 643                 }
 644                 *p2pll = *p1pll;
 645
 646                 /* system clock */
 647                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 648                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 649                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 650                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 651
 652                 if (rev > 10) {
 653                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 654                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 655                 } else {
 656                         /* ??? */
 657                         spll->pll_in_min = 40;
 658                         spll->pll_in_max = 500;
 659                 }
 660
 661                 /* memory clock */
 662                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 663                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 664                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 665                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 666
 667                 if (rev > 10) {
 668                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 669                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 670                 } else {
 671                         /* ??? */
 672                         mpll->pll_in_min = 40;
 673                         mpll->pll_in_max = 500;
 674                 }
 675
 676                 /* default sclk/mclk */
 677                 sclk = RBIOS16(pll_info + 0xa);
 678                 mclk = RBIOS16(pll_info + 0x8);
 679                 if (sclk == 0)
 680                         sclk = 200 * 100;
 681                 if (mclk == 0)
 682                         mclk = 200 * 100;
 683
 684                 rdev->clock.default_sclk = sclk;
 685                 rdev->clock.default_mclk = mclk;
 686
 687                 return true;
 688         }
 689         return false;
 690 }
 691
 692 bool radeon_combios_sideport_present(struct radeon_device *rdev)
 693 {
 694         struct drm_device *dev = rdev->ddev;
 695         u16 igp_info;
 696
 697         igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
 698
 699         if (igp_info) {
 700                 if (RBIOS16(igp_info + 0x4))
 701                         return true;
 702         }
 703         return false;
 704 }
 705
 706 static const uint32_t default_primarydac_adj[CHIP_LAST] = {
 707         0x00000808,             /* r100  */
 708         0x00000808,             /* rv100 */
 709         0x00000808,             /* rs100 */
 710         0x00000808,             /* rv200 */
 711         0x00000808,             /* rs200 */
 712         0x00000808,             /* r200  */
 713         0x00000808,             /* rv250 */
 714         0x00000000,             /* rs300 */
 715         0x00000808,             /* rv280 */
 716         0x00000808,             /* r300  */
 717         0x00000808,             /* r350  */
 718         0x00000808,             /* rv350 */
 719         0x00000808,             /* rv380 */
 720         0x00000808,             /* r420  */
 721         0x00000808,             /* r423  */
 722         0x00000808,             /* rv410 */
 723         0x00000000,             /* rs400 */
 724         0x00000000,             /* rs480 */
 725 };
 726
 727 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
 728                                                           struct radeon_encoder_primary_dac *p_dac)
 729 {
 730         p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
 731         return;
 732 }
 733
 734 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 735                                                                        radeon_encoder
 736                                                                        *encoder)
 737 {
 738         struct drm_device *dev = encoder->base.dev;
 739         struct radeon_device *rdev = dev->dev_private;
 740         uint16_t dac_info;
 741         uint8_t rev, bg, dac;
 742         struct radeon_encoder_primary_dac *p_dac = NULL;
 743         int found = 0;
 744
 745         p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
 746                         GFP_KERNEL);
 747
 748         if (!p_dac)
 749                 return NULL;
 750
 751         /* check CRT table */
 752         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 753         if (dac_info) {
 754                 rev = RBIOS8(dac_info) & 0x3;
 755                 if (rev < 2) {
 756                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 757                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 758                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 759                 } else {
 760                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 761                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 762                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 763                 }
 764                 found = 1;
 765         }
 766
 767         if (!found) /* fallback to defaults */
 768                 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
 769
 770         return p_dac;
 771 }
 772
 773 enum radeon_tv_std
 774 radeon_combios_get_tv_info(struct radeon_device *rdev)
 775 {
 776         struct drm_device *dev = rdev->ddev;
 777         uint16_t tv_info;
 778         enum radeon_tv_std tv_std = TV_STD_NTSC;
 779
 780         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 781         if (tv_info) {
 782                 if (RBIOS8(tv_info + 6) == 'T') {
 783                         switch (RBIOS8(tv_info + 7) & 0xf) {
 784                         case 1:
 785                                 tv_std = TV_STD_NTSC;
 786                                 DRM_INFO("Default TV standard: NTSC\n");
 787                                 break;
 788                         case 2:
 789                                 tv_std = TV_STD_PAL;
 790                                 DRM_INFO("Default TV standard: PAL\n");
 791                                 break;
 792                         case 3:
 793                                 tv_std = TV_STD_PAL_M;
 794                                 DRM_INFO("Default TV standard: PAL-M\n");
 795                                 break;
 796                         case 4:
 797                                 tv_std = TV_STD_PAL_60;
 798                                 DRM_INFO("Default TV standard: PAL-60\n");
 799                                 break;
 800                         case 5:
 801                                 tv_std = TV_STD_NTSC_J;
 802                                 DRM_INFO("Default TV standard: NTSC-J\n");
 803                                 break;
 804                         case 6:
 805                                 tv_std = TV_STD_SCART_PAL;
 806                                 DRM_INFO("Default TV standard: SCART-PAL\n");
 807                                 break;
 808                         default:
 809                                 tv_std = TV_STD_NTSC;
 810                                 DRM_INFO
 811                                     ("Unknown TV standard; defaulting to NTSC\n");
 812                                 break;
 813                         }
 814
 815                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
 816                         case 0:
 817                                 DRM_INFO("29.498928713 MHz TV ref clk\n");
 818                                 break;
 819                         case 1:
 820                                 DRM_INFO("28.636360000 MHz TV ref clk\n");
 821                                 break;
 822                         case 2:
 823                                 DRM_INFO("14.318180000 MHz TV ref clk\n");
 824                                 break;
 825                         case 3:
 826                                 DRM_INFO("27.000000000 MHz TV ref clk\n");
 827                                 break;
 828                         default:
 829                                 break;
 830                         }
 831                 }
 832         }
 833         return tv_std;
 834 }
 835
 836 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
 837         0x00000000,             /* r100  */
 838         0x00280000,             /* rv100 */
 839         0x00000000,             /* rs100 */
 840         0x00880000,             /* rv200 */
 841         0x00000000,             /* rs200 */
 842         0x00000000,             /* r200  */
 843         0x00770000,             /* rv250 */
 844         0x00290000,             /* rs300 */
 845         0x00560000,             /* rv280 */
 846         0x00780000,             /* r300  */
 847         0x00770000,             /* r350  */
 848         0x00780000,             /* rv350 */
 849         0x00780000,             /* rv380 */
 850         0x01080000,             /* r420  */
 851         0x01080000,             /* r423  */
 852         0x01080000,             /* rv410 */
 853         0x00780000,             /* rs400 */
 854         0x00780000,             /* rs480 */
 855 };
 856
 857 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
 858                                                      struct radeon_encoder_tv_dac *tv_dac)
 859 {
 860         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
 861         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
 862                 tv_dac->ps2_tvdac_adj = 0x00880000;
 863         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 864         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 865         return;
 866 }
 867
 868 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
 869                                                              radeon_encoder
 870                                                              *encoder)
 871 {
 872         struct drm_device *dev = encoder->base.dev;
 873         struct radeon_device *rdev = dev->dev_private;
 874         uint16_t dac_info;
 875         uint8_t rev, bg, dac;
 876         struct radeon_encoder_tv_dac *tv_dac = NULL;
 877         int found = 0;
 878
 879         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
 880         if (!tv_dac)
 881                 return NULL;
 882
 883         /* first check TV table */
 884         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 885         if (dac_info) {
 886                 rev = RBIOS8(dac_info + 0x3);
 887                 if (rev > 4) {
 888                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 889                         dac = RBIOS8(dac_info + 0xd) & 0xf;
 890                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 891
 892                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 893                         dac = RBIOS8(dac_info + 0xf) & 0xf;
 894                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 895
 896                         bg = RBIOS8(dac_info + 0x10) & 0xf;
 897                         dac = RBIOS8(dac_info + 0x11) & 0xf;
 898                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 899                         found = 1;
 900                 } else if (rev > 1) {
 901                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 902                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
 903                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 904
 905                         bg = RBIOS8(dac_info + 0xd) & 0xf;
 906                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
 907                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 908
 909                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 910                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
 911                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 912                         found = 1;
 913                 }
 914                 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
 915         }
 916         if (!found) {
 917                 /* then check CRT table */
 918                 dac_info =
 919                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 920                 if (dac_info) {
 921                         rev = RBIOS8(dac_info) & 0x3;
 922                         if (rev < 2) {
 923                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
 924                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
 925                                 tv_dac->ps2_tvdac_adj =
 926                                     (bg << 16) | (dac << 20);
 927                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 928                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 929                                 found = 1;
 930                         } else {
 931                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
 932                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
 933                                 tv_dac->ps2_tvdac_adj =
 934                                     (bg << 16) | (dac << 20);
 935                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 936                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 937                                 found = 1;
 938                         }
 939                 } else {
 940                         DRM_INFO("No TV DAC info found in BIOS\n");
 941                 }
 942         }
 943
 944         if (!found) /* fallback to defaults */
 945                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
 946
 947         return tv_dac;
 948 }
 949
 950 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
 951                                                                          radeon_device
 952                                                                          *rdev)
 953 {
 954         struct radeon_encoder_lvds *lvds = NULL;
 955         uint32_t fp_vert_stretch, fp_horz_stretch;
 956         uint32_t ppll_div_sel, ppll_val;
 957         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
 958
 959         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
 960
 961         if (!lvds)
 962                 return NULL;
 963
 964         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
 965         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
 966
 967         /* These should be fail-safe defaults, fingers crossed */
 968         lvds->panel_pwr_delay = 200;
 969         lvds->panel_vcc_delay = 2000;
 970
 971         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 972         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
 973         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
 974
 975         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
 976                 lvds->native_mode.vdisplay =
 977                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
 978                      RADEON_VERT_PANEL_SHIFT) + 1;
 979         else
 980                 lvds->native_mode.vdisplay =
 981                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
 982
 983         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
 984                 lvds->native_mode.hdisplay =
 985                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
 986                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
 987         else
 988                 lvds->native_mode.hdisplay =
 989                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
 990
 991         if ((lvds->native_mode.hdisplay < 640) ||
 992             (lvds->native_mode.vdisplay < 480)) {
 993                 lvds->native_mode.hdisplay = 640;
 994                 lvds->native_mode.vdisplay = 480;
 995         }
 996
 997         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
 998         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
 999         if ((ppll_val & 0x000707ff) == 0x1bb)
1000                 lvds->use_bios_dividers = false;
1001         else {
1002                 lvds->panel_ref_divider =
1003                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1004                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1005                 lvds->panel_fb_divider = ppll_val & 0x7ff;
1006
1007                 if ((lvds->panel_ref_divider != 0) &&
1008                     (lvds->panel_fb_divider > 3))
1009                         lvds->use_bios_dividers = true;
1010         }
1011         lvds->panel_vcc_delay = 200;
1012
1013         DRM_INFO("Panel info derived from registers\n");
1014         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1015                  lvds->native_mode.vdisplay);
1016
1017         return lvds;
1018 }
1019
1020 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1021                                                          *encoder)
1022 {
1023         struct drm_device *dev = encoder->base.dev;
1024         struct radeon_device *rdev = dev->dev_private;
1025         uint16_t lcd_info;
1026         uint32_t panel_setup;
1027         char stmp[30];
1028         int tmp, i;
1029         struct radeon_encoder_lvds *lvds = NULL;
1030
1031         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1032
1033         if (lcd_info) {
1034                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1035
1036                 if (!lvds)
1037                         return NULL;
1038
1039                 for (i = 0; i < 24; i++)
1040                         stmp[i] = RBIOS8(lcd_info + i + 1);
1041                 stmp[24] = 0;
1042
1043                 DRM_INFO("Panel ID String: %s\n", stmp);
1044
1045                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1046                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1047
1048                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1049                          lvds->native_mode.vdisplay);
1050
1051                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1052                 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1053
1054                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1055                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1056                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1057
1058                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1059                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1060                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1061                 if ((lvds->panel_ref_divider != 0) &&
1062                     (lvds->panel_fb_divider > 3))
1063                         lvds->use_bios_dividers = true;
1064
1065                 panel_setup = RBIOS32(lcd_info + 0x39);
1066                 lvds->lvds_gen_cntl = 0xff00;
1067                 if (panel_setup & 0x1)
1068                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1069
1070                 if ((panel_setup >> 4) & 0x1)
1071                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1072
1073                 switch ((panel_setup >> 8) & 0x7) {
1074                 case 0:
1075                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1076                         break;
1077                 case 1:
1078                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1079                         break;
1080                 case 2:
1081                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1082                         break;
1083                 default:
1084                         break;
1085                 }
1086
1087                 if ((panel_setup >> 16) & 0x1)
1088                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1089
1090                 if ((panel_setup >> 17) & 0x1)
1091                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1092
1093                 if ((panel_setup >> 18) & 0x1)
1094                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1095
1096                 if ((panel_setup >> 23) & 0x1)
1097                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1098
1099                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1100
1101                 for (i = 0; i < 32; i++) {
1102                         tmp = RBIOS16(lcd_info + 64 + i * 2);
1103                         if (tmp == 0)
1104                                 break;
1105
1106                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1107                             (RBIOS16(tmp + 2) ==
1108                              lvds->native_mode.vdisplay)) {
1109                                 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
1110                                 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
1111                                 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
1112                                                                RBIOS16(tmp + 21)) * 8;
1113
1114                                 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
1115                                 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
1116                                 lvds->native_mode.vsync_end =
1117                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
1118                                         (RBIOS16(tmp + 28) & 0x7ff);
1119
1120                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1121                                 lvds->native_mode.flags = 0;
1122                                 /* set crtc values */
1123                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1124
1125                         }
1126                 }
1127         } else {
1128                 DRM_INFO("No panel info found in BIOS\n");
1129                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1130         }
1131
1132         if (lvds)
1133                 encoder->native_mode = lvds->native_mode;
1134         return lvds;
1135 }
1136
1137 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1138         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
1139         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
1140         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
1141         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
1142         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
1143         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
1144         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
1145         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
1146         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
1147         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
1148         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
1149         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
1150         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
1151         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
1152         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
1153         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
1154         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS400 */
1155         { {0, 0}, {0, 0}, {0, 0}, {0, 0} },     /* CHIP_RS480 */
1156 };
1157
1158 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1159                                             struct radeon_encoder_int_tmds *tmds)
1160 {
1161         struct drm_device *dev = encoder->base.dev;
1162         struct radeon_device *rdev = dev->dev_private;
1163         int i;
1164
1165         for (i = 0; i < 4; i++) {
1166                 tmds->tmds_pll[i].value =
1167                         default_tmds_pll[rdev->family][i].value;
1168                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1169         }
1170
1171         return true;
1172 }
1173
1174 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1175                                               struct radeon_encoder_int_tmds *tmds)
1176 {
1177         struct drm_device *dev = encoder->base.dev;
1178         struct radeon_device *rdev = dev->dev_private;
1179         uint16_t tmds_info;
1180         int i, n;
1181         uint8_t ver;
1182
1183         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1184
1185         if (tmds_info) {
1186                 ver = RBIOS8(tmds_info);
1187                 DRM_INFO("DFP table revision: %d\n", ver);
1188                 if (ver == 3) {
1189                         n = RBIOS8(tmds_info + 5) + 1;
1190                         if (n > 4)
1191                                 n = 4;
1192                         for (i = 0; i < n; i++) {
1193                                 tmds->tmds_pll[i].value =
1194                                     RBIOS32(tmds_info + i * 10 + 0x08);
1195                                 tmds->tmds_pll[i].freq =
1196                                     RBIOS16(tmds_info + i * 10 + 0x10);
1197                                 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1198                                           tmds->tmds_pll[i].freq,
1199                                           tmds->tmds_pll[i].value);
1200                         }
1201                 } else if (ver == 4) {
1202                         int stride = 0;
1203                         n = RBIOS8(tmds_info + 5) + 1;
1204                         if (n > 4)
1205                                 n = 4;
1206                         for (i = 0; i < n; i++) {
1207                                 tmds->tmds_pll[i].value =
1208                                     RBIOS32(tmds_info + stride + 0x08);
1209                                 tmds->tmds_pll[i].freq =
1210                                     RBIOS16(tmds_info + stride + 0x10);
1211                                 if (i == 0)
1212                                         stride += 10;
1213                                 else
1214                                         stride += 6;
1215                                 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1216                                           tmds->tmds_pll[i].freq,
1217                                           tmds->tmds_pll[i].value);
1218                         }
1219                 }
1220         } else {
1221                 DRM_INFO("No TMDS info found in BIOS\n");
1222                 return false;
1223         }
1224         return true;
1225 }
1226
1227 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1228                                                 struct radeon_encoder_ext_tmds *tmds)
1229 {
1230         struct drm_device *dev = encoder->base.dev;
1231         struct radeon_device *rdev = dev->dev_private;
1232         struct radeon_i2c_bus_rec i2c_bus;
1233
1234         /* default for macs */
1235         i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1236         tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1237
1238         /* XXX some macs have duallink chips */
1239         switch (rdev->mode_info.connector_table) {
1240         case CT_POWERBOOK_EXTERNAL:
1241         case CT_MINI_EXTERNAL:
1242         default:
1243                 tmds->dvo_chip = DVO_SIL164;
1244                 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1245                 break;
1246         }
1247
1248         return true;
1249 }
1250
1251 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1252                                                   struct radeon_encoder_ext_tmds *tmds)
1253 {
1254         struct drm_device *dev = encoder->base.dev;
1255         struct radeon_device *rdev = dev->dev_private;
1256         uint16_t offset;
1257         uint8_t ver, id, blocks, clk, data;
1258         int i;
1259         enum radeon_combios_ddc gpio;
1260         struct radeon_i2c_bus_rec i2c_bus;
1261
1262         tmds->i2c_bus = NULL;
1263         if (rdev->flags & RADEON_IS_IGP) {
1264                 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
1265                 if (offset) {
1266                         ver = RBIOS8(offset);
1267                         DRM_INFO("GPIO Table revision: %d\n", ver);
1268                         blocks = RBIOS8(offset + 2);
1269                         for (i = 0; i < blocks; i++) {
1270                                 id = RBIOS8(offset + 3 + (i * 5) + 0);
1271                                 if (id == 136) {
1272                                         clk = RBIOS8(offset + 3 + (i * 5) + 3);
1273                                         data = RBIOS8(offset + 3 + (i * 5) + 4);
1274                                         i2c_bus.valid = true;
1275                                         i2c_bus.mask_clk_mask = (1 << clk);
1276                                         i2c_bus.mask_data_mask = (1 << data);
1277                                         i2c_bus.a_clk_mask = (1 << clk);
1278                                         i2c_bus.a_data_mask = (1 << data);
1279                                         i2c_bus.en_clk_mask = (1 << clk);
1280                                         i2c_bus.en_data_mask = (1 << data);
1281                                         i2c_bus.y_clk_mask = (1 << clk);
1282                                         i2c_bus.y_data_mask = (1 << data);
1283                                         i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK;
1284                                         i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK;
1285                                         i2c_bus.a_clk_reg = RADEON_GPIOPAD_A;
1286                                         i2c_bus.a_data_reg = RADEON_GPIOPAD_A;
1287                                         i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN;
1288                                         i2c_bus.en_data_reg = RADEON_GPIOPAD_EN;
1289                                         i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y;
1290                                         i2c_bus.y_data_reg = RADEON_GPIOPAD_Y;
1291                                         tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1292                                         tmds->dvo_chip = DVO_SIL164;
1293                                         tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1294                                         break;
1295                                 }
1296                         }
1297                 }
1298         } else {
1299                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1300                 if (offset) {
1301                         ver = RBIOS8(offset);
1302                         DRM_INFO("External TMDS Table revision: %d\n", ver);
1303                         tmds->slave_addr = RBIOS8(offset + 4 + 2);
1304                         tmds->slave_addr >>= 1; /* 7 bit addressing */
1305                         gpio = RBIOS8(offset + 4 + 3);
1306                         switch (gpio) {
1307                         case DDC_MONID:
1308                                 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1309                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1310                                 break;
1311                         case DDC_DVI:
1312                                 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1313                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1314                                 break;
1315                         case DDC_VGA:
1316                                 i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1317                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1318                                 break;
1319                         case DDC_CRT2:
1320                                 /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1321                                 if (rdev->family >= CHIP_R300)
1322                                         i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1323                                 else
1324                                         i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1325                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1326                                 break;
1327                         case DDC_LCD: /* MM i2c */
1328                                 i2c_bus.valid = true;
1329                                 i2c_bus.hw_capable = true;
1330                                 i2c_bus.mm_i2c = true;
1331                                 tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO");
1332                                 break;
1333                         default:
1334                                 DRM_ERROR("Unsupported gpio %d\n", gpio);
1335                                 break;
1336                         }
1337                 }
1338         }
1339
1340         if (!tmds->i2c_bus) {
1341                 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1342                 return false;
1343         }
1344
1345         return true;
1346 }
1347
1348 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1349 {
1350         struct radeon_device *rdev = dev->dev_private;
1351         struct radeon_i2c_bus_rec ddc_i2c;
1352         struct radeon_hpd hpd;
1353
1354         rdev->mode_info.connector_table = radeon_connector_table;
1355         if (rdev->mode_info.connector_table == CT_NONE) {
1356 #ifdef CONFIG_PPC_PMAC
1357                 if (of_machine_is_compatible("PowerBook3,3")) {
1358                         /* powerbook with VGA */
1359                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1360                 } else if (of_machine_is_compatible("PowerBook3,4") ||
1361                            of_machine_is_compatible("PowerBook3,5")) {
1362                         /* powerbook with internal tmds */
1363                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1364                 } else if (of_machine_is_compatible("PowerBook5,1") ||
1365                            of_machine_is_compatible("PowerBook5,2") ||
1366                            of_machine_is_compatible("PowerBook5,3") ||
1367                            of_machine_is_compatible("PowerBook5,4") ||
1368                            of_machine_is_compatible("PowerBook5,5")) {
1369                         /* powerbook with external single link tmds (sil164) */
1370                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1371                 } else if (of_machine_is_compatible("PowerBook5,6")) {
1372                         /* powerbook with external dual or single link tmds */
1373                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1374                 } else if (of_machine_is_compatible("PowerBook5,7") ||
1375                            of_machine_is_compatible("PowerBook5,8") ||
1376                            of_machine_is_compatible("PowerBook5,9")) {
1377                         /* PowerBook6,2 ? */
1378                         /* powerbook with external dual link tmds (sil1178?) */
1379                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1380                 } else if (of_machine_is_compatible("PowerBook4,1") ||
1381                            of_machine_is_compatible("PowerBook4,2") ||
1382                            of_machine_is_compatible("PowerBook4,3") ||
1383                            of_machine_is_compatible("PowerBook6,3") ||
1384                            of_machine_is_compatible("PowerBook6,5") ||
1385                            of_machine_is_compatible("PowerBook6,7")) {
1386                         /* ibook */
1387                         rdev->mode_info.connector_table = CT_IBOOK;
1388                 } else if (of_machine_is_compatible("PowerMac4,4")) {
1389                         /* emac */
1390                         rdev->mode_info.connector_table = CT_EMAC;
1391                 } else if (of_machine_is_compatible("PowerMac10,1")) {
1392                         /* mini with internal tmds */
1393                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1394                 } else if (of_machine_is_compatible("PowerMac10,2")) {
1395                         /* mini with external tmds */
1396                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1397                 } else if (of_machine_is_compatible("PowerMac12,1")) {
1398                         /* PowerMac8,1 ? */
1399                         /* imac g5 isight */
1400                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1401                 } else
1402 #endif /* CONFIG_PPC_PMAC */
1403                         rdev->mode_info.connector_table = CT_GENERIC;
1404         }
1405
1406         switch (rdev->mode_info.connector_table) {
1407         case CT_GENERIC:
1408                 DRM_INFO("Connector Table: %d (generic)\n",
1409                          rdev->mode_info.connector_table);
1410                 /* these are the most common settings */
1411                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1412                         /* VGA - primary dac */
1413                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1414                         hpd.hpd = RADEON_HPD_NONE;
1415                         radeon_add_legacy_encoder(dev,
1416                                                   radeon_get_encoder_id(dev,
1417                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1418                                                                         1),
1419                                                   ATOM_DEVICE_CRT1_SUPPORT);
1420                         radeon_add_legacy_connector(dev, 0,
1421                                                     ATOM_DEVICE_CRT1_SUPPORT,
1422                                                     DRM_MODE_CONNECTOR_VGA,
1423                                                     &ddc_i2c,
1424                                                     CONNECTOR_OBJECT_ID_VGA,
1425                                                     &hpd);
1426                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1427                         /* LVDS */
1428                         ddc_i2c = combios_setup_i2c_bus(rdev, 0);
1429                         hpd.hpd = RADEON_HPD_NONE;
1430                         radeon_add_legacy_encoder(dev,
1431                                                   radeon_get_encoder_id(dev,
1432                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1433                                                                         0),
1434                                                   ATOM_DEVICE_LCD1_SUPPORT);
1435                         radeon_add_legacy_connector(dev, 0,
1436                                                     ATOM_DEVICE_LCD1_SUPPORT,
1437                                                     DRM_MODE_CONNECTOR_LVDS,
1438                                                     &ddc_i2c,
1439                                                     CONNECTOR_OBJECT_ID_LVDS,
1440                                                     &hpd);
1441
1442                         /* VGA - primary dac */
1443                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1444                         hpd.hpd = RADEON_HPD_NONE;
1445                         radeon_add_legacy_encoder(dev,
1446                                                   radeon_get_encoder_id(dev,
1447                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1448                                                                         1),
1449                                                   ATOM_DEVICE_CRT1_SUPPORT);
1450                         radeon_add_legacy_connector(dev, 1,
1451                                                     ATOM_DEVICE_CRT1_SUPPORT,
1452                                                     DRM_MODE_CONNECTOR_VGA,
1453                                                     &ddc_i2c,
1454                                                     CONNECTOR_OBJECT_ID_VGA,
1455                                                     &hpd);
1456                 } else {
1457                         /* DVI-I - tv dac, int tmds */
1458                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1459                         hpd.hpd = RADEON_HPD_1;
1460                         radeon_add_legacy_encoder(dev,
1461                                                   radeon_get_encoder_id(dev,
1462                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1463                                                                         0),
1464                                                   ATOM_DEVICE_DFP1_SUPPORT);
1465                         radeon_add_legacy_encoder(dev,
1466                                                   radeon_get_encoder_id(dev,
1467                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1468                                                                         2),
1469                                                   ATOM_DEVICE_CRT2_SUPPORT);
1470                         radeon_add_legacy_connector(dev, 0,
1471                                                     ATOM_DEVICE_DFP1_SUPPORT |
1472                                                     ATOM_DEVICE_CRT2_SUPPORT,
1473                                                     DRM_MODE_CONNECTOR_DVII,
1474                                                     &ddc_i2c,
1475                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1476                                                     &hpd);
1477
1478                         /* VGA - primary dac */
1479                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1480                         hpd.hpd = RADEON_HPD_NONE;
1481                         radeon_add_legacy_encoder(dev,
1482                                                   radeon_get_encoder_id(dev,
1483                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1484                                                                         1),
1485                                                   ATOM_DEVICE_CRT1_SUPPORT);
1486                         radeon_add_legacy_connector(dev, 1,
1487                                                     ATOM_DEVICE_CRT1_SUPPORT,
1488                                                     DRM_MODE_CONNECTOR_VGA,
1489                                                     &ddc_i2c,
1490                                                     CONNECTOR_OBJECT_ID_VGA,
1491                                                     &hpd);
1492                 }
1493
1494                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1495                         /* TV - tv dac */
1496                         ddc_i2c.valid = false;
1497                         hpd.hpd = RADEON_HPD_NONE;
1498                         radeon_add_legacy_encoder(dev,
1499                                                   radeon_get_encoder_id(dev,
1500                                                                         ATOM_DEVICE_TV1_SUPPORT,
1501                                                                         2),
1502                                                   ATOM_DEVICE_TV1_SUPPORT);
1503                         radeon_add_legacy_connector(dev, 2,
1504                                                     ATOM_DEVICE_TV1_SUPPORT,
1505                                                     DRM_MODE_CONNECTOR_SVIDEO,
1506                                                     &ddc_i2c,
1507                                                     CONNECTOR_OBJECT_ID_SVIDEO,
1508                                                     &hpd);
1509                 }
1510                 break;
1511         case CT_IBOOK:
1512                 DRM_INFO("Connector Table: %d (ibook)\n",
1513                          rdev->mode_info.connector_table);
1514                 /* LVDS */
1515                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1516                 hpd.hpd = RADEON_HPD_NONE;
1517                 radeon_add_legacy_encoder(dev,
1518                                           radeon_get_encoder_id(dev,
1519                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1520                                                                 0),
1521                                           ATOM_DEVICE_LCD1_SUPPORT);
1522                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1523                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1524                                             CONNECTOR_OBJECT_ID_LVDS,
1525                                             &hpd);
1526                 /* VGA - TV DAC */
1527                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1528                 hpd.hpd = RADEON_HPD_NONE;
1529                 radeon_add_legacy_encoder(dev,
1530                                           radeon_get_encoder_id(dev,
1531                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1532                                                                 2),
1533                                           ATOM_DEVICE_CRT2_SUPPORT);
1534                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1535                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1536                                             CONNECTOR_OBJECT_ID_VGA,
1537                                             &hpd);
1538                 /* TV - TV DAC */
1539                 ddc_i2c.valid = false;
1540                 hpd.hpd = RADEON_HPD_NONE;
1541                 radeon_add_legacy_encoder(dev,
1542                                           radeon_get_encoder_id(dev,
1543                                                                 ATOM_DEVICE_TV1_SUPPORT,
1544                                                                 2),
1545                                           ATOM_DEVICE_TV1_SUPPORT);
1546                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1547                                             DRM_MODE_CONNECTOR_SVIDEO,
1548                                             &ddc_i2c,
1549                                             CONNECTOR_OBJECT_ID_SVIDEO,
1550                                             &hpd);
1551                 break;
1552         case CT_POWERBOOK_EXTERNAL:
1553                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1554                          rdev->mode_info.connector_table);
1555                 /* LVDS */
1556                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1557                 hpd.hpd = RADEON_HPD_NONE;
1558                 radeon_add_legacy_encoder(dev,
1559                                           radeon_get_encoder_id(dev,
1560                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1561                                                                 0),
1562                                           ATOM_DEVICE_LCD1_SUPPORT);
1563                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1564                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1565                                             CONNECTOR_OBJECT_ID_LVDS,
1566                                             &hpd);
1567                 /* DVI-I - primary dac, ext tmds */
1568                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1569                 hpd.hpd = RADEON_HPD_2; /* ??? */
1570                 radeon_add_legacy_encoder(dev,
1571                                           radeon_get_encoder_id(dev,
1572                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1573                                                                 0),
1574                                           ATOM_DEVICE_DFP2_SUPPORT);
1575                 radeon_add_legacy_encoder(dev,
1576                                           radeon_get_encoder_id(dev,
1577                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1578                                                                 1),
1579                                           ATOM_DEVICE_CRT1_SUPPORT);
1580                 /* XXX some are SL */
1581                 radeon_add_legacy_connector(dev, 1,
1582                                             ATOM_DEVICE_DFP2_SUPPORT |
1583                                             ATOM_DEVICE_CRT1_SUPPORT,
1584                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1585                                             CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1586                                             &hpd);
1587                 /* TV - TV DAC */
1588                 ddc_i2c.valid = false;
1589                 hpd.hpd = RADEON_HPD_NONE;
1590                 radeon_add_legacy_encoder(dev,
1591                                           radeon_get_encoder_id(dev,
1592                                                                 ATOM_DEVICE_TV1_SUPPORT,
1593                                                                 2),
1594                                           ATOM_DEVICE_TV1_SUPPORT);
1595                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1596                                             DRM_MODE_CONNECTOR_SVIDEO,
1597                                             &ddc_i2c,
1598                                             CONNECTOR_OBJECT_ID_SVIDEO,
1599                                             &hpd);
1600                 break;
1601         case CT_POWERBOOK_INTERNAL:
1602                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1603                          rdev->mode_info.connector_table);
1604                 /* LVDS */
1605                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1606                 hpd.hpd = RADEON_HPD_NONE;
1607                 radeon_add_legacy_encoder(dev,
1608                                           radeon_get_encoder_id(dev,
1609                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1610                                                                 0),
1611                                           ATOM_DEVICE_LCD1_SUPPORT);
1612                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1613                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1614                                             CONNECTOR_OBJECT_ID_LVDS,
1615                                             &hpd);
1616                 /* DVI-I - primary dac, int tmds */
1617                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1618                 hpd.hpd = RADEON_HPD_1; /* ??? */
1619                 radeon_add_legacy_encoder(dev,
1620                                           radeon_get_encoder_id(dev,
1621                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1622                                                                 0),
1623                                           ATOM_DEVICE_DFP1_SUPPORT);
1624                 radeon_add_legacy_encoder(dev,
1625                                           radeon_get_encoder_id(dev,
1626                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1627                                                                 1),
1628                                           ATOM_DEVICE_CRT1_SUPPORT);
1629                 radeon_add_legacy_connector(dev, 1,
1630                                             ATOM_DEVICE_DFP1_SUPPORT |
1631                                             ATOM_DEVICE_CRT1_SUPPORT,
1632                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1633                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1634                                             &hpd);
1635                 /* TV - TV DAC */
1636                 ddc_i2c.valid = false;
1637                 hpd.hpd = RADEON_HPD_NONE;
1638                 radeon_add_legacy_encoder(dev,
1639                                           radeon_get_encoder_id(dev,
1640                                                                 ATOM_DEVICE_TV1_SUPPORT,
1641                                                                 2),
1642                                           ATOM_DEVICE_TV1_SUPPORT);
1643                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1644                                             DRM_MODE_CONNECTOR_SVIDEO,
1645                                             &ddc_i2c,
1646                                             CONNECTOR_OBJECT_ID_SVIDEO,
1647                                             &hpd);
1648                 break;
1649         case CT_POWERBOOK_VGA:
1650                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1651                          rdev->mode_info.connector_table);
1652                 /* LVDS */
1653                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1654                 hpd.hpd = RADEON_HPD_NONE;
1655                 radeon_add_legacy_encoder(dev,
1656                                           radeon_get_encoder_id(dev,
1657                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1658                                                                 0),
1659                                           ATOM_DEVICE_LCD1_SUPPORT);
1660                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1661                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1662                                             CONNECTOR_OBJECT_ID_LVDS,
1663                                             &hpd);
1664                 /* VGA - primary dac */
1665                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1666                 hpd.hpd = RADEON_HPD_NONE;
1667                 radeon_add_legacy_encoder(dev,
1668                                           radeon_get_encoder_id(dev,
1669                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1670                                                                 1),
1671                                           ATOM_DEVICE_CRT1_SUPPORT);
1672                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1673                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1674                                             CONNECTOR_OBJECT_ID_VGA,
1675                                             &hpd);
1676                 /* TV - TV DAC */
1677                 ddc_i2c.valid = false;
1678                 hpd.hpd = RADEON_HPD_NONE;
1679                 radeon_add_legacy_encoder(dev,
1680                                           radeon_get_encoder_id(dev,
1681                                                                 ATOM_DEVICE_TV1_SUPPORT,
1682                                                                 2),
1683                                           ATOM_DEVICE_TV1_SUPPORT);
1684                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1685                                             DRM_MODE_CONNECTOR_SVIDEO,
1686                                             &ddc_i2c,
1687                                             CONNECTOR_OBJECT_ID_SVIDEO,
1688                                             &hpd);
1689                 break;
1690         case CT_MINI_EXTERNAL:
1691                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1692                          rdev->mode_info.connector_table);
1693                 /* DVI-I - tv dac, ext tmds */
1694                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1695                 hpd.hpd = RADEON_HPD_2; /* ??? */
1696                 radeon_add_legacy_encoder(dev,
1697                                           radeon_get_encoder_id(dev,
1698                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1699                                                                 0),
1700                                           ATOM_DEVICE_DFP2_SUPPORT);
1701                 radeon_add_legacy_encoder(dev,
1702                                           radeon_get_encoder_id(dev,
1703                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1704                                                                 2),
1705                                           ATOM_DEVICE_CRT2_SUPPORT);
1706                 /* XXX are any DL? */
1707                 radeon_add_legacy_connector(dev, 0,
1708                                             ATOM_DEVICE_DFP2_SUPPORT |
1709                                             ATOM_DEVICE_CRT2_SUPPORT,
1710                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1711                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1712                                             &hpd);
1713                 /* TV - TV DAC */
1714                 ddc_i2c.valid = false;
1715                 hpd.hpd = RADEON_HPD_NONE;
1716                 radeon_add_legacy_encoder(dev,
1717                                           radeon_get_encoder_id(dev,
1718                                                                 ATOM_DEVICE_TV1_SUPPORT,
1719                                                                 2),
1720                                           ATOM_DEVICE_TV1_SUPPORT);
1721                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1722                                             DRM_MODE_CONNECTOR_SVIDEO,
1723                                             &ddc_i2c,
1724                                             CONNECTOR_OBJECT_ID_SVIDEO,
1725                                             &hpd);
1726                 break;
1727         case CT_MINI_INTERNAL:
1728                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1729                          rdev->mode_info.connector_table);
1730                 /* DVI-I - tv dac, int tmds */
1731                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1732                 hpd.hpd = RADEON_HPD_1; /* ??? */
1733                 radeon_add_legacy_encoder(dev,
1734                                           radeon_get_encoder_id(dev,
1735                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1736                                                                 0),
1737                                           ATOM_DEVICE_DFP1_SUPPORT);
1738                 radeon_add_legacy_encoder(dev,
1739                                           radeon_get_encoder_id(dev,
1740                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1741                                                                 2),
1742                                           ATOM_DEVICE_CRT2_SUPPORT);
1743                 radeon_add_legacy_connector(dev, 0,
1744                                             ATOM_DEVICE_DFP1_SUPPORT |
1745                                             ATOM_DEVICE_CRT2_SUPPORT,
1746                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1747                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1748                                             &hpd);
1749                 /* TV - TV DAC */
1750                 ddc_i2c.valid = false;
1751                 hpd.hpd = RADEON_HPD_NONE;
1752                 radeon_add_legacy_encoder(dev,
1753                                           radeon_get_encoder_id(dev,
1754                                                                 ATOM_DEVICE_TV1_SUPPORT,
1755                                                                 2),
1756                                           ATOM_DEVICE_TV1_SUPPORT);
1757                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1758                                             DRM_MODE_CONNECTOR_SVIDEO,
1759                                             &ddc_i2c,
1760                                             CONNECTOR_OBJECT_ID_SVIDEO,
1761                                             &hpd);
1762                 break;
1763         case CT_IMAC_G5_ISIGHT:
1764                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1765                          rdev->mode_info.connector_table);
1766                 /* DVI-D - int tmds */
1767                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1768                 hpd.hpd = RADEON_HPD_1; /* ??? */
1769                 radeon_add_legacy_encoder(dev,
1770                                           radeon_get_encoder_id(dev,
1771                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1772                                                                 0),
1773                                           ATOM_DEVICE_DFP1_SUPPORT);
1774                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1775                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1776                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1777                                             &hpd);
1778                 /* VGA - tv dac */
1779                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1780                 hpd.hpd = RADEON_HPD_NONE;
1781                 radeon_add_legacy_encoder(dev,
1782                                           radeon_get_encoder_id(dev,
1783                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1784                                                                 2),
1785                                           ATOM_DEVICE_CRT2_SUPPORT);
1786                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1787                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1788                                             CONNECTOR_OBJECT_ID_VGA,
1789                                             &hpd);
1790                 /* TV - TV DAC */
1791                 ddc_i2c.valid = false;
1792                 hpd.hpd = RADEON_HPD_NONE;
1793                 radeon_add_legacy_encoder(dev,
1794                                           radeon_get_encoder_id(dev,
1795                                                                 ATOM_DEVICE_TV1_SUPPORT,
1796                                                                 2),
1797                                           ATOM_DEVICE_TV1_SUPPORT);
1798                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1799                                             DRM_MODE_CONNECTOR_SVIDEO,
1800                                             &ddc_i2c,
1801                                             CONNECTOR_OBJECT_ID_SVIDEO,
1802                                             &hpd);
1803                 break;
1804         case CT_EMAC:
1805                 DRM_INFO("Connector Table: %d (emac)\n",
1806                          rdev->mode_info.connector_table);
1807                 /* VGA - primary dac */
1808                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
1809                 hpd.hpd = RADEON_HPD_NONE;
1810                 radeon_add_legacy_encoder(dev,
1811                                           radeon_get_encoder_id(dev,
1812                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1813                                                                 1),
1814                                           ATOM_DEVICE_CRT1_SUPPORT);
1815                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1816                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1817                                             CONNECTOR_OBJECT_ID_VGA,
1818                                             &hpd);
1819                 /* VGA - tv dac */
1820                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
1821                 hpd.hpd = RADEON_HPD_NONE;
1822                 radeon_add_legacy_encoder(dev,
1823                                           radeon_get_encoder_id(dev,
1824                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1825                                                                 2),
1826                                           ATOM_DEVICE_CRT2_SUPPORT);
1827                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1828                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1829                                             CONNECTOR_OBJECT_ID_VGA,
1830                                             &hpd);
1831                 /* TV - TV DAC */
1832                 ddc_i2c.valid = false;
1833                 hpd.hpd = RADEON_HPD_NONE;
1834                 radeon_add_legacy_encoder(dev,
1835                                           radeon_get_encoder_id(dev,
1836                                                                 ATOM_DEVICE_TV1_SUPPORT,
1837                                                                 2),
1838                                           ATOM_DEVICE_TV1_SUPPORT);
1839                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1840                                             DRM_MODE_CONNECTOR_SVIDEO,
1841                                             &ddc_i2c,
1842                                             CONNECTOR_OBJECT_ID_SVIDEO,
1843                                             &hpd);
1844                 break;
1845         default:
1846                 DRM_INFO("Connector table: %d (invalid)\n",
1847                          rdev->mode_info.connector_table);
1848                 return false;
1849         }
1850
1851         radeon_link_encoder_connector(dev);
1852
1853         return true;
1854 }
1855
1856 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1857                                        int bios_index,
1858                                        enum radeon_combios_connector
1859                                        *legacy_connector,
1860                                        struct radeon_i2c_bus_rec *ddc_i2c,
1861                                        struct radeon_hpd *hpd)
1862 {
1863         struct radeon_device *rdev = dev->dev_private;
1864
1865         /* XPRESS DDC quirks */
1866         if ((rdev->family == CHIP_RS400 ||
1867              rdev->family == CHIP_RS480) &&
1868             ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1869                 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
1870         else if ((rdev->family == CHIP_RS400 ||
1871                   rdev->family == CHIP_RS480) &&
1872                  ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1873                 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK);
1874                 ddc_i2c->mask_clk_mask = (0x20 << 8);
1875                 ddc_i2c->mask_data_mask = 0x80;
1876                 ddc_i2c->a_clk_mask = (0x20 << 8);
1877                 ddc_i2c->a_data_mask = 0x80;
1878                 ddc_i2c->en_clk_mask = (0x20 << 8);
1879                 ddc_i2c->en_data_mask = 0x80;
1880                 ddc_i2c->y_clk_mask = (0x20 << 8);
1881                 ddc_i2c->y_data_mask = 0x80;
1882         }
1883
1884         /* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */
1885         if ((rdev->family >= CHIP_R300) &&
1886             ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1887                 *ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
1888
1889         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1890            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1891         if (dev->pdev->device == 0x515e &&
1892             dev->pdev->subsystem_vendor == 0x1014) {
1893                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1894                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1895                         return false;
1896         }
1897
1898         /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1899         if (dev->pdev->device == 0x5159 &&
1900             dev->pdev->subsystem_vendor == 0x1002 &&
1901             dev->pdev->subsystem_device == 0x013a) {
1902                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1903                         *legacy_connector = CONNECTOR_CRT_LEGACY;
1904
1905         }
1906
1907         /* X300 card with extra non-existent DVI port */
1908         if (dev->pdev->device == 0x5B60 &&
1909             dev->pdev->subsystem_vendor == 0x17af &&
1910             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1911                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1912                         return false;
1913         }
1914
1915         return true;
1916 }
1917
1918 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1919 {
1920         /* Acer 5102 has non-existent TV port */
1921         if (dev->pdev->device == 0x5975 &&
1922             dev->pdev->subsystem_vendor == 0x1025 &&
1923             dev->pdev->subsystem_device == 0x009f)
1924                 return false;
1925
1926         /* HP dc5750 has non-existent TV port */
1927         if (dev->pdev->device == 0x5974 &&
1928             dev->pdev->subsystem_vendor == 0x103c &&
1929             dev->pdev->subsystem_device == 0x280a)
1930                 return false;
1931
1932         /* MSI S270 has non-existent TV port */
1933         if (dev->pdev->device == 0x5955 &&
1934             dev->pdev->subsystem_vendor == 0x1462 &&
1935             dev->pdev->subsystem_device == 0x0131)
1936                 return false;
1937
1938         return true;
1939 }
1940
1941 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1942 {
1943         struct radeon_device *rdev = dev->dev_private;
1944         uint32_t ext_tmds_info;
1945
1946         if (rdev->flags & RADEON_IS_IGP) {
1947                 if (is_dvi_d)
1948                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1949                 else
1950                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1951         }
1952         ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1953         if (ext_tmds_info) {
1954                 uint8_t rev = RBIOS8(ext_tmds_info);
1955                 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1956                 if (rev >= 3) {
1957                         if (is_dvi_d)
1958                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1959                         else
1960                                 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1961                 } else {
1962                         if (flags & 1) {
1963                                 if (is_dvi_d)
1964                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1965                                 else
1966                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1967                         }
1968                 }
1969         }
1970         if (is_dvi_d)
1971                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1972         else
1973                 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1974 }
1975
1976 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1977 {
1978         struct radeon_device *rdev = dev->dev_private;
1979         uint32_t conn_info, entry, devices;
1980         uint16_t tmp, connector_object_id;
1981         enum radeon_combios_ddc ddc_type;
1982         enum radeon_combios_connector connector;
1983         int i = 0;
1984         struct radeon_i2c_bus_rec ddc_i2c;
1985         struct radeon_hpd hpd;
1986
1987         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1988         if (conn_info) {
1989                 for (i = 0; i < 4; i++) {
1990                         entry = conn_info + 2 + i * 2;
1991
1992                         if (!RBIOS16(entry))
1993                                 break;
1994
1995                         tmp = RBIOS16(entry);
1996
1997                         connector = (tmp >> 12) & 0xf;
1998
1999                         ddc_type = (tmp >> 8) & 0xf;
2000                         switch (ddc_type) {
2001                         case DDC_MONID:
2002                                 ddc_i2c =
2003                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID);
2004                                 break;
2005                         case DDC_DVI:
2006                                 ddc_i2c =
2007                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2008                                 break;
2009                         case DDC_VGA:
2010                                 ddc_i2c =
2011                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2012                                 break;
2013                         case DDC_CRT2:
2014                                 ddc_i2c =
2015                                         combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC);
2016                                 break;
2017                         default:
2018                                 break;
2019                         }
2020
2021                         switch (connector) {
2022                         case CONNECTOR_PROPRIETARY_LEGACY:
2023                         case CONNECTOR_DVI_I_LEGACY:
2024                         case CONNECTOR_DVI_D_LEGACY:
2025                                 if ((tmp >> 4) & 0x1)
2026                                         hpd.hpd = RADEON_HPD_2;
2027                                 else
2028                                         hpd.hpd = RADEON_HPD_1;
2029                                 break;
2030                         default:
2031                                 hpd.hpd = RADEON_HPD_NONE;
2032                                 break;
2033                         }
2034
2035                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
2036                                                         &ddc_i2c, &hpd))
2037                                 continue;
2038
2039                         switch (connector) {
2040                         case CONNECTOR_PROPRIETARY_LEGACY:
2041                                 if ((tmp >> 4) & 0x1)
2042                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2043                                 else
2044                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2045                                 radeon_add_legacy_encoder(dev,
2046                                                           radeon_get_encoder_id
2047                                                           (dev, devices, 0),
2048                                                           devices);
2049                                 radeon_add_legacy_connector(dev, i, devices,
2050                                                             legacy_connector_convert
2051                                                             [connector],
2052                                                             &ddc_i2c,
2053                                                             CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2054                                                             &hpd);
2055                                 break;
2056                         case CONNECTOR_CRT_LEGACY:
2057                                 if (tmp & 0x1) {
2058                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
2059                                         radeon_add_legacy_encoder(dev,
2060                                                                   radeon_get_encoder_id
2061                                                                   (dev,
2062                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2063                                                                    2),
2064                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2065                                 } else {
2066                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
2067                                         radeon_add_legacy_encoder(dev,
2068                                                                   radeon_get_encoder_id
2069                                                                   (dev,
2070                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2071                                                                    1),
2072                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2073                                 }
2074                                 radeon_add_legacy_connector(dev,
2075                                                             i,
2076                                                             devices,
2077                                                             legacy_connector_convert
2078                                                             [connector],
2079                                                             &ddc_i2c,
2080                                                             CONNECTOR_OBJECT_ID_VGA,
2081                                                             &hpd);
2082                                 break;
2083                         case CONNECTOR_DVI_I_LEGACY:
2084                                 devices = 0;
2085                                 if (tmp & 0x1) {
2086                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
2087                                         radeon_add_legacy_encoder(dev,
2088                                                                   radeon_get_encoder_id
2089                                                                   (dev,
2090                                                                    ATOM_DEVICE_CRT2_SUPPORT,
2091                                                                    2),
2092                                                                   ATOM_DEVICE_CRT2_SUPPORT);
2093                                 } else {
2094                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
2095                                         radeon_add_legacy_encoder(dev,
2096                                                                   radeon_get_encoder_id
2097                                                                   (dev,
2098                                                                    ATOM_DEVICE_CRT1_SUPPORT,
2099                                                                    1),
2100                                                                   ATOM_DEVICE_CRT1_SUPPORT);
2101                                 }
2102                                 if ((tmp >> 4) & 0x1) {
2103                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
2104                                         radeon_add_legacy_encoder(dev,
2105                                                                   radeon_get_encoder_id
2106                                                                   (dev,
2107                                                                    ATOM_DEVICE_DFP2_SUPPORT,
2108                                                                    0),
2109                                                                   ATOM_DEVICE_DFP2_SUPPORT);
2110                                         connector_object_id = combios_check_dl_dvi(dev, 0);
2111                                 } else {
2112                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
2113                                         radeon_add_legacy_encoder(dev,
2114                                                                   radeon_get_encoder_id
2115                                                                   (dev,
2116                                                                    ATOM_DEVICE_DFP1_SUPPORT,
2117                                                                    0),
2118                                                                   ATOM_DEVICE_DFP1_SUPPORT);
2119                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2120                                 }
2121                                 radeon_add_legacy_connector(dev,
2122                                                             i,
2123                                                             devices,
2124                                                             legacy_connector_convert
2125                                                             [connector],
2126                                                             &ddc_i2c,
2127                                                             connector_object_id,
2128                                                             &hpd);
2129                                 break;
2130                         case CONNECTOR_DVI_D_LEGACY:
2131                                 if ((tmp >> 4) & 0x1) {
2132                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
2133                                         connector_object_id = combios_check_dl_dvi(dev, 1);
2134                                 } else {
2135                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
2136                                         connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2137                                 }
2138                                 radeon_add_legacy_encoder(dev,
2139                                                           radeon_get_encoder_id
2140                                                           (dev, devices, 0),
2141                                                           devices);
2142                                 radeon_add_legacy_connector(dev, i, devices,
2143                                                             legacy_connector_convert
2144                                                             [connector],
2145                                                             &ddc_i2c,
2146                                                             connector_object_id,
2147                                                             &hpd);
2148                                 break;
2149                         case CONNECTOR_CTV_LEGACY:
2150                         case CONNECTOR_STV_LEGACY:
2151                                 radeon_add_legacy_encoder(dev,
2152                                                           radeon_get_encoder_id
2153                                                           (dev,
2154                                                            ATOM_DEVICE_TV1_SUPPORT,
2155                                                            2),
2156                                                           ATOM_DEVICE_TV1_SUPPORT);
2157                                 radeon_add_legacy_connector(dev, i,
2158                                                             ATOM_DEVICE_TV1_SUPPORT,
2159                                                             legacy_connector_convert
2160                                                             [connector],
2161                                                             &ddc_i2c,
2162                                                             CONNECTOR_OBJECT_ID_SVIDEO,
2163                                                             &hpd);
2164                                 break;
2165                         default:
2166                                 DRM_ERROR("Unknown connector type: %d\n",
2167                                           connector);
2168                                 continue;
2169                         }
2170
2171                 }
2172         } else {
2173                 uint16_t tmds_info =
2174                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2175                 if (tmds_info) {
2176                         DRM_DEBUG("Found DFP table, assuming DVI connector\n");
2177
2178                         radeon_add_legacy_encoder(dev,
2179                                                   radeon_get_encoder_id(dev,
2180                                                                         ATOM_DEVICE_CRT1_SUPPORT,
2181                                                                         1),
2182                                                   ATOM_DEVICE_CRT1_SUPPORT);
2183                         radeon_add_legacy_encoder(dev,
2184                                                   radeon_get_encoder_id(dev,
2185                                                                         ATOM_DEVICE_DFP1_SUPPORT,
2186                                                                         0),
2187                                                   ATOM_DEVICE_DFP1_SUPPORT);
2188
2189                         ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC);
2190                         hpd.hpd = RADEON_HPD_NONE;
2191                         radeon_add_legacy_connector(dev,
2192                                                     0,
2193                                                     ATOM_DEVICE_CRT1_SUPPORT |
2194                                                     ATOM_DEVICE_DFP1_SUPPORT,
2195                                                     DRM_MODE_CONNECTOR_DVII,
2196                                                     &ddc_i2c,
2197                                                     CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2198                                                     &hpd);
2199                 } else {
2200                         uint16_t crt_info =
2201                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2202                         DRM_DEBUG("Found CRT table, assuming VGA connector\n");
2203                         if (crt_info) {
2204                                 radeon_add_legacy_encoder(dev,
2205                                                           radeon_get_encoder_id(dev,
2206                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
2207                                                                                 1),
2208                                                           ATOM_DEVICE_CRT1_SUPPORT);
2209                                 ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC);
2210                                 hpd.hpd = RADEON_HPD_NONE;
2211                                 radeon_add_legacy_connector(dev,
2212                                                             0,
2213                                                             ATOM_DEVICE_CRT1_SUPPORT,
2214                                                             DRM_MODE_CONNECTOR_VGA,
2215                                                             &ddc_i2c,
2216                                                             CONNECTOR_OBJECT_ID_VGA,
2217                                                             &hpd);
2218                         } else {
2219                                 DRM_DEBUG("No connector info found\n");
2220                                 return false;
2221                         }
2222                 }
2223         }
2224
2225         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2226                 uint16_t lcd_info =
2227                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2228                 if (lcd_info) {
2229                         uint16_t lcd_ddc_info =
2230                             combios_get_table_offset(dev,
2231                                                      COMBIOS_LCD_DDC_INFO_TABLE);
2232
2233                         radeon_add_legacy_encoder(dev,
2234                                                   radeon_get_encoder_id(dev,
2235                                                                         ATOM_DEVICE_LCD1_SUPPORT,
2236                                                                         0),
2237                                                   ATOM_DEVICE_LCD1_SUPPORT);
2238
2239                         if (lcd_ddc_info) {
2240                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
2241                                 switch (ddc_type) {
2242                                 case DDC_MONID:
2243                                         ddc_i2c =
2244                                             combios_setup_i2c_bus
2245                                                 (rdev, RADEON_GPIO_MONID);
2246                                         break;
2247                                 case DDC_DVI:
2248                                         ddc_i2c =
2249                                             combios_setup_i2c_bus
2250                                                 (rdev, RADEON_GPIO_DVI_DDC);
2251                                         break;
2252                                 case DDC_VGA:
2253                                         ddc_i2c =
2254                                             combios_setup_i2c_bus
2255                                                 (rdev, RADEON_GPIO_VGA_DDC);
2256                                         break;
2257                                 case DDC_CRT2:
2258                                         ddc_i2c =
2259                                             combios_setup_i2c_bus
2260                                                 (rdev, RADEON_GPIO_CRT2_DDC);
2261                                         break;
2262                                 case DDC_LCD:
2263                                         ddc_i2c =
2264                                             combios_setup_i2c_bus
2265                                                 (rdev, RADEON_GPIOPAD_MASK);
2266                                         ddc_i2c.mask_clk_mask =
2267                                             RBIOS32(lcd_ddc_info + 3);
2268                                         ddc_i2c.mask_data_mask =
2269                                             RBIOS32(lcd_ddc_info + 7);
2270                                         ddc_i2c.a_clk_mask =
2271                                             RBIOS32(lcd_ddc_info + 3);
2272                                         ddc_i2c.a_data_mask =
2273                                             RBIOS32(lcd_ddc_info + 7);
2274                                         ddc_i2c.en_clk_mask =
2275                                             RBIOS32(lcd_ddc_info + 3);
2276                                         ddc_i2c.en_data_mask =
2277                                             RBIOS32(lcd_ddc_info + 7);
2278                                         ddc_i2c.y_clk_mask =
2279                                             RBIOS32(lcd_ddc_info + 3);
2280                                         ddc_i2c.y_data_mask =
2281                                             RBIOS32(lcd_ddc_info + 7);
2282                                         break;
2283                                 case DDC_GPIO:
2284                                         ddc_i2c =
2285                                             combios_setup_i2c_bus
2286                                                 (rdev, RADEON_MDGPIO_MASK);
2287                                         ddc_i2c.mask_clk_mask =
2288                                             RBIOS32(lcd_ddc_info + 3);
2289                                         ddc_i2c.mask_data_mask =
2290                                             RBIOS32(lcd_ddc_info + 7);
2291                                         ddc_i2c.a_clk_mask =
2292                                             RBIOS32(lcd_ddc_info + 3);
2293                                         ddc_i2c.a_data_mask =
2294                                             RBIOS32(lcd_ddc_info + 7);
2295                                         ddc_i2c.en_clk_mask =
2296                                             RBIOS32(lcd_ddc_info + 3);
2297                                         ddc_i2c.en_data_mask =
2298                                             RBIOS32(lcd_ddc_info + 7);
2299                                         ddc_i2c.y_clk_mask =
2300                                             RBIOS32(lcd_ddc_info + 3);
2301                                         ddc_i2c.y_data_mask =
2302                                             RBIOS32(lcd_ddc_info + 7);
2303                                         break;
2304                                 default:
2305                                         ddc_i2c.valid = false;
2306                                         break;
2307                                 }
2308                                 DRM_DEBUG("LCD DDC Info Table found!\n");
2309                         } else
2310                                 ddc_i2c.valid = false;
2311
2312                         hpd.hpd = RADEON_HPD_NONE;
2313                         radeon_add_legacy_connector(dev,
2314                                                     5,
2315                                                     ATOM_DEVICE_LCD1_SUPPORT,
2316                                                     DRM_MODE_CONNECTOR_LVDS,
2317                                                     &ddc_i2c,
2318                                                     CONNECTOR_OBJECT_ID_LVDS,
2319                                                     &hpd);
2320                 }
2321         }
2322
2323         /* check TV table */
2324         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2325                 uint32_t tv_info =
2326                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2327                 if (tv_info) {
2328                         if (RBIOS8(tv_info + 6) == 'T') {
2329                                 if (radeon_apply_legacy_tv_quirks(dev)) {
2330                                         hpd.hpd = RADEON_HPD_NONE;
2331                                         radeon_add_legacy_encoder(dev,
2332                                                                   radeon_get_encoder_id
2333                                                                   (dev,
2334                                                                    ATOM_DEVICE_TV1_SUPPORT,
2335                                                                    2),
2336                                                                   ATOM_DEVICE_TV1_SUPPORT);
2337                                         radeon_add_legacy_connector(dev, 6,
2338                                                                     ATOM_DEVICE_TV1_SUPPORT,
2339                                                                     DRM_MODE_CONNECTOR_SVIDEO,
2340                                                                     &ddc_i2c,
2341                                                                     CONNECTOR_OBJECT_ID_SVIDEO,
2342                                                                     &hpd);
2343                                 }
2344                         }
2345                 }
2346         }
2347
2348         radeon_link_encoder_connector(dev);
2349
2350         return true;
2351 }
2352
2353 void radeon_combios_get_power_modes(struct radeon_device *rdev)
2354 {
2355         struct drm_device *dev = rdev->ddev;
2356         u16 offset, misc, misc2 = 0;
2357         u8 rev, blocks, tmp;
2358         int state_index = 0;
2359
2360         rdev->pm.default_power_state = NULL;
2361
2362         if (rdev->flags & RADEON_IS_MOBILITY) {
2363                 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2364                 if (offset) {
2365                         rev = RBIOS8(offset);
2366                         blocks = RBIOS8(offset + 0x2);
2367                         /* power mode 0 tends to be the only valid one */
2368                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2369                         rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2370                         rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2371                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2372                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2373                                 goto default_mode;
2374                         /* skip overclock modes for now */
2375                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
2376                              rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
2377                             (rdev->pm.power_state[state_index].clock_info[0].sclk >
2378                              rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
2379                                 goto default_mode;
2380                         rdev->pm.power_state[state_index].type =
2381                                 POWER_STATE_TYPE_BATTERY;
2382                         misc = RBIOS16(offset + 0x5 + 0x0);
2383                         if (rev > 4)
2384                                 misc2 = RBIOS16(offset + 0x5 + 0xe);
2385                         if (misc & 0x4) {
2386                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2387                                 if (misc & 0x8)
2388                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2389                                                 true;
2390                                 else
2391                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2392                                                 false;
2393                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2394                                 if (rev < 6) {
2395                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2396                                                 RBIOS16(offset + 0x5 + 0xb) * 4;
2397                                         tmp = RBIOS8(offset + 0x5 + 0xd);
2398                                         rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2399                                 } else {
2400                                         u8 entries = RBIOS8(offset + 0x5 + 0xb);
2401                                         u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2402                                         if (entries && voltage_table_offset) {
2403                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2404                                                         RBIOS16(voltage_table_offset) * 4;
2405                                                 tmp = RBIOS8(voltage_table_offset + 0x2);
2406                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2407                                         } else
2408                                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2409                                 }
2410                                 switch ((misc2 & 0x700) >> 8) {
2411                                 case 0:
2412                                 default:
2413                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2414                                         break;
2415                                 case 1:
2416                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2417                                         break;
2418                                 case 2:
2419                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2420                                         break;
2421                                 case 3:
2422                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2423                                         break;
2424                                 case 4:
2425                                         rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2426                                         break;
2427                                 }
2428                         } else
2429                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2430                         if (rev > 6)
2431                                 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
2432                                         RBIOS8(offset + 0x5 + 0x10);
2433                         state_index++;
2434                 } else {
2435                         /* XXX figure out some good default low power mode for mobility cards w/out power tables */
2436                 }
2437         } else {
2438                 /* XXX figure out some good default low power mode for desktop cards */
2439         }
2440
2441 default_mode:
2442         /* add the default mode */
2443         rdev->pm.power_state[state_index].type =
2444                 POWER_STATE_TYPE_DEFAULT;
2445         rdev->pm.power_state[state_index].num_clock_modes = 1;
2446         rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2447         rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2448         rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2449         rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2450         if (rdev->asic->get_pcie_lanes)
2451                 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
2452         else
2453                 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
2454         rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
2455         rdev->pm.num_power_states = state_index + 1;
2456
2457         rdev->pm.current_power_state = rdev->pm.default_power_state;
2458         rdev->pm.current_clock_mode =
2459                 rdev->pm.default_power_state->default_clock_mode;
2460 }
2461
2462 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2463 {
2464         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2465         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2466
2467         if (!tmds)
2468                 return;
2469
2470         switch (tmds->dvo_chip) {
2471         case DVO_SIL164:
2472                 /* sil 164 */
2473                 radeon_i2c_put_byte(tmds->i2c_bus,
2474                                     tmds->slave_addr,
2475                                     0x08, 0x30);
2476                 radeon_i2c_put_byte(tmds->i2c_bus,
2477                                        tmds->slave_addr,
2478                                        0x09, 0x00);
2479                 radeon_i2c_put_byte(tmds->i2c_bus,
2480                                     tmds->slave_addr,
2481                                     0x0a, 0x90);
2482                 radeon_i2c_put_byte(tmds->i2c_bus,
2483                                     tmds->slave_addr,
2484                                     0x0c, 0x89);
2485                 radeon_i2c_put_byte(tmds->i2c_bus,
2486                                        tmds->slave_addr,
2487                                        0x08, 0x3b);
2488                 break;
2489         case DVO_SIL1178:
2490                 /* sil 1178 - untested */
2491                 /*
2492                  * 0x0f, 0x44
2493                  * 0x0f, 0x4c
2494                  * 0x0e, 0x01
2495                  * 0x0a, 0x80
2496                  * 0x09, 0x30
2497                  * 0x0c, 0xc9
2498                  * 0x0d, 0x70
2499                  * 0x08, 0x32
2500                  * 0x08, 0x33
2501                  */
2502                 break;
2503         default:
2504                 break;
2505         }
2506
2507 }
2508
2509 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2510 {
2511         struct drm_device *dev = encoder->dev;
2512         struct radeon_device *rdev = dev->dev_private;
2513         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2514         uint16_t offset;
2515         uint8_t blocks, slave_addr, rev;
2516         uint32_t index, id;
2517         uint32_t reg, val, and_mask, or_mask;
2518         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2519
2520         if (!tmds)
2521                 return false;
2522
2523         if (rdev->flags & RADEON_IS_IGP) {
2524                 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2525                 rev = RBIOS8(offset);
2526                 if (offset) {
2527                         rev = RBIOS8(offset);
2528                         if (rev > 1) {
2529                                 blocks = RBIOS8(offset + 3);
2530                                 index = offset + 4;
2531                                 while (blocks > 0) {
2532                                         id = RBIOS16(index);
2533                                         index += 2;
2534                                         switch (id >> 13) {
2535                                         case 0:
2536                                                 reg = (id & 0x1fff) * 4;
2537                                                 val = RBIOS32(index);
2538                                                 index += 4;
2539                                                 WREG32(reg, val);
2540                                                 break;
2541                                         case 2:
2542                                                 reg = (id & 0x1fff) * 4;
2543                                                 and_mask = RBIOS32(index);
2544                                                 index += 4;
2545                                                 or_mask = RBIOS32(index);
2546                                                 index += 4;
2547                                                 val = RREG32(reg);
2548                                                 val = (val & and_mask) | or_mask;
2549                                                 WREG32(reg, val);
2550                                                 break;
2551                                         case 3:
2552                                                 val = RBIOS16(index);
2553                                                 index += 2;
2554                                                 udelay(val);
2555                                                 break;
2556                                         case 4:
2557                                                 val = RBIOS16(index);
2558                                                 index += 2;
2559                                                 udelay(val * 1000);
2560                                                 break;
2561                                         case 6:
2562                                                 slave_addr = id & 0xff;
2563                                                 slave_addr >>= 1; /* 7 bit addressing */
2564                                                 index++;
2565                                                 reg = RBIOS8(index);
2566                                                 index++;
2567                                                 val = RBIOS8(index);
2568                                                 index++;
2569                                                 radeon_i2c_put_byte(tmds->i2c_bus,
2570                                                                     slave_addr,
2571                                                                     reg, val);
2572                                                 break;
2573                                         default:
2574                                                 DRM_ERROR("Unknown id %d\n", id >> 13);
2575                                                 break;
2576                                         }
2577                                         blocks--;
2578                                 }
2579                                 return true;
2580                         }
2581                 }
2582         } else {
2583                 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2584                 if (offset) {
2585                         index = offset + 10;
2586                         id = RBIOS16(index);
2587                         while (id != 0xffff) {
2588                                 index += 2;
2589                                 switch (id >> 13) {
2590                                 case 0:
2591                                         reg = (id & 0x1fff) * 4;
2592                                         val = RBIOS32(index);
2593                                         WREG32(reg, val);
2594                                         break;
2595                                 case 2:
2596                                         reg = (id & 0x1fff) * 4;
2597                                         and_mask = RBIOS32(index);
2598                                         index += 4;
2599                                         or_mask = RBIOS32(index);
2600                                         index += 4;
2601                                         val = RREG32(reg);
2602                                         val = (val & and_mask) | or_mask;
2603                                         WREG32(reg, val);
2604                                         break;
2605                                 case 4:
2606                                         val = RBIOS16(index);
2607                                         index += 2;
2608                                         udelay(val);
2609                                         break;
2610                                 case 5:
2611                                         reg = id & 0x1fff;
2612                                         and_mask = RBIOS32(index);
2613                                         index += 4;
2614                                         or_mask = RBIOS32(index);
2615                                         index += 4;
2616                                         val = RREG32_PLL(reg);
2617                                         val = (val & and_mask) | or_mask;
2618                                         WREG32_PLL(reg, val);
2619                                         break;
2620                                 case 6:
2621                                         reg = id & 0x1fff;
2622                                         val = RBIOS8(index);
2623                                         index += 1;
2624                                         radeon_i2c_put_byte(tmds->i2c_bus,
2625                                                             tmds->slave_addr,
2626                                                             reg, val);
2627                                         break;
2628                                 default:
2629                                         DRM_ERROR("Unknown id %d\n", id >> 13);
2630                                         break;
2631                                 }
2632                                 id = RBIOS16(index);
2633                         }
2634                         return true;
2635                 }
2636         }
2637         return false;
2638 }
2639
2640 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2641 {
2642         struct radeon_device *rdev = dev->dev_private;
2643
2644         if (offset) {
2645                 while (RBIOS16(offset)) {
2646                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
2647                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
2648                         uint32_t val, and_mask, or_mask;
2649                         uint32_t tmp;
2650
2651                         offset += 2;
2652                         switch (cmd) {
2653                         case 0:
2654                                 val = RBIOS32(offset);
2655                                 offset += 4;
2656                                 WREG32(addr, val);
2657                                 break;
2658                         case 1:
2659                                 val = RBIOS32(offset);
2660                                 offset += 4;
2661                                 WREG32(addr, val);
2662                                 break;
2663                         case 2:
2664                                 and_mask = RBIOS32(offset);
2665                                 offset += 4;
2666                                 or_mask = RBIOS32(offset);
2667                                 offset += 4;
2668                                 tmp = RREG32(addr);
2669                                 tmp &= and_mask;
2670                                 tmp |= or_mask;
2671                                 WREG32(addr, tmp);
2672                                 break;
2673                         case 3:
2674                                 and_mask = RBIOS32(offset);
2675                                 offset += 4;
2676                                 or_mask = RBIOS32(offset);
2677                                 offset += 4;
2678                                 tmp = RREG32(addr);
2679                                 tmp &= and_mask;
2680                                 tmp |= or_mask;
2681                                 WREG32(addr, tmp);
2682                                 break;
2683                         case 4:
2684                                 val = RBIOS16(offset);
2685                                 offset += 2;
2686                                 udelay(val);
2687                                 break;
2688                         case 5:
2689                                 val = RBIOS16(offset);
2690                                 offset += 2;
2691                                 switch (addr) {
2692                                 case 8:
2693                                         while (val--) {
2694                                                 if (!
2695                                                     (RREG32_PLL
2696                                                      (RADEON_CLK_PWRMGT_CNTL) &
2697                                                      RADEON_MC_BUSY))
2698                                                         break;
2699                                         }
2700                                         break;
2701                                 case 9:
2702                                         while (val--) {
2703                                                 if ((RREG32(RADEON_MC_STATUS) &
2704                                                      RADEON_MC_IDLE))
2705                                                         break;
2706                                         }
2707                                         break;
2708                                 default:
2709                                         break;
2710                                 }
2711                                 break;
2712                         default:
2713                                 break;
2714                         }
2715                 }
2716         }
2717 }
2718
2719 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
2720 {
2721         struct radeon_device *rdev = dev->dev_private;
2722
2723         if (offset) {
2724                 while (RBIOS8(offset)) {
2725                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2726                         uint8_t addr = (RBIOS8(offset) & 0x3f);
2727                         uint32_t val, shift, tmp;
2728                         uint32_t and_mask, or_mask;
2729
2730                         offset++;
2731                         switch (cmd) {
2732                         case 0:
2733                                 val = RBIOS32(offset);
2734                                 offset += 4;
2735                                 WREG32_PLL(addr, val);
2736                                 break;
2737                         case 1:
2738                                 shift = RBIOS8(offset) * 8;
2739                                 offset++;
2740                                 and_mask = RBIOS8(offset) << shift;
2741                                 and_mask |= ~(0xff << shift);
2742                                 offset++;
2743                                 or_mask = RBIOS8(offset) << shift;
2744                                 offset++;
2745                                 tmp = RREG32_PLL(addr);
2746                                 tmp &= and_mask;
2747                                 tmp |= or_mask;
2748                                 WREG32_PLL(addr, tmp);
2749                                 break;
2750                         case 2:
2751                         case 3:
2752                                 tmp = 1000;
2753                                 switch (addr) {
2754                                 case 1:
2755                                         udelay(150);
2756                                         break;
2757                                 case 2:
2758                                         udelay(1000);
2759                                         break;
2760                                 case 3:
2761                                         while (tmp--) {
2762                                                 if (!
2763                                                     (RREG32_PLL
2764                                                      (RADEON_CLK_PWRMGT_CNTL) &
2765                                                      RADEON_MC_BUSY))
2766                                                         break;
2767                                         }
2768                                         break;
2769                                 case 4:
2770                                         while (tmp--) {
2771                                                 if (RREG32_PLL
2772                                                     (RADEON_CLK_PWRMGT_CNTL) &
2773                                                     RADEON_DLL_READY)
2774                                                         break;
2775                                         }
2776                                         break;
2777                                 case 5:
2778                                         tmp =
2779                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2780                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
2781 #if 0
2782                                                 uint32_t mclk_cntl =
2783                                                     RREG32_PLL
2784                                                     (RADEON_MCLK_CNTL);
2785                                                 mclk_cntl &= 0xffff0000;
2786                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
2787                                                 WREG32_PLL(RADEON_MCLK_CNTL,
2788                                                            mclk_cntl);
2789                                                 udelay(10000);
2790 #endif
2791                                                 WREG32_PLL
2792                                                     (RADEON_CLK_PWRMGT_CNTL,
2793                                                      tmp &
2794                                                      ~RADEON_CG_NO1_DEBUG_0);
2795                                                 udelay(10000);
2796                                         }
2797                                         break;
2798                                 default:
2799                                         break;
2800                                 }
2801                                 break;
2802                         default:
2803                                 break;
2804                         }
2805                 }
2806         }
2807 }
2808
2809 static void combios_parse_ram_reset_table(struct drm_device *dev,
2810                                           uint16_t offset)
2811 {
2812         struct radeon_device *rdev = dev->dev_private;
2813         uint32_t tmp;
2814
2815         if (offset) {
2816                 uint8_t val = RBIOS8(offset);
2817                 while (val != 0xff) {
2818                         offset++;
2819
2820                         if (val == 0x0f) {
2821                                 uint32_t channel_complete_mask;
2822
2823                                 if (ASIC_IS_R300(rdev))
2824                                         channel_complete_mask =
2825                                             R300_MEM_PWRUP_COMPLETE;
2826                                 else
2827                                         channel_complete_mask =
2828                                             RADEON_MEM_PWRUP_COMPLETE;
2829                                 tmp = 20000;
2830                                 while (tmp--) {
2831                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
2832                                              channel_complete_mask) ==
2833                                             channel_complete_mask)
2834                                                 break;
2835                                 }
2836                         } else {
2837                                 uint32_t or_mask = RBIOS16(offset);
2838                                 offset += 2;
2839
2840                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2841                                 tmp &= RADEON_SDRAM_MODE_MASK;
2842                                 tmp |= or_mask;
2843                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2844
2845                                 or_mask = val << 24;
2846                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2847                                 tmp &= RADEON_B3MEM_RESET_MASK;
2848                                 tmp |= or_mask;
2849                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2850                         }
2851                         val = RBIOS8(offset);
2852                 }
2853         }
2854 }
2855
2856 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2857                                    int mem_addr_mapping)
2858 {
2859         struct radeon_device *rdev = dev->dev_private;
2860         uint32_t mem_cntl;
2861         uint32_t mem_size;
2862         uint32_t addr = 0;
2863
2864         mem_cntl = RREG32(RADEON_MEM_CNTL);
2865         if (mem_cntl & RV100_HALF_MODE)
2866                 ram /= 2;
2867         mem_size = ram;
2868         mem_cntl &= ~(0xff << 8);
2869         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2870         WREG32(RADEON_MEM_CNTL, mem_cntl);
2871         RREG32(RADEON_MEM_CNTL);
2872
2873         /* sdram reset ? */
2874
2875         /* something like this????  */
2876         while (ram--) {
2877                 addr = ram * 1024 * 1024;
2878                 /* write to each page */
2879                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2880                 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2881                 /* read back and verify */
2882                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2883                 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2884                         return 0;
2885         }
2886
2887         return mem_size;
2888 }
2889
2890 static void combios_write_ram_size(struct drm_device *dev)
2891 {
2892         struct radeon_device *rdev = dev->dev_private;
2893         uint8_t rev;
2894         uint16_t offset;
2895         uint32_t mem_size = 0;
2896         uint32_t mem_cntl = 0;
2897
2898         /* should do something smarter here I guess... */
2899         if (rdev->flags & RADEON_IS_IGP)
2900                 return;
2901
2902         /* first check detected mem table */
2903         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2904         if (offset) {
2905                 rev = RBIOS8(offset);
2906                 if (rev < 3) {
2907                         mem_cntl = RBIOS32(offset + 1);
2908                         mem_size = RBIOS16(offset + 5);
2909                         if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2910                             ((dev->pdev->device != 0x515e)
2911                              && (dev->pdev->device != 0x5969)))
2912                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
2913                 }
2914         }
2915
2916         if (!mem_size) {
2917                 offset =
2918                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2919                 if (offset) {
2920                         rev = RBIOS8(offset - 1);
2921                         if (rev < 1) {
2922                                 if (((rdev->flags & RADEON_FAMILY_MASK) <
2923                                      CHIP_R200)
2924                                     && ((dev->pdev->device != 0x515e)
2925                                         && (dev->pdev->device != 0x5969))) {
2926                                         int ram = 0;
2927                                         int mem_addr_mapping = 0;
2928
2929                                         while (RBIOS8(offset)) {
2930                                                 ram = RBIOS8(offset);
2931                                                 mem_addr_mapping =
2932                                                     RBIOS8(offset + 1);
2933                                                 if (mem_addr_mapping != 0x25)
2934                                                         ram *= 2;
2935                                                 mem_size =
2936                                                     combios_detect_ram(dev, ram,
2937                                                                        mem_addr_mapping);
2938                                                 if (mem_size)
2939                                                         break;
2940                                                 offset += 2;
2941                                         }
2942                                 } else
2943                                         mem_size = RBIOS8(offset);
2944                         } else {
2945                                 mem_size = RBIOS8(offset);
2946                                 mem_size *= 2;  /* convert to MB */
2947                         }
2948                 }
2949         }
2950
2951         mem_size *= (1024 * 1024);      /* convert to bytes */
2952         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2953 }
2954
2955 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2956 {
2957         uint16_t dyn_clk_info =
2958             combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2959
2960         if (dyn_clk_info)
2961                 combios_parse_pll_table(dev, dyn_clk_info);
2962 }
2963
2964 void radeon_combios_asic_init(struct drm_device *dev)
2965 {
2966         struct radeon_device *rdev = dev->dev_private;
2967         uint16_t table;
2968
2969         /* port hardcoded mac stuff from radeonfb */
2970         if (rdev->bios == NULL)
2971                 return;
2972
2973         /* ASIC INIT 1 */
2974         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2975         if (table)
2976                 combios_parse_mmio_table(dev, table);
2977
2978         /* PLL INIT */
2979         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2980         if (table)
2981                 combios_parse_pll_table(dev, table);
2982
2983         /* ASIC INIT 2 */
2984         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2985         if (table)
2986                 combios_parse_mmio_table(dev, table);
2987
2988         if (!(rdev->flags & RADEON_IS_IGP)) {
2989                 /* ASIC INIT 4 */
2990                 table =
2991                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2992                 if (table)
2993                         combios_parse_mmio_table(dev, table);
2994
2995                 /* RAM RESET */
2996                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2997                 if (table)
2998                         combios_parse_ram_reset_table(dev, table);
2999
3000                 /* ASIC INIT 3 */
3001                 table =
3002                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3003                 if (table)
3004                         combios_parse_mmio_table(dev, table);
3005
3006                 /* write CONFIG_MEMSIZE */
3007                 combios_write_ram_size(dev);
3008         }
3009
3010         /* DYN CLK 1 */
3011         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3012         if (table)
3013                 combios_parse_pll_table(dev, table);
3014
3015 }
3016
3017 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3018 {
3019         struct radeon_device *rdev = dev->dev_private;
3020         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3021
3022         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3023         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3024         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3025
3026         /* let the bios control the backlight */
3027         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3028
3029         /* tell the bios not to handle mode switching */
3030         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3031                            RADEON_ACC_MODE_CHANGE);
3032
3033         /* tell the bios a driver is loaded */
3034         bios_7_scratch |= RADEON_DRV_LOADED;
3035
3036         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3037         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3038         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3039 }
3040
3041 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3042 {
3043         struct drm_device *dev = encoder->dev;
3044         struct radeon_device *rdev = dev->dev_private;
3045         uint32_t bios_6_scratch;
3046
3047         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3048
3049         if (lock)
3050                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3051         else
3052                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3053
3054         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3055 }
3056
3057 void
3058 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3059                                       struct drm_encoder *encoder,
3060                                       bool connected)
3061 {
3062         struct drm_device *dev = connector->dev;
3063         struct radeon_device *rdev = dev->dev_private;
3064         struct radeon_connector *radeon_connector =
3065             to_radeon_connector(connector);
3066         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3067         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3068         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3069
3070         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3071             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3072                 if (connected) {
3073                         DRM_DEBUG("TV1 connected\n");
3074                         /* fix me */
3075                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3076                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3077                         bios_5_scratch |= RADEON_TV1_ON;
3078                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
3079                 } else {
3080                         DRM_DEBUG("TV1 disconnected\n");
3081                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3082                         bios_5_scratch &= ~RADEON_TV1_ON;
3083                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3084                 }
3085         }
3086         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3087             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3088                 if (connected) {
3089                         DRM_DEBUG("LCD1 connected\n");
3090                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
3091                         bios_5_scratch |= RADEON_LCD1_ON;
3092                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3093                 } else {
3094                         DRM_DEBUG("LCD1 disconnected\n");
3095                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3096                         bios_5_scratch &= ~RADEON_LCD1_ON;
3097                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3098                 }
3099         }
3100         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3101             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3102                 if (connected) {
3103                         DRM_DEBUG("CRT1 connected\n");
3104                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3105                         bios_5_scratch |= RADEON_CRT1_ON;
3106                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3107                 } else {
3108                         DRM_DEBUG("CRT1 disconnected\n");
3109                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3110                         bios_5_scratch &= ~RADEON_CRT1_ON;
3111                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3112                 }
3113         }
3114         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3115             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3116                 if (connected) {
3117                         DRM_DEBUG("CRT2 connected\n");
3118                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3119                         bios_5_scratch |= RADEON_CRT2_ON;
3120                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3121                 } else {
3122                         DRM_DEBUG("CRT2 disconnected\n");
3123                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3124                         bios_5_scratch &= ~RADEON_CRT2_ON;
3125                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3126                 }
3127         }
3128         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3129             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3130                 if (connected) {
3131                         DRM_DEBUG("DFP1 connected\n");
3132                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
3133                         bios_5_scratch |= RADEON_DFP1_ON;
3134                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3135                 } else {
3136                         DRM_DEBUG("DFP1 disconnected\n");
3137                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3138                         bios_5_scratch &= ~RADEON_DFP1_ON;
3139                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3140                 }
3141         }
3142         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3143             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3144                 if (connected) {
3145                         DRM_DEBUG("DFP2 connected\n");
3146                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
3147                         bios_5_scratch |= RADEON_DFP2_ON;
3148                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3149                 } else {
3150                         DRM_DEBUG("DFP2 disconnected\n");
3151                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3152                         bios_5_scratch &= ~RADEON_DFP2_ON;
3153                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3154                 }
3155         }
3156         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3157         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3158 }
3159
3160 void
3161 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3162 {
3163         struct drm_device *dev = encoder->dev;
3164         struct radeon_device *rdev = dev->dev_private;
3165         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3166         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3167
3168         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3169                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3170                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3171         }
3172         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3173                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3174                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3175         }
3176         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3177                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3178                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3179         }
3180         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3181                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3182                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3183         }
3184         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3185                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3186                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3187         }
3188         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3189                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3190                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3191         }
3192         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3193 }
3194
3195 void
3196 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3197 {
3198         struct drm_device *dev = encoder->dev;
3199         struct radeon_device *rdev = dev->dev_private;
3200         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3201         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3202
3203         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3204                 if (on)
3205                         bios_6_scratch |= RADEON_TV_DPMS_ON;
3206                 else
3207                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3208         }
3209         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3210                 if (on)
3211                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
3212                 else
3213                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3214         }
3215         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3216                 if (on)
3217                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
3218                 else
3219                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3220         }
3221         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3222                 if (on)
3223                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
3224                 else
3225                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3226         }
3227         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3228 }