Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/radeon_atombios.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include "atom-bits.h"
  32
  33 /* from radeon_encoder.c */
  34 extern uint32_t
  35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  36                         uint8_t dac);
  37 extern void radeon_link_encoder_connector(struct drm_device *dev);
  38 extern void
  39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum,
  40                         uint32_t supported_device);
  41
  42 /* from radeon_connector.c */
  43 extern void
  44 radeon_add_atom_connector(struct drm_device *dev,
  45                           uint32_t connector_id,
  46                           uint32_t supported_device,
  47                           int connector_type,
  48                           struct radeon_i2c_bus_rec *i2c_bus,
  49                           uint32_t igp_lane_info,
  50                           uint16_t connector_object_id,
  51                           struct radeon_hpd *hpd,
  52                           struct radeon_router *router);
  53
  54 /* from radeon_legacy_encoder.c */
  55 extern void
  56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
  57                           uint32_t supported_device);
  58
  59 union atom_supported_devices {
  60         struct _ATOM_SUPPORTED_DEVICES_INFO info;
  61         struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
  62         struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
  63 };
  64
  65 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
  66                                                                uint8_t id)
  67 {
  68         struct atom_context *ctx = rdev->mode_info.atom_context;
  69         ATOM_GPIO_I2C_ASSIGMENT *gpio;
  70         struct radeon_i2c_bus_rec i2c;
  71         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
  72         struct _ATOM_GPIO_I2C_INFO *i2c_info;
  73         uint16_t data_offset, size;
  74         int i, num_indices;
  75
  76         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
  77         i2c.valid = false;
  78
  79         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
  80                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
  81
  82                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
  83                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
  84
  85                 for (i = 0; i < num_indices; i++) {
  86                         gpio = &i2c_info->asGPIO_Info[i];
  87
  88                         /* some evergreen boards have bad data for this entry */
  89                         if (ASIC_IS_DCE4(rdev)) {
  90                                 if ((i == 7) &&
  91                                     (gpio->usClkMaskRegisterIndex == 0x1936) &&
  92                                     (gpio->sucI2cId.ucAccess == 0)) {
  93                                         gpio->sucI2cId.ucAccess = 0x97;
  94                                         gpio->ucDataMaskShift = 8;
  95                                         gpio->ucDataEnShift = 8;
  96                                         gpio->ucDataY_Shift = 8;
  97                                         gpio->ucDataA_Shift = 8;
  98                                 }
  99                         }
 100
 101                         /* some DCE3 boards have bad data for this entry */
 102                         if (ASIC_IS_DCE3(rdev)) {
 103                                 if ((i == 4) &&
 104                                     (gpio->usClkMaskRegisterIndex == 0x1fda) &&
 105                                     (gpio->sucI2cId.ucAccess == 0x94))
 106                                         gpio->sucI2cId.ucAccess = 0x14;
 107                         }
 108
 109                         if (gpio->sucI2cId.ucAccess == id) {
 110                                 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 111                                 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 112                                 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 113                                 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 114                                 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 115                                 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 116                                 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 117                                 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 118                                 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 119                                 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 120                                 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 121                                 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 122                                 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 123                                 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 124                                 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 125                                 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 126
 127                                 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 128                                         i2c.hw_capable = true;
 129                                 else
 130                                         i2c.hw_capable = false;
 131
 132                                 if (gpio->sucI2cId.ucAccess == 0xa0)
 133                                         i2c.mm_i2c = true;
 134                                 else
 135                                         i2c.mm_i2c = false;
 136
 137                                 i2c.i2c_id = gpio->sucI2cId.ucAccess;
 138
 139                                 if (i2c.mask_clk_reg)
 140                                         i2c.valid = true;
 141                                 break;
 142                         }
 143                 }
 144         }
 145
 146         return i2c;
 147 }
 148
 149 void radeon_atombios_i2c_init(struct radeon_device *rdev)
 150 {
 151         struct atom_context *ctx = rdev->mode_info.atom_context;
 152         ATOM_GPIO_I2C_ASSIGMENT *gpio;
 153         struct radeon_i2c_bus_rec i2c;
 154         int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
 155         struct _ATOM_GPIO_I2C_INFO *i2c_info;
 156         uint16_t data_offset, size;
 157         int i, num_indices;
 158         char stmp[32];
 159
 160         memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
 161
 162         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 163                 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
 164
 165                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 166                         sizeof(ATOM_GPIO_I2C_ASSIGMENT);
 167
 168                 for (i = 0; i < num_indices; i++) {
 169                         gpio = &i2c_info->asGPIO_Info[i];
 170                         i2c.valid = false;
 171
 172                         /* some evergreen boards have bad data for this entry */
 173                         if (ASIC_IS_DCE4(rdev)) {
 174                                 if ((i == 7) &&
 175                                     (gpio->usClkMaskRegisterIndex == 0x1936) &&
 176                                     (gpio->sucI2cId.ucAccess == 0)) {
 177                                         gpio->sucI2cId.ucAccess = 0x97;
 178                                         gpio->ucDataMaskShift = 8;
 179                                         gpio->ucDataEnShift = 8;
 180                                         gpio->ucDataY_Shift = 8;
 181                                         gpio->ucDataA_Shift = 8;
 182                                 }
 183                         }
 184
 185                         /* some DCE3 boards have bad data for this entry */
 186                         if (ASIC_IS_DCE3(rdev)) {
 187                                 if ((i == 4) &&
 188                                     (gpio->usClkMaskRegisterIndex == 0x1fda) &&
 189                                     (gpio->sucI2cId.ucAccess == 0x94))
 190                                         gpio->sucI2cId.ucAccess = 0x14;
 191                         }
 192
 193                         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
 194                         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
 195                         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
 196                         i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
 197                         i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
 198                         i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
 199                         i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
 200                         i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
 201                         i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
 202                         i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
 203                         i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
 204                         i2c.en_data_mask = (1 << gpio->ucDataEnShift);
 205                         i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
 206                         i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
 207                         i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
 208                         i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
 209
 210                         if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
 211                                 i2c.hw_capable = true;
 212                         else
 213                                 i2c.hw_capable = false;
 214
 215                         if (gpio->sucI2cId.ucAccess == 0xa0)
 216                                 i2c.mm_i2c = true;
 217                         else
 218                                 i2c.mm_i2c = false;
 219
 220                         i2c.i2c_id = gpio->sucI2cId.ucAccess;
 221
 222                         if (i2c.mask_clk_reg) {
 223                                 i2c.valid = true;
 224                                 sprintf(stmp, "0x%x", i2c.i2c_id);
 225                                 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
 226                         }
 227                 }
 228         }
 229 }
 230
 231 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
 232                                                         u8 id)
 233 {
 234         struct atom_context *ctx = rdev->mode_info.atom_context;
 235         struct radeon_gpio_rec gpio;
 236         int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
 237         struct _ATOM_GPIO_PIN_LUT *gpio_info;
 238         ATOM_GPIO_PIN_ASSIGNMENT *pin;
 239         u16 data_offset, size;
 240         int i, num_indices;
 241
 242         memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
 243         gpio.valid = false;
 244
 245         if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
 246                 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
 247
 248                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
 249                         sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
 250
 251                 for (i = 0; i < num_indices; i++) {
 252                         pin = &gpio_info->asGPIO_Pin[i];
 253                         if (id == pin->ucGPIO_ID) {
 254                                 gpio.id = pin->ucGPIO_ID;
 255                                 gpio.reg = pin->usGpioPin_AIndex * 4;
 256                                 gpio.mask = (1 << pin->ucGpioPinBitShift);
 257                                 gpio.valid = true;
 258                                 break;
 259                         }
 260                 }
 261         }
 262
 263         return gpio;
 264 }
 265
 266 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
 267                                                             struct radeon_gpio_rec *gpio)
 268 {
 269         struct radeon_hpd hpd;
 270         u32 reg;
 271
 272         memset(&hpd, 0, sizeof(struct radeon_hpd));
 273
 274         if (ASIC_IS_DCE4(rdev))
 275                 reg = EVERGREEN_DC_GPIO_HPD_A;
 276         else
 277                 reg = AVIVO_DC_GPIO_HPD_A;
 278
 279         hpd.gpio = *gpio;
 280         if (gpio->reg == reg) {
 281                 switch(gpio->mask) {
 282                 case (1 << 0):
 283                         hpd.hpd = RADEON_HPD_1;
 284                         break;
 285                 case (1 << 8):
 286                         hpd.hpd = RADEON_HPD_2;
 287                         break;
 288                 case (1 << 16):
 289                         hpd.hpd = RADEON_HPD_3;
 290                         break;
 291                 case (1 << 24):
 292                         hpd.hpd = RADEON_HPD_4;
 293                         break;
 294                 case (1 << 26):
 295                         hpd.hpd = RADEON_HPD_5;
 296                         break;
 297                 case (1 << 28):
 298                         hpd.hpd = RADEON_HPD_6;
 299                         break;
 300                 default:
 301                         hpd.hpd = RADEON_HPD_NONE;
 302                         break;
 303                 }
 304         } else
 305                 hpd.hpd = RADEON_HPD_NONE;
 306         return hpd;
 307 }
 308
 309 static bool radeon_atom_apply_quirks(struct drm_device *dev,
 310                                      uint32_t supported_device,
 311                                      int *connector_type,
 312                                      struct radeon_i2c_bus_rec *i2c_bus,
 313                                      uint16_t *line_mux,
 314                                      struct radeon_hpd *hpd)
 315 {
 316
 317         /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
 318         if ((dev->pdev->device == 0x791e) &&
 319             (dev->pdev->subsystem_vendor == 0x1043) &&
 320             (dev->pdev->subsystem_device == 0x826d)) {
 321                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 322                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 323                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 324         }
 325
 326         /* Asrock RS600 board lists the DVI port as HDMI */
 327         if ((dev->pdev->device == 0x7941) &&
 328             (dev->pdev->subsystem_vendor == 0x1849) &&
 329             (dev->pdev->subsystem_device == 0x7941)) {
 330                 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
 331                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 332                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 333         }
 334
 335         /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
 336         if ((dev->pdev->device == 0x796e) &&
 337             (dev->pdev->subsystem_vendor == 0x1462) &&
 338             (dev->pdev->subsystem_device == 0x7302)) {
 339                 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
 340                     (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
 341                         return false;
 342         }
 343
 344         /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
 345         if ((dev->pdev->device == 0x7941) &&
 346             (dev->pdev->subsystem_vendor == 0x147b) &&
 347             (dev->pdev->subsystem_device == 0x2412)) {
 348                 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
 349                         return false;
 350         }
 351
 352         /* Falcon NW laptop lists vga ddc line for LVDS */
 353         if ((dev->pdev->device == 0x5653) &&
 354             (dev->pdev->subsystem_vendor == 0x1462) &&
 355             (dev->pdev->subsystem_device == 0x0291)) {
 356                 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
 357                         i2c_bus->valid = false;
 358                         *line_mux = 53;
 359                 }
 360         }
 361
 362         /* HIS X1300 is DVI+VGA, not DVI+DVI */
 363         if ((dev->pdev->device == 0x7146) &&
 364             (dev->pdev->subsystem_vendor == 0x17af) &&
 365             (dev->pdev->subsystem_device == 0x2058)) {
 366                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 367                         return false;
 368         }
 369
 370         /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
 371         if ((dev->pdev->device == 0x7142) &&
 372             (dev->pdev->subsystem_vendor == 0x1458) &&
 373             (dev->pdev->subsystem_device == 0x2134)) {
 374                 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
 375                         return false;
 376         }
 377
 378
 379         /* Funky macbooks */
 380         if ((dev->pdev->device == 0x71C5) &&
 381             (dev->pdev->subsystem_vendor == 0x106b) &&
 382             (dev->pdev->subsystem_device == 0x0080)) {
 383                 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
 384                     (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
 385                         return false;
 386                 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
 387                         *line_mux = 0x90;
 388         }
 389
 390         /* mac rv630 */
 391         if ((dev->pdev->device == 0x9588) &&
 392             (dev->pdev->subsystem_vendor == 0x106b) &&
 393             (dev->pdev->subsystem_device == 0x00a6)) {
 394                 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
 395                     (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
 396                         *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
 397                         *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
 398                 }
 399         }
 400
 401         /* ASUS HD 3600 XT board lists the DVI port as HDMI */
 402         if ((dev->pdev->device == 0x9598) &&
 403             (dev->pdev->subsystem_vendor == 0x1043) &&
 404             (dev->pdev->subsystem_device == 0x01da)) {
 405                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 406                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 407                 }
 408         }
 409
 410         /* ASUS HD 3600 board lists the DVI port as HDMI */
 411         if ((dev->pdev->device == 0x9598) &&
 412             (dev->pdev->subsystem_vendor == 0x1043) &&
 413             (dev->pdev->subsystem_device == 0x01e4)) {
 414                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 415                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 416                 }
 417         }
 418
 419         /* ASUS HD 3450 board lists the DVI port as HDMI */
 420         if ((dev->pdev->device == 0x95C5) &&
 421             (dev->pdev->subsystem_vendor == 0x1043) &&
 422             (dev->pdev->subsystem_device == 0x01e2)) {
 423                 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 424                         *connector_type = DRM_MODE_CONNECTOR_DVII;
 425                 }
 426         }
 427
 428         /* some BIOSes seem to report DAC on HDMI - usually this is a board with
 429          * HDMI + VGA reporting as HDMI
 430          */
 431         if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
 432                 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
 433                         *connector_type = DRM_MODE_CONNECTOR_VGA;
 434                         *line_mux = 0;
 435                 }
 436         }
 437
 438         /* Acer laptop (Acer TravelMate 5730G) has an HDMI port
 439          * on the laptop and a DVI port on the docking station and
 440          * both share the same encoder, hpd pin, and ddc line.
 441          * So while the bios table is technically correct,
 442          * we drop the DVI port here since xrandr has no concept of
 443          * encoders and will try and drive both connectors
 444          * with different crtcs which isn't possible on the hardware
 445          * side and leaves no crtcs for LVDS or VGA.
 446          */
 447         if ((dev->pdev->device == 0x95c4) &&
 448             (dev->pdev->subsystem_vendor == 0x1025) &&
 449             (dev->pdev->subsystem_device == 0x013c)) {
 450                 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
 451                     (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
 452                         /* actually it's a DVI-D port not DVI-I */
 453                         *connector_type = DRM_MODE_CONNECTOR_DVID;
 454                         return false;
 455                 }
 456         }
 457
 458         /* XFX Pine Group device rv730 reports no VGA DDC lines
 459          * even though they are wired up to record 0x93
 460          */
 461         if ((dev->pdev->device == 0x9498) &&
 462             (dev->pdev->subsystem_vendor == 0x1682) &&
 463             (dev->pdev->subsystem_device == 0x2452)) {
 464                 struct radeon_device *rdev = dev->dev_private;
 465                 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
 466         }
 467         return true;
 468 }
 469
 470 const int supported_devices_connector_convert[] = {
 471         DRM_MODE_CONNECTOR_Unknown,
 472         DRM_MODE_CONNECTOR_VGA,
 473         DRM_MODE_CONNECTOR_DVII,
 474         DRM_MODE_CONNECTOR_DVID,
 475         DRM_MODE_CONNECTOR_DVIA,
 476         DRM_MODE_CONNECTOR_SVIDEO,
 477         DRM_MODE_CONNECTOR_Composite,
 478         DRM_MODE_CONNECTOR_LVDS,
 479         DRM_MODE_CONNECTOR_Unknown,
 480         DRM_MODE_CONNECTOR_Unknown,
 481         DRM_MODE_CONNECTOR_HDMIA,
 482         DRM_MODE_CONNECTOR_HDMIB,
 483         DRM_MODE_CONNECTOR_Unknown,
 484         DRM_MODE_CONNECTOR_Unknown,
 485         DRM_MODE_CONNECTOR_9PinDIN,
 486         DRM_MODE_CONNECTOR_DisplayPort
 487 };
 488
 489 const uint16_t supported_devices_connector_object_id_convert[] = {
 490         CONNECTOR_OBJECT_ID_NONE,
 491         CONNECTOR_OBJECT_ID_VGA,
 492         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
 493         CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
 494         CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
 495         CONNECTOR_OBJECT_ID_COMPOSITE,
 496         CONNECTOR_OBJECT_ID_SVIDEO,
 497         CONNECTOR_OBJECT_ID_LVDS,
 498         CONNECTOR_OBJECT_ID_9PIN_DIN,
 499         CONNECTOR_OBJECT_ID_9PIN_DIN,
 500         CONNECTOR_OBJECT_ID_DISPLAYPORT,
 501         CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
 502         CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
 503         CONNECTOR_OBJECT_ID_SVIDEO
 504 };
 505
 506 const int object_connector_convert[] = {
 507         DRM_MODE_CONNECTOR_Unknown,
 508         DRM_MODE_CONNECTOR_DVII,
 509         DRM_MODE_CONNECTOR_DVII,
 510         DRM_MODE_CONNECTOR_DVID,
 511         DRM_MODE_CONNECTOR_DVID,
 512         DRM_MODE_CONNECTOR_VGA,
 513         DRM_MODE_CONNECTOR_Composite,
 514         DRM_MODE_CONNECTOR_SVIDEO,
 515         DRM_MODE_CONNECTOR_Unknown,
 516         DRM_MODE_CONNECTOR_Unknown,
 517         DRM_MODE_CONNECTOR_9PinDIN,
 518         DRM_MODE_CONNECTOR_Unknown,
 519         DRM_MODE_CONNECTOR_HDMIA,
 520         DRM_MODE_CONNECTOR_HDMIB,
 521         DRM_MODE_CONNECTOR_LVDS,
 522         DRM_MODE_CONNECTOR_9PinDIN,
 523         DRM_MODE_CONNECTOR_Unknown,
 524         DRM_MODE_CONNECTOR_Unknown,
 525         DRM_MODE_CONNECTOR_Unknown,
 526         DRM_MODE_CONNECTOR_DisplayPort,
 527         DRM_MODE_CONNECTOR_eDP,
 528         DRM_MODE_CONNECTOR_Unknown
 529 };
 530
 531 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
 532 {
 533         struct radeon_device *rdev = dev->dev_private;
 534         struct radeon_mode_info *mode_info = &rdev->mode_info;
 535         struct atom_context *ctx = mode_info->atom_context;
 536         int index = GetIndexIntoMasterTable(DATA, Object_Header);
 537         u16 size, data_offset;
 538         u8 frev, crev;
 539         ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
 540         ATOM_OBJECT_TABLE *router_obj;
 541         ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
 542         ATOM_OBJECT_HEADER *obj_header;
 543         int i, j, k, path_size, device_support;
 544         int connector_type;
 545         u16 igp_lane_info, conn_id, connector_object_id;
 546         struct radeon_i2c_bus_rec ddc_bus;
 547         struct radeon_router router;
 548         struct radeon_gpio_rec gpio;
 549         struct radeon_hpd hpd;
 550
 551         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
 552                 return false;
 553
 554         if (crev < 2)
 555                 return false;
 556
 557         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
 558         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
 559             (ctx->bios + data_offset +
 560              le16_to_cpu(obj_header->usDisplayPathTableOffset));
 561         con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
 562             (ctx->bios + data_offset +
 563              le16_to_cpu(obj_header->usConnectorObjectTableOffset));
 564         router_obj = (ATOM_OBJECT_TABLE *)
 565                 (ctx->bios + data_offset +
 566                  le16_to_cpu(obj_header->usRouterObjectTableOffset));
 567         device_support = le16_to_cpu(obj_header->usDeviceSupport);
 568
 569         path_size = 0;
 570         for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
 571                 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
 572                 ATOM_DISPLAY_OBJECT_PATH *path;
 573                 addr += path_size;
 574                 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
 575                 path_size += le16_to_cpu(path->usSize);
 576
 577                 if (device_support & le16_to_cpu(path->usDeviceTag)) {
 578                         uint8_t con_obj_id, con_obj_num, con_obj_type;
 579
 580                         con_obj_id =
 581                             (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
 582                             >> OBJECT_ID_SHIFT;
 583                         con_obj_num =
 584                             (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
 585                             >> ENUM_ID_SHIFT;
 586                         con_obj_type =
 587                             (le16_to_cpu(path->usConnObjectId) &
 588                              OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 589
 590                         /* TODO CV support */
 591                         if (le16_to_cpu(path->usDeviceTag) ==
 592                                 ATOM_DEVICE_CV_SUPPORT)
 593                                 continue;
 594
 595                         /* IGP chips */
 596                         if ((rdev->flags & RADEON_IS_IGP) &&
 597                             (con_obj_id ==
 598                              CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
 599                                 uint16_t igp_offset = 0;
 600                                 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
 601
 602                                 index =
 603                                     GetIndexIntoMasterTable(DATA,
 604                                                             IntegratedSystemInfo);
 605
 606                                 if (atom_parse_data_header(ctx, index, &size, &frev,
 607                                                            &crev, &igp_offset)) {
 608
 609                                         if (crev >= 2) {
 610                                                 igp_obj =
 611                                                         (ATOM_INTEGRATED_SYSTEM_INFO_V2
 612                                                          *) (ctx->bios + igp_offset);
 613
 614                                                 if (igp_obj) {
 615                                                         uint32_t slot_config, ct;
 616
 617                                                         if (con_obj_num == 1)
 618                                                                 slot_config =
 619                                                                         igp_obj->
 620                                                                         ulDDISlot1Config;
 621                                                         else
 622                                                                 slot_config =
 623                                                                         igp_obj->
 624                                                                         ulDDISlot2Config;
 625
 626                                                         ct = (slot_config >> 16) & 0xff;
 627                                                         connector_type =
 628                                                                 object_connector_convert
 629                                                                 [ct];
 630                                                         connector_object_id = ct;
 631                                                         igp_lane_info =
 632                                                                 slot_config & 0xffff;
 633                                                 } else
 634                                                         continue;
 635                                         } else
 636                                                 continue;
 637                                 } else {
 638                                         igp_lane_info = 0;
 639                                         connector_type =
 640                                                 object_connector_convert[con_obj_id];
 641                                         connector_object_id = con_obj_id;
 642                                 }
 643                         } else {
 644                                 igp_lane_info = 0;
 645                                 connector_type =
 646                                     object_connector_convert[con_obj_id];
 647                                 connector_object_id = con_obj_id;
 648                         }
 649
 650                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
 651                                 continue;
 652
 653                         router.ddc_valid = false;
 654                         router.cd_valid = false;
 655                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
 656                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 657
 658                                 grph_obj_id =
 659                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 660                                      OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 661                                 grph_obj_num =
 662                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 663                                      ENUM_ID_MASK) >> ENUM_ID_SHIFT;
 664                                 grph_obj_type =
 665                                     (le16_to_cpu(path->usGraphicObjIds[j]) &
 666                                      OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
 667
 668                                 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
 669                                         u16 encoder_obj = le16_to_cpu(path->usGraphicObjIds[j]);
 670
 671                                         radeon_add_atom_encoder(dev,
 672                                                                 encoder_obj,
 673                                                                 le16_to_cpu
 674                                                                 (path->
 675                                                                  usDeviceTag));
 676
 677                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
 678                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
 679                                                 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
 680                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
 681                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
 682                                                                 (ctx->bios + data_offset +
 683                                                                  le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
 684                                                         ATOM_I2C_RECORD *i2c_record;
 685                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 686                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
 687                                                         ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
 688                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
 689                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
 690                                                                 (ctx->bios + data_offset +
 691                                                                  le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
 692                                                         int enum_id;
 693
 694                                                         router.router_id = router_obj_id;
 695                                                         for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst;
 696                                                              enum_id++) {
 697                                                                 if (le16_to_cpu(path->usConnObjectId) ==
 698                                                                     le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id]))
 699                                                                         break;
 700                                                         }
 701
 702                                                         while (record->ucRecordType > 0 &&
 703                                                                record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
 704                                                                 switch (record->ucRecordType) {
 705                                                                 case ATOM_I2C_RECORD_TYPE:
 706                                                                         i2c_record =
 707                                                                                 (ATOM_I2C_RECORD *)
 708                                                                                 record;
 709                                                                         i2c_config =
 710                                                                                 (ATOM_I2C_ID_CONFIG_ACCESS *)
 711                                                                                 &i2c_record->sucI2cId;
 712                                                                         router.i2c_info =
 713                                                                                 radeon_lookup_i2c_gpio(rdev,
 714                                                                                                        i2c_config->
 715                                                                                                        ucAccess);
 716                                                                         router.i2c_addr = i2c_record->ucI2CAddr >> 1;
 717                                                                         break;
 718                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
 719                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
 720                                                                                 record;
 721                                                                         router.ddc_valid = true;
 722                                                                         router.ddc_mux_type = ddc_path->ucMuxType;
 723                                                                         router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
 724                                                                         router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
 725                                                                         break;
 726                                                                 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
 727                                                                         cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
 728                                                                                 record;
 729                                                                         router.cd_valid = true;
 730                                                                         router.cd_mux_type = cd_path->ucMuxType;
 731                                                                         router.cd_mux_control_pin = cd_path->ucMuxControlPin;
 732                                                                         router.cd_mux_state = cd_path->ucMuxState[enum_id];
 733                                                                         break;
 734                                                                 }
 735                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
 736                                                                         ((char *)record + record->ucRecordSize);
 737                                                         }
 738                                                 }
 739                                         }
 740                                 }
 741                         }
 742
 743                         /* look up gpio for ddc, hpd */
 744                         ddc_bus.valid = false;
 745                         hpd.hpd = RADEON_HPD_NONE;
 746                         if ((le16_to_cpu(path->usDeviceTag) &
 747                              (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
 748                                 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
 749                                         if (le16_to_cpu(path->usConnObjectId) ==
 750                                             le16_to_cpu(con_obj->asObjects[j].
 751                                                         usObjectID)) {
 752                                                 ATOM_COMMON_RECORD_HEADER
 753                                                     *record =
 754                                                     (ATOM_COMMON_RECORD_HEADER
 755                                                      *)
 756                                                     (ctx->bios + data_offset +
 757                                                      le16_to_cpu(con_obj->
 758                                                                  asObjects[j].
 759                                                                  usRecordOffset));
 760                                                 ATOM_I2C_RECORD *i2c_record;
 761                                                 ATOM_HPD_INT_RECORD *hpd_record;
 762                                                 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
 763
 764                                                 while (record->ucRecordType > 0
 765                                                        && record->
 766                                                        ucRecordType <=
 767                                                        ATOM_MAX_OBJECT_RECORD_NUMBER) {
 768                                                         switch (record->ucRecordType) {
 769                                                         case ATOM_I2C_RECORD_TYPE:
 770                                                                 i2c_record =
 771                                                                     (ATOM_I2C_RECORD *)
 772                                                                         record;
 773                                                                 i2c_config =
 774                                                                         (ATOM_I2C_ID_CONFIG_ACCESS *)
 775                                                                         &i2c_record->sucI2cId;
 776                                                                 ddc_bus = radeon_lookup_i2c_gpio(rdev,
 777                                                                                                  i2c_config->
 778                                                                                                  ucAccess);
 779                                                                 break;
 780                                                         case ATOM_HPD_INT_RECORD_TYPE:
 781                                                                 hpd_record =
 782                                                                         (ATOM_HPD_INT_RECORD *)
 783                                                                         record;
 784                                                                 gpio = radeon_lookup_gpio(rdev,
 785                                                                                           hpd_record->ucHPDIntGPIOID);
 786                                                                 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
 787                                                                 hpd.plugged_state = hpd_record->ucPlugged_PinState;
 788                                                                 break;
 789                                                         }
 790                                                         record =
 791                                                             (ATOM_COMMON_RECORD_HEADER
 792                                                              *) ((char *)record
 793                                                                  +
 794                                                                  record->
 795                                                                  ucRecordSize);
 796                                                 }
 797                                                 break;
 798                                         }
 799                                 }
 800                         }
 801
 802                         /* needed for aux chan transactions */
 803                         ddc_bus.hpd = hpd.hpd;
 804
 805                         conn_id = le16_to_cpu(path->usConnObjectId);
 806
 807                         if (!radeon_atom_apply_quirks
 808                             (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
 809                              &ddc_bus, &conn_id, &hpd))
 810                                 continue;
 811
 812                         radeon_add_atom_connector(dev,
 813                                                   conn_id,
 814                                                   le16_to_cpu(path->
 815                                                               usDeviceTag),
 816                                                   connector_type, &ddc_bus,
 817                                                   igp_lane_info,
 818                                                   connector_object_id,
 819                                                   &hpd,
 820                                                   &router);
 821
 822                 }
 823         }
 824
 825         radeon_link_encoder_connector(dev);
 826
 827         return true;
 828 }
 829
 830 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
 831                                                  int connector_type,
 832                                                  uint16_t devices)
 833 {
 834         struct radeon_device *rdev = dev->dev_private;
 835
 836         if (rdev->flags & RADEON_IS_IGP) {
 837                 return supported_devices_connector_object_id_convert
 838                         [connector_type];
 839         } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
 840                     (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
 841                    (devices & ATOM_DEVICE_DFP2_SUPPORT))  {
 842                 struct radeon_mode_info *mode_info = &rdev->mode_info;
 843                 struct atom_context *ctx = mode_info->atom_context;
 844                 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
 845                 uint16_t size, data_offset;
 846                 uint8_t frev, crev;
 847                 ATOM_XTMDS_INFO *xtmds;
 848
 849                 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
 850                         xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
 851
 852                         if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
 853                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 854                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
 855                                 else
 856                                         return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
 857                         } else {
 858                                 if (connector_type == DRM_MODE_CONNECTOR_DVII)
 859                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
 860                                 else
 861                                         return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
 862                         }
 863                 } else
 864                         return supported_devices_connector_object_id_convert
 865                                 [connector_type];
 866         } else {
 867                 return supported_devices_connector_object_id_convert
 868                         [connector_type];
 869         }
 870 }
 871
 872 struct bios_connector {
 873         bool valid;
 874         uint16_t line_mux;
 875         uint16_t devices;
 876         int connector_type;
 877         struct radeon_i2c_bus_rec ddc_bus;
 878         struct radeon_hpd hpd;
 879 };
 880
 881 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 882                                                                  drm_device
 883                                                                  *dev)
 884 {
 885         struct radeon_device *rdev = dev->dev_private;
 886         struct radeon_mode_info *mode_info = &rdev->mode_info;
 887         struct atom_context *ctx = mode_info->atom_context;
 888         int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
 889         uint16_t size, data_offset;
 890         uint8_t frev, crev;
 891         uint16_t device_support;
 892         uint8_t dac;
 893         union atom_supported_devices *supported_devices;
 894         int i, j, max_device;
 895         struct bios_connector *bios_connectors;
 896         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
 897         struct radeon_router router;
 898
 899         router.ddc_valid = false;
 900         router.cd_valid = false;
 901
 902         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
 903         if (!bios_connectors)
 904                 return false;
 905
 906         if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
 907                                     &data_offset)) {
 908                 kfree(bios_connectors);
 909                 return false;
 910         }
 911
 912         supported_devices =
 913             (union atom_supported_devices *)(ctx->bios + data_offset);
 914
 915         device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
 916
 917         if (frev > 1)
 918                 max_device = ATOM_MAX_SUPPORTED_DEVICE;
 919         else
 920                 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
 921
 922         for (i = 0; i < max_device; i++) {
 923                 ATOM_CONNECTOR_INFO_I2C ci =
 924                     supported_devices->info.asConnInfo[i];
 925
 926                 bios_connectors[i].valid = false;
 927
 928                 if (!(device_support & (1 << i))) {
 929                         continue;
 930                 }
 931
 932                 if (i == ATOM_DEVICE_CV_INDEX) {
 933                         DRM_DEBUG_KMS("Skipping Component Video\n");
 934                         continue;
 935                 }
 936
 937                 bios_connectors[i].connector_type =
 938                     supported_devices_connector_convert[ci.sucConnectorInfo.
 939                                                         sbfAccess.
 940                                                         bfConnectorType];
 941
 942                 if (bios_connectors[i].connector_type ==
 943                     DRM_MODE_CONNECTOR_Unknown)
 944                         continue;
 945
 946                 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
 947
 948                 bios_connectors[i].line_mux =
 949                         ci.sucI2cId.ucAccess;
 950
 951                 /* give tv unique connector ids */
 952                 if (i == ATOM_DEVICE_TV1_INDEX) {
 953                         bios_connectors[i].ddc_bus.valid = false;
 954                         bios_connectors[i].line_mux = 50;
 955                 } else if (i == ATOM_DEVICE_TV2_INDEX) {
 956                         bios_connectors[i].ddc_bus.valid = false;
 957                         bios_connectors[i].line_mux = 51;
 958                 } else if (i == ATOM_DEVICE_CV_INDEX) {
 959                         bios_connectors[i].ddc_bus.valid = false;
 960                         bios_connectors[i].line_mux = 52;
 961                 } else
 962                         bios_connectors[i].ddc_bus =
 963                             radeon_lookup_i2c_gpio(rdev,
 964                                                    bios_connectors[i].line_mux);
 965
 966                 if ((crev > 1) && (frev > 1)) {
 967                         u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
 968                         switch (isb) {
 969                         case 0x4:
 970                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 971                                 break;
 972                         case 0xa:
 973                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 974                                 break;
 975                         default:
 976                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 977                                 break;
 978                         }
 979                 } else {
 980                         if (i == ATOM_DEVICE_DFP1_INDEX)
 981                                 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
 982                         else if (i == ATOM_DEVICE_DFP2_INDEX)
 983                                 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
 984                         else
 985                                 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
 986                 }
 987
 988                 /* Always set the connector type to VGA for CRT1/CRT2. if they are
 989                  * shared with a DVI port, we'll pick up the DVI connector when we
 990                  * merge the outputs.  Some bioses incorrectly list VGA ports as DVI.
 991                  */
 992                 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
 993                         bios_connectors[i].connector_type =
 994                             DRM_MODE_CONNECTOR_VGA;
 995
 996                 if (!radeon_atom_apply_quirks
 997                     (dev, (1 << i), &bios_connectors[i].connector_type,
 998                      &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
 999                      &bios_connectors[i].hpd))
1000                         continue;
1001
1002                 bios_connectors[i].valid = true;
1003                 bios_connectors[i].devices = (1 << i);
1004
1005                 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1006                         radeon_add_atom_encoder(dev,
1007                                                 radeon_get_encoder_enum(dev,
1008                                                                       (1 << i),
1009                                                                       dac),
1010                                                 (1 << i));
1011                 else
1012                         radeon_add_legacy_encoder(dev,
1013                                                   radeon_get_encoder_enum(dev,
1014                                                                         (1 << i),
1015                                                                         dac),
1016                                                   (1 << i));
1017         }
1018
1019         /* combine shared connectors */
1020         for (i = 0; i < max_device; i++) {
1021                 if (bios_connectors[i].valid) {
1022                         for (j = 0; j < max_device; j++) {
1023                                 if (bios_connectors[j].valid && (i != j)) {
1024                                         if (bios_connectors[i].line_mux ==
1025                                             bios_connectors[j].line_mux) {
1026                                                 /* make sure not to combine LVDS */
1027                                                 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1028                                                         bios_connectors[i].line_mux = 53;
1029                                                         bios_connectors[i].ddc_bus.valid = false;
1030                                                         continue;
1031                                                 }
1032                                                 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1033                                                         bios_connectors[j].line_mux = 53;
1034                                                         bios_connectors[j].ddc_bus.valid = false;
1035                                                         continue;
1036                                                 }
1037                                                 /* combine analog and digital for DVI-I */
1038                                                 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1039                                                      (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1040                                                     ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1041                                                      (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1042                                                         bios_connectors[i].devices |=
1043                                                                 bios_connectors[j].devices;
1044                                                         bios_connectors[i].connector_type =
1045                                                                 DRM_MODE_CONNECTOR_DVII;
1046                                                         if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1047                                                                 bios_connectors[i].hpd =
1048                                                                         bios_connectors[j].hpd;
1049                                                         bios_connectors[j].valid = false;
1050                                                 }
1051                                         }
1052                                 }
1053                         }
1054                 }
1055         }
1056
1057         /* add the connectors */
1058         for (i = 0; i < max_device; i++) {
1059                 if (bios_connectors[i].valid) {
1060                         uint16_t connector_object_id =
1061                                 atombios_get_connector_object_id(dev,
1062                                                       bios_connectors[i].connector_type,
1063                                                       bios_connectors[i].devices);
1064                         radeon_add_atom_connector(dev,
1065                                                   bios_connectors[i].line_mux,
1066                                                   bios_connectors[i].devices,
1067                                                   bios_connectors[i].
1068                                                   connector_type,
1069                                                   &bios_connectors[i].ddc_bus,
1070                                                   0,
1071                                                   connector_object_id,
1072                                                   &bios_connectors[i].hpd,
1073                                                   &router);
1074                 }
1075         }
1076
1077         radeon_link_encoder_connector(dev);
1078
1079         kfree(bios_connectors);
1080         return true;
1081 }
1082
1083 union firmware_info {
1084         ATOM_FIRMWARE_INFO info;
1085         ATOM_FIRMWARE_INFO_V1_2 info_12;
1086         ATOM_FIRMWARE_INFO_V1_3 info_13;
1087         ATOM_FIRMWARE_INFO_V1_4 info_14;
1088         ATOM_FIRMWARE_INFO_V2_1 info_21;
1089 };
1090
1091 bool radeon_atom_get_clock_info(struct drm_device *dev)
1092 {
1093         struct radeon_device *rdev = dev->dev_private;
1094         struct radeon_mode_info *mode_info = &rdev->mode_info;
1095         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1096         union firmware_info *firmware_info;
1097         uint8_t frev, crev;
1098         struct radeon_pll *p1pll = &rdev->clock.p1pll;
1099         struct radeon_pll *p2pll = &rdev->clock.p2pll;
1100         struct radeon_pll *dcpll = &rdev->clock.dcpll;
1101         struct radeon_pll *spll = &rdev->clock.spll;
1102         struct radeon_pll *mpll = &rdev->clock.mpll;
1103         uint16_t data_offset;
1104
1105         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1106                                    &frev, &crev, &data_offset)) {
1107                 firmware_info =
1108                         (union firmware_info *)(mode_info->atom_context->bios +
1109                                                 data_offset);
1110                 /* pixel clocks */
1111                 p1pll->reference_freq =
1112                     le16_to_cpu(firmware_info->info.usReferenceClock);
1113                 p1pll->reference_div = 0;
1114
1115                 if (crev < 2)
1116                         p1pll->pll_out_min =
1117                                 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1118                 else
1119                         p1pll->pll_out_min =
1120                                 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1121                 p1pll->pll_out_max =
1122                     le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1123
1124                 if (crev >= 4) {
1125                         p1pll->lcd_pll_out_min =
1126                                 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1127                         if (p1pll->lcd_pll_out_min == 0)
1128                                 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1129                         p1pll->lcd_pll_out_max =
1130                                 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1131                         if (p1pll->lcd_pll_out_max == 0)
1132                                 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1133                 } else {
1134                         p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1135                         p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1136                 }
1137
1138                 if (p1pll->pll_out_min == 0) {
1139                         if (ASIC_IS_AVIVO(rdev))
1140                                 p1pll->pll_out_min = 64800;
1141                         else
1142                                 p1pll->pll_out_min = 20000;
1143                 } else if (p1pll->pll_out_min > 64800) {
1144                         /* Limiting the pll output range is a good thing generally as
1145                          * it limits the number of possible pll combinations for a given
1146                          * frequency presumably to the ones that work best on each card.
1147                          * However, certain duallink DVI monitors seem to like
1148                          * pll combinations that would be limited by this at least on
1149                          * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
1150                          * family.
1151                          */
1152                         p1pll->pll_out_min = 64800;
1153                 }
1154
1155                 p1pll->pll_in_min =
1156                     le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1157                 p1pll->pll_in_max =
1158                     le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1159
1160                 *p2pll = *p1pll;
1161
1162                 /* system clock */
1163                 spll->reference_freq =
1164                     le16_to_cpu(firmware_info->info.usReferenceClock);
1165                 spll->reference_div = 0;
1166
1167                 spll->pll_out_min =
1168                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1169                 spll->pll_out_max =
1170                     le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1171
1172                 /* ??? */
1173                 if (spll->pll_out_min == 0) {
1174                         if (ASIC_IS_AVIVO(rdev))
1175                                 spll->pll_out_min = 64800;
1176                         else
1177                                 spll->pll_out_min = 20000;
1178                 }
1179
1180                 spll->pll_in_min =
1181                     le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1182                 spll->pll_in_max =
1183                     le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1184
1185                 /* memory clock */
1186                 mpll->reference_freq =
1187                     le16_to_cpu(firmware_info->info.usReferenceClock);
1188                 mpll->reference_div = 0;
1189
1190                 mpll->pll_out_min =
1191                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1192                 mpll->pll_out_max =
1193                     le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1194
1195                 /* ??? */
1196                 if (mpll->pll_out_min == 0) {
1197                         if (ASIC_IS_AVIVO(rdev))
1198                                 mpll->pll_out_min = 64800;
1199                         else
1200                                 mpll->pll_out_min = 20000;
1201                 }
1202
1203                 mpll->pll_in_min =
1204                     le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1205                 mpll->pll_in_max =
1206                     le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1207
1208                 rdev->clock.default_sclk =
1209                     le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1210                 rdev->clock.default_mclk =
1211                     le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1212
1213                 if (ASIC_IS_DCE4(rdev)) {
1214                         rdev->clock.default_dispclk =
1215                                 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1216                         if (rdev->clock.default_dispclk == 0)
1217                                 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1218                         rdev->clock.dp_extclk =
1219                                 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1220                 }
1221                 *dcpll = *p1pll;
1222
1223                 return true;
1224         }
1225
1226         return false;
1227 }
1228
1229 union igp_info {
1230         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1231         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1232 };
1233
1234 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1235 {
1236         struct radeon_mode_info *mode_info = &rdev->mode_info;
1237         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1238         union igp_info *igp_info;
1239         u8 frev, crev;
1240         u16 data_offset;
1241
1242         /* sideport is AMD only */
1243         if (rdev->family == CHIP_RS600)
1244                 return false;
1245
1246         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1247                                    &frev, &crev, &data_offset)) {
1248                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1249                                       data_offset);
1250                 switch (crev) {
1251                 case 1:
1252                         if (igp_info->info.ulBootUpMemoryClock)
1253                                 return true;
1254                         break;
1255                 case 2:
1256                         if (igp_info->info_2.ulBootUpSidePortClock)
1257                                 return true;
1258                         break;
1259                 default:
1260                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1261                         break;
1262                 }
1263         }
1264         return false;
1265 }
1266
1267 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1268                                    struct radeon_encoder_int_tmds *tmds)
1269 {
1270         struct drm_device *dev = encoder->base.dev;
1271         struct radeon_device *rdev = dev->dev_private;
1272         struct radeon_mode_info *mode_info = &rdev->mode_info;
1273         int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1274         uint16_t data_offset;
1275         struct _ATOM_TMDS_INFO *tmds_info;
1276         uint8_t frev, crev;
1277         uint16_t maxfreq;
1278         int i;
1279
1280         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1281                                    &frev, &crev, &data_offset)) {
1282                 tmds_info =
1283                         (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1284                                                    data_offset);
1285
1286                 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1287                 for (i = 0; i < 4; i++) {
1288                         tmds->tmds_pll[i].freq =
1289                             le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1290                         tmds->tmds_pll[i].value =
1291                             tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1292                         tmds->tmds_pll[i].value |=
1293                             (tmds_info->asMiscInfo[i].
1294                              ucPLL_VCO_Gain & 0x3f) << 6;
1295                         tmds->tmds_pll[i].value |=
1296                             (tmds_info->asMiscInfo[i].
1297                              ucPLL_DutyCycle & 0xf) << 12;
1298                         tmds->tmds_pll[i].value |=
1299                             (tmds_info->asMiscInfo[i].
1300                              ucPLL_VoltageSwing & 0xf) << 16;
1301
1302                         DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1303                                   tmds->tmds_pll[i].freq,
1304                                   tmds->tmds_pll[i].value);
1305
1306                         if (maxfreq == tmds->tmds_pll[i].freq) {
1307                                 tmds->tmds_pll[i].freq = 0xffffffff;
1308                                 break;
1309                         }
1310                 }
1311                 return true;
1312         }
1313         return false;
1314 }
1315
1316 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1317                                       struct radeon_atom_ss *ss,
1318                                       int id)
1319 {
1320         struct radeon_mode_info *mode_info = &rdev->mode_info;
1321         int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1322         uint16_t data_offset, size;
1323         struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1324         uint8_t frev, crev;
1325         int i, num_indices;
1326
1327         memset(ss, 0, sizeof(struct radeon_atom_ss));
1328         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1329                                    &frev, &crev, &data_offset)) {
1330                 ss_info =
1331                         (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1332
1333                 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1334                         sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1335
1336                 for (i = 0; i < num_indices; i++) {
1337                         if (ss_info->asSS_Info[i].ucSS_Id == id) {
1338                                 ss->percentage =
1339                                         le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1340                                 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1341                                 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1342                                 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1343                                 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1344                                 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1345                                 return true;
1346                         }
1347                 }
1348         }
1349         return false;
1350 }
1351
1352 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1353                                                  struct radeon_atom_ss *ss,
1354                                                  int id)
1355 {
1356         struct radeon_mode_info *mode_info = &rdev->mode_info;
1357         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1358         u16 data_offset, size;
1359         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *igp_info;
1360         u8 frev, crev;
1361         u16 percentage = 0, rate = 0;
1362
1363         /* get any igp specific overrides */
1364         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1365                                    &frev, &crev, &data_offset)) {
1366                 igp_info = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 *)
1367                         (mode_info->atom_context->bios + data_offset);
1368                 switch (id) {
1369                 case ASIC_INTERNAL_SS_ON_TMDS:
1370                         percentage = le16_to_cpu(igp_info->usDVISSPercentage);
1371                         rate = le16_to_cpu(igp_info->usDVISSpreadRateIn10Hz);
1372                         break;
1373                 case ASIC_INTERNAL_SS_ON_HDMI:
1374                         percentage = le16_to_cpu(igp_info->usHDMISSPercentage);
1375                         rate = le16_to_cpu(igp_info->usHDMISSpreadRateIn10Hz);
1376                         break;
1377                 case ASIC_INTERNAL_SS_ON_LVDS:
1378                         percentage = le16_to_cpu(igp_info->usLvdsSSPercentage);
1379                         rate = le16_to_cpu(igp_info->usLvdsSSpreadRateIn10Hz);
1380                         break;
1381                 }
1382                 if (percentage)
1383                         ss->percentage = percentage;
1384                 if (rate)
1385                         ss->rate = rate;
1386         }
1387 }
1388
1389 union asic_ss_info {
1390         struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1391         struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1392         struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1393 };
1394
1395 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1396                                       struct radeon_atom_ss *ss,
1397                                       int id, u32 clock)
1398 {
1399         struct radeon_mode_info *mode_info = &rdev->mode_info;
1400         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1401         uint16_t data_offset, size;
1402         union asic_ss_info *ss_info;
1403         uint8_t frev, crev;
1404         int i, num_indices;
1405
1406         memset(ss, 0, sizeof(struct radeon_atom_ss));
1407         if (atom_parse_data_header(mode_info->atom_context, index, &size,
1408                                    &frev, &crev, &data_offset)) {
1409
1410                 ss_info =
1411                         (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1412
1413                 switch (frev) {
1414                 case 1:
1415                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1416                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1417
1418                         for (i = 0; i < num_indices; i++) {
1419                                 if ((ss_info->info.asSpreadSpectrum[i].ucClockIndication == id) &&
1420                                     (clock <= ss_info->info.asSpreadSpectrum[i].ulTargetClockRange)) {
1421                                         ss->percentage =
1422                                                 le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1423                                         ss->type = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1424                                         ss->rate = le16_to_cpu(ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz);
1425                                         return true;
1426                                 }
1427                         }
1428                         break;
1429                 case 2:
1430                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1431                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1432                         for (i = 0; i < num_indices; i++) {
1433                                 if ((ss_info->info_2.asSpreadSpectrum[i].ucClockIndication == id) &&
1434                                     (clock <= ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange)) {
1435                                         ss->percentage =
1436                                                 le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1437                                         ss->type = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1438                                         ss->rate = le16_to_cpu(ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1439                                         return true;
1440                                 }
1441                         }
1442                         break;
1443                 case 3:
1444                         num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1445                                 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1446                         for (i = 0; i < num_indices; i++) {
1447                                 if ((ss_info->info_3.asSpreadSpectrum[i].ucClockIndication == id) &&
1448                                     (clock <= ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange)) {
1449                                         ss->percentage =
1450                                                 le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage);
1451                                         ss->type = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode;
1452                                         ss->rate = le16_to_cpu(ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz);
1453                                         if (rdev->flags & RADEON_IS_IGP)
1454                                                 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1455                                         return true;
1456                                 }
1457                         }
1458                         break;
1459                 default:
1460                         DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1461                         break;
1462                 }
1463
1464         }
1465         return false;
1466 }
1467
1468 union lvds_info {
1469         struct _ATOM_LVDS_INFO info;
1470         struct _ATOM_LVDS_INFO_V12 info_12;
1471 };
1472
1473 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1474                                                               radeon_encoder
1475                                                               *encoder)
1476 {
1477         struct drm_device *dev = encoder->base.dev;
1478         struct radeon_device *rdev = dev->dev_private;
1479         struct radeon_mode_info *mode_info = &rdev->mode_info;
1480         int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1481         uint16_t data_offset, misc;
1482         union lvds_info *lvds_info;
1483         uint8_t frev, crev;
1484         struct radeon_encoder_atom_dig *lvds = NULL;
1485         int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1486
1487         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1488                                    &frev, &crev, &data_offset)) {
1489                 lvds_info =
1490                         (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1491                 lvds =
1492                     kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1493
1494                 if (!lvds)
1495                         return NULL;
1496
1497                 lvds->native_mode.clock =
1498                     le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1499                 lvds->native_mode.hdisplay =
1500                     le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1501                 lvds->native_mode.vdisplay =
1502                     le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1503                 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1504                         le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1505                 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1506                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1507                 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1508                         le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1509                 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1510                         le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1511                 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1512                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1513                 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1514                         le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1515                 lvds->panel_pwr_delay =
1516                     le16_to_cpu(lvds_info->info.usOffDelayInMs);
1517                 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1518
1519                 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1520                 if (misc & ATOM_VSYNC_POLARITY)
1521                         lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1522                 if (misc & ATOM_HSYNC_POLARITY)
1523                         lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1524                 if (misc & ATOM_COMPOSITESYNC)
1525                         lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1526                 if (misc & ATOM_INTERLACE)
1527                         lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1528                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1529                         lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1530
1531                 lvds->native_mode.width_mm = lvds_info->info.sLCDTiming.usImageHSize;
1532                 lvds->native_mode.height_mm = lvds_info->info.sLCDTiming.usImageVSize;
1533
1534                 /* set crtc values */
1535                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1536
1537                 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1538
1539                 encoder->native_mode = lvds->native_mode;
1540
1541                 if (encoder_enum == 2)
1542                         lvds->linkb = true;
1543                 else
1544                         lvds->linkb = false;
1545
1546                 /* parse the lcd record table */
1547                 if (lvds_info->info.usModePatchTableOffset) {
1548                         ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1549                         ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1550                         bool bad_record = false;
1551                         u8 *record = (u8 *)(mode_info->atom_context->bios +
1552                                             data_offset +
1553                                             lvds_info->info.usModePatchTableOffset);
1554                         while (*record != ATOM_RECORD_END_TYPE) {
1555                                 switch (*record) {
1556                                 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1557                                         record += sizeof(ATOM_PATCH_RECORD_MODE);
1558                                         break;
1559                                 case LCD_RTS_RECORD_TYPE:
1560                                         record += sizeof(ATOM_LCD_RTS_RECORD);
1561                                         break;
1562                                 case LCD_CAP_RECORD_TYPE:
1563                                         record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1564                                         break;
1565                                 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1566                                         fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1567                                         if (fake_edid_record->ucFakeEDIDLength) {
1568                                                 struct edid *edid;
1569                                                 int edid_size =
1570                                                         max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1571                                                 edid = kmalloc(edid_size, GFP_KERNEL);
1572                                                 if (edid) {
1573                                                         memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1574                                                                fake_edid_record->ucFakeEDIDLength);
1575
1576                                                         if (drm_edid_is_valid(edid))
1577                                                                 rdev->mode_info.bios_hardcoded_edid = edid;
1578                                                         else
1579                                                                 kfree(edid);
1580                                                 }
1581                                         }
1582                                         record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
1583                                         break;
1584                                 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1585                                         panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1586                                         lvds->native_mode.width_mm = panel_res_record->usHSize;
1587                                         lvds->native_mode.height_mm = panel_res_record->usVSize;
1588                                         record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1589                                         break;
1590                                 default:
1591                                         DRM_ERROR("Bad LCD record %d\n", *record);
1592                                         bad_record = true;
1593                                         break;
1594                                 }
1595                                 if (bad_record)
1596                                         break;
1597                         }
1598                 }
1599         }
1600         return lvds;
1601 }
1602
1603 struct radeon_encoder_primary_dac *
1604 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1605 {
1606         struct drm_device *dev = encoder->base.dev;
1607         struct radeon_device *rdev = dev->dev_private;
1608         struct radeon_mode_info *mode_info = &rdev->mode_info;
1609         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1610         uint16_t data_offset;
1611         struct _COMPASSIONATE_DATA *dac_info;
1612         uint8_t frev, crev;
1613         uint8_t bg, dac;
1614         struct radeon_encoder_primary_dac *p_dac = NULL;
1615
1616         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1617                                    &frev, &crev, &data_offset)) {
1618                 dac_info = (struct _COMPASSIONATE_DATA *)
1619                         (mode_info->atom_context->bios + data_offset);
1620
1621                 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1622
1623                 if (!p_dac)
1624                         return NULL;
1625
1626                 bg = dac_info->ucDAC1_BG_Adjustment;
1627                 dac = dac_info->ucDAC1_DAC_Adjustment;
1628                 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1629
1630         }
1631         return p_dac;
1632 }
1633
1634 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1635                                 struct drm_display_mode *mode)
1636 {
1637         struct radeon_mode_info *mode_info = &rdev->mode_info;
1638         ATOM_ANALOG_TV_INFO *tv_info;
1639         ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1640         ATOM_DTD_FORMAT *dtd_timings;
1641         int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1642         u8 frev, crev;
1643         u16 data_offset, misc;
1644
1645         if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1646                                     &frev, &crev, &data_offset))
1647                 return false;
1648
1649         switch (crev) {
1650         case 1:
1651                 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1652                 if (index >= MAX_SUPPORTED_TV_TIMING)
1653                         return false;
1654
1655                 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1656                 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1657                 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1658                 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1659                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1660
1661                 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1662                 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1663                 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1664                 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1665                         le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1666
1667                 mode->flags = 0;
1668                 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1669                 if (misc & ATOM_VSYNC_POLARITY)
1670                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1671                 if (misc & ATOM_HSYNC_POLARITY)
1672                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1673                 if (misc & ATOM_COMPOSITESYNC)
1674                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1675                 if (misc & ATOM_INTERLACE)
1676                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1677                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1678                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1679
1680                 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1681
1682                 if (index == 1) {
1683                         /* PAL timings appear to have wrong values for totals */
1684                         mode->crtc_htotal -= 1;
1685                         mode->crtc_vtotal -= 1;
1686                 }
1687                 break;
1688         case 2:
1689                 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1690                 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1691                         return false;
1692
1693                 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1694                 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1695                         le16_to_cpu(dtd_timings->usHBlanking_Time);
1696                 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1697                 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1698                         le16_to_cpu(dtd_timings->usHSyncOffset);
1699                 mode->crtc_hsync_end = mode->crtc_hsync_start +
1700                         le16_to_cpu(dtd_timings->usHSyncWidth);
1701
1702                 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1703                         le16_to_cpu(dtd_timings->usVBlanking_Time);
1704                 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1705                 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1706                         le16_to_cpu(dtd_timings->usVSyncOffset);
1707                 mode->crtc_vsync_end = mode->crtc_vsync_start +
1708                         le16_to_cpu(dtd_timings->usVSyncWidth);
1709
1710                 mode->flags = 0;
1711                 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1712                 if (misc & ATOM_VSYNC_POLARITY)
1713                         mode->flags |= DRM_MODE_FLAG_NVSYNC;
1714                 if (misc & ATOM_HSYNC_POLARITY)
1715                         mode->flags |= DRM_MODE_FLAG_NHSYNC;
1716                 if (misc & ATOM_COMPOSITESYNC)
1717                         mode->flags |= DRM_MODE_FLAG_CSYNC;
1718                 if (misc & ATOM_INTERLACE)
1719                         mode->flags |= DRM_MODE_FLAG_INTERLACE;
1720                 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1721                         mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1722
1723                 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1724                 break;
1725         }
1726         return true;
1727 }
1728
1729 enum radeon_tv_std
1730 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1731 {
1732         struct radeon_mode_info *mode_info = &rdev->mode_info;
1733         int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1734         uint16_t data_offset;
1735         uint8_t frev, crev;
1736         struct _ATOM_ANALOG_TV_INFO *tv_info;
1737         enum radeon_tv_std tv_std = TV_STD_NTSC;
1738
1739         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1740                                    &frev, &crev, &data_offset)) {
1741
1742                 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1743                         (mode_info->atom_context->bios + data_offset);
1744
1745                 switch (tv_info->ucTV_BootUpDefaultStandard) {
1746                 case ATOM_TV_NTSC:
1747                         tv_std = TV_STD_NTSC;
1748                         DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1749                         break;
1750                 case ATOM_TV_NTSCJ:
1751                         tv_std = TV_STD_NTSC_J;
1752                         DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1753                         break;
1754                 case ATOM_TV_PAL:
1755                         tv_std = TV_STD_PAL;
1756                         DRM_DEBUG_KMS("Default TV standard: PAL\n");
1757                         break;
1758                 case ATOM_TV_PALM:
1759                         tv_std = TV_STD_PAL_M;
1760                         DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1761                         break;
1762                 case ATOM_TV_PALN:
1763                         tv_std = TV_STD_PAL_N;
1764                         DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1765                         break;
1766                 case ATOM_TV_PALCN:
1767                         tv_std = TV_STD_PAL_CN;
1768                         DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1769                         break;
1770                 case ATOM_TV_PAL60:
1771                         tv_std = TV_STD_PAL_60;
1772                         DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1773                         break;
1774                 case ATOM_TV_SECAM:
1775                         tv_std = TV_STD_SECAM;
1776                         DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1777                         break;
1778                 default:
1779                         tv_std = TV_STD_NTSC;
1780                         DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1781                         break;
1782                 }
1783         }
1784         return tv_std;
1785 }
1786
1787 struct radeon_encoder_tv_dac *
1788 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1789 {
1790         struct drm_device *dev = encoder->base.dev;
1791         struct radeon_device *rdev = dev->dev_private;
1792         struct radeon_mode_info *mode_info = &rdev->mode_info;
1793         int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1794         uint16_t data_offset;
1795         struct _COMPASSIONATE_DATA *dac_info;
1796         uint8_t frev, crev;
1797         uint8_t bg, dac;
1798         struct radeon_encoder_tv_dac *tv_dac = NULL;
1799
1800         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1801                                    &frev, &crev, &data_offset)) {
1802
1803                 dac_info = (struct _COMPASSIONATE_DATA *)
1804                         (mode_info->atom_context->bios + data_offset);
1805
1806                 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1807
1808                 if (!tv_dac)
1809                         return NULL;
1810
1811                 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1812                 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1813                 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1814
1815                 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1816                 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1817                 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1818
1819                 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1820                 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1821                 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1822
1823                 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1824         }
1825         return tv_dac;
1826 }
1827
1828 static const char *thermal_controller_names[] = {
1829         "NONE",
1830         "lm63",
1831         "adm1032",
1832         "adm1030",
1833         "max6649",
1834         "lm64",
1835         "f75375",
1836         "asc7xxx",
1837 };
1838
1839 static const char *pp_lib_thermal_controller_names[] = {
1840         "NONE",
1841         "lm63",
1842         "adm1032",
1843         "adm1030",
1844         "max6649",
1845         "lm64",
1846         "f75375",
1847         "RV6xx",
1848         "RV770",
1849         "adt7473",
1850         "NONE",
1851         "External GPIO",
1852         "Evergreen",
1853         "emc2103",
1854         "Sumo",
1855 };
1856
1857 union power_info {
1858         struct _ATOM_POWERPLAY_INFO info;
1859         struct _ATOM_POWERPLAY_INFO_V2 info_2;
1860         struct _ATOM_POWERPLAY_INFO_V3 info_3;
1861         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1862         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1863         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1864 };
1865
1866 union pplib_clock_info {
1867         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1868         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1869         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1870         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1871 };
1872
1873 union pplib_power_state {
1874         struct _ATOM_PPLIB_STATE v1;
1875         struct _ATOM_PPLIB_STATE_V2 v2;
1876 };
1877
1878 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
1879                                                  int state_index,
1880                                                  u32 misc, u32 misc2)
1881 {
1882         rdev->pm.power_state[state_index].misc = misc;
1883         rdev->pm.power_state[state_index].misc2 = misc2;
1884         /* order matters! */
1885         if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1886                 rdev->pm.power_state[state_index].type =
1887                         POWER_STATE_TYPE_POWERSAVE;
1888         if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1889                 rdev->pm.power_state[state_index].type =
1890                         POWER_STATE_TYPE_BATTERY;
1891         if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1892                 rdev->pm.power_state[state_index].type =
1893                         POWER_STATE_TYPE_BATTERY;
1894         if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1895                 rdev->pm.power_state[state_index].type =
1896                         POWER_STATE_TYPE_BALANCED;
1897         if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1898                 rdev->pm.power_state[state_index].type =
1899                         POWER_STATE_TYPE_PERFORMANCE;
1900                 rdev->pm.power_state[state_index].flags &=
1901                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1902         }
1903         if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1904                 rdev->pm.power_state[state_index].type =
1905                         POWER_STATE_TYPE_BALANCED;
1906         if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1907                 rdev->pm.power_state[state_index].type =
1908                         POWER_STATE_TYPE_DEFAULT;
1909                 rdev->pm.default_power_state_index = state_index;
1910                 rdev->pm.power_state[state_index].default_clock_mode =
1911                         &rdev->pm.power_state[state_index].clock_info[0];
1912         } else if (state_index == 0) {
1913                 rdev->pm.power_state[state_index].clock_info[0].flags |=
1914                         RADEON_PM_MODE_NO_DISPLAY;
1915         }
1916 }
1917
1918 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1919 {
1920         struct radeon_mode_info *mode_info = &rdev->mode_info;
1921         u32 misc, misc2 = 0;
1922         int num_modes = 0, i;
1923         int state_index = 0;
1924         struct radeon_i2c_bus_rec i2c_bus;
1925         union power_info *power_info;
1926         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1927         u16 data_offset;
1928         u8 frev, crev;
1929
1930         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1931                                    &frev, &crev, &data_offset))
1932                 return state_index;
1933         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1934
1935         /* add the i2c bus for thermal/fan chip */
1936         if (power_info->info.ucOverdriveThermalController > 0) {
1937                 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1938                          thermal_controller_names[power_info->info.ucOverdriveThermalController],
1939                          power_info->info.ucOverdriveControllerAddress >> 1);
1940                 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1941                 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1942                 if (rdev->pm.i2c_bus) {
1943                         struct i2c_board_info info = { };
1944                         const char *name = thermal_controller_names[power_info->info.
1945                                                                     ucOverdriveThermalController];
1946                         info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
1947                         strlcpy(info.type, name, sizeof(info.type));
1948                         i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
1949                 }
1950         }
1951         num_modes = power_info->info.ucNumOfPowerModeEntries;
1952         if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1953                 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1954         /* last mode is usually default, array is low to high */
1955         for (i = 0; i < num_modes; i++) {
1956                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1957                 switch (frev) {
1958                 case 1:
1959                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1960                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1961                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1962                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1963                                 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1964                         /* skip invalid modes */
1965                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1966                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1967                                 continue;
1968                         rdev->pm.power_state[state_index].pcie_lanes =
1969                                 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1970                         misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1971                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
1972                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
1973                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1974                                         VOLTAGE_GPIO;
1975                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1976                                         radeon_lookup_gpio(rdev,
1977                                                            power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1978                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1979                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1980                                                 true;
1981                                 else
1982                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1983                                                 false;
1984                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1985                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1986                                         VOLTAGE_VDDC;
1987                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1988                                         power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1989                         }
1990                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
1991                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
1992                         state_index++;
1993                         break;
1994                 case 2:
1995                         rdev->pm.power_state[state_index].num_clock_modes = 1;
1996                         rdev->pm.power_state[state_index].clock_info[0].mclk =
1997                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1998                         rdev->pm.power_state[state_index].clock_info[0].sclk =
1999                                 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2000                         /* skip invalid modes */
2001                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2002                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2003                                 continue;
2004                         rdev->pm.power_state[state_index].pcie_lanes =
2005                                 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2006                         misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2007                         misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2008                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2009                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2010                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2011                                         VOLTAGE_GPIO;
2012                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2013                                         radeon_lookup_gpio(rdev,
2014                                                            power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2015                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2016                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2017                                                 true;
2018                                 else
2019                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2020                                                 false;
2021                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2022                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2023                                         VOLTAGE_VDDC;
2024                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2025                                         power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2026                         }
2027                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2028                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2029                         state_index++;
2030                         break;
2031                 case 3:
2032                         rdev->pm.power_state[state_index].num_clock_modes = 1;
2033                         rdev->pm.power_state[state_index].clock_info[0].mclk =
2034                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2035                         rdev->pm.power_state[state_index].clock_info[0].sclk =
2036                                 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2037                         /* skip invalid modes */
2038                         if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2039                             (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2040                                 continue;
2041                         rdev->pm.power_state[state_index].pcie_lanes =
2042                                 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2043                         misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2044                         misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2045                         if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2046                             (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2047                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2048                                         VOLTAGE_GPIO;
2049                                 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2050                                         radeon_lookup_gpio(rdev,
2051                                                            power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2052                                 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2053                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2054                                                 true;
2055                                 else
2056                                         rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2057                                                 false;
2058                         } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2059                                 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2060                                         VOLTAGE_VDDC;
2061                                 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2062                                         power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2063                                 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2064                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2065                                                 true;
2066                                         rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2067                                                 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2068                                 }
2069                         }
2070                         rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2071                         radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2072                         state_index++;
2073                         break;
2074                 }
2075         }
2076         /* last mode is usually default */
2077         if (rdev->pm.default_power_state_index == -1) {
2078                 rdev->pm.power_state[state_index - 1].type =
2079                         POWER_STATE_TYPE_DEFAULT;
2080                 rdev->pm.default_power_state_index = state_index - 1;
2081                 rdev->pm.power_state[state_index - 1].default_clock_mode =
2082                         &rdev->pm.power_state[state_index - 1].clock_info[0];
2083                 rdev->pm.power_state[state_index].flags &=
2084                         ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2085                 rdev->pm.power_state[state_index].misc = 0;
2086                 rdev->pm.power_state[state_index].misc2 = 0;
2087         }
2088         return state_index;
2089 }
2090
2091 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2092                                                          ATOM_PPLIB_THERMALCONTROLLER *controller)
2093 {
2094         struct radeon_i2c_bus_rec i2c_bus;
2095
2096         /* add the i2c bus for thermal/fan chip */
2097         if (controller->ucType > 0) {
2098                 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2099                         DRM_INFO("Internal thermal controller %s fan control\n",
2100                                  (controller->ucFanParameters &
2101                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2102                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2103                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2104                         DRM_INFO("Internal thermal controller %s fan control\n",
2105                                  (controller->ucFanParameters &
2106                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2107                         rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2108                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2109                         DRM_INFO("Internal thermal controller %s fan control\n",
2110                                  (controller->ucFanParameters &
2111                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2112                         rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2113                 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2114                         DRM_INFO("Internal thermal controller %s fan control\n",
2115                                  (controller->ucFanParameters &
2116                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2117                         rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2118                 } else if ((controller->ucType ==
2119                             ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
2120                            (controller->ucType ==
2121                             ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
2122                            (controller->ucType ==
2123                             ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
2124                         DRM_INFO("Special thermal controller config\n");
2125                 } else {
2126                         DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2127                                  pp_lib_thermal_controller_names[controller->ucType],
2128                                  controller->ucI2cAddress >> 1,
2129                                  (controller->ucFanParameters &
2130                                   ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2131                         i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2132                         rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2133                         if (rdev->pm.i2c_bus) {
2134                                 struct i2c_board_info info = { };
2135                                 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2136                                 info.addr = controller->ucI2cAddress >> 1;
2137                                 strlcpy(info.type, name, sizeof(info.type));
2138                                 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2139                         }
2140                 }
2141         }
2142 }
2143
2144 static u16 radeon_atombios_get_default_vddc(struct radeon_device *rdev)
2145 {
2146         struct radeon_mode_info *mode_info = &rdev->mode_info;
2147         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2148         u8 frev, crev;
2149         u16 data_offset;
2150         union firmware_info *firmware_info;
2151         u16 vddc = 0;
2152
2153         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2154                                    &frev, &crev, &data_offset)) {
2155                 firmware_info =
2156                         (union firmware_info *)(mode_info->atom_context->bios +
2157                                                 data_offset);
2158                 vddc = firmware_info->info_14.usBootUpVDDCVoltage;
2159         }
2160
2161         return vddc;
2162 }
2163
2164 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2165                                                        int state_index, int mode_index,
2166                                                        struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2167 {
2168         int j;
2169         u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2170         u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2171         u16 vddc = radeon_atombios_get_default_vddc(rdev);
2172
2173         rdev->pm.power_state[state_index].misc = misc;
2174         rdev->pm.power_state[state_index].misc2 = misc2;
2175         rdev->pm.power_state[state_index].pcie_lanes =
2176                 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2177                  ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2178         switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2179         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2180                 rdev->pm.power_state[state_index].type =
2181                         POWER_STATE_TYPE_BATTERY;
2182                 break;
2183         case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2184                 rdev->pm.power_state[state_index].type =
2185                         POWER_STATE_TYPE_BALANCED;
2186                 break;
2187         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2188                 rdev->pm.power_state[state_index].type =
2189                         POWER_STATE_TYPE_PERFORMANCE;
2190                 break;
2191         case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2192                 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2193                         rdev->pm.power_state[state_index].type =
2194                                 POWER_STATE_TYPE_PERFORMANCE;
2195                 break;
2196         }
2197         rdev->pm.power_state[state_index].flags = 0;
2198         if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2199                 rdev->pm.power_state[state_index].flags |=
2200                         RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2201         if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2202                 rdev->pm.power_state[state_index].type =
2203                         POWER_STATE_TYPE_DEFAULT;
2204                 rdev->pm.default_power_state_index = state_index;
2205                 rdev->pm.power_state[state_index].default_clock_mode =
2206                         &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2207                 /* patch the table values with the default slck/mclk from firmware info */
2208                 for (j = 0; j < mode_index; j++) {
2209                         rdev->pm.power_state[state_index].clock_info[j].mclk =
2210                                 rdev->clock.default_mclk;
2211                         rdev->pm.power_state[state_index].clock_info[j].sclk =
2212                                 rdev->clock.default_sclk;
2213                         if (vddc)
2214                                 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2215                                         vddc;
2216                 }
2217         }
2218 }
2219
2220 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2221                                                    int state_index, int mode_index,
2222                                                    union pplib_clock_info *clock_info)
2223 {
2224         u32 sclk, mclk;
2225
2226         if (rdev->flags & RADEON_IS_IGP) {
2227                 if (rdev->family >= CHIP_PALM) {
2228                         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2229                         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2230                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2231                 } else {
2232                         sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2233                         sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2234                         rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2235                 }
2236         } else if (ASIC_IS_DCE4(rdev)) {
2237                 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2238                 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2239                 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2240                 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2241                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2242                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2243                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2244                         VOLTAGE_SW;
2245                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2246                         clock_info->evergreen.usVDDC;
2247         } else {
2248                 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2249                 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2250                 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2251                 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2252                 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2253                 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2254                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2255                         VOLTAGE_SW;
2256                 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2257                         clock_info->r600.usVDDC;
2258         }
2259
2260         if (rdev->flags & RADEON_IS_IGP) {
2261                 /* skip invalid modes */
2262                 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2263                         return false;
2264         } else {
2265                 /* skip invalid modes */
2266                 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2267                     (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2268                         return false;
2269         }
2270         return true;
2271 }
2272
2273 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2274 {
2275         struct radeon_mode_info *mode_info = &rdev->mode_info;
2276         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2277         union pplib_power_state *power_state;
2278         int i, j;
2279         int state_index = 0, mode_index = 0;
2280         union pplib_clock_info *clock_info;
2281         bool valid;
2282         union power_info *power_info;
2283         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2284         u16 data_offset;
2285         u8 frev, crev;
2286
2287         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2288                                    &frev, &crev, &data_offset))
2289                 return state_index;
2290         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2291
2292         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2293         /* first mode is usually default, followed by low to high */
2294         for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2295                 mode_index = 0;
2296                 power_state = (union pplib_power_state *)
2297                         (mode_info->atom_context->bios + data_offset +
2298                          le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2299                          i * power_info->pplib.ucStateEntrySize);
2300                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2301                         (mode_info->atom_context->bios + data_offset +
2302                          le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2303                          (power_state->v1.ucNonClockStateIndex *
2304                           power_info->pplib.ucNonClockSize));
2305                 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2306                         clock_info = (union pplib_clock_info *)
2307                                 (mode_info->atom_context->bios + data_offset +
2308                                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2309                                  (power_state->v1.ucClockStateIndices[j] *
2310                                   power_info->pplib.ucClockInfoSize));
2311                         valid = radeon_atombios_parse_pplib_clock_info(rdev,
2312                                                                        state_index, mode_index,
2313                                                                        clock_info);
2314                         if (valid)
2315                                 mode_index++;
2316                 }
2317                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2318                 if (mode_index) {
2319                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2320                                                                    non_clock_info);
2321                         state_index++;
2322                 }
2323         }
2324         /* if multiple clock modes, mark the lowest as no display */
2325         for (i = 0; i < state_index; i++) {
2326                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2327                         rdev->pm.power_state[i].clock_info[0].flags |=
2328                                 RADEON_PM_MODE_NO_DISPLAY;
2329         }
2330         /* first mode is usually default */
2331         if (rdev->pm.default_power_state_index == -1) {
2332                 rdev->pm.power_state[0].type =
2333                         POWER_STATE_TYPE_DEFAULT;
2334                 rdev->pm.default_power_state_index = 0;
2335                 rdev->pm.power_state[0].default_clock_mode =
2336                         &rdev->pm.power_state[0].clock_info[0];
2337         }
2338         return state_index;
2339 }
2340
2341 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2342 {
2343         struct radeon_mode_info *mode_info = &rdev->mode_info;
2344         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2345         union pplib_power_state *power_state;
2346         int i, j, non_clock_array_index, clock_array_index;
2347         int state_index = 0, mode_index = 0;
2348         union pplib_clock_info *clock_info;
2349         struct StateArray *state_array;
2350         struct ClockInfoArray *clock_info_array;
2351         struct NonClockInfoArray *non_clock_info_array;
2352         bool valid;
2353         union power_info *power_info;
2354         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2355         u16 data_offset;
2356         u8 frev, crev;
2357
2358         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2359                                    &frev, &crev, &data_offset))
2360                 return state_index;
2361         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2362
2363         radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2364         state_array = (struct StateArray *)
2365                 (mode_info->atom_context->bios + data_offset +
2366                  power_info->pplib.usStateArrayOffset);
2367         clock_info_array = (struct ClockInfoArray *)
2368                 (mode_info->atom_context->bios + data_offset +
2369                  power_info->pplib.usClockInfoArrayOffset);
2370         non_clock_info_array = (struct NonClockInfoArray *)
2371                 (mode_info->atom_context->bios + data_offset +
2372                  power_info->pplib.usNonClockInfoArrayOffset);
2373         for (i = 0; i < state_array->ucNumEntries; i++) {
2374                 mode_index = 0;
2375                 power_state = (union pplib_power_state *)&state_array->states[i];
2376                 /* XXX this might be an inagua bug... */
2377                 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2378                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2379                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2380                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2381                         clock_array_index = power_state->v2.clockInfoIndex[j];
2382                         /* XXX this might be an inagua bug... */
2383                         if (clock_array_index >= clock_info_array->ucNumEntries)
2384                                 continue;
2385                         clock_info = (union pplib_clock_info *)
2386                                 &clock_info_array->clockInfo[clock_array_index];
2387                         valid = radeon_atombios_parse_pplib_clock_info(rdev,
2388                                                                        state_index, mode_index,
2389                                                                        clock_info);
2390                         if (valid)
2391                                 mode_index++;
2392                 }
2393                 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2394                 if (mode_index) {
2395                         radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2396                                                                    non_clock_info);
2397                         state_index++;
2398                 }
2399         }
2400         /* if multiple clock modes, mark the lowest as no display */
2401         for (i = 0; i < state_index; i++) {
2402                 if (rdev->pm.power_state[i].num_clock_modes > 1)
2403                         rdev->pm.power_state[i].clock_info[0].flags |=
2404                                 RADEON_PM_MODE_NO_DISPLAY;
2405         }
2406         /* first mode is usually default */
2407         if (rdev->pm.default_power_state_index == -1) {
2408                 rdev->pm.power_state[0].type =
2409                         POWER_STATE_TYPE_DEFAULT;
2410                 rdev->pm.default_power_state_index = 0;
2411                 rdev->pm.power_state[0].default_clock_mode =
2412                         &rdev->pm.power_state[0].clock_info[0];
2413         }
2414         return state_index;
2415 }
2416
2417 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2418 {
2419         struct radeon_mode_info *mode_info = &rdev->mode_info;
2420         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2421         u16 data_offset;
2422         u8 frev, crev;
2423         int state_index = 0;
2424
2425         rdev->pm.default_power_state_index = -1;
2426
2427         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2428                                    &frev, &crev, &data_offset)) {
2429                 switch (frev) {
2430                 case 1:
2431                 case 2:
2432                 case 3:
2433                         state_index = radeon_atombios_parse_power_table_1_3(rdev);
2434                         break;
2435                 case 4:
2436                 case 5:
2437                         state_index = radeon_atombios_parse_power_table_4_5(rdev);
2438                         break;
2439                 case 6:
2440                         state_index = radeon_atombios_parse_power_table_6(rdev);
2441                         break;
2442                 default:
2443                         break;
2444                 }
2445         } else {
2446                 /* add the default mode */
2447                 rdev->pm.power_state[state_index].type =
2448                         POWER_STATE_TYPE_DEFAULT;
2449                 rdev->pm.power_state[state_index].num_clock_modes = 1;
2450                 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2451                 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2452                 rdev->pm.power_state[state_index].default_clock_mode =
2453                         &rdev->pm.power_state[state_index].clock_info[0];
2454                 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2455                 rdev->pm.power_state[state_index].pcie_lanes = 16;
2456                 rdev->pm.default_power_state_index = state_index;
2457                 rdev->pm.power_state[state_index].flags = 0;
2458                 state_index++;
2459         }
2460
2461         rdev->pm.num_power_states = state_index;
2462
2463         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2464         rdev->pm.current_clock_mode_index = 0;
2465         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2466 }
2467
2468 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
2469 {
2470         DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
2471         int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
2472
2473         args.ucEnable = enable;
2474
2475         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2476 }
2477
2478 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
2479 {
2480         GET_ENGINE_CLOCK_PS_ALLOCATION args;
2481         int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
2482
2483         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2484         return args.ulReturnEngineClock;
2485 }
2486
2487 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
2488 {
2489         GET_MEMORY_CLOCK_PS_ALLOCATION args;
2490         int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
2491
2492         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2493         return args.ulReturnMemoryClock;
2494 }
2495
2496 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
2497                                   uint32_t eng_clock)
2498 {
2499         SET_ENGINE_CLOCK_PS_ALLOCATION args;
2500         int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
2501
2502         args.ulTargetEngineClock = eng_clock;   /* 10 khz */
2503
2504         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2505 }
2506
2507 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
2508                                   uint32_t mem_clock)
2509 {
2510         SET_MEMORY_CLOCK_PS_ALLOCATION args;
2511         int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
2512
2513         if (rdev->flags & RADEON_IS_IGP)
2514                 return;
2515
2516         args.ulTargetMemoryClock = mem_clock;   /* 10 khz */
2517
2518         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2519 }
2520
2521 union set_voltage {
2522         struct _SET_VOLTAGE_PS_ALLOCATION alloc;
2523         struct _SET_VOLTAGE_PARAMETERS v1;
2524         struct _SET_VOLTAGE_PARAMETERS_V2 v2;
2525 };
2526
2527 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level)
2528 {
2529         union set_voltage args;
2530         int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
2531         u8 frev, crev, volt_index = level;
2532
2533         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2534                 return;
2535
2536         switch (crev) {
2537         case 1:
2538                 args.v1.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2539                 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
2540                 args.v1.ucVoltageIndex = volt_index;
2541                 break;
2542         case 2:
2543                 args.v2.ucVoltageType = SET_VOLTAGE_TYPE_ASIC_VDDC;
2544                 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
2545                 args.v2.usVoltageLevel = cpu_to_le16(level);
2546                 break;
2547         default:
2548                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
2549                 return;
2550         }
2551
2552         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2553 }
2554
2555
2556
2557 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
2558 {
2559         struct radeon_device *rdev = dev->dev_private;
2560         uint32_t bios_2_scratch, bios_6_scratch;
2561
2562         if (rdev->family >= CHIP_R600) {
2563                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2564                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2565         } else {
2566                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2567                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2568         }
2569
2570         /* let the bios control the backlight */
2571         bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
2572
2573         /* tell the bios not to handle mode switching */
2574         bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
2575
2576         if (rdev->family >= CHIP_R600) {
2577                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2578                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2579         } else {
2580                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2581                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2582         }
2583
2584 }
2585
2586 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
2587 {
2588         uint32_t scratch_reg;
2589         int i;
2590
2591         if (rdev->family >= CHIP_R600)
2592                 scratch_reg = R600_BIOS_0_SCRATCH;
2593         else
2594                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2595
2596         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2597                 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
2598 }
2599
2600 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2601 {
2602         uint32_t scratch_reg;
2603         int i;
2604
2605         if (rdev->family >= CHIP_R600)
2606                 scratch_reg = R600_BIOS_0_SCRATCH;
2607         else
2608                 scratch_reg = RADEON_BIOS_0_SCRATCH;
2609
2610         for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2611                 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2612 }
2613
2614 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2615 {
2616         struct drm_device *dev = encoder->dev;
2617         struct radeon_device *rdev = dev->dev_private;
2618         uint32_t bios_6_scratch;
2619
2620         if (rdev->family >= CHIP_R600)
2621                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2622         else
2623                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2624
2625         if (lock)
2626                 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2627         else
2628                 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2629
2630         if (rdev->family >= CHIP_R600)
2631                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2632         else
2633                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2634 }
2635
2636 /* at some point we may want to break this out into individual functions */
2637 void
2638 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2639                                        struct drm_encoder *encoder,
2640                                        bool connected)
2641 {
2642         struct drm_device *dev = connector->dev;
2643         struct radeon_device *rdev = dev->dev_private;
2644         struct radeon_connector *radeon_connector =
2645             to_radeon_connector(connector);
2646         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2647         uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2648
2649         if (rdev->family >= CHIP_R600) {
2650                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2651                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2652                 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2653         } else {
2654                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2655                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2656                 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2657         }
2658
2659         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2660             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2661                 if (connected) {
2662                         DRM_DEBUG_KMS("TV1 connected\n");
2663                         bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2664                         bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2665                 } else {
2666                         DRM_DEBUG_KMS("TV1 disconnected\n");
2667                         bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2668                         bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2669                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2670                 }
2671         }
2672         if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2673             (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2674                 if (connected) {
2675                         DRM_DEBUG_KMS("CV connected\n");
2676                         bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2677                         bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2678                 } else {
2679                         DRM_DEBUG_KMS("CV disconnected\n");
2680                         bios_0_scratch &= ~ATOM_S0_CV_MASK;
2681                         bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2682                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2683                 }
2684         }
2685         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2686             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2687                 if (connected) {
2688                         DRM_DEBUG_KMS("LCD1 connected\n");
2689                         bios_0_scratch |= ATOM_S0_LCD1;
2690                         bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2691                         bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2692                 } else {
2693                         DRM_DEBUG_KMS("LCD1 disconnected\n");
2694                         bios_0_scratch &= ~ATOM_S0_LCD1;
2695                         bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2696                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2697                 }
2698         }
2699         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2700             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2701                 if (connected) {
2702                         DRM_DEBUG_KMS("CRT1 connected\n");
2703                         bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2704                         bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2705                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2706                 } else {
2707                         DRM_DEBUG_KMS("CRT1 disconnected\n");
2708                         bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2709                         bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2710                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2711                 }
2712         }
2713         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2714             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2715                 if (connected) {
2716                         DRM_DEBUG_KMS("CRT2 connected\n");
2717                         bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2718                         bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2719                         bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2720                 } else {
2721                         DRM_DEBUG_KMS("CRT2 disconnected\n");
2722                         bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2723                         bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2724                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2725                 }
2726         }
2727         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2728             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2729                 if (connected) {
2730                         DRM_DEBUG_KMS("DFP1 connected\n");
2731                         bios_0_scratch |= ATOM_S0_DFP1;
2732                         bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2733                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2734                 } else {
2735                         DRM_DEBUG_KMS("DFP1 disconnected\n");
2736                         bios_0_scratch &= ~ATOM_S0_DFP1;
2737                         bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2738                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2739                 }
2740         }
2741         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2742             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2743                 if (connected) {
2744                         DRM_DEBUG_KMS("DFP2 connected\n");
2745                         bios_0_scratch |= ATOM_S0_DFP2;
2746                         bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2747                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2748                 } else {
2749                         DRM_DEBUG_KMS("DFP2 disconnected\n");
2750                         bios_0_scratch &= ~ATOM_S0_DFP2;
2751                         bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2752                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2753                 }
2754         }
2755         if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2756             (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2757                 if (connected) {
2758                         DRM_DEBUG_KMS("DFP3 connected\n");
2759                         bios_0_scratch |= ATOM_S0_DFP3;
2760                         bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2761                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2762                 } else {
2763                         DRM_DEBUG_KMS("DFP3 disconnected\n");
2764                         bios_0_scratch &= ~ATOM_S0_DFP3;
2765                         bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2766                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2767                 }
2768         }
2769         if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2770             (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2771                 if (connected) {
2772                         DRM_DEBUG_KMS("DFP4 connected\n");
2773                         bios_0_scratch |= ATOM_S0_DFP4;
2774                         bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2775                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2776                 } else {
2777                         DRM_DEBUG_KMS("DFP4 disconnected\n");
2778                         bios_0_scratch &= ~ATOM_S0_DFP4;
2779                         bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2780                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2781                 }
2782         }
2783         if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2784             (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2785                 if (connected) {
2786                         DRM_DEBUG_KMS("DFP5 connected\n");
2787                         bios_0_scratch |= ATOM_S0_DFP5;
2788                         bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2789                         bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2790                 } else {
2791                         DRM_DEBUG_KMS("DFP5 disconnected\n");
2792                         bios_0_scratch &= ~ATOM_S0_DFP5;
2793                         bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2794                         bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2795                 }
2796         }
2797
2798         if (rdev->family >= CHIP_R600) {
2799                 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2800                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2801                 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2802         } else {
2803                 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2804                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2805                 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2806         }
2807 }
2808
2809 void
2810 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2811 {
2812         struct drm_device *dev = encoder->dev;
2813         struct radeon_device *rdev = dev->dev_private;
2814         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2815         uint32_t bios_3_scratch;
2816
2817         if (rdev->family >= CHIP_R600)
2818                 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2819         else
2820                 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2821
2822         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2823                 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2824                 bios_3_scratch |= (crtc << 18);
2825         }
2826         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2827                 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2828                 bios_3_scratch |= (crtc << 24);
2829         }
2830         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2831                 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2832                 bios_3_scratch |= (crtc << 16);
2833         }
2834         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2835                 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2836                 bios_3_scratch |= (crtc << 20);
2837         }
2838         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2839                 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2840                 bios_3_scratch |= (crtc << 17);
2841         }
2842         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2843                 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2844                 bios_3_scratch |= (crtc << 19);
2845         }
2846         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2847                 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2848                 bios_3_scratch |= (crtc << 23);
2849         }
2850         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2851                 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2852                 bios_3_scratch |= (crtc << 25);
2853         }
2854
2855         if (rdev->family >= CHIP_R600)
2856                 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2857         else
2858                 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2859 }
2860
2861 void
2862 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2863 {
2864         struct drm_device *dev = encoder->dev;
2865         struct radeon_device *rdev = dev->dev_private;
2866         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2867         uint32_t bios_2_scratch;
2868
2869         if (rdev->family >= CHIP_R600)
2870                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2871         else
2872                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2873
2874         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2875                 if (on)
2876                         bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2877                 else
2878                         bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2879         }
2880         if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2881                 if (on)
2882                         bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2883                 else
2884                         bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2885         }
2886         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2887                 if (on)
2888                         bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2889                 else
2890                         bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2891         }
2892         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2893                 if (on)
2894                         bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2895                 else
2896                         bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2897         }
2898         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2899                 if (on)
2900                         bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2901                 else
2902                         bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2903         }
2904         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2905                 if (on)
2906                         bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2907                 else
2908                         bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2909         }
2910         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2911                 if (on)
2912                         bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2913                 else
2914                         bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2915         }
2916         if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2917                 if (on)
2918                         bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2919                 else
2920                         bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2921         }
2922         if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2923                 if (on)
2924                         bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2925                 else
2926                         bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2927         }
2928         if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2929                 if (on)
2930                         bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2931                 else
2932                         bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2933         }
2934
2935         if (rdev->family >= CHIP_R600)
2936                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2937         else
2938                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2939 }